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Merge branch 'pci/virtualization'
[mirror_ubuntu-jammy-kernel.git] / drivers / pci / quirks.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
13 */
14
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <linux/pm_runtime.h>
30 #include <asm/dma.h> /* isa_dma_bridge_buggy */
31 #include "pci.h"
32
33 /*
34 * Decoding should be disabled for a PCI device during BAR sizing to avoid
35 * conflict. But doing so may cause problems on host bridge and perhaps other
36 * key system devices. For devices that need to have mmio decoding always-on,
37 * we need to set the dev->mmio_always_on bit.
38 */
39 static void quirk_mmio_always_on(struct pci_dev *dev)
40 {
41 dev->mmio_always_on = 1;
42 }
43 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
44 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
45
46 /* The Mellanox Tavor device gives false positive parity errors
47 * Mark this device with a broken_parity_status, to allow
48 * PCI scanning code to "skip" this now blacklisted device.
49 */
50 static void quirk_mellanox_tavor(struct pci_dev *dev)
51 {
52 dev->broken_parity_status = 1; /* This device gives false positives */
53 }
54 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
56
57 /* Deal with broken BIOSes that neglect to enable passive release,
58 which can cause problems in combination with the 82441FX/PPro MTRRs */
59 static void quirk_passive_release(struct pci_dev *dev)
60 {
61 struct pci_dev *d = NULL;
62 unsigned char dlc;
63
64 /* We have to make sure a particular bit is set in the PIIX3
65 ISA bridge, so we have to go out and find it. */
66 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
67 pci_read_config_byte(d, 0x82, &dlc);
68 if (!(dlc & 1<<1)) {
69 pci_info(d, "PIIX3: Enabling Passive Release\n");
70 dlc |= 1<<1;
71 pci_write_config_byte(d, 0x82, dlc);
72 }
73 }
74 }
75 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77
78 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
79 but VIA don't answer queries. If you happen to have good contacts at VIA
80 ask them for me please -- Alan
81
82 This appears to be BIOS not version dependent. So presumably there is a
83 chipset level fix */
84
85 static void quirk_isa_dma_hangs(struct pci_dev *dev)
86 {
87 if (!isa_dma_bridge_buggy) {
88 isa_dma_bridge_buggy = 1;
89 pci_info(dev, "Activating ISA DMA hang workarounds\n");
90 }
91 }
92 /*
93 * Its not totally clear which chipsets are the problematic ones
94 * We know 82C586 and 82C596 variants are affected.
95 */
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
103
104 /*
105 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
106 * for some HT machines to use C4 w/o hanging.
107 */
108 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
109 {
110 u32 pmbase;
111 u16 pm1a;
112
113 pci_read_config_dword(dev, 0x40, &pmbase);
114 pmbase = pmbase & 0xff80;
115 pm1a = inw(pmbase);
116
117 if (pm1a & 0x10) {
118 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
119 outw(0x10, pmbase);
120 }
121 }
122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123
124 /*
125 * Chipsets where PCI->PCI transfers vanish or hang
126 */
127 static void quirk_nopcipci(struct pci_dev *dev)
128 {
129 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
130 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
131 pci_pci_problems |= PCIPCI_FAIL;
132 }
133 }
134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
136
137 static void quirk_nopciamd(struct pci_dev *dev)
138 {
139 u8 rev;
140 pci_read_config_byte(dev, 0x08, &rev);
141 if (rev == 0x13) {
142 /* Erratum 24 */
143 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
144 pci_pci_problems |= PCIAGP_FAIL;
145 }
146 }
147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148
149 /*
150 * Triton requires workarounds to be used by the drivers
151 */
152 static void quirk_triton(struct pci_dev *dev)
153 {
154 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
155 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
156 pci_pci_problems |= PCIPCI_TRITON;
157 }
158 }
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163
164 /*
165 * VIA Apollo KT133 needs PCI latency patch
166 * Made according to a windows driver based patch by George E. Breese
167 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
168 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
169 * the info on which Mr Breese based his work.
170 *
171 * Updated based on further information from the site and also on
172 * information provided by VIA
173 */
174 static void quirk_vialatency(struct pci_dev *dev)
175 {
176 struct pci_dev *p;
177 u8 busarb;
178 /* Ok we have a potential problem chipset here. Now see if we have
179 a buggy southbridge */
180
181 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
182 if (p != NULL) {
183 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
184 /* Check for buggy part revisions */
185 if (p->revision < 0x40 || p->revision > 0x42)
186 goto exit;
187 } else {
188 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
189 if (p == NULL) /* No problem parts */
190 goto exit;
191 /* Check for buggy part revisions */
192 if (p->revision < 0x10 || p->revision > 0x12)
193 goto exit;
194 }
195
196 /*
197 * Ok we have the problem. Now set the PCI master grant to
198 * occur every master grant. The apparent bug is that under high
199 * PCI load (quite common in Linux of course) you can get data
200 * loss when the CPU is held off the bus for 3 bus master requests
201 * This happens to include the IDE controllers....
202 *
203 * VIA only apply this fix when an SB Live! is present but under
204 * both Linux and Windows this isn't enough, and we have seen
205 * corruption without SB Live! but with things like 3 UDMA IDE
206 * controllers. So we ignore that bit of the VIA recommendation..
207 */
208
209 pci_read_config_byte(dev, 0x76, &busarb);
210 /* Set bit 4 and bi 5 of byte 76 to 0x01
211 "Master priority rotation on every PCI master grant */
212 busarb &= ~(1<<5);
213 busarb |= (1<<4);
214 pci_write_config_byte(dev, 0x76, busarb);
215 pci_info(dev, "Applying VIA southbridge workaround\n");
216 exit:
217 pci_dev_put(p);
218 }
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
222 /* Must restore this on a resume from RAM */
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
226
227 /*
228 * VIA Apollo VP3 needs ETBF on BT848/878
229 */
230 static void quirk_viaetbf(struct pci_dev *dev)
231 {
232 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
233 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
234 pci_pci_problems |= PCIPCI_VIAETBF;
235 }
236 }
237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
238
239 static void quirk_vsfx(struct pci_dev *dev)
240 {
241 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
242 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
243 pci_pci_problems |= PCIPCI_VSFX;
244 }
245 }
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
247
248 /*
249 * Ali Magik requires workarounds to be used by the drivers
250 * that DMA to AGP space. Latency must be set to 0xA and triton
251 * workaround applied too
252 * [Info kindly provided by ALi]
253 */
254 static void quirk_alimagik(struct pci_dev *dev)
255 {
256 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
257 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
258 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
259 }
260 }
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
263
264 /*
265 * Natoma has some interesting boundary conditions with Zoran stuff
266 * at least
267 */
268 static void quirk_natoma(struct pci_dev *dev)
269 {
270 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
271 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
272 pci_pci_problems |= PCIPCI_NATOMA;
273 }
274 }
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
281
282 /*
283 * This chip can cause PCI parity errors if config register 0xA0 is read
284 * while DMAs are occurring.
285 */
286 static void quirk_citrine(struct pci_dev *dev)
287 {
288 dev->cfg_size = 0xA0;
289 }
290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
291
292 /*
293 * This chip can cause bus lockups if config addresses above 0x600
294 * are read or written.
295 */
296 static void quirk_nfp6000(struct pci_dev *dev)
297 {
298 dev->cfg_size = 0x600;
299 }
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
303
304 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
305 static void quirk_extend_bar_to_page(struct pci_dev *dev)
306 {
307 int i;
308
309 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
310 struct resource *r = &dev->resource[i];
311
312 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
313 r->end = PAGE_SIZE - 1;
314 r->start = 0;
315 r->flags |= IORESOURCE_UNSET;
316 pci_info(dev, "expanded BAR %d to page size: %pR\n",
317 i, r);
318 }
319 }
320 }
321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
322
323 /*
324 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
325 * If it's needed, re-allocate the region.
326 */
327 static void quirk_s3_64M(struct pci_dev *dev)
328 {
329 struct resource *r = &dev->resource[0];
330
331 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
332 r->flags |= IORESOURCE_UNSET;
333 r->start = 0;
334 r->end = 0x3ffffff;
335 }
336 }
337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
339
340 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
341 const char *name)
342 {
343 u32 region;
344 struct pci_bus_region bus_region;
345 struct resource *res = dev->resource + pos;
346
347 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
348
349 if (!region)
350 return;
351
352 res->name = pci_name(dev);
353 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
354 res->flags |=
355 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
356 region &= ~(size - 1);
357
358 /* Convert from PCI bus to resource space */
359 bus_region.start = region;
360 bus_region.end = region + size - 1;
361 pcibios_bus_to_resource(dev->bus, res, &bus_region);
362
363 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
364 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
365 }
366
367 /*
368 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
369 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
370 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
371 * (which conflicts w/ BAR1's memory range).
372 *
373 * CS553x's ISA PCI BARs may also be read-only (ref:
374 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
375 */
376 static void quirk_cs5536_vsa(struct pci_dev *dev)
377 {
378 static char *name = "CS5536 ISA bridge";
379
380 if (pci_resource_len(dev, 0) != 8) {
381 quirk_io(dev, 0, 8, name); /* SMB */
382 quirk_io(dev, 1, 256, name); /* GPIO */
383 quirk_io(dev, 2, 64, name); /* MFGPT */
384 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
385 name);
386 }
387 }
388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
389
390 static void quirk_io_region(struct pci_dev *dev, int port,
391 unsigned size, int nr, const char *name)
392 {
393 u16 region;
394 struct pci_bus_region bus_region;
395 struct resource *res = dev->resource + nr;
396
397 pci_read_config_word(dev, port, &region);
398 region &= ~(size - 1);
399
400 if (!region)
401 return;
402
403 res->name = pci_name(dev);
404 res->flags = IORESOURCE_IO;
405
406 /* Convert from PCI bus to resource space */
407 bus_region.start = region;
408 bus_region.end = region + size - 1;
409 pcibios_bus_to_resource(dev->bus, res, &bus_region);
410
411 if (!pci_claim_resource(dev, nr))
412 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
413 }
414
415 /*
416 * ATI Northbridge setups MCE the processor if you even
417 * read somewhere between 0x3b0->0x3bb or read 0x3d3
418 */
419 static void quirk_ati_exploding_mce(struct pci_dev *dev)
420 {
421 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
422 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
423 request_region(0x3b0, 0x0C, "RadeonIGP");
424 request_region(0x3d3, 0x01, "RadeonIGP");
425 }
426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
427
428 /*
429 * In the AMD NL platform, this device ([1022:7912]) has a class code of
430 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
431 * claim it.
432 * But the dwc3 driver is a more specific driver for this device, and we'd
433 * prefer to use it instead of xhci. To prevent xhci from claiming the
434 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
435 * defines as "USB device (not host controller)". The dwc3 driver can then
436 * claim it based on its Vendor and Device ID.
437 */
438 static void quirk_amd_nl_class(struct pci_dev *pdev)
439 {
440 u32 class = pdev->class;
441
442 /* Use "USB Device (not host controller)" class */
443 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
444 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
445 class, pdev->class);
446 }
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
448 quirk_amd_nl_class);
449
450 /*
451 * Let's make the southbridge information explicit instead
452 * of having to worry about people probing the ACPI areas,
453 * for example.. (Yes, it happens, and if you read the wrong
454 * ACPI register it will put the machine to sleep with no
455 * way of waking it up again. Bummer).
456 *
457 * ALI M7101: Two IO regions pointed to by words at
458 * 0xE0 (64 bytes of ACPI registers)
459 * 0xE2 (32 bytes of SMB registers)
460 */
461 static void quirk_ali7101_acpi(struct pci_dev *dev)
462 {
463 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
464 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
465 }
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
467
468 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
469 {
470 u32 devres;
471 u32 mask, size, base;
472
473 pci_read_config_dword(dev, port, &devres);
474 if ((devres & enable) != enable)
475 return;
476 mask = (devres >> 16) & 15;
477 base = devres & 0xffff;
478 size = 16;
479 for (;;) {
480 unsigned bit = size >> 1;
481 if ((bit & mask) == bit)
482 break;
483 size = bit;
484 }
485 /*
486 * For now we only print it out. Eventually we'll want to
487 * reserve it (at least if it's in the 0x1000+ range), but
488 * let's get enough confirmation reports first.
489 */
490 base &= -size;
491 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
492 }
493
494 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
495 {
496 u32 devres;
497 u32 mask, size, base;
498
499 pci_read_config_dword(dev, port, &devres);
500 if ((devres & enable) != enable)
501 return;
502 base = devres & 0xffff0000;
503 mask = (devres & 0x3f) << 16;
504 size = 128 << 16;
505 for (;;) {
506 unsigned bit = size >> 1;
507 if ((bit & mask) == bit)
508 break;
509 size = bit;
510 }
511 /*
512 * For now we only print it out. Eventually we'll want to
513 * reserve it, but let's get enough confirmation reports first.
514 */
515 base &= -size;
516 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
517 }
518
519 /*
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
522 * 0x90 (16 bytes of SMB registers)
523 * and a few strange programmable PIIX4 device resources.
524 */
525 static void quirk_piix4_acpi(struct pci_dev *dev)
526 {
527 u32 res_a;
528
529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
531
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538 /* Device resource D is just bitfields for static resources */
539
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
552 }
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
555
556 #define ICH_PMBASE 0x40
557 #define ICH_ACPI_CNTL 0x44
558 #define ICH4_ACPI_EN 0x10
559 #define ICH6_ACPI_EN 0x80
560 #define ICH4_GPIOBASE 0x58
561 #define ICH4_GPIO_CNTL 0x5c
562 #define ICH4_GPIO_EN 0x10
563 #define ICH6_GPIOBASE 0x48
564 #define ICH6_GPIO_CNTL 0x4c
565 #define ICH6_GPIO_EN 0x10
566
567 /*
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
571 */
572 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
573 {
574 u8 enable;
575
576 /*
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
581 * BIOSes.
582 */
583
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
588
589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
593 }
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
604
605 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
606 {
607 u8 enable;
608
609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
613
614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
618 }
619
620 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
621 {
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627 /* Enabled? */
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632 /*
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
635 *
636 * But this gets us at least _part_ of it.
637 */
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644 /* Just print it out for now. We should reserve it after more debugging */
645 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646 }
647
648 static void quirk_ich6_lpc(struct pci_dev *dev)
649 {
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
652
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656 }
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
660 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
661 {
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667 /* Enabled? */
668 if (!(val & 1))
669 return;
670
671 /*
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679 /* Just print it out for now. We should reserve it after more debugging */
680 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681 }
682
683 /* ICH7-10 has the same common LPC generic IO decode registers */
684 static void quirk_ich7_lpc(struct pci_dev *dev)
685 {
686 /* We share the common ACPI/GPIO decode with ICH6 */
687 ich6_lpc_acpi_gpio(dev);
688
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694 }
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
708
709 /*
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
712 */
713 static void quirk_vt82c586_acpi(struct pci_dev *dev)
714 {
715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
718 }
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
720
721 /*
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
726 */
727 static void quirk_vt82c686_acpi(struct pci_dev *dev)
728 {
729 quirk_vt82c586_acpi(dev);
730
731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
733
734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
735 }
736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
737
738 /*
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
742 */
743 static void quirk_vt8235_acpi(struct pci_dev *dev)
744 {
745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
747 }
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
750 /*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
753 */
754 static void quirk_xio2000a(struct pci_dev *dev)
755 {
756 struct pci_dev *pdev;
757 u16 command;
758
759 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765 }
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
768
769 #ifdef CONFIG_X86_IO_APIC
770
771 #include <asm/io_apic.h>
772
773 /*
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
776 *
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
779 */
780 static void quirk_via_ioapic(struct pci_dev *dev)
781 {
782 u8 tmp;
783
784 if (nr_ioapics < 1)
785 tmp = 0; /* nothing routed to external APIC */
786 else
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
788
789 pci_info(dev, "%sbling VIA external APIC routing\n",
790 tmp == 0 ? "Disa" : "Ena");
791
792 /* Offset 0x58: External APIC IRQ output control */
793 pci_write_config_byte(dev, 0x58, tmp);
794 }
795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
797
798 /*
799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
803 */
804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
805 {
806 u8 misc_control2;
807 #define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
811 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814 }
815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
817
818 /*
819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
822 *
823 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so..
826 */
827 static void quirk_amd_ioapic(struct pci_dev *dev)
828 {
829 if (dev->revision >= 0x02) {
830 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 pci_warn(dev, " : booting with the \"noapic\" option\n");
832 }
833 }
834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
835 #endif /* CONFIG_X86_IO_APIC */
836
837 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
838
839 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
840 {
841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
842 if (dev->subsystem_device == 0xa118)
843 dev->sriov->link = dev->devfn;
844 }
845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
846 #endif
847
848 /*
849 * Some settings of MMRBC can lead to data corruption so block changes.
850 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
851 */
852 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
853 {
854 if (dev->subordinate && dev->revision <= 0x12) {
855 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
856 dev->revision);
857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
858 }
859 }
860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
861
862 /*
863 * FIXME: it is questionable that quirk_via_acpi
864 * is needed. It shows up as an ISA bridge, and does not
865 * support the PCI_INTERRUPT_LINE register at all. Therefore
866 * it seems like setting the pci_dev's 'irq' to the
867 * value of the ACPI SCI interrupt is only done for convenience.
868 * -jgarzik
869 */
870 static void quirk_via_acpi(struct pci_dev *d)
871 {
872 /*
873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
874 */
875 u8 irq;
876 pci_read_config_byte(d, 0x42, &irq);
877 irq &= 0xf;
878 if (irq && (irq != 2))
879 d->irq = irq;
880 }
881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
883
884
885 /*
886 * VIA bridges which have VLink
887 */
888
889 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
890
891 static void quirk_via_bridge(struct pci_dev *dev)
892 {
893 /* See what bridge we have and find the device ranges */
894 switch (dev->device) {
895 case PCI_DEVICE_ID_VIA_82C686:
896 /* The VT82C686 is special, it attaches to PCI and can have
897 any device number. All its subdevices are functions of
898 that single device. */
899 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
900 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
901 break;
902 case PCI_DEVICE_ID_VIA_8237:
903 case PCI_DEVICE_ID_VIA_8237A:
904 via_vlink_dev_lo = 15;
905 break;
906 case PCI_DEVICE_ID_VIA_8235:
907 via_vlink_dev_lo = 16;
908 break;
909 case PCI_DEVICE_ID_VIA_8231:
910 case PCI_DEVICE_ID_VIA_8233_0:
911 case PCI_DEVICE_ID_VIA_8233A:
912 case PCI_DEVICE_ID_VIA_8233C_0:
913 via_vlink_dev_lo = 17;
914 break;
915 }
916 }
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
925
926 /**
927 * quirk_via_vlink - VIA VLink IRQ number update
928 * @dev: PCI device
929 *
930 * If the device we are dealing with is on a PIC IRQ we need to
931 * ensure that the IRQ line register which usually is not relevant
932 * for PCI cards, is actually written so that interrupts get sent
933 * to the right place.
934 * We only do this on systems where a VIA south bridge was detected,
935 * and only for VIA devices on the motherboard (see quirk_via_bridge
936 * above).
937 */
938
939 static void quirk_via_vlink(struct pci_dev *dev)
940 {
941 u8 irq, new_irq;
942
943 /* Check if we have VLink at all */
944 if (via_vlink_dev_lo == -1)
945 return;
946
947 new_irq = dev->irq;
948
949 /* Don't quirk interrupts outside the legacy IRQ range */
950 if (!new_irq || new_irq > 15)
951 return;
952
953 /* Internal device ? */
954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
956 return;
957
958 /* This is an internal VLink device on a PIC interrupt. The BIOS
959 ought to have set this but may not have, so we redo it */
960
961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
962 if (new_irq != irq) {
963 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
964 irq, new_irq);
965 udelay(15); /* unknown if delay really needed */
966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
967 }
968 }
969 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
970
971 /*
972 * VIA VT82C598 has its device ID settable and many BIOSes
973 * set it to the ID of VT82C597 for backward compatibility.
974 * We need to switch it off to be able to recognize the real
975 * type of the chip.
976 */
977 static void quirk_vt82c598_id(struct pci_dev *dev)
978 {
979 pci_write_config_byte(dev, 0xfc, 0);
980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
981 }
982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
983
984 /*
985 * CardBus controllers have a legacy base address that enables them
986 * to respond as i82365 pcmcia controllers. We don't want them to
987 * do this even if the Linux CardBus driver is not loaded, because
988 * the Linux i82365 driver does not (and should not) handle CardBus.
989 */
990 static void quirk_cardbus_legacy(struct pci_dev *dev)
991 {
992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
993 }
994 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
996 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
998
999 /*
1000 * Following the PCI ordering rules is optional on the AMD762. I'm not
1001 * sure what the designers were smoking but let's not inhale...
1002 *
1003 * To be fair to AMD, it follows the spec by default, its BIOS people
1004 * who turn it off!
1005 */
1006 static void quirk_amd_ordering(struct pci_dev *dev)
1007 {
1008 u32 pcic;
1009 pci_read_config_dword(dev, 0x4C, &pcic);
1010 if ((pcic & 6) != 6) {
1011 pcic |= 6;
1012 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1013 pci_write_config_dword(dev, 0x4C, pcic);
1014 pci_read_config_dword(dev, 0x84, &pcic);
1015 pcic |= (1 << 23); /* Required in this mode */
1016 pci_write_config_dword(dev, 0x84, pcic);
1017 }
1018 }
1019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1021
1022 /*
1023 * DreamWorks provided workaround for Dunord I-3000 problem
1024 *
1025 * This card decodes and responds to addresses not apparently
1026 * assigned to it. We force a larger allocation to ensure that
1027 * nothing gets put too close to it.
1028 */
1029 static void quirk_dunord(struct pci_dev *dev)
1030 {
1031 struct resource *r = &dev->resource[1];
1032
1033 r->flags |= IORESOURCE_UNSET;
1034 r->start = 0;
1035 r->end = 0xffffff;
1036 }
1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1038
1039 /*
1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1041 * is subtractive decoding (transparent), and does indicate this
1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1043 * instead of 0x01.
1044 */
1045 static void quirk_transparent_bridge(struct pci_dev *dev)
1046 {
1047 dev->transparent = 1;
1048 }
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1051
1052 /*
1053 * Common misconfiguration of the MediaGX/Geode PCI master that will
1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1055 * datasheets found at http://www.national.com/analog for info on what
1056 * these bits do. <christer@weinigel.se>
1057 */
1058 static void quirk_mediagx_master(struct pci_dev *dev)
1059 {
1060 u8 reg;
1061
1062 pci_read_config_byte(dev, 0x41, &reg);
1063 if (reg & 2) {
1064 reg &= ~2;
1065 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1066 reg);
1067 pci_write_config_byte(dev, 0x41, reg);
1068 }
1069 }
1070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1072
1073 /*
1074 * Ensure C0 rev restreaming is off. This is normally done by
1075 * the BIOS but in the odd case it is not the results are corruption
1076 * hence the presence of a Linux check
1077 */
1078 static void quirk_disable_pxb(struct pci_dev *pdev)
1079 {
1080 u16 config;
1081
1082 if (pdev->revision != 0x04) /* Only C0 requires this */
1083 return;
1084 pci_read_config_word(pdev, 0x40, &config);
1085 if (config & (1<<6)) {
1086 config &= ~(1<<6);
1087 pci_write_config_word(pdev, 0x40, config);
1088 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1089 }
1090 }
1091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1093
1094 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1095 {
1096 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1097 u8 tmp;
1098
1099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1100 if (tmp == 0x01) {
1101 pci_read_config_byte(pdev, 0x40, &tmp);
1102 pci_write_config_byte(pdev, 0x40, tmp|1);
1103 pci_write_config_byte(pdev, 0x9, 1);
1104 pci_write_config_byte(pdev, 0xa, 6);
1105 pci_write_config_byte(pdev, 0x40, tmp);
1106
1107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1108 pci_info(pdev, "set SATA to AHCI mode\n");
1109 }
1110 }
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1112 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1119
1120 /*
1121 * Serverworks CSB5 IDE does not fully support native mode
1122 */
1123 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1124 {
1125 u8 prog;
1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1127 if (prog & 5) {
1128 prog &= ~5;
1129 pdev->class &= ~5;
1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1131 /* PCI layer will sort out resources */
1132 }
1133 }
1134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1135
1136 /*
1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1138 */
1139 static void quirk_ide_samemode(struct pci_dev *pdev)
1140 {
1141 u8 prog;
1142
1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1144
1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1146 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1147 prog &= ~5;
1148 pdev->class &= ~5;
1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1150 }
1151 }
1152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1153
1154 /*
1155 * Some ATA devices break if put into D3
1156 */
1157
1158 static void quirk_no_ata_d3(struct pci_dev *pdev)
1159 {
1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1161 }
1162 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1163 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1167 /* ALi loses some register settings that we cannot then restore */
1168 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1170 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1171 occur when mode detecting */
1172 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1174
1175 /* This was originally an Alpha specific thing, but it really fits here.
1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1177 */
1178 static void quirk_eisa_bridge(struct pci_dev *dev)
1179 {
1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1181 }
1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1183
1184
1185 /*
1186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1187 * is not activated. The myth is that Asus said that they do not want the
1188 * users to be irritated by just another PCI Device in the Win98 device
1189 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1190 * package 2.7.0 for details)
1191 *
1192 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1193 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1194 * becomes necessary to do this tweak in two steps -- the chosen trigger
1195 * is either the Host bridge (preferred) or on-board VGA controller.
1196 *
1197 * Note that we used to unhide the SMBus that way on Toshiba laptops
1198 * (Satellite A40 and Tecra M2) but then found that the thermal management
1199 * was done by SMM code, which could cause unsynchronized concurrent
1200 * accesses to the SMBus registers, with potentially bad effects. Thus you
1201 * should be very careful when adding new entries: if SMM is accessing the
1202 * Intel SMBus, this is a very good reason to leave it hidden.
1203 *
1204 * Likewise, many recent laptops use ACPI for thermal management. If the
1205 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1206 * natively, and keeping the SMBus hidden is the right thing to do. If you
1207 * are about to add an entry in the table below, please first disassemble
1208 * the DSDT and double-check that there is no code accessing the SMBus.
1209 */
1210 static int asus_hides_smbus;
1211
1212 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1213 {
1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1216 switch (dev->subsystem_device) {
1217 case 0x8025: /* P4B-LX */
1218 case 0x8070: /* P4B */
1219 case 0x8088: /* P4B533 */
1220 case 0x1626: /* L3C notebook */
1221 asus_hides_smbus = 1;
1222 }
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1224 switch (dev->subsystem_device) {
1225 case 0x80b1: /* P4GE-V */
1226 case 0x80b2: /* P4PE */
1227 case 0x8093: /* P4B533-V */
1228 asus_hides_smbus = 1;
1229 }
1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1231 switch (dev->subsystem_device) {
1232 case 0x8030: /* P4T533 */
1233 asus_hides_smbus = 1;
1234 }
1235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1236 switch (dev->subsystem_device) {
1237 case 0x8070: /* P4G8X Deluxe */
1238 asus_hides_smbus = 1;
1239 }
1240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1241 switch (dev->subsystem_device) {
1242 case 0x80c9: /* PU-DLS */
1243 asus_hides_smbus = 1;
1244 }
1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1246 switch (dev->subsystem_device) {
1247 case 0x1751: /* M2N notebook */
1248 case 0x1821: /* M5N notebook */
1249 case 0x1897: /* A6L notebook */
1250 asus_hides_smbus = 1;
1251 }
1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1253 switch (dev->subsystem_device) {
1254 case 0x184b: /* W1N notebook */
1255 case 0x186a: /* M6Ne notebook */
1256 asus_hides_smbus = 1;
1257 }
1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1259 switch (dev->subsystem_device) {
1260 case 0x80f2: /* P4P800-X */
1261 asus_hides_smbus = 1;
1262 }
1263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1264 switch (dev->subsystem_device) {
1265 case 0x1882: /* M6V notebook */
1266 case 0x1977: /* A6VA notebook */
1267 asus_hides_smbus = 1;
1268 }
1269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1271 switch (dev->subsystem_device) {
1272 case 0x088C: /* HP Compaq nc8000 */
1273 case 0x0890: /* HP Compaq nc6000 */
1274 asus_hides_smbus = 1;
1275 }
1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1277 switch (dev->subsystem_device) {
1278 case 0x12bc: /* HP D330L */
1279 case 0x12bd: /* HP D530 */
1280 case 0x006a: /* HP Compaq nx9500 */
1281 asus_hides_smbus = 1;
1282 }
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x12bf: /* HP xw4100 */
1286 asus_hides_smbus = 1;
1287 }
1288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1290 switch (dev->subsystem_device) {
1291 case 0xC00C: /* Samsung P35 notebook */
1292 asus_hides_smbus = 1;
1293 }
1294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1296 switch (dev->subsystem_device) {
1297 case 0x0058: /* Compaq Evo N620c */
1298 asus_hides_smbus = 1;
1299 }
1300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1301 switch (dev->subsystem_device) {
1302 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1303 /* Motherboard doesn't have Host bridge
1304 * subvendor/subdevice IDs, therefore checking
1305 * its on-board VGA controller */
1306 asus_hides_smbus = 1;
1307 }
1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1309 switch (dev->subsystem_device) {
1310 case 0x00b8: /* Compaq Evo D510 CMT */
1311 case 0x00b9: /* Compaq Evo D510 SFF */
1312 case 0x00ba: /* Compaq Evo D510 USDT */
1313 /* Motherboard doesn't have Host bridge
1314 * subvendor/subdevice IDs and on-board VGA
1315 * controller is disabled if an AGP card is
1316 * inserted, therefore checking USB UHCI
1317 * Controller #1 */
1318 asus_hides_smbus = 1;
1319 }
1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1321 switch (dev->subsystem_device) {
1322 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1323 /* Motherboard doesn't have host bridge
1324 * subvendor/subdevice IDs, therefore checking
1325 * its on-board VGA controller */
1326 asus_hides_smbus = 1;
1327 }
1328 }
1329 }
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1340
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1344
1345 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1346 {
1347 u16 val;
1348
1349 if (likely(!asus_hides_smbus))
1350 return;
1351
1352 pci_read_config_word(dev, 0xF2, &val);
1353 if (val & 0x8) {
1354 pci_write_config_word(dev, 0xF2, val & (~0x8));
1355 pci_read_config_word(dev, 0xF2, &val);
1356 if (val & 0x8)
1357 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1358 val);
1359 else
1360 pci_info(dev, "Enabled i801 SMBus device\n");
1361 }
1362 }
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1377
1378 /* It appears we just have one such device. If not, we have a warning */
1379 static void __iomem *asus_rcba_base;
1380 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1381 {
1382 u32 rcba;
1383
1384 if (likely(!asus_hides_smbus))
1385 return;
1386 WARN_ON(asus_rcba_base);
1387
1388 pci_read_config_dword(dev, 0xF0, &rcba);
1389 /* use bits 31:14, 16 kB aligned */
1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1391 if (asus_rcba_base == NULL)
1392 return;
1393 }
1394
1395 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1396 {
1397 u32 val;
1398
1399 if (likely(!asus_hides_smbus || !asus_rcba_base))
1400 return;
1401 /* read the Function Disable register, dword mode only */
1402 val = readl(asus_rcba_base + 0x3418);
1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1404 }
1405
1406 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1407 {
1408 if (likely(!asus_hides_smbus || !asus_rcba_base))
1409 return;
1410 iounmap(asus_rcba_base);
1411 asus_rcba_base = NULL;
1412 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1413 }
1414
1415 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1416 {
1417 asus_hides_smbus_lpc_ich6_suspend(dev);
1418 asus_hides_smbus_lpc_ich6_resume_early(dev);
1419 asus_hides_smbus_lpc_ich6_resume(dev);
1420 }
1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1422 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1425
1426 /*
1427 * SiS 96x south bridge: BIOS typically hides SMBus device...
1428 */
1429 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1430 {
1431 u8 val = 0;
1432 pci_read_config_byte(dev, 0x77, &val);
1433 if (val & 0x10) {
1434 pci_info(dev, "Enabling SiS 96x SMBus\n");
1435 pci_write_config_byte(dev, 0x77, val & ~0x10);
1436 }
1437 }
1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1442 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1446
1447 /*
1448 * ... This is further complicated by the fact that some SiS96x south
1449 * bridges pretend to be 85C503/5513 instead. In that case see if we
1450 * spotted a compatible north bridge to make sure.
1451 * (pci_find_device doesn't work yet)
1452 *
1453 * We can also enable the sis96x bit in the discovery register..
1454 */
1455 #define SIS_DETECT_REGISTER 0x40
1456
1457 static void quirk_sis_503(struct pci_dev *dev)
1458 {
1459 u8 reg;
1460 u16 devid;
1461
1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1467 return;
1468 }
1469
1470 /*
1471 * Ok, it now shows up as a 96x.. run the 96x quirk by
1472 * hand in case it has already been processed.
1473 * (depends on link order, which is apparently not guaranteed)
1474 */
1475 dev->device = devid;
1476 quirk_sis_96x_smbus(dev);
1477 }
1478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1479 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1480
1481
1482 /*
1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1484 * and MC97 modem controller are disabled when a second PCI soundcard is
1485 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1486 * -- bjd
1487 */
1488 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1489 {
1490 u8 val;
1491 int asus_hides_ac97 = 0;
1492
1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1494 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1495 asus_hides_ac97 = 1;
1496 }
1497
1498 if (!asus_hides_ac97)
1499 return;
1500
1501 pci_read_config_byte(dev, 0x50, &val);
1502 if (val & 0xc0) {
1503 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1504 pci_read_config_byte(dev, 0x50, &val);
1505 if (val & 0xc0)
1506 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1507 val);
1508 else
1509 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1510 }
1511 }
1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1514
1515 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1516
1517 /*
1518 * If we are using libata we can drive this chip properly but must
1519 * do this early on to make the additional device appear during
1520 * the PCI scanning.
1521 */
1522 static void quirk_jmicron_ata(struct pci_dev *pdev)
1523 {
1524 u32 conf1, conf5, class;
1525 u8 hdr;
1526
1527 /* Only poke fn 0 */
1528 if (PCI_FUNC(pdev->devfn))
1529 return;
1530
1531 pci_read_config_dword(pdev, 0x40, &conf1);
1532 pci_read_config_dword(pdev, 0x80, &conf5);
1533
1534 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1535 conf5 &= ~(1 << 24); /* Clear bit 24 */
1536
1537 switch (pdev->device) {
1538 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1539 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1540 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1541 /* The controller should be in single function ahci mode */
1542 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1543 break;
1544
1545 case PCI_DEVICE_ID_JMICRON_JMB365:
1546 case PCI_DEVICE_ID_JMICRON_JMB366:
1547 /* Redirect IDE second PATA port to the right spot */
1548 conf5 |= (1 << 24);
1549 /* Fall through */
1550 case PCI_DEVICE_ID_JMICRON_JMB361:
1551 case PCI_DEVICE_ID_JMICRON_JMB363:
1552 case PCI_DEVICE_ID_JMICRON_JMB369:
1553 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1554 /* Set the class codes correctly and then direct IDE 0 */
1555 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1556 break;
1557
1558 case PCI_DEVICE_ID_JMICRON_JMB368:
1559 /* The controller should be in single function IDE mode */
1560 conf1 |= 0x00C00000; /* Set 22, 23 */
1561 break;
1562 }
1563
1564 pci_write_config_dword(pdev, 0x40, conf1);
1565 pci_write_config_dword(pdev, 0x80, conf5);
1566
1567 /* Update pdev accordingly */
1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1569 pdev->hdr_type = hdr & 0x7f;
1570 pdev->multifunction = !!(hdr & 0x80);
1571
1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1573 pdev->class = class >> 8;
1574 }
1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1584 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1593
1594 #endif
1595
1596 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1597 {
1598 if (dev->multifunction) {
1599 device_disable_async_suspend(&dev->dev);
1600 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1601 }
1602 }
1603 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1604 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1607
1608 #ifdef CONFIG_X86_IO_APIC
1609 static void quirk_alder_ioapic(struct pci_dev *pdev)
1610 {
1611 int i;
1612
1613 if ((pdev->class >> 8) != 0xff00)
1614 return;
1615
1616 /* the first BAR is the location of the IO APIC...we must
1617 * not touch this (and it's already covered by the fixmap), so
1618 * forcibly insert it into the resource tree */
1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1620 insert_resource(&iomem_resource, &pdev->resource[0]);
1621
1622 /* The next five BARs all seem to be rubbish, so just clean
1623 * them out */
1624 for (i = 1; i < 6; i++)
1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1626 }
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1628 #endif
1629
1630 static void quirk_pcie_mch(struct pci_dev *pdev)
1631 {
1632 pdev->no_msi = 1;
1633 }
1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1637
1638 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1639
1640 /*
1641 * It's possible for the MSI to get corrupted if shpc and acpi
1642 * are used together on certain PXH-based systems.
1643 */
1644 static void quirk_pcie_pxh(struct pci_dev *dev)
1645 {
1646 dev->no_msi = 1;
1647 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1648 }
1649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1654
1655 /*
1656 * Some Intel PCI Express chipsets have trouble with downstream
1657 * device power management.
1658 */
1659 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1660 {
1661 pci_pm_d3_delay = 120;
1662 dev->no_d1d2 = 1;
1663 }
1664
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1686
1687 static void quirk_radeon_pm(struct pci_dev *dev)
1688 {
1689 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1690 dev->subsystem_device == 0x00e2) {
1691 if (dev->d3_delay < 20) {
1692 dev->d3_delay = 20;
1693 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
1694 dev->d3_delay);
1695 }
1696 }
1697 }
1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1699
1700 #ifdef CONFIG_X86_IO_APIC
1701 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1702 {
1703 noioapicreroute = 1;
1704 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1705
1706 return 0;
1707 }
1708
1709 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1710 /*
1711 * Systems to exclude from boot interrupt reroute quirks
1712 */
1713 {
1714 .callback = dmi_disable_ioapicreroute,
1715 .ident = "ASUSTek Computer INC. M2N-LR",
1716 .matches = {
1717 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1718 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1719 },
1720 },
1721 {}
1722 };
1723
1724 /*
1725 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1726 * remap the original interrupt in the linux kernel to the boot interrupt, so
1727 * that a PCI device's interrupt handler is installed on the boot interrupt
1728 * line instead.
1729 */
1730 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1731 {
1732 dmi_check_system(boot_interrupt_dmi_table);
1733 if (noioapicquirk || noioapicreroute)
1734 return;
1735
1736 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1737 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1738 dev->vendor, dev->device);
1739 }
1740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1748 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1749 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1754 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1755 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1756
1757 /*
1758 * On some chipsets we can disable the generation of legacy INTx boot
1759 * interrupts.
1760 */
1761
1762 /*
1763 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1764 * 300641-004US, section 5.7.3.
1765 */
1766 #define INTEL_6300_IOAPIC_ABAR 0x40
1767 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1768
1769 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1770 {
1771 u16 pci_config_word;
1772
1773 if (noioapicquirk)
1774 return;
1775
1776 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1777 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1778 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1779
1780 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1781 dev->vendor, dev->device);
1782 }
1783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1784 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1785
1786 /*
1787 * disable boot interrupts on HT-1000
1788 */
1789 #define BC_HT1000_FEATURE_REG 0x64
1790 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1791 #define BC_HT1000_MAP_IDX 0xC00
1792 #define BC_HT1000_MAP_DATA 0xC01
1793
1794 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1795 {
1796 u32 pci_config_dword;
1797 u8 irq;
1798
1799 if (noioapicquirk)
1800 return;
1801
1802 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1803 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1804 BC_HT1000_PIC_REGS_ENABLE);
1805
1806 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1807 outb(irq, BC_HT1000_MAP_IDX);
1808 outb(0x00, BC_HT1000_MAP_DATA);
1809 }
1810
1811 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1812
1813 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1814 dev->vendor, dev->device);
1815 }
1816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1817 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1818
1819 /*
1820 * disable boot interrupts on AMD and ATI chipsets
1821 */
1822 /*
1823 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1824 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1825 * (due to an erratum).
1826 */
1827 #define AMD_813X_MISC 0x40
1828 #define AMD_813X_NOIOAMODE (1<<0)
1829 #define AMD_813X_REV_B1 0x12
1830 #define AMD_813X_REV_B2 0x13
1831
1832 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1833 {
1834 u32 pci_config_dword;
1835
1836 if (noioapicquirk)
1837 return;
1838 if ((dev->revision == AMD_813X_REV_B1) ||
1839 (dev->revision == AMD_813X_REV_B2))
1840 return;
1841
1842 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1843 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1844 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1845
1846 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1847 dev->vendor, dev->device);
1848 }
1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1850 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1852 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1853
1854 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1855
1856 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1857 {
1858 u16 pci_config_word;
1859
1860 if (noioapicquirk)
1861 return;
1862
1863 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1864 if (!pci_config_word) {
1865 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1866 dev->vendor, dev->device);
1867 return;
1868 }
1869 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1870 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1871 dev->vendor, dev->device);
1872 }
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1874 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1875 #endif /* CONFIG_X86_IO_APIC */
1876
1877 /*
1878 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1879 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1880 * Re-allocate the region if needed...
1881 */
1882 static void quirk_tc86c001_ide(struct pci_dev *dev)
1883 {
1884 struct resource *r = &dev->resource[0];
1885
1886 if (r->start & 0x8) {
1887 r->flags |= IORESOURCE_UNSET;
1888 r->start = 0;
1889 r->end = 0xf;
1890 }
1891 }
1892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1893 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1894 quirk_tc86c001_ide);
1895
1896 /*
1897 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1898 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1899 * being read correctly if bit 7 of the base address is set.
1900 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1901 * Re-allocate the regions to a 256-byte boundary if necessary.
1902 */
1903 static void quirk_plx_pci9050(struct pci_dev *dev)
1904 {
1905 unsigned int bar;
1906
1907 /* Fixed in revision 2 (PCI 9052). */
1908 if (dev->revision >= 2)
1909 return;
1910 for (bar = 0; bar <= 1; bar++)
1911 if (pci_resource_len(dev, bar) == 0x80 &&
1912 (pci_resource_start(dev, bar) & 0x80)) {
1913 struct resource *r = &dev->resource[bar];
1914 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1915 bar);
1916 r->flags |= IORESOURCE_UNSET;
1917 r->start = 0;
1918 r->end = 0xff;
1919 }
1920 }
1921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1922 quirk_plx_pci9050);
1923 /*
1924 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1925 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1926 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1927 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1928 *
1929 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1930 * driver.
1931 */
1932 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1933 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1934
1935 static void quirk_netmos(struct pci_dev *dev)
1936 {
1937 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1938 unsigned int num_serial = dev->subsystem_device & 0xf;
1939
1940 /*
1941 * These Netmos parts are multiport serial devices with optional
1942 * parallel ports. Even when parallel ports are present, they
1943 * are identified as class SERIAL, which means the serial driver
1944 * will claim them. To prevent this, mark them as class OTHER.
1945 * These combo devices should be claimed by parport_serial.
1946 *
1947 * The subdevice ID is of the form 0x00PS, where <P> is the number
1948 * of parallel ports and <S> is the number of serial ports.
1949 */
1950 switch (dev->device) {
1951 case PCI_DEVICE_ID_NETMOS_9835:
1952 /* Well, this rule doesn't hold for the following 9835 device */
1953 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1954 dev->subsystem_device == 0x0299)
1955 return;
1956 case PCI_DEVICE_ID_NETMOS_9735:
1957 case PCI_DEVICE_ID_NETMOS_9745:
1958 case PCI_DEVICE_ID_NETMOS_9845:
1959 case PCI_DEVICE_ID_NETMOS_9855:
1960 if (num_parallel) {
1961 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1962 dev->device, num_parallel, num_serial);
1963 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1964 (dev->class & 0xff);
1965 }
1966 }
1967 }
1968 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1969 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1970
1971 static void quirk_e100_interrupt(struct pci_dev *dev)
1972 {
1973 u16 command, pmcsr;
1974 u8 __iomem *csr;
1975 u8 cmd_hi;
1976
1977 switch (dev->device) {
1978 /* PCI IDs taken from drivers/net/e100.c */
1979 case 0x1029:
1980 case 0x1030 ... 0x1034:
1981 case 0x1038 ... 0x103E:
1982 case 0x1050 ... 0x1057:
1983 case 0x1059:
1984 case 0x1064 ... 0x106B:
1985 case 0x1091 ... 0x1095:
1986 case 0x1209:
1987 case 0x1229:
1988 case 0x2449:
1989 case 0x2459:
1990 case 0x245D:
1991 case 0x27DC:
1992 break;
1993 default:
1994 return;
1995 }
1996
1997 /*
1998 * Some firmware hands off the e100 with interrupts enabled,
1999 * which can cause a flood of interrupts if packets are
2000 * received before the driver attaches to the device. So
2001 * disable all e100 interrupts here. The driver will
2002 * re-enable them when it's ready.
2003 */
2004 pci_read_config_word(dev, PCI_COMMAND, &command);
2005
2006 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2007 return;
2008
2009 /*
2010 * Check that the device is in the D0 power state. If it's not,
2011 * there is no point to look any further.
2012 */
2013 if (dev->pm_cap) {
2014 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2015 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2016 return;
2017 }
2018
2019 /* Convert from PCI bus to resource space. */
2020 csr = ioremap(pci_resource_start(dev, 0), 8);
2021 if (!csr) {
2022 pci_warn(dev, "Can't map e100 registers\n");
2023 return;
2024 }
2025
2026 cmd_hi = readb(csr + 3);
2027 if (cmd_hi == 0) {
2028 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2029 writeb(1, csr + 3);
2030 }
2031
2032 iounmap(csr);
2033 }
2034 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2035 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2036
2037 /*
2038 * The 82575 and 82598 may experience data corruption issues when transitioning
2039 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2040 */
2041 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2042 {
2043 pci_info(dev, "Disabling L0s\n");
2044 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2045 }
2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2060
2061 static void fixup_rev1_53c810(struct pci_dev *dev)
2062 {
2063 u32 class = dev->class;
2064
2065 /*
2066 * rev 1 ncr53c810 chips don't set the class at all which means
2067 * they don't get their resources remapped. Fix that here.
2068 */
2069 if (class)
2070 return;
2071
2072 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2073 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2074 class, dev->class);
2075 }
2076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2077
2078 /* Enable 1k I/O space granularity on the Intel P64H2 */
2079 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2080 {
2081 u16 en1k;
2082
2083 pci_read_config_word(dev, 0x40, &en1k);
2084
2085 if (en1k & 0x200) {
2086 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2087 dev->io_window_1k = 1;
2088 }
2089 }
2090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2091
2092 /* Under some circumstances, AER is not linked with extended capabilities.
2093 * Force it to be linked by setting the corresponding control bit in the
2094 * config space.
2095 */
2096 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2097 {
2098 uint8_t b;
2099 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2100 if (!(b & 0x20)) {
2101 pci_write_config_byte(dev, 0xf41, b | 0x20);
2102 pci_info(dev, "Linking AER extended capability\n");
2103 }
2104 }
2105 }
2106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2107 quirk_nvidia_ck804_pcie_aer_ext_cap);
2108 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2109 quirk_nvidia_ck804_pcie_aer_ext_cap);
2110
2111 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2112 {
2113 /*
2114 * Disable PCI Bus Parking and PCI Master read caching on CX700
2115 * which causes unspecified timing errors with a VT6212L on the PCI
2116 * bus leading to USB2.0 packet loss.
2117 *
2118 * This quirk is only enabled if a second (on the external PCI bus)
2119 * VT6212L is found -- the CX700 core itself also contains a USB
2120 * host controller with the same PCI ID as the VT6212L.
2121 */
2122
2123 /* Count VT6212L instances */
2124 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2125 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2126 uint8_t b;
2127
2128 /* p should contain the first (internal) VT6212L -- see if we have
2129 an external one by searching again */
2130 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2131 if (!p)
2132 return;
2133 pci_dev_put(p);
2134
2135 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2136 if (b & 0x40) {
2137 /* Turn off PCI Bus Parking */
2138 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2139
2140 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2141 }
2142 }
2143
2144 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2145 if (b != 0) {
2146 /* Turn off PCI Master read caching */
2147 pci_write_config_byte(dev, 0x72, 0x0);
2148
2149 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2150 pci_write_config_byte(dev, 0x75, 0x1);
2151
2152 /* Disable "Read FIFO Timer" */
2153 pci_write_config_byte(dev, 0x77, 0x0);
2154
2155 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2156 }
2157 }
2158 }
2159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2160
2161 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2162 {
2163 u32 rev;
2164
2165 pci_read_config_dword(dev, 0xf4, &rev);
2166
2167 /* Only CAP the MRRS if the device is a 5719 A0 */
2168 if (rev == 0x05719000) {
2169 int readrq = pcie_get_readrq(dev);
2170 if (readrq > 2048)
2171 pcie_set_readrq(dev, 2048);
2172 }
2173 }
2174
2175 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2176 PCI_DEVICE_ID_TIGON3_5719,
2177 quirk_brcm_5719_limit_mrrs);
2178
2179 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2180 static void quirk_paxc_bridge(struct pci_dev *pdev)
2181 {
2182 /* The PCI config space is shared with the PAXC root port and the first
2183 * Ethernet device. So, we need to workaround this by telling the PCI
2184 * code that the bridge is not an Ethernet device.
2185 */
2186 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2187 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2188
2189 /* MPSS is not being set properly (as it is currently 0). This is
2190 * because that area of the PCI config space is hard coded to zero, and
2191 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2192 * so that the MPS can be set to the real max value.
2193 */
2194 pdev->pcie_mpss = 2;
2195 }
2196 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2197 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2198 #endif
2199
2200 /* Originally in EDAC sources for i82875P:
2201 * Intel tells BIOS developers to hide device 6 which
2202 * configures the overflow device access containing
2203 * the DRBs - this is where we expose device 6.
2204 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2205 */
2206 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2207 {
2208 u8 reg;
2209
2210 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2211 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2212 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2213 }
2214 }
2215
2216 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2217 quirk_unhide_mch_dev6);
2218 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2219 quirk_unhide_mch_dev6);
2220
2221 #ifdef CONFIG_PCI_MSI
2222 /* Some chipsets do not support MSI. We cannot easily rely on setting
2223 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2224 * some other buses controlled by the chipset even if Linux is not
2225 * aware of it. Instead of setting the flag on all buses in the
2226 * machine, simply disable MSI globally.
2227 */
2228 static void quirk_disable_all_msi(struct pci_dev *dev)
2229 {
2230 pci_no_msi();
2231 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2232 }
2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2241
2242 /* Disable MSI on chipsets that are known to not support it */
2243 static void quirk_disable_msi(struct pci_dev *dev)
2244 {
2245 if (dev->subordinate) {
2246 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2247 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2248 }
2249 }
2250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2253
2254 /*
2255 * The APC bridge device in AMD 780 family northbridges has some random
2256 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2257 * we use the possible vendor/device IDs of the host bridge for the
2258 * declared quirk, and search for the APC bridge by slot number.
2259 */
2260 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2261 {
2262 struct pci_dev *apc_bridge;
2263
2264 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2265 if (apc_bridge) {
2266 if (apc_bridge->device == 0x9602)
2267 quirk_disable_msi(apc_bridge);
2268 pci_dev_put(apc_bridge);
2269 }
2270 }
2271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2273
2274 /* Go through the list of Hypertransport capabilities and
2275 * return 1 if a HT MSI capability is found and enabled */
2276 static int msi_ht_cap_enabled(struct pci_dev *dev)
2277 {
2278 int pos, ttl = PCI_FIND_CAP_TTL;
2279
2280 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2281 while (pos && ttl--) {
2282 u8 flags;
2283
2284 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2285 &flags) == 0) {
2286 pci_info(dev, "Found %s HT MSI Mapping\n",
2287 flags & HT_MSI_FLAGS_ENABLE ?
2288 "enabled" : "disabled");
2289 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2290 }
2291
2292 pos = pci_find_next_ht_capability(dev, pos,
2293 HT_CAPTYPE_MSI_MAPPING);
2294 }
2295 return 0;
2296 }
2297
2298 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2299 static void quirk_msi_ht_cap(struct pci_dev *dev)
2300 {
2301 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2302 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2303 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2304 }
2305 }
2306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2307 quirk_msi_ht_cap);
2308
2309 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2310 * MSI are supported if the MSI capability set in any of these mappings.
2311 */
2312 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2313 {
2314 struct pci_dev *pdev;
2315
2316 if (!dev->subordinate)
2317 return;
2318
2319 /* check HT MSI cap on this chipset and the root one.
2320 * a single one having MSI is enough to be sure that MSI are supported.
2321 */
2322 pdev = pci_get_slot(dev->bus, 0);
2323 if (!pdev)
2324 return;
2325 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2326 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2327 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2328 }
2329 pci_dev_put(pdev);
2330 }
2331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2332 quirk_nvidia_ck804_msi_ht_cap);
2333
2334 /* Force enable MSI mapping capability on HT bridges */
2335 static void ht_enable_msi_mapping(struct pci_dev *dev)
2336 {
2337 int pos, ttl = PCI_FIND_CAP_TTL;
2338
2339 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2340 while (pos && ttl--) {
2341 u8 flags;
2342
2343 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2344 &flags) == 0) {
2345 pci_info(dev, "Enabling HT MSI Mapping\n");
2346
2347 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2348 flags | HT_MSI_FLAGS_ENABLE);
2349 }
2350 pos = pci_find_next_ht_capability(dev, pos,
2351 HT_CAPTYPE_MSI_MAPPING);
2352 }
2353 }
2354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2355 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2356 ht_enable_msi_mapping);
2357
2358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2359 ht_enable_msi_mapping);
2360
2361 /* The P5N32-SLI motherboards from Asus have a problem with msi
2362 * for the MCP55 NIC. It is not yet determined whether the msi problem
2363 * also affects other devices. As for now, turn off msi for this device.
2364 */
2365 static void nvenet_msi_disable(struct pci_dev *dev)
2366 {
2367 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2368
2369 if (board_name &&
2370 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2371 strstr(board_name, "P5N32-E SLI"))) {
2372 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2373 dev->no_msi = 1;
2374 }
2375 }
2376 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2377 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2378 nvenet_msi_disable);
2379
2380 /*
2381 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2382 * config register. This register controls the routing of legacy
2383 * interrupts from devices that route through the MCP55. If this register
2384 * is misprogrammed, interrupts are only sent to the BSP, unlike
2385 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2386 * having this register set properly prevents kdump from booting up
2387 * properly, so let's make sure that we have it set correctly.
2388 * Note that this is an undocumented register.
2389 */
2390 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2391 {
2392 u32 cfg;
2393
2394 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2395 return;
2396
2397 pci_read_config_dword(dev, 0x74, &cfg);
2398
2399 if (cfg & ((1 << 2) | (1 << 15))) {
2400 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2401 cfg &= ~((1 << 2) | (1 << 15));
2402 pci_write_config_dword(dev, 0x74, cfg);
2403 }
2404 }
2405
2406 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2407 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2408 nvbridge_check_legacy_irq_routing);
2409
2410 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2411 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2412 nvbridge_check_legacy_irq_routing);
2413
2414 static int ht_check_msi_mapping(struct pci_dev *dev)
2415 {
2416 int pos, ttl = PCI_FIND_CAP_TTL;
2417 int found = 0;
2418
2419 /* check if there is HT MSI cap or enabled on this device */
2420 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2421 while (pos && ttl--) {
2422 u8 flags;
2423
2424 if (found < 1)
2425 found = 1;
2426 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2427 &flags) == 0) {
2428 if (flags & HT_MSI_FLAGS_ENABLE) {
2429 if (found < 2) {
2430 found = 2;
2431 break;
2432 }
2433 }
2434 }
2435 pos = pci_find_next_ht_capability(dev, pos,
2436 HT_CAPTYPE_MSI_MAPPING);
2437 }
2438
2439 return found;
2440 }
2441
2442 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2443 {
2444 struct pci_dev *dev;
2445 int pos;
2446 int i, dev_no;
2447 int found = 0;
2448
2449 dev_no = host_bridge->devfn >> 3;
2450 for (i = dev_no + 1; i < 0x20; i++) {
2451 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2452 if (!dev)
2453 continue;
2454
2455 /* found next host bridge ?*/
2456 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2457 if (pos != 0) {
2458 pci_dev_put(dev);
2459 break;
2460 }
2461
2462 if (ht_check_msi_mapping(dev)) {
2463 found = 1;
2464 pci_dev_put(dev);
2465 break;
2466 }
2467 pci_dev_put(dev);
2468 }
2469
2470 return found;
2471 }
2472
2473 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2474 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2475
2476 static int is_end_of_ht_chain(struct pci_dev *dev)
2477 {
2478 int pos, ctrl_off;
2479 int end = 0;
2480 u16 flags, ctrl;
2481
2482 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2483
2484 if (!pos)
2485 goto out;
2486
2487 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2488
2489 ctrl_off = ((flags >> 10) & 1) ?
2490 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2491 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2492
2493 if (ctrl & (1 << 6))
2494 end = 1;
2495
2496 out:
2497 return end;
2498 }
2499
2500 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2501 {
2502 struct pci_dev *host_bridge;
2503 int pos;
2504 int i, dev_no;
2505 int found = 0;
2506
2507 dev_no = dev->devfn >> 3;
2508 for (i = dev_no; i >= 0; i--) {
2509 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2510 if (!host_bridge)
2511 continue;
2512
2513 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2514 if (pos != 0) {
2515 found = 1;
2516 break;
2517 }
2518 pci_dev_put(host_bridge);
2519 }
2520
2521 if (!found)
2522 return;
2523
2524 /* don't enable end_device/host_bridge with leaf directly here */
2525 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2526 host_bridge_with_leaf(host_bridge))
2527 goto out;
2528
2529 /* root did that ! */
2530 if (msi_ht_cap_enabled(host_bridge))
2531 goto out;
2532
2533 ht_enable_msi_mapping(dev);
2534
2535 out:
2536 pci_dev_put(host_bridge);
2537 }
2538
2539 static void ht_disable_msi_mapping(struct pci_dev *dev)
2540 {
2541 int pos, ttl = PCI_FIND_CAP_TTL;
2542
2543 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2544 while (pos && ttl--) {
2545 u8 flags;
2546
2547 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2548 &flags) == 0) {
2549 pci_info(dev, "Disabling HT MSI Mapping\n");
2550
2551 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2552 flags & ~HT_MSI_FLAGS_ENABLE);
2553 }
2554 pos = pci_find_next_ht_capability(dev, pos,
2555 HT_CAPTYPE_MSI_MAPPING);
2556 }
2557 }
2558
2559 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2560 {
2561 struct pci_dev *host_bridge;
2562 int pos;
2563 int found;
2564
2565 if (!pci_msi_enabled())
2566 return;
2567
2568 /* check if there is HT MSI cap or enabled on this device */
2569 found = ht_check_msi_mapping(dev);
2570
2571 /* no HT MSI CAP */
2572 if (found == 0)
2573 return;
2574
2575 /*
2576 * HT MSI mapping should be disabled on devices that are below
2577 * a non-Hypertransport host bridge. Locate the host bridge...
2578 */
2579 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2580 PCI_DEVFN(0, 0));
2581 if (host_bridge == NULL) {
2582 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2583 return;
2584 }
2585
2586 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2587 if (pos != 0) {
2588 /* Host bridge is to HT */
2589 if (found == 1) {
2590 /* it is not enabled, try to enable it */
2591 if (all)
2592 ht_enable_msi_mapping(dev);
2593 else
2594 nv_ht_enable_msi_mapping(dev);
2595 }
2596 goto out;
2597 }
2598
2599 /* HT MSI is not enabled */
2600 if (found == 1)
2601 goto out;
2602
2603 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2604 ht_disable_msi_mapping(dev);
2605
2606 out:
2607 pci_dev_put(host_bridge);
2608 }
2609
2610 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2611 {
2612 return __nv_msi_ht_cap_quirk(dev, 1);
2613 }
2614
2615 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2616 {
2617 return __nv_msi_ht_cap_quirk(dev, 0);
2618 }
2619
2620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2621 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2622
2623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2624 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2625
2626 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2627 {
2628 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2629 }
2630 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2631 {
2632 struct pci_dev *p;
2633
2634 /* SB700 MSI issue will be fixed at HW level from revision A21,
2635 * we need check PCI REVISION ID of SMBus controller to get SB700
2636 * revision.
2637 */
2638 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2639 NULL);
2640 if (!p)
2641 return;
2642
2643 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2644 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2645 pci_dev_put(p);
2646 }
2647 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2648 {
2649 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2650 if (dev->revision < 0x18) {
2651 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2652 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2653 }
2654 }
2655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2656 PCI_DEVICE_ID_TIGON3_5780,
2657 quirk_msi_intx_disable_bug);
2658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2659 PCI_DEVICE_ID_TIGON3_5780S,
2660 quirk_msi_intx_disable_bug);
2661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2662 PCI_DEVICE_ID_TIGON3_5714,
2663 quirk_msi_intx_disable_bug);
2664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2665 PCI_DEVICE_ID_TIGON3_5714S,
2666 quirk_msi_intx_disable_bug);
2667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2668 PCI_DEVICE_ID_TIGON3_5715,
2669 quirk_msi_intx_disable_bug);
2670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2671 PCI_DEVICE_ID_TIGON3_5715S,
2672 quirk_msi_intx_disable_bug);
2673
2674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2675 quirk_msi_intx_disable_ati_bug);
2676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2677 quirk_msi_intx_disable_ati_bug);
2678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2679 quirk_msi_intx_disable_ati_bug);
2680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2681 quirk_msi_intx_disable_ati_bug);
2682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2683 quirk_msi_intx_disable_ati_bug);
2684
2685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2686 quirk_msi_intx_disable_bug);
2687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2688 quirk_msi_intx_disable_bug);
2689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2690 quirk_msi_intx_disable_bug);
2691
2692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2693 quirk_msi_intx_disable_bug);
2694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2695 quirk_msi_intx_disable_bug);
2696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2697 quirk_msi_intx_disable_bug);
2698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2699 quirk_msi_intx_disable_bug);
2700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2701 quirk_msi_intx_disable_bug);
2702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2703 quirk_msi_intx_disable_bug);
2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2705 quirk_msi_intx_disable_qca_bug);
2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2707 quirk_msi_intx_disable_qca_bug);
2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2709 quirk_msi_intx_disable_qca_bug);
2710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2711 quirk_msi_intx_disable_qca_bug);
2712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2713 quirk_msi_intx_disable_qca_bug);
2714 #endif /* CONFIG_PCI_MSI */
2715
2716 /* Allow manual resource allocation for PCI hotplug bridges
2717 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2718 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2719 * kernel fails to allocate resources when hotplug device is
2720 * inserted and PCI bus is rescanned.
2721 */
2722 static void quirk_hotplug_bridge(struct pci_dev *dev)
2723 {
2724 dev->is_hotplug_bridge = 1;
2725 }
2726
2727 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2728
2729 /*
2730 * This is a quirk for the Ricoh MMC controller found as a part of
2731 * some mulifunction chips.
2732
2733 * This is very similar and based on the ricoh_mmc driver written by
2734 * Philip Langdale. Thank you for these magic sequences.
2735 *
2736 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2737 * and one or both of cardbus or firewire.
2738 *
2739 * It happens that they implement SD and MMC
2740 * support as separate controllers (and PCI functions). The linux SDHCI
2741 * driver supports MMC cards but the chip detects MMC cards in hardware
2742 * and directs them to the MMC controller - so the SDHCI driver never sees
2743 * them.
2744 *
2745 * To get around this, we must disable the useless MMC controller.
2746 * At that point, the SDHCI controller will start seeing them
2747 * It seems to be the case that the relevant PCI registers to deactivate the
2748 * MMC controller live on PCI function 0, which might be the cardbus controller
2749 * or the firewire controller, depending on the particular chip in question
2750 *
2751 * This has to be done early, because as soon as we disable the MMC controller
2752 * other pci functions shift up one level, e.g. function #2 becomes function
2753 * #1, and this will confuse the pci core.
2754 */
2755
2756 #ifdef CONFIG_MMC_RICOH_MMC
2757 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2758 {
2759 /* disable via cardbus interface */
2760 u8 write_enable;
2761 u8 write_target;
2762 u8 disable;
2763
2764 /* disable must be done via function #0 */
2765 if (PCI_FUNC(dev->devfn))
2766 return;
2767
2768 pci_read_config_byte(dev, 0xB7, &disable);
2769 if (disable & 0x02)
2770 return;
2771
2772 pci_read_config_byte(dev, 0x8E, &write_enable);
2773 pci_write_config_byte(dev, 0x8E, 0xAA);
2774 pci_read_config_byte(dev, 0x8D, &write_target);
2775 pci_write_config_byte(dev, 0x8D, 0xB7);
2776 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2777 pci_write_config_byte(dev, 0x8E, write_enable);
2778 pci_write_config_byte(dev, 0x8D, write_target);
2779
2780 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2781 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2782 }
2783 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2784 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2785
2786 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2787 {
2788 /* disable via firewire interface */
2789 u8 write_enable;
2790 u8 disable;
2791
2792 /* disable must be done via function #0 */
2793 if (PCI_FUNC(dev->devfn))
2794 return;
2795 /*
2796 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2797 * certain types of SD/MMC cards. Lowering the SD base
2798 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2799 *
2800 * 0x150 - SD2.0 mode enable for changing base clock
2801 * frequency to 50Mhz
2802 * 0xe1 - Base clock frequency
2803 * 0x32 - 50Mhz new clock frequency
2804 * 0xf9 - Key register for 0x150
2805 * 0xfc - key register for 0xe1
2806 */
2807 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2808 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2809 pci_write_config_byte(dev, 0xf9, 0xfc);
2810 pci_write_config_byte(dev, 0x150, 0x10);
2811 pci_write_config_byte(dev, 0xf9, 0x00);
2812 pci_write_config_byte(dev, 0xfc, 0x01);
2813 pci_write_config_byte(dev, 0xe1, 0x32);
2814 pci_write_config_byte(dev, 0xfc, 0x00);
2815
2816 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
2817 }
2818
2819 pci_read_config_byte(dev, 0xCB, &disable);
2820
2821 if (disable & 0x02)
2822 return;
2823
2824 pci_read_config_byte(dev, 0xCA, &write_enable);
2825 pci_write_config_byte(dev, 0xCA, 0x57);
2826 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2827 pci_write_config_byte(dev, 0xCA, write_enable);
2828
2829 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2830 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2831
2832 }
2833 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2834 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2835 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2836 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2837 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2838 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2839 #endif /*CONFIG_MMC_RICOH_MMC*/
2840
2841 #ifdef CONFIG_DMAR_TABLE
2842 #define VTUNCERRMSK_REG 0x1ac
2843 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2844 /*
2845 * This is a quirk for masking vt-d spec defined errors to platform error
2846 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2847 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2848 * on the RAS config settings of the platform) when a vt-d fault happens.
2849 * The resulting SMI caused the system to hang.
2850 *
2851 * VT-d spec related errors are already handled by the VT-d OS code, so no
2852 * need to report the same error through other channels.
2853 */
2854 static void vtd_mask_spec_errors(struct pci_dev *dev)
2855 {
2856 u32 word;
2857
2858 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2859 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2860 }
2861 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2862 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2863 #endif
2864
2865 static void fixup_ti816x_class(struct pci_dev *dev)
2866 {
2867 u32 class = dev->class;
2868
2869 /* TI 816x devices do not have class code set when in PCIe boot mode */
2870 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2871 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
2872 class, dev->class);
2873 }
2874 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2875 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2876
2877 /* Some PCIe devices do not work reliably with the claimed maximum
2878 * payload size supported.
2879 */
2880 static void fixup_mpss_256(struct pci_dev *dev)
2881 {
2882 dev->pcie_mpss = 1; /* 256 bytes */
2883 }
2884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2885 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2887 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2889 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2890
2891 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2892 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2893 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2894 * until all of the devices are discovered and buses walked, read completion
2895 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2896 * it is possible to hotplug a device with MPS of 256B.
2897 */
2898 static void quirk_intel_mc_errata(struct pci_dev *dev)
2899 {
2900 int err;
2901 u16 rcc;
2902
2903 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2904 pcie_bus_config == PCIE_BUS_DEFAULT)
2905 return;
2906
2907 /* Intel errata specifies bits to change but does not say what they are.
2908 * Keeping them magical until such time as the registers and values can
2909 * be explained.
2910 */
2911 err = pci_read_config_word(dev, 0x48, &rcc);
2912 if (err) {
2913 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
2914 return;
2915 }
2916
2917 if (!(rcc & (1 << 10)))
2918 return;
2919
2920 rcc &= ~(1 << 10);
2921
2922 err = pci_write_config_word(dev, 0x48, rcc);
2923 if (err) {
2924 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
2925 return;
2926 }
2927
2928 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2929 }
2930 /* Intel 5000 series memory controllers and ports 2-7 */
2931 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2945 /* Intel 5100 series memory controllers and ports 2-7 */
2946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2951 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2953 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2954 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2955 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2956 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2957
2958
2959 /*
2960 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2961 * work around this, query the size it should be configured to by the device and
2962 * modify the resource end to correspond to this new size.
2963 */
2964 static void quirk_intel_ntb(struct pci_dev *dev)
2965 {
2966 int rc;
2967 u8 val;
2968
2969 rc = pci_read_config_byte(dev, 0x00D0, &val);
2970 if (rc)
2971 return;
2972
2973 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2974
2975 rc = pci_read_config_byte(dev, 0x00D1, &val);
2976 if (rc)
2977 return;
2978
2979 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2980 }
2981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2983
2984 static ktime_t fixup_debug_start(struct pci_dev *dev,
2985 void (*fn)(struct pci_dev *dev))
2986 {
2987 if (initcall_debug)
2988 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current));
2989
2990 return ktime_get();
2991 }
2992
2993 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2994 void (*fn)(struct pci_dev *dev))
2995 {
2996 ktime_t delta, rettime;
2997 unsigned long long duration;
2998
2999 rettime = ktime_get();
3000 delta = ktime_sub(rettime, calltime);
3001 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3002 if (initcall_debug || duration > 10000)
3003 pci_info(dev, "%pF took %lld usecs\n", fn, duration);
3004 }
3005
3006 /*
3007 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3008 * even though no one is handling them (f.e. i915 driver is never loaded).
3009 * Additionally the interrupt destination is not set up properly
3010 * and the interrupt ends up -somewhere-.
3011 *
3012 * These spurious interrupts are "sticky" and the kernel disables
3013 * the (shared) interrupt line after 100.000+ generated interrupts.
3014 *
3015 * Fix it by disabling the still enabled interrupts.
3016 * This resolves crashes often seen on monitor unplug.
3017 */
3018 #define I915_DEIER_REG 0x4400c
3019 static void disable_igfx_irq(struct pci_dev *dev)
3020 {
3021 void __iomem *regs = pci_iomap(dev, 0, 0);
3022 if (regs == NULL) {
3023 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3024 return;
3025 }
3026
3027 /* Check if any interrupt line is still enabled */
3028 if (readl(regs + I915_DEIER_REG) != 0) {
3029 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3030
3031 writel(0, regs + I915_DEIER_REG);
3032 }
3033
3034 pci_iounmap(dev, regs);
3035 }
3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3039
3040 /*
3041 * PCI devices which are on Intel chips can skip the 10ms delay
3042 * before entering D3 mode.
3043 */
3044 static void quirk_remove_d3_delay(struct pci_dev *dev)
3045 {
3046 dev->d3_delay = 0;
3047 }
3048 /* C600 Series devices do not need 10ms d3_delay */
3049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3052 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3064 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3074
3075 /*
3076 * Some devices may pass our check in pci_intx_mask_supported() if
3077 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3078 * support this feature.
3079 */
3080 static void quirk_broken_intx_masking(struct pci_dev *dev)
3081 {
3082 dev->broken_intx_masking = 1;
3083 }
3084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3085 quirk_broken_intx_masking);
3086 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3087 quirk_broken_intx_masking);
3088 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3089 quirk_broken_intx_masking);
3090
3091 /*
3092 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3093 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3094 *
3095 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3096 */
3097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3098 quirk_broken_intx_masking);
3099
3100 /*
3101 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3102 * DisINTx can be set but the interrupt status bit is non-functional.
3103 */
3104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3105 quirk_broken_intx_masking);
3106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3107 quirk_broken_intx_masking);
3108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3109 quirk_broken_intx_masking);
3110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3111 quirk_broken_intx_masking);
3112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3113 quirk_broken_intx_masking);
3114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3115 quirk_broken_intx_masking);
3116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3117 quirk_broken_intx_masking);
3118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3119 quirk_broken_intx_masking);
3120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3121 quirk_broken_intx_masking);
3122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3123 quirk_broken_intx_masking);
3124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3125 quirk_broken_intx_masking);
3126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3127 quirk_broken_intx_masking);
3128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3129 quirk_broken_intx_masking);
3130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3131 quirk_broken_intx_masking);
3132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3133 quirk_broken_intx_masking);
3134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3135 quirk_broken_intx_masking);
3136
3137 static u16 mellanox_broken_intx_devs[] = {
3138 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3139 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3140 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3141 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3142 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3143 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3144 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3145 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3146 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3147 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3148 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3149 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3150 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3151 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3152 };
3153
3154 #define CONNECTX_4_CURR_MAX_MINOR 99
3155 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3156
3157 /*
3158 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3159 * If so, don't mark it as broken.
3160 * FW minor > 99 means older FW version format and no INTx masking support.
3161 * FW minor < 14 means new FW version format and no INTx masking support.
3162 */
3163 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3164 {
3165 __be32 __iomem *fw_ver;
3166 u16 fw_major;
3167 u16 fw_minor;
3168 u16 fw_subminor;
3169 u32 fw_maj_min;
3170 u32 fw_sub_min;
3171 int i;
3172
3173 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3174 if (pdev->device == mellanox_broken_intx_devs[i]) {
3175 pdev->broken_intx_masking = 1;
3176 return;
3177 }
3178 }
3179
3180 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3181 * support so shouldn't be checked further
3182 */
3183 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3184 return;
3185
3186 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3187 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3188 return;
3189
3190 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3191 if (pci_enable_device_mem(pdev)) {
3192 pci_warn(pdev, "Can't enable device memory\n");
3193 return;
3194 }
3195
3196 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3197 if (!fw_ver) {
3198 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3199 goto out;
3200 }
3201
3202 /* Reading from resource space should be 32b aligned */
3203 fw_maj_min = ioread32be(fw_ver);
3204 fw_sub_min = ioread32be(fw_ver + 1);
3205 fw_major = fw_maj_min & 0xffff;
3206 fw_minor = fw_maj_min >> 16;
3207 fw_subminor = fw_sub_min & 0xffff;
3208 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3209 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3210 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3211 fw_major, fw_minor, fw_subminor, pdev->device ==
3212 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3213 pdev->broken_intx_masking = 1;
3214 }
3215
3216 iounmap(fw_ver);
3217
3218 out:
3219 pci_disable_device(pdev);
3220 }
3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3222 mellanox_check_broken_intx_masking);
3223
3224 static void quirk_no_bus_reset(struct pci_dev *dev)
3225 {
3226 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3227 }
3228
3229 /*
3230 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3231 * The device will throw a Link Down error on AER-capable systems and
3232 * regardless of AER, config space of the device is never accessible again
3233 * and typically causes the system to hang or reset when access is attempted.
3234 * http://www.spinics.net/lists/linux-pci/msg34797.html
3235 */
3236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3240
3241 /*
3242 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3243 * reset when used with certain child devices. After the reset, config
3244 * accesses to the child may fail.
3245 */
3246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3247
3248 static void quirk_no_pm_reset(struct pci_dev *dev)
3249 {
3250 /*
3251 * We can't do a bus reset on root bus devices, but an ineffective
3252 * PM reset may be better than nothing.
3253 */
3254 if (!pci_is_root_bus(dev->bus))
3255 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3256 }
3257
3258 /*
3259 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3260 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3261 * to have no effect on the device: it retains the framebuffer contents and
3262 * monitor sync. Advertising this support makes other layers, like VFIO,
3263 * assume pci_reset_function() is viable for this device. Mark it as
3264 * unavailable to skip it when testing reset methods.
3265 */
3266 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3267 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3268
3269 /*
3270 * Thunderbolt controllers with broken MSI hotplug signaling:
3271 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3272 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3273 */
3274 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3275 {
3276 if (pdev->is_hotplug_bridge &&
3277 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3278 pdev->revision <= 1))
3279 pdev->no_msi = 1;
3280 }
3281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3282 quirk_thunderbolt_hotplug_msi);
3283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3284 quirk_thunderbolt_hotplug_msi);
3285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3286 quirk_thunderbolt_hotplug_msi);
3287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3288 quirk_thunderbolt_hotplug_msi);
3289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3290 quirk_thunderbolt_hotplug_msi);
3291
3292 #ifdef CONFIG_ACPI
3293 /*
3294 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3295 *
3296 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3297 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3298 * be present after resume if a device was plugged in before suspend.
3299 *
3300 * The thunderbolt controller consists of a pcie switch with downstream
3301 * bridges leading to the NHI and to the tunnel pci bridges.
3302 *
3303 * This quirk cuts power to the whole chip. Therefore we have to apply it
3304 * during suspend_noirq of the upstream bridge.
3305 *
3306 * Power is automagically restored before resume. No action is needed.
3307 */
3308 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3309 {
3310 acpi_handle bridge, SXIO, SXFP, SXLV;
3311
3312 if (!x86_apple_machine)
3313 return;
3314 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3315 return;
3316 bridge = ACPI_HANDLE(&dev->dev);
3317 if (!bridge)
3318 return;
3319 /*
3320 * SXIO and SXLV are present only on machines requiring this quirk.
3321 * TB bridges in external devices might have the same device id as those
3322 * on the host, but they will not have the associated ACPI methods. This
3323 * implicitly checks that we are at the right bridge.
3324 */
3325 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3326 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3327 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3328 return;
3329 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n");
3330
3331 /* magic sequence */
3332 acpi_execute_simple_method(SXIO, NULL, 1);
3333 acpi_execute_simple_method(SXFP, NULL, 0);
3334 msleep(300);
3335 acpi_execute_simple_method(SXLV, NULL, 0);
3336 acpi_execute_simple_method(SXIO, NULL, 0);
3337 acpi_execute_simple_method(SXLV, NULL, 0);
3338 }
3339 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3340 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3341 quirk_apple_poweroff_thunderbolt);
3342
3343 /*
3344 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3345 *
3346 * During suspend the thunderbolt controller is reset and all pci
3347 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3348 * during resume. We have to manually wait for the NHI since there is
3349 * no parent child relationship between the NHI and the tunneled
3350 * bridges.
3351 */
3352 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3353 {
3354 struct pci_dev *sibling = NULL;
3355 struct pci_dev *nhi = NULL;
3356
3357 if (!x86_apple_machine)
3358 return;
3359 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3360 return;
3361 /*
3362 * Find the NHI and confirm that we are a bridge on the tb host
3363 * controller and not on a tb endpoint.
3364 */
3365 sibling = pci_get_slot(dev->bus, 0x0);
3366 if (sibling == dev)
3367 goto out; /* we are the downstream bridge to the NHI */
3368 if (!sibling || !sibling->subordinate)
3369 goto out;
3370 nhi = pci_get_slot(sibling->subordinate, 0x0);
3371 if (!nhi)
3372 goto out;
3373 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3374 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3375 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3376 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3377 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3378 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3379 goto out;
3380 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3381 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3382 out:
3383 pci_dev_put(nhi);
3384 pci_dev_put(sibling);
3385 }
3386 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3387 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3388 quirk_apple_wait_for_thunderbolt);
3389 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3390 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3391 quirk_apple_wait_for_thunderbolt);
3392 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3393 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3394 quirk_apple_wait_for_thunderbolt);
3395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3396 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3397 quirk_apple_wait_for_thunderbolt);
3398 #endif
3399
3400 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3401 struct pci_fixup *end)
3402 {
3403 ktime_t calltime;
3404
3405 for (; f < end; f++)
3406 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3407 f->class == (u32) PCI_ANY_ID) &&
3408 (f->vendor == dev->vendor ||
3409 f->vendor == (u16) PCI_ANY_ID) &&
3410 (f->device == dev->device ||
3411 f->device == (u16) PCI_ANY_ID)) {
3412 calltime = fixup_debug_start(dev, f->hook);
3413 f->hook(dev);
3414 fixup_debug_report(dev, calltime, f->hook);
3415 }
3416 }
3417
3418 extern struct pci_fixup __start_pci_fixups_early[];
3419 extern struct pci_fixup __end_pci_fixups_early[];
3420 extern struct pci_fixup __start_pci_fixups_header[];
3421 extern struct pci_fixup __end_pci_fixups_header[];
3422 extern struct pci_fixup __start_pci_fixups_final[];
3423 extern struct pci_fixup __end_pci_fixups_final[];
3424 extern struct pci_fixup __start_pci_fixups_enable[];
3425 extern struct pci_fixup __end_pci_fixups_enable[];
3426 extern struct pci_fixup __start_pci_fixups_resume[];
3427 extern struct pci_fixup __end_pci_fixups_resume[];
3428 extern struct pci_fixup __start_pci_fixups_resume_early[];
3429 extern struct pci_fixup __end_pci_fixups_resume_early[];
3430 extern struct pci_fixup __start_pci_fixups_suspend[];
3431 extern struct pci_fixup __end_pci_fixups_suspend[];
3432 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3433 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3434
3435 static bool pci_apply_fixup_final_quirks;
3436
3437 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3438 {
3439 struct pci_fixup *start, *end;
3440
3441 switch (pass) {
3442 case pci_fixup_early:
3443 start = __start_pci_fixups_early;
3444 end = __end_pci_fixups_early;
3445 break;
3446
3447 case pci_fixup_header:
3448 start = __start_pci_fixups_header;
3449 end = __end_pci_fixups_header;
3450 break;
3451
3452 case pci_fixup_final:
3453 if (!pci_apply_fixup_final_quirks)
3454 return;
3455 start = __start_pci_fixups_final;
3456 end = __end_pci_fixups_final;
3457 break;
3458
3459 case pci_fixup_enable:
3460 start = __start_pci_fixups_enable;
3461 end = __end_pci_fixups_enable;
3462 break;
3463
3464 case pci_fixup_resume:
3465 start = __start_pci_fixups_resume;
3466 end = __end_pci_fixups_resume;
3467 break;
3468
3469 case pci_fixup_resume_early:
3470 start = __start_pci_fixups_resume_early;
3471 end = __end_pci_fixups_resume_early;
3472 break;
3473
3474 case pci_fixup_suspend:
3475 start = __start_pci_fixups_suspend;
3476 end = __end_pci_fixups_suspend;
3477 break;
3478
3479 case pci_fixup_suspend_late:
3480 start = __start_pci_fixups_suspend_late;
3481 end = __end_pci_fixups_suspend_late;
3482 break;
3483
3484 default:
3485 /* stupid compiler warning, you would think with an enum... */
3486 return;
3487 }
3488 pci_do_fixups(dev, start, end);
3489 }
3490 EXPORT_SYMBOL(pci_fixup_device);
3491
3492
3493 static int __init pci_apply_final_quirks(void)
3494 {
3495 struct pci_dev *dev = NULL;
3496 u8 cls = 0;
3497 u8 tmp;
3498
3499 if (pci_cache_line_size)
3500 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3501 pci_cache_line_size << 2);
3502
3503 pci_apply_fixup_final_quirks = true;
3504 for_each_pci_dev(dev) {
3505 pci_fixup_device(pci_fixup_final, dev);
3506 /*
3507 * If arch hasn't set it explicitly yet, use the CLS
3508 * value shared by all PCI devices. If there's a
3509 * mismatch, fall back to the default value.
3510 */
3511 if (!pci_cache_line_size) {
3512 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3513 if (!cls)
3514 cls = tmp;
3515 if (!tmp || cls == tmp)
3516 continue;
3517
3518 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3519 cls << 2, tmp << 2,
3520 pci_dfl_cache_line_size << 2);
3521 pci_cache_line_size = pci_dfl_cache_line_size;
3522 }
3523 }
3524
3525 if (!pci_cache_line_size) {
3526 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3527 cls << 2, pci_dfl_cache_line_size << 2);
3528 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3529 }
3530
3531 return 0;
3532 }
3533
3534 fs_initcall_sync(pci_apply_final_quirks);
3535
3536 /*
3537 * Following are device-specific reset methods which can be used to
3538 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3539 * not available.
3540 */
3541 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3542 {
3543 /*
3544 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3545 *
3546 * The 82599 supports FLR on VFs, but FLR support is reported only
3547 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3548 * Thus we must call pcie_flr() directly without first checking if it is
3549 * supported.
3550 */
3551 if (!probe)
3552 pcie_flr(dev);
3553 return 0;
3554 }
3555
3556 #define SOUTH_CHICKEN2 0xc2004
3557 #define PCH_PP_STATUS 0xc7200
3558 #define PCH_PP_CONTROL 0xc7204
3559 #define MSG_CTL 0x45010
3560 #define NSDE_PWR_STATE 0xd0100
3561 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3562
3563 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3564 {
3565 void __iomem *mmio_base;
3566 unsigned long timeout;
3567 u32 val;
3568
3569 if (probe)
3570 return 0;
3571
3572 mmio_base = pci_iomap(dev, 0, 0);
3573 if (!mmio_base)
3574 return -ENOMEM;
3575
3576 iowrite32(0x00000002, mmio_base + MSG_CTL);
3577
3578 /*
3579 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3580 * driver loaded sets the right bits. However, this's a reset and
3581 * the bits have been set by i915 previously, so we clobber
3582 * SOUTH_CHICKEN2 register directly here.
3583 */
3584 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3585
3586 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3587 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3588
3589 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3590 do {
3591 val = ioread32(mmio_base + PCH_PP_STATUS);
3592 if ((val & 0xb0000000) == 0)
3593 goto reset_complete;
3594 msleep(10);
3595 } while (time_before(jiffies, timeout));
3596 pci_warn(dev, "timeout during reset\n");
3597
3598 reset_complete:
3599 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3600
3601 pci_iounmap(dev, mmio_base);
3602 return 0;
3603 }
3604
3605 /*
3606 * Device-specific reset method for Chelsio T4-based adapters.
3607 */
3608 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3609 {
3610 u16 old_command;
3611 u16 msix_flags;
3612
3613 /*
3614 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3615 * that we have no device-specific reset method.
3616 */
3617 if ((dev->device & 0xf000) != 0x4000)
3618 return -ENOTTY;
3619
3620 /*
3621 * If this is the "probe" phase, return 0 indicating that we can
3622 * reset this device.
3623 */
3624 if (probe)
3625 return 0;
3626
3627 /*
3628 * T4 can wedge if there are DMAs in flight within the chip and Bus
3629 * Master has been disabled. We need to have it on till the Function
3630 * Level Reset completes. (BUS_MASTER is disabled in
3631 * pci_reset_function()).
3632 */
3633 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3634 pci_write_config_word(dev, PCI_COMMAND,
3635 old_command | PCI_COMMAND_MASTER);
3636
3637 /*
3638 * Perform the actual device function reset, saving and restoring
3639 * configuration information around the reset.
3640 */
3641 pci_save_state(dev);
3642
3643 /*
3644 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3645 * are disabled when an MSI-X interrupt message needs to be delivered.
3646 * So we briefly re-enable MSI-X interrupts for the duration of the
3647 * FLR. The pci_restore_state() below will restore the original
3648 * MSI-X state.
3649 */
3650 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3651 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3652 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3653 msix_flags |
3654 PCI_MSIX_FLAGS_ENABLE |
3655 PCI_MSIX_FLAGS_MASKALL);
3656
3657 pcie_flr(dev);
3658
3659 /*
3660 * Restore the configuration information (BAR values, etc.) including
3661 * the original PCI Configuration Space Command word, and return
3662 * success.
3663 */
3664 pci_restore_state(dev);
3665 pci_write_config_word(dev, PCI_COMMAND, old_command);
3666 return 0;
3667 }
3668
3669 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3670 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3671 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3672
3673 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3674 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3675 reset_intel_82599_sfp_virtfn },
3676 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3677 reset_ivb_igd },
3678 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3679 reset_ivb_igd },
3680 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3681 reset_chelsio_generic_dev },
3682 { 0 }
3683 };
3684
3685 /*
3686 * These device-specific reset methods are here rather than in a driver
3687 * because when a host assigns a device to a guest VM, the host may need
3688 * to reset the device but probably doesn't have a driver for it.
3689 */
3690 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3691 {
3692 const struct pci_dev_reset_methods *i;
3693
3694 for (i = pci_dev_reset_methods; i->reset; i++) {
3695 if ((i->vendor == dev->vendor ||
3696 i->vendor == (u16)PCI_ANY_ID) &&
3697 (i->device == dev->device ||
3698 i->device == (u16)PCI_ANY_ID))
3699 return i->reset(dev, probe);
3700 }
3701
3702 return -ENOTTY;
3703 }
3704
3705 static void quirk_dma_func0_alias(struct pci_dev *dev)
3706 {
3707 if (PCI_FUNC(dev->devfn) != 0)
3708 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3709 }
3710
3711 /*
3712 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3713 *
3714 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3715 */
3716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3718
3719 static void quirk_dma_func1_alias(struct pci_dev *dev)
3720 {
3721 if (PCI_FUNC(dev->devfn) != 1)
3722 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3723 }
3724
3725 /*
3726 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3727 * SKUs function 1 is present and is a legacy IDE controller, in other
3728 * SKUs this function is not present, making this a ghost requester.
3729 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3730 */
3731 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3732 quirk_dma_func1_alias);
3733 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3734 quirk_dma_func1_alias);
3735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3736 quirk_dma_func1_alias);
3737 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3739 quirk_dma_func1_alias);
3740 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3741 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3742 quirk_dma_func1_alias);
3743 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3745 quirk_dma_func1_alias);
3746 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3748 quirk_dma_func1_alias);
3749 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3751 quirk_dma_func1_alias);
3752 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3753 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3754 quirk_dma_func1_alias);
3755 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3757 quirk_dma_func1_alias);
3758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3759 quirk_dma_func1_alias);
3760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3761 quirk_dma_func1_alias);
3762 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3764 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3765 quirk_dma_func1_alias);
3766 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3767 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3768 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3769 quirk_dma_func1_alias);
3770
3771 /*
3772 * Some devices DMA with the wrong devfn, not just the wrong function.
3773 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3774 * the alias is "fixed" and independent of the device devfn.
3775 *
3776 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3777 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3778 * single device on the secondary bus. In reality, the single exposed
3779 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3780 * that provides a bridge to the internal bus of the I/O processor. The
3781 * controller supports private devices, which can be hidden from PCI config
3782 * space. In the case of the Adaptec 3405, a private device at 01.0
3783 * appears to be the DMA engine, which therefore needs to become a DMA
3784 * alias for the device.
3785 */
3786 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3787 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3788 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3789 .driver_data = PCI_DEVFN(1, 0) },
3790 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3791 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3792 .driver_data = PCI_DEVFN(1, 0) },
3793 { 0 }
3794 };
3795
3796 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3797 {
3798 const struct pci_device_id *id;
3799
3800 id = pci_match_id(fixed_dma_alias_tbl, dev);
3801 if (id)
3802 pci_add_dma_alias(dev, id->driver_data);
3803 }
3804
3805 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3806
3807 /*
3808 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3809 * using the wrong DMA alias for the device. Some of these devices can be
3810 * used as either forward or reverse bridges, so we need to test whether the
3811 * device is operating in the correct mode. We could probably apply this
3812 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3813 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3814 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3815 */
3816 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3817 {
3818 if (!pci_is_root_bus(pdev->bus) &&
3819 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3820 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3821 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3822 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3823 }
3824 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3826 quirk_use_pcie_bridge_dma_alias);
3827 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3828 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3829 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3830 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3831 /* ITE 8893 has the same problem as the 8892 */
3832 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
3833 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3834 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3835
3836 /*
3837 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3838 * be added as aliases to the DMA device in order to allow buffer access
3839 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3840 * programmed in the EEPROM.
3841 */
3842 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3843 {
3844 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3845 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3846 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3847 }
3848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3850
3851 /*
3852 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
3853 * associated not at the root bus, but at a bridge below. This quirk avoids
3854 * generating invalid DMA aliases.
3855 */
3856 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
3857 {
3858 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
3859 }
3860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
3861 quirk_bridge_cavm_thrx2_pcie_root);
3862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
3863 quirk_bridge_cavm_thrx2_pcie_root);
3864
3865 /*
3866 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3867 * class code. Fix it.
3868 */
3869 static void quirk_tw686x_class(struct pci_dev *pdev)
3870 {
3871 u32 class = pdev->class;
3872
3873 /* Use "Multimedia controller" class */
3874 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3875 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3876 class, pdev->class);
3877 }
3878 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3879 quirk_tw686x_class);
3880 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3881 quirk_tw686x_class);
3882 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3883 quirk_tw686x_class);
3884 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3885 quirk_tw686x_class);
3886
3887 /*
3888 * Some devices have problems with Transaction Layer Packets with the Relaxed
3889 * Ordering Attribute set. Such devices should mark themselves and other
3890 * Device Drivers should check before sending TLPs with RO set.
3891 */
3892 static void quirk_relaxedordering_disable(struct pci_dev *dev)
3893 {
3894 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
3895 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
3896 }
3897
3898 /*
3899 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
3900 * Complex has a Flow Control Credit issue which can cause performance
3901 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
3902 */
3903 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
3904 quirk_relaxedordering_disable);
3905 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
3906 quirk_relaxedordering_disable);
3907 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
3908 quirk_relaxedordering_disable);
3909 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
3910 quirk_relaxedordering_disable);
3911 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
3912 quirk_relaxedordering_disable);
3913 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
3914 quirk_relaxedordering_disable);
3915 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
3916 quirk_relaxedordering_disable);
3917 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
3918 quirk_relaxedordering_disable);
3919 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
3920 quirk_relaxedordering_disable);
3921 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
3922 quirk_relaxedordering_disable);
3923 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
3924 quirk_relaxedordering_disable);
3925 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
3926 quirk_relaxedordering_disable);
3927 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
3928 quirk_relaxedordering_disable);
3929 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
3930 quirk_relaxedordering_disable);
3931 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
3932 quirk_relaxedordering_disable);
3933 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
3934 quirk_relaxedordering_disable);
3935 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
3936 quirk_relaxedordering_disable);
3937 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
3938 quirk_relaxedordering_disable);
3939 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
3940 quirk_relaxedordering_disable);
3941 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
3942 quirk_relaxedordering_disable);
3943 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
3944 quirk_relaxedordering_disable);
3945 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
3946 quirk_relaxedordering_disable);
3947 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
3948 quirk_relaxedordering_disable);
3949 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
3950 quirk_relaxedordering_disable);
3951 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
3952 quirk_relaxedordering_disable);
3953 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
3954 quirk_relaxedordering_disable);
3955 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
3956 quirk_relaxedordering_disable);
3957 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
3958 quirk_relaxedordering_disable);
3959
3960 /*
3961 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
3962 * where Upstream Transaction Layer Packets with the Relaxed Ordering
3963 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
3964 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
3965 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
3966 * November 10, 2010). As a result, on this platform we can't use Relaxed
3967 * Ordering for Upstream TLPs.
3968 */
3969 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
3970 quirk_relaxedordering_disable);
3971 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
3972 quirk_relaxedordering_disable);
3973 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
3974 quirk_relaxedordering_disable);
3975
3976 /*
3977 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3978 * values for the Attribute as were supplied in the header of the
3979 * corresponding Request, except as explicitly allowed when IDO is used."
3980 *
3981 * If a non-compliant device generates a completion with a different
3982 * attribute than the request, the receiver may accept it (which itself
3983 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3984 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3985 * device access timeout.
3986 *
3987 * If the non-compliant device generates completions with zero attributes
3988 * (instead of copying the attributes from the request), we can work around
3989 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3990 * upstream devices so they always generate requests with zero attributes.
3991 *
3992 * This affects other devices under the same Root Port, but since these
3993 * attributes are performance hints, there should be no functional problem.
3994 *
3995 * Note that Configuration Space accesses are never supposed to have TLP
3996 * Attributes, so we're safe waiting till after any Configuration Space
3997 * accesses to do the Root Port fixup.
3998 */
3999 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4000 {
4001 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4002
4003 if (!root_port) {
4004 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4005 return;
4006 }
4007
4008 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4009 dev_name(&pdev->dev));
4010 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4011 PCI_EXP_DEVCTL_RELAX_EN |
4012 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4013 }
4014
4015 /*
4016 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4017 * Completion it generates.
4018 */
4019 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4020 {
4021 /*
4022 * This mask/compare operation selects for Physical Function 4 on a
4023 * T5. We only need to fix up the Root Port once for any of the
4024 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4025 * 0x54xx so we use that one,
4026 */
4027 if ((pdev->device & 0xff00) == 0x5400)
4028 quirk_disable_root_port_attributes(pdev);
4029 }
4030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4031 quirk_chelsio_T5_disable_root_port_attributes);
4032
4033 /*
4034 * AMD has indicated that the devices below do not support peer-to-peer
4035 * in any system where they are found in the southbridge with an AMD
4036 * IOMMU in the system. Multifunction devices that do not support
4037 * peer-to-peer between functions can claim to support a subset of ACS.
4038 * Such devices effectively enable request redirect (RR) and completion
4039 * redirect (CR) since all transactions are redirected to the upstream
4040 * root complex.
4041 *
4042 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4043 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4044 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4045 *
4046 * 1002:4385 SBx00 SMBus Controller
4047 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4048 * 1002:4383 SBx00 Azalia (Intel HDA)
4049 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4050 * 1002:4384 SBx00 PCI to PCI Bridge
4051 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4052 *
4053 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4054 *
4055 * 1022:780f [AMD] FCH PCI Bridge
4056 * 1022:7809 [AMD] FCH USB OHCI Controller
4057 */
4058 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4059 {
4060 #ifdef CONFIG_ACPI
4061 struct acpi_table_header *header = NULL;
4062 acpi_status status;
4063
4064 /* Targeting multifunction devices on the SB (appears on root bus) */
4065 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4066 return -ENODEV;
4067
4068 /* The IVRS table describes the AMD IOMMU */
4069 status = acpi_get_table("IVRS", 0, &header);
4070 if (ACPI_FAILURE(status))
4071 return -ENODEV;
4072
4073 /* Filter out flags not applicable to multifunction */
4074 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4075
4076 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4077 #else
4078 return -ENODEV;
4079 #endif
4080 }
4081
4082 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4083 {
4084 /*
4085 * Effectively selects all downstream ports for whole ThunderX 1
4086 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4087 * bits of device ID are used to indicate which subdevice is used
4088 * within the SoC.
4089 */
4090 return (pci_is_pcie(dev) &&
4091 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4092 ((dev->device & 0xf800) == 0xa000));
4093 }
4094
4095 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4096 {
4097 /*
4098 * Cavium root ports don't advertise an ACS capability. However,
4099 * the RTL internally implements similar protection as if ACS had
4100 * Request Redirection, Completion Redirection, Source Validation,
4101 * and Upstream Forwarding features enabled. Assert that the
4102 * hardware implements and enables equivalent ACS functionality for
4103 * these flags.
4104 */
4105 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4106
4107 if (!pci_quirk_cavium_acs_match(dev))
4108 return -ENOTTY;
4109
4110 return acs_flags ? 0 : 1;
4111 }
4112
4113 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4114 {
4115 /*
4116 * X-Gene root matching this quirk do not allow peer-to-peer
4117 * transactions with others, allowing masking out these bits as if they
4118 * were unimplemented in the ACS capability.
4119 */
4120 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4121
4122 return acs_flags ? 0 : 1;
4123 }
4124
4125 /*
4126 * Many Intel PCH root ports do provide ACS-like features to disable peer
4127 * transactions and validate bus numbers in requests, but do not provide an
4128 * actual PCIe ACS capability. This is the list of device IDs known to fall
4129 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4130 */
4131 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4132 /* Ibexpeak PCH */
4133 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4134 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4135 /* Cougarpoint PCH */
4136 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4137 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4138 /* Pantherpoint PCH */
4139 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4140 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4141 /* Lynxpoint-H PCH */
4142 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4143 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4144 /* Lynxpoint-LP PCH */
4145 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4146 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4147 /* Wildcat PCH */
4148 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4149 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4150 /* Patsburg (X79) PCH */
4151 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4152 /* Wellsburg (X99) PCH */
4153 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4154 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4155 /* Lynx Point (9 series) PCH */
4156 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4157 };
4158
4159 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4160 {
4161 int i;
4162
4163 /* Filter out a few obvious non-matches first */
4164 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4165 return false;
4166
4167 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4168 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4169 return true;
4170
4171 return false;
4172 }
4173
4174 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4175
4176 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4177 {
4178 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4179 INTEL_PCH_ACS_FLAGS : 0;
4180
4181 if (!pci_quirk_intel_pch_acs_match(dev))
4182 return -ENOTTY;
4183
4184 return acs_flags & ~flags ? 0 : 1;
4185 }
4186
4187 /*
4188 * These QCOM root ports do provide ACS-like features to disable peer
4189 * transactions and validate bus numbers in requests, but do not provide an
4190 * actual PCIe ACS capability. Hardware supports source validation but it
4191 * will report the issue as Completer Abort instead of ACS Violation.
4192 * Hardware doesn't support peer-to-peer and each root port is a root
4193 * complex with unique segment numbers. It is not possible for one root
4194 * port to pass traffic to another root port. All PCIe transactions are
4195 * terminated inside the root port.
4196 */
4197 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4198 {
4199 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4200 int ret = acs_flags & ~flags ? 0 : 1;
4201
4202 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
4203
4204 return ret;
4205 }
4206
4207 /*
4208 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4209 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4210 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4211 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4212 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4213 * control register is at offset 8 instead of 6 and we should probably use
4214 * dword accesses to them. This applies to the following PCI Device IDs, as
4215 * found in volume 1 of the datasheet[2]:
4216 *
4217 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4218 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4219 *
4220 * N.B. This doesn't fix what lspci shows.
4221 *
4222 * The 100 series chipset specification update includes this as errata #23[3].
4223 *
4224 * The 200 series chipset (Union Point) has the same bug according to the
4225 * specification update (Intel 200 Series Chipset Family Platform Controller
4226 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4227 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4228 * chipset include:
4229 *
4230 * 0xa290-0xa29f PCI Express Root port #{0-16}
4231 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4232 *
4233 * Mobile chipsets are also affected, 7th & 8th Generation
4234 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4235 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4236 * Processor Family I/O for U Quad Core Platforms Specification Update,
4237 * August 2017, Revision 002, Document#: 334660-002)[6]
4238 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4239 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4240 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4241 *
4242 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4243 *
4244 * The 300 series chipset suffers from the same bug so include those root
4245 * ports here as well.
4246 *
4247 * 0xa32c-0xa343 PCI Express Root port #{0-24}
4248 *
4249 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4250 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4251 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4252 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4253 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4254 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4255 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4256 */
4257 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4258 {
4259 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4260 return false;
4261
4262 switch (dev->device) {
4263 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4264 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4265 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4266 case 0xa32c ... 0xa343: /* 300 series */
4267 return true;
4268 }
4269
4270 return false;
4271 }
4272
4273 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4274
4275 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4276 {
4277 int pos;
4278 u32 cap, ctrl;
4279
4280 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4281 return -ENOTTY;
4282
4283 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4284 if (!pos)
4285 return -ENOTTY;
4286
4287 /* see pci_acs_flags_enabled() */
4288 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4289 acs_flags &= (cap | PCI_ACS_EC);
4290
4291 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4292
4293 return acs_flags & ~ctrl ? 0 : 1;
4294 }
4295
4296 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4297 {
4298 /*
4299 * SV, TB, and UF are not relevant to multifunction endpoints.
4300 *
4301 * Multifunction devices are only required to implement RR, CR, and DT
4302 * in their ACS capability if they support peer-to-peer transactions.
4303 * Devices matching this quirk have been verified by the vendor to not
4304 * perform peer-to-peer with other functions, allowing us to mask out
4305 * these bits as if they were unimplemented in the ACS capability.
4306 */
4307 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4308 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4309
4310 return acs_flags ? 0 : 1;
4311 }
4312
4313 static const struct pci_dev_acs_enabled {
4314 u16 vendor;
4315 u16 device;
4316 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4317 } pci_dev_acs_enabled[] = {
4318 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4319 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4320 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4321 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4322 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4323 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4324 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4325 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4326 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4327 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4328 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4329 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4330 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4331 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4332 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4333 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4334 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4335 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4336 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4337 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4338 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4339 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4340 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4341 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4342 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4343 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4344 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4345 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4346 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4347 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4348 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4349 /* 82580 */
4350 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4351 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4352 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4353 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4354 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4355 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4356 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4357 /* 82576 */
4358 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4359 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4360 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4361 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4362 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4363 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4364 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4365 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4366 /* 82575 */
4367 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4368 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4369 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4370 /* I350 */
4371 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4372 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4373 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4374 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4375 /* 82571 (Quads omitted due to non-ACS switch) */
4376 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4377 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4378 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4379 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4380 /* I219 */
4381 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4382 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4383 /* QCOM QDF2xxx root ports */
4384 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4385 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4386 /* Intel PCH root ports */
4387 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4388 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4389 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4390 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4391 /* Cavium ThunderX */
4392 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4393 /* APM X-Gene */
4394 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4395 /* Ampere Computing */
4396 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4397 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4398 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4399 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4400 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4401 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4402 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4403 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4404 { 0 }
4405 };
4406
4407 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4408 {
4409 const struct pci_dev_acs_enabled *i;
4410 int ret;
4411
4412 /*
4413 * Allow devices that do not expose standard PCIe ACS capabilities
4414 * or control to indicate their support here. Multi-function express
4415 * devices which do not allow internal peer-to-peer between functions,
4416 * but do not implement PCIe ACS may wish to return true here.
4417 */
4418 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4419 if ((i->vendor == dev->vendor ||
4420 i->vendor == (u16)PCI_ANY_ID) &&
4421 (i->device == dev->device ||
4422 i->device == (u16)PCI_ANY_ID)) {
4423 ret = i->acs_enabled(dev, acs_flags);
4424 if (ret >= 0)
4425 return ret;
4426 }
4427 }
4428
4429 return -ENOTTY;
4430 }
4431
4432 /* Config space offset of Root Complex Base Address register */
4433 #define INTEL_LPC_RCBA_REG 0xf0
4434 /* 31:14 RCBA address */
4435 #define INTEL_LPC_RCBA_MASK 0xffffc000
4436 /* RCBA Enable */
4437 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4438
4439 /* Backbone Scratch Pad Register */
4440 #define INTEL_BSPR_REG 0x1104
4441 /* Backbone Peer Non-Posted Disable */
4442 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4443 /* Backbone Peer Posted Disable */
4444 #define INTEL_BSPR_REG_BPPD (1 << 9)
4445
4446 /* Upstream Peer Decode Configuration Register */
4447 #define INTEL_UPDCR_REG 0x1114
4448 /* 5:0 Peer Decode Enable bits */
4449 #define INTEL_UPDCR_REG_MASK 0x3f
4450
4451 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4452 {
4453 u32 rcba, bspr, updcr;
4454 void __iomem *rcba_mem;
4455
4456 /*
4457 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4458 * are D28:F* and therefore get probed before LPC, thus we can't
4459 * use pci_get_slot/pci_read_config_dword here.
4460 */
4461 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4462 INTEL_LPC_RCBA_REG, &rcba);
4463 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4464 return -EINVAL;
4465
4466 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4467 PAGE_ALIGN(INTEL_UPDCR_REG));
4468 if (!rcba_mem)
4469 return -ENOMEM;
4470
4471 /*
4472 * The BSPR can disallow peer cycles, but it's set by soft strap and
4473 * therefore read-only. If both posted and non-posted peer cycles are
4474 * disallowed, we're ok. If either are allowed, then we need to use
4475 * the UPDCR to disable peer decodes for each port. This provides the
4476 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4477 */
4478 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4479 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4480 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4481 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4482 if (updcr & INTEL_UPDCR_REG_MASK) {
4483 pci_info(dev, "Disabling UPDCR peer decodes\n");
4484 updcr &= ~INTEL_UPDCR_REG_MASK;
4485 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4486 }
4487 }
4488
4489 iounmap(rcba_mem);
4490 return 0;
4491 }
4492
4493 /* Miscellaneous Port Configuration register */
4494 #define INTEL_MPC_REG 0xd8
4495 /* MPC: Invalid Receive Bus Number Check Enable */
4496 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4497
4498 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4499 {
4500 u32 mpc;
4501
4502 /*
4503 * When enabled, the IRBNCE bit of the MPC register enables the
4504 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4505 * ensures that requester IDs fall within the bus number range
4506 * of the bridge. Enable if not already.
4507 */
4508 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4509 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4510 pci_info(dev, "Enabling MPC IRBNCE\n");
4511 mpc |= INTEL_MPC_REG_IRBNCE;
4512 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4513 }
4514 }
4515
4516 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4517 {
4518 if (!pci_quirk_intel_pch_acs_match(dev))
4519 return -ENOTTY;
4520
4521 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4522 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4523 return 0;
4524 }
4525
4526 pci_quirk_enable_intel_rp_mpc_acs(dev);
4527
4528 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4529
4530 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4531
4532 return 0;
4533 }
4534
4535 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4536 {
4537 int pos;
4538 u32 cap, ctrl;
4539
4540 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4541 return -ENOTTY;
4542
4543 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4544 if (!pos)
4545 return -ENOTTY;
4546
4547 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4548 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4549
4550 ctrl |= (cap & PCI_ACS_SV);
4551 ctrl |= (cap & PCI_ACS_RR);
4552 ctrl |= (cap & PCI_ACS_CR);
4553 ctrl |= (cap & PCI_ACS_UF);
4554
4555 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4556
4557 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4558
4559 return 0;
4560 }
4561
4562 static const struct pci_dev_enable_acs {
4563 u16 vendor;
4564 u16 device;
4565 int (*enable_acs)(struct pci_dev *dev);
4566 } pci_dev_enable_acs[] = {
4567 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4568 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4569 { 0 }
4570 };
4571
4572 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4573 {
4574 const struct pci_dev_enable_acs *i;
4575 int ret;
4576
4577 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4578 if ((i->vendor == dev->vendor ||
4579 i->vendor == (u16)PCI_ANY_ID) &&
4580 (i->device == dev->device ||
4581 i->device == (u16)PCI_ANY_ID)) {
4582 ret = i->enable_acs(dev);
4583 if (ret >= 0)
4584 return ret;
4585 }
4586 }
4587
4588 return -ENOTTY;
4589 }
4590
4591 /*
4592 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4593 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4594 * Next Capability pointer in the MSI Capability Structure should point to
4595 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4596 * the list.
4597 */
4598 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4599 {
4600 int pos, i = 0;
4601 u8 next_cap;
4602 u16 reg16, *cap;
4603 struct pci_cap_saved_state *state;
4604
4605 /* Bail if the hardware bug is fixed */
4606 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4607 return;
4608
4609 /* Bail if MSI Capability Structure is not found for some reason */
4610 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4611 if (!pos)
4612 return;
4613
4614 /*
4615 * Bail if Next Capability pointer in the MSI Capability Structure
4616 * is not the expected incorrect 0x00.
4617 */
4618 pci_read_config_byte(pdev, pos + 1, &next_cap);
4619 if (next_cap)
4620 return;
4621
4622 /*
4623 * PCIe Capability Structure is expected to be at 0x50 and should
4624 * terminate the list (Next Capability pointer is 0x00). Verify
4625 * Capability Id and Next Capability pointer is as expected.
4626 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4627 * to correctly set kernel data structures which have already been
4628 * set incorrectly due to the hardware bug.
4629 */
4630 pos = 0x50;
4631 pci_read_config_word(pdev, pos, &reg16);
4632 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4633 u32 status;
4634 #ifndef PCI_EXP_SAVE_REGS
4635 #define PCI_EXP_SAVE_REGS 7
4636 #endif
4637 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4638
4639 pdev->pcie_cap = pos;
4640 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4641 pdev->pcie_flags_reg = reg16;
4642 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4643 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4644
4645 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4646 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4647 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4648 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4649
4650 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4651 return;
4652
4653 /*
4654 * Save PCIE cap
4655 */
4656 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4657 if (!state)
4658 return;
4659
4660 state->cap.cap_nr = PCI_CAP_ID_EXP;
4661 state->cap.cap_extended = 0;
4662 state->cap.size = size;
4663 cap = (u16 *)&state->cap.data[0];
4664 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4665 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4666 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4667 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4668 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4669 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4670 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4671 hlist_add_head(&state->next, &pdev->saved_cap_space);
4672 }
4673 }
4674 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4675
4676 /* FLR may cause some 82579 devices to hang. */
4677 static void quirk_intel_no_flr(struct pci_dev *dev)
4678 {
4679 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4680 }
4681 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4682 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4683
4684 static void quirk_no_ext_tags(struct pci_dev *pdev)
4685 {
4686 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4687
4688 if (!bridge)
4689 return;
4690
4691 bridge->no_ext_tags = 1;
4692 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
4693
4694 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4695 }
4696 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
4697 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
4698 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
4699 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
4700 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
4701 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
4702 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
4703
4704 #ifdef CONFIG_PCI_ATS
4705 /*
4706 * Some devices have a broken ATS implementation causing IOMMU stalls.
4707 * Don't use ATS for those devices.
4708 */
4709 static void quirk_no_ats(struct pci_dev *pdev)
4710 {
4711 pci_info(pdev, "disabling ATS (broken on this device)\n");
4712 pdev->ats_cap = 0;
4713 }
4714
4715 /* AMD Stoney platform GPU */
4716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
4717 #endif /* CONFIG_PCI_ATS */
4718
4719 /* Freescale PCIe doesn't support MSI in RC mode */
4720 static void quirk_fsl_no_msi(struct pci_dev *pdev)
4721 {
4722 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
4723 pdev->no_msi = 1;
4724 }
4725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
4726
4727 /*
4728 * GPUs with integrated HDA controller for streaming audio to attached displays
4729 * need a device link from the HDA controller (consumer) to the GPU (supplier)
4730 * so that the GPU is powered up whenever the HDA controller is accessed.
4731 * The GPU and HDA controller are functions 0 and 1 of the same PCI device.
4732 * The device link stays in place until shutdown (or removal of the PCI device
4733 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller
4734 * to prevent it from permanently keeping the GPU awake.
4735 */
4736 static void quirk_gpu_hda(struct pci_dev *hda)
4737 {
4738 struct pci_dev *gpu;
4739
4740 if (PCI_FUNC(hda->devfn) != 1)
4741 return;
4742
4743 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus),
4744 hda->bus->number,
4745 PCI_DEVFN(PCI_SLOT(hda->devfn), 0));
4746 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) {
4747 pci_dev_put(gpu);
4748 return;
4749 }
4750
4751 if (!device_link_add(&hda->dev, &gpu->dev,
4752 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
4753 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu));
4754
4755 pm_runtime_allow(&hda->dev);
4756 pci_dev_put(gpu);
4757 }
4758 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
4759 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4760 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
4761 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4762 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
4763 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
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