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[mirror_ubuntu-zesty-kernel.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29 #include "pci.h"
30
31 /*
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
37 static void quirk_mmio_always_on(struct pci_dev *dev)
38 {
39 dev->mmio_always_on = 1;
40 }
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
43
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
48 static void quirk_mellanox_tavor(struct pci_dev *dev)
49 {
50 dev->broken_parity_status = 1; /* This device gives false positives */
51 }
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
54
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev *dev)
58 {
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
68 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72 }
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
75
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
81 chipset level fix */
82
83 static void quirk_isa_dma_hangs(struct pci_dev *dev)
84 {
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy = 1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
88 }
89 }
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
101
102 /*
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
107 {
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119 }
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122 /*
123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
125 static void quirk_nopcipci(struct pci_dev *dev)
126 {
127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131 }
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
134
135 static void quirk_nopciamd(struct pci_dev *dev)
136 {
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144 }
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
146
147 /*
148 * Triton requires workarounds to be used by the drivers
149 */
150 static void quirk_triton(struct pci_dev *dev)
151 {
152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156 }
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
161
162 /*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172 static void quirk_vialatency(struct pci_dev *dev)
173 {
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p != NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p == NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214 exit:
215 pci_dev_put(p);
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220 /* Must restore this on a resume from RAM */
221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225 /*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228 static void quirk_viaetbf(struct pci_dev *dev)
229 {
230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234 }
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237 static void quirk_vsfx(struct pci_dev *dev)
238 {
239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243 }
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246 /*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252 static void quirk_alimagik(struct pci_dev *dev)
253 {
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258 }
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262 /*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266 static void quirk_natoma(struct pci_dev *dev)
267 {
268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272 }
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280 /*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284 static void quirk_citrine(struct pci_dev *dev)
285 {
286 dev->cfg_size = 0xA0;
287 }
288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290 /*
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
293 */
294 static void quirk_nfp6000(struct pci_dev *dev)
295 {
296 dev->cfg_size = 0x600;
297 }
298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
301
302 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
303 static void quirk_extend_bar_to_page(struct pci_dev *dev)
304 {
305 int i;
306
307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
308 struct resource *r = &dev->resource[i];
309
310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
311 r->end = PAGE_SIZE - 1;
312 r->start = 0;
313 r->flags |= IORESOURCE_UNSET;
314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
315 i, r);
316 }
317 }
318 }
319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
320
321 /*
322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
323 * If it's needed, re-allocate the region.
324 */
325 static void quirk_s3_64M(struct pci_dev *dev)
326 {
327 struct resource *r = &dev->resource[0];
328
329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
330 r->flags |= IORESOURCE_UNSET;
331 r->start = 0;
332 r->end = 0x3ffffff;
333 }
334 }
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
337
338 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
339 const char *name)
340 {
341 u32 region;
342 struct pci_bus_region bus_region;
343 struct resource *res = dev->resource + pos;
344
345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
346
347 if (!region)
348 return;
349
350 res->name = pci_name(dev);
351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
352 res->flags |=
353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
354 region &= ~(size - 1);
355
356 /* Convert from PCI bus to resource space */
357 bus_region.start = region;
358 bus_region.end = region + size - 1;
359 pcibios_bus_to_resource(dev->bus, res, &bus_region);
360
361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
363 }
364
365 /*
366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
369 * (which conflicts w/ BAR1's memory range).
370 *
371 * CS553x's ISA PCI BARs may also be read-only (ref:
372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
373 */
374 static void quirk_cs5536_vsa(struct pci_dev *dev)
375 {
376 static char *name = "CS5536 ISA bridge";
377
378 if (pci_resource_len(dev, 0) != 8) {
379 quirk_io(dev, 0, 8, name); /* SMB */
380 quirk_io(dev, 1, 256, name); /* GPIO */
381 quirk_io(dev, 2, 64, name); /* MFGPT */
382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
383 name);
384 }
385 }
386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
387
388 static void quirk_io_region(struct pci_dev *dev, int port,
389 unsigned size, int nr, const char *name)
390 {
391 u16 region;
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
394
395 pci_read_config_word(dev, port, &region);
396 region &= ~(size - 1);
397
398 if (!region)
399 return;
400
401 res->name = pci_name(dev);
402 res->flags = IORESOURCE_IO;
403
404 /* Convert from PCI bus to resource space */
405 bus_region.start = region;
406 bus_region.end = region + size - 1;
407 pcibios_bus_to_resource(dev->bus, res, &bus_region);
408
409 if (!pci_claim_resource(dev, nr))
410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
411 }
412
413 /*
414 * ATI Northbridge setups MCE the processor if you even
415 * read somewhere between 0x3b0->0x3bb or read 0x3d3
416 */
417 static void quirk_ati_exploding_mce(struct pci_dev *dev)
418 {
419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
421 request_region(0x3b0, 0x0C, "RadeonIGP");
422 request_region(0x3d3, 0x01, "RadeonIGP");
423 }
424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
425
426 /*
427 * In the AMD NL platform, this device ([1022:7912]) has a class code of
428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
429 * claim it.
430 * But the dwc3 driver is a more specific driver for this device, and we'd
431 * prefer to use it instead of xhci. To prevent xhci from claiming the
432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
433 * defines as "USB device (not host controller)". The dwc3 driver can then
434 * claim it based on its Vendor and Device ID.
435 */
436 static void quirk_amd_nl_class(struct pci_dev *pdev)
437 {
438 u32 class = pdev->class;
439
440 /* Use "USB Device (not host controller)" class */
441 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
443 class, pdev->class);
444 }
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
446 quirk_amd_nl_class);
447
448 /*
449 * Let's make the southbridge information explicit instead
450 * of having to worry about people probing the ACPI areas,
451 * for example.. (Yes, it happens, and if you read the wrong
452 * ACPI register it will put the machine to sleep with no
453 * way of waking it up again. Bummer).
454 *
455 * ALI M7101: Two IO regions pointed to by words at
456 * 0xE0 (64 bytes of ACPI registers)
457 * 0xE2 (32 bytes of SMB registers)
458 */
459 static void quirk_ali7101_acpi(struct pci_dev *dev)
460 {
461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
463 }
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
465
466 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
467 {
468 u32 devres;
469 u32 mask, size, base;
470
471 pci_read_config_dword(dev, port, &devres);
472 if ((devres & enable) != enable)
473 return;
474 mask = (devres >> 16) & 15;
475 base = devres & 0xffff;
476 size = 16;
477 for (;;) {
478 unsigned bit = size >> 1;
479 if ((bit & mask) == bit)
480 break;
481 size = bit;
482 }
483 /*
484 * For now we only print it out. Eventually we'll want to
485 * reserve it (at least if it's in the 0x1000+ range), but
486 * let's get enough confirmation reports first.
487 */
488 base &= -size;
489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
490 base + size - 1);
491 }
492
493 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
494 {
495 u32 devres;
496 u32 mask, size, base;
497
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
500 return;
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
503 size = 128 << 16;
504 for (;;) {
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
507 break;
508 size = bit;
509 }
510 /*
511 * For now we only print it out. Eventually we'll want to
512 * reserve it, but let's get enough confirmation reports first.
513 */
514 base &= -size;
515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
516 base + size - 1);
517 }
518
519 /*
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
522 * 0x90 (16 bytes of SMB registers)
523 * and a few strange programmable PIIX4 device resources.
524 */
525 static void quirk_piix4_acpi(struct pci_dev *dev)
526 {
527 u32 res_a;
528
529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
531
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538 /* Device resource D is just bitfields for static resources */
539
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
552 }
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
555
556 #define ICH_PMBASE 0x40
557 #define ICH_ACPI_CNTL 0x44
558 #define ICH4_ACPI_EN 0x10
559 #define ICH6_ACPI_EN 0x80
560 #define ICH4_GPIOBASE 0x58
561 #define ICH4_GPIO_CNTL 0x5c
562 #define ICH4_GPIO_EN 0x10
563 #define ICH6_GPIOBASE 0x48
564 #define ICH6_GPIO_CNTL 0x4c
565 #define ICH6_GPIO_EN 0x10
566
567 /*
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
571 */
572 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
573 {
574 u8 enable;
575
576 /*
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
581 * BIOSes.
582 */
583
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
588
589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
593 }
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
604
605 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
606 {
607 u8 enable;
608
609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
613
614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
618 }
619
620 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
621 {
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627 /* Enabled? */
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632 /*
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
635 *
636 * But this gets us at least _part_ of it.
637 */
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644 /* Just print it out for now. We should reserve it after more debugging */
645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646 }
647
648 static void quirk_ich6_lpc(struct pci_dev *dev)
649 {
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
652
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656 }
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
660 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
661 {
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667 /* Enabled? */
668 if (!(val & 1))
669 return;
670
671 /*
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679 /* Just print it out for now. We should reserve it after more debugging */
680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681 }
682
683 /* ICH7-10 has the same common LPC generic IO decode registers */
684 static void quirk_ich7_lpc(struct pci_dev *dev)
685 {
686 /* We share the common ACPI/GPIO decode with ICH6 */
687 ich6_lpc_acpi_gpio(dev);
688
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694 }
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
708
709 /*
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
712 */
713 static void quirk_vt82c586_acpi(struct pci_dev *dev)
714 {
715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
718 }
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
720
721 /*
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
726 */
727 static void quirk_vt82c686_acpi(struct pci_dev *dev)
728 {
729 quirk_vt82c586_acpi(dev);
730
731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
733
734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
735 }
736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
737
738 /*
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
742 */
743 static void quirk_vt8235_acpi(struct pci_dev *dev)
744 {
745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
747 }
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
750 /*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
753 */
754 static void quirk_xio2000a(struct pci_dev *dev)
755 {
756 struct pci_dev *pdev;
757 u16 command;
758
759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765 }
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
768
769 #ifdef CONFIG_X86_IO_APIC
770
771 #include <asm/io_apic.h>
772
773 /*
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
776 *
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
779 */
780 static void quirk_via_ioapic(struct pci_dev *dev)
781 {
782 u8 tmp;
783
784 if (nr_ioapics < 1)
785 tmp = 0; /* nothing routed to external APIC */
786 else
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
788
789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
790 tmp == 0 ? "Disa" : "Ena");
791
792 /* Offset 0x58: External APIC IRQ output control */
793 pci_write_config_byte(dev, 0x58, tmp);
794 }
795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
797
798 /*
799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
803 */
804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
805 {
806 u8 misc_control2;
807 #define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814 }
815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
817
818 /*
819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
822 *
823 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so..
826 */
827 static void quirk_amd_ioapic(struct pci_dev *dev)
828 {
829 if (dev->revision >= 0x02) {
830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
832 }
833 }
834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
835 #endif /* CONFIG_X86_IO_APIC */
836
837 /*
838 * Some settings of MMRBC can lead to data corruption so block changes.
839 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
840 */
841 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
842 {
843 if (dev->subordinate && dev->revision <= 0x12) {
844 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
845 dev->revision);
846 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
847 }
848 }
849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
850
851 /*
852 * FIXME: it is questionable that quirk_via_acpi
853 * is needed. It shows up as an ISA bridge, and does not
854 * support the PCI_INTERRUPT_LINE register at all. Therefore
855 * it seems like setting the pci_dev's 'irq' to the
856 * value of the ACPI SCI interrupt is only done for convenience.
857 * -jgarzik
858 */
859 static void quirk_via_acpi(struct pci_dev *d)
860 {
861 /*
862 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
863 */
864 u8 irq;
865 pci_read_config_byte(d, 0x42, &irq);
866 irq &= 0xf;
867 if (irq && (irq != 2))
868 d->irq = irq;
869 }
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
872
873
874 /*
875 * VIA bridges which have VLink
876 */
877
878 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
879
880 static void quirk_via_bridge(struct pci_dev *dev)
881 {
882 /* See what bridge we have and find the device ranges */
883 switch (dev->device) {
884 case PCI_DEVICE_ID_VIA_82C686:
885 /* The VT82C686 is special, it attaches to PCI and can have
886 any device number. All its subdevices are functions of
887 that single device. */
888 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
889 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
890 break;
891 case PCI_DEVICE_ID_VIA_8237:
892 case PCI_DEVICE_ID_VIA_8237A:
893 via_vlink_dev_lo = 15;
894 break;
895 case PCI_DEVICE_ID_VIA_8235:
896 via_vlink_dev_lo = 16;
897 break;
898 case PCI_DEVICE_ID_VIA_8231:
899 case PCI_DEVICE_ID_VIA_8233_0:
900 case PCI_DEVICE_ID_VIA_8233A:
901 case PCI_DEVICE_ID_VIA_8233C_0:
902 via_vlink_dev_lo = 17;
903 break;
904 }
905 }
906 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
914
915 /**
916 * quirk_via_vlink - VIA VLink IRQ number update
917 * @dev: PCI device
918 *
919 * If the device we are dealing with is on a PIC IRQ we need to
920 * ensure that the IRQ line register which usually is not relevant
921 * for PCI cards, is actually written so that interrupts get sent
922 * to the right place.
923 * We only do this on systems where a VIA south bridge was detected,
924 * and only for VIA devices on the motherboard (see quirk_via_bridge
925 * above).
926 */
927
928 static void quirk_via_vlink(struct pci_dev *dev)
929 {
930 u8 irq, new_irq;
931
932 /* Check if we have VLink at all */
933 if (via_vlink_dev_lo == -1)
934 return;
935
936 new_irq = dev->irq;
937
938 /* Don't quirk interrupts outside the legacy IRQ range */
939 if (!new_irq || new_irq > 15)
940 return;
941
942 /* Internal device ? */
943 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
944 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
945 return;
946
947 /* This is an internal VLink device on a PIC interrupt. The BIOS
948 ought to have set this but may not have, so we redo it */
949
950 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
951 if (new_irq != irq) {
952 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
953 irq, new_irq);
954 udelay(15); /* unknown if delay really needed */
955 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
956 }
957 }
958 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
959
960 /*
961 * VIA VT82C598 has its device ID settable and many BIOSes
962 * set it to the ID of VT82C597 for backward compatibility.
963 * We need to switch it off to be able to recognize the real
964 * type of the chip.
965 */
966 static void quirk_vt82c598_id(struct pci_dev *dev)
967 {
968 pci_write_config_byte(dev, 0xfc, 0);
969 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
970 }
971 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
972
973 /*
974 * CardBus controllers have a legacy base address that enables them
975 * to respond as i82365 pcmcia controllers. We don't want them to
976 * do this even if the Linux CardBus driver is not loaded, because
977 * the Linux i82365 driver does not (and should not) handle CardBus.
978 */
979 static void quirk_cardbus_legacy(struct pci_dev *dev)
980 {
981 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
982 }
983 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
984 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
985 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
986 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
987
988 /*
989 * Following the PCI ordering rules is optional on the AMD762. I'm not
990 * sure what the designers were smoking but let's not inhale...
991 *
992 * To be fair to AMD, it follows the spec by default, its BIOS people
993 * who turn it off!
994 */
995 static void quirk_amd_ordering(struct pci_dev *dev)
996 {
997 u32 pcic;
998 pci_read_config_dword(dev, 0x4C, &pcic);
999 if ((pcic & 6) != 6) {
1000 pcic |= 6;
1001 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1002 pci_write_config_dword(dev, 0x4C, pcic);
1003 pci_read_config_dword(dev, 0x84, &pcic);
1004 pcic |= (1 << 23); /* Required in this mode */
1005 pci_write_config_dword(dev, 0x84, pcic);
1006 }
1007 }
1008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1009 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1010
1011 /*
1012 * DreamWorks provided workaround for Dunord I-3000 problem
1013 *
1014 * This card decodes and responds to addresses not apparently
1015 * assigned to it. We force a larger allocation to ensure that
1016 * nothing gets put too close to it.
1017 */
1018 static void quirk_dunord(struct pci_dev *dev)
1019 {
1020 struct resource *r = &dev->resource[1];
1021
1022 r->flags |= IORESOURCE_UNSET;
1023 r->start = 0;
1024 r->end = 0xffffff;
1025 }
1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1027
1028 /*
1029 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1030 * is subtractive decoding (transparent), and does indicate this
1031 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1032 * instead of 0x01.
1033 */
1034 static void quirk_transparent_bridge(struct pci_dev *dev)
1035 {
1036 dev->transparent = 1;
1037 }
1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1040
1041 /*
1042 * Common misconfiguration of the MediaGX/Geode PCI master that will
1043 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1044 * datasheets found at http://www.national.com/analog for info on what
1045 * these bits do. <christer@weinigel.se>
1046 */
1047 static void quirk_mediagx_master(struct pci_dev *dev)
1048 {
1049 u8 reg;
1050
1051 pci_read_config_byte(dev, 0x41, &reg);
1052 if (reg & 2) {
1053 reg &= ~2;
1054 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1055 reg);
1056 pci_write_config_byte(dev, 0x41, reg);
1057 }
1058 }
1059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1060 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1061
1062 /*
1063 * Ensure C0 rev restreaming is off. This is normally done by
1064 * the BIOS but in the odd case it is not the results are corruption
1065 * hence the presence of a Linux check
1066 */
1067 static void quirk_disable_pxb(struct pci_dev *pdev)
1068 {
1069 u16 config;
1070
1071 if (pdev->revision != 0x04) /* Only C0 requires this */
1072 return;
1073 pci_read_config_word(pdev, 0x40, &config);
1074 if (config & (1<<6)) {
1075 config &= ~(1<<6);
1076 pci_write_config_word(pdev, 0x40, config);
1077 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1078 }
1079 }
1080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1081 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1082
1083 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1084 {
1085 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1086 u8 tmp;
1087
1088 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1089 if (tmp == 0x01) {
1090 pci_read_config_byte(pdev, 0x40, &tmp);
1091 pci_write_config_byte(pdev, 0x40, tmp|1);
1092 pci_write_config_byte(pdev, 0x9, 1);
1093 pci_write_config_byte(pdev, 0xa, 6);
1094 pci_write_config_byte(pdev, 0x40, tmp);
1095
1096 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1097 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1098 }
1099 }
1100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1101 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1103 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1105 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1107 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1108
1109 /*
1110 * Serverworks CSB5 IDE does not fully support native mode
1111 */
1112 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1113 {
1114 u8 prog;
1115 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1116 if (prog & 5) {
1117 prog &= ~5;
1118 pdev->class &= ~5;
1119 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1120 /* PCI layer will sort out resources */
1121 }
1122 }
1123 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1124
1125 /*
1126 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1127 */
1128 static void quirk_ide_samemode(struct pci_dev *pdev)
1129 {
1130 u8 prog;
1131
1132 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1133
1134 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1135 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1136 prog &= ~5;
1137 pdev->class &= ~5;
1138 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1139 }
1140 }
1141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1142
1143 /*
1144 * Some ATA devices break if put into D3
1145 */
1146
1147 static void quirk_no_ata_d3(struct pci_dev *pdev)
1148 {
1149 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1150 }
1151 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1152 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1153 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1154 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1155 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1156 /* ALi loses some register settings that we cannot then restore */
1157 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1158 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1159 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1160 occur when mode detecting */
1161 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1162 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1163
1164 /* This was originally an Alpha specific thing, but it really fits here.
1165 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1166 */
1167 static void quirk_eisa_bridge(struct pci_dev *dev)
1168 {
1169 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1170 }
1171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1172
1173
1174 /*
1175 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1176 * is not activated. The myth is that Asus said that they do not want the
1177 * users to be irritated by just another PCI Device in the Win98 device
1178 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1179 * package 2.7.0 for details)
1180 *
1181 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1182 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1183 * becomes necessary to do this tweak in two steps -- the chosen trigger
1184 * is either the Host bridge (preferred) or on-board VGA controller.
1185 *
1186 * Note that we used to unhide the SMBus that way on Toshiba laptops
1187 * (Satellite A40 and Tecra M2) but then found that the thermal management
1188 * was done by SMM code, which could cause unsynchronized concurrent
1189 * accesses to the SMBus registers, with potentially bad effects. Thus you
1190 * should be very careful when adding new entries: if SMM is accessing the
1191 * Intel SMBus, this is a very good reason to leave it hidden.
1192 *
1193 * Likewise, many recent laptops use ACPI for thermal management. If the
1194 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1195 * natively, and keeping the SMBus hidden is the right thing to do. If you
1196 * are about to add an entry in the table below, please first disassemble
1197 * the DSDT and double-check that there is no code accessing the SMBus.
1198 */
1199 static int asus_hides_smbus;
1200
1201 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1202 {
1203 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1204 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1205 switch (dev->subsystem_device) {
1206 case 0x8025: /* P4B-LX */
1207 case 0x8070: /* P4B */
1208 case 0x8088: /* P4B533 */
1209 case 0x1626: /* L3C notebook */
1210 asus_hides_smbus = 1;
1211 }
1212 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1213 switch (dev->subsystem_device) {
1214 case 0x80b1: /* P4GE-V */
1215 case 0x80b2: /* P4PE */
1216 case 0x8093: /* P4B533-V */
1217 asus_hides_smbus = 1;
1218 }
1219 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1220 switch (dev->subsystem_device) {
1221 case 0x8030: /* P4T533 */
1222 asus_hides_smbus = 1;
1223 }
1224 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1225 switch (dev->subsystem_device) {
1226 case 0x8070: /* P4G8X Deluxe */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1230 switch (dev->subsystem_device) {
1231 case 0x80c9: /* PU-DLS */
1232 asus_hides_smbus = 1;
1233 }
1234 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1235 switch (dev->subsystem_device) {
1236 case 0x1751: /* M2N notebook */
1237 case 0x1821: /* M5N notebook */
1238 case 0x1897: /* A6L notebook */
1239 asus_hides_smbus = 1;
1240 }
1241 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1242 switch (dev->subsystem_device) {
1243 case 0x184b: /* W1N notebook */
1244 case 0x186a: /* M6Ne notebook */
1245 asus_hides_smbus = 1;
1246 }
1247 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1248 switch (dev->subsystem_device) {
1249 case 0x80f2: /* P4P800-X */
1250 asus_hides_smbus = 1;
1251 }
1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1253 switch (dev->subsystem_device) {
1254 case 0x1882: /* M6V notebook */
1255 case 0x1977: /* A6VA notebook */
1256 asus_hides_smbus = 1;
1257 }
1258 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1259 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1260 switch (dev->subsystem_device) {
1261 case 0x088C: /* HP Compaq nc8000 */
1262 case 0x0890: /* HP Compaq nc6000 */
1263 asus_hides_smbus = 1;
1264 }
1265 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1266 switch (dev->subsystem_device) {
1267 case 0x12bc: /* HP D330L */
1268 case 0x12bd: /* HP D530 */
1269 case 0x006a: /* HP Compaq nx9500 */
1270 asus_hides_smbus = 1;
1271 }
1272 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1273 switch (dev->subsystem_device) {
1274 case 0x12bf: /* HP xw4100 */
1275 asus_hides_smbus = 1;
1276 }
1277 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1278 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1279 switch (dev->subsystem_device) {
1280 case 0xC00C: /* Samsung P35 notebook */
1281 asus_hides_smbus = 1;
1282 }
1283 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1284 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1285 switch (dev->subsystem_device) {
1286 case 0x0058: /* Compaq Evo N620c */
1287 asus_hides_smbus = 1;
1288 }
1289 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1290 switch (dev->subsystem_device) {
1291 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1292 /* Motherboard doesn't have Host bridge
1293 * subvendor/subdevice IDs, therefore checking
1294 * its on-board VGA controller */
1295 asus_hides_smbus = 1;
1296 }
1297 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1298 switch (dev->subsystem_device) {
1299 case 0x00b8: /* Compaq Evo D510 CMT */
1300 case 0x00b9: /* Compaq Evo D510 SFF */
1301 case 0x00ba: /* Compaq Evo D510 USDT */
1302 /* Motherboard doesn't have Host bridge
1303 * subvendor/subdevice IDs and on-board VGA
1304 * controller is disabled if an AGP card is
1305 * inserted, therefore checking USB UHCI
1306 * Controller #1 */
1307 asus_hides_smbus = 1;
1308 }
1309 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1310 switch (dev->subsystem_device) {
1311 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1312 /* Motherboard doesn't have host bridge
1313 * subvendor/subdevice IDs, therefore checking
1314 * its on-board VGA controller */
1315 asus_hides_smbus = 1;
1316 }
1317 }
1318 }
1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1329
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1333
1334 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1335 {
1336 u16 val;
1337
1338 if (likely(!asus_hides_smbus))
1339 return;
1340
1341 pci_read_config_word(dev, 0xF2, &val);
1342 if (val & 0x8) {
1343 pci_write_config_word(dev, 0xF2, val & (~0x8));
1344 pci_read_config_word(dev, 0xF2, &val);
1345 if (val & 0x8)
1346 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1347 val);
1348 else
1349 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1350 }
1351 }
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1359 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1360 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1361 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1362 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1363 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1364 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1365 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1366
1367 /* It appears we just have one such device. If not, we have a warning */
1368 static void __iomem *asus_rcba_base;
1369 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1370 {
1371 u32 rcba;
1372
1373 if (likely(!asus_hides_smbus))
1374 return;
1375 WARN_ON(asus_rcba_base);
1376
1377 pci_read_config_dword(dev, 0xF0, &rcba);
1378 /* use bits 31:14, 16 kB aligned */
1379 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1380 if (asus_rcba_base == NULL)
1381 return;
1382 }
1383
1384 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1385 {
1386 u32 val;
1387
1388 if (likely(!asus_hides_smbus || !asus_rcba_base))
1389 return;
1390 /* read the Function Disable register, dword mode only */
1391 val = readl(asus_rcba_base + 0x3418);
1392 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1393 }
1394
1395 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1396 {
1397 if (likely(!asus_hides_smbus || !asus_rcba_base))
1398 return;
1399 iounmap(asus_rcba_base);
1400 asus_rcba_base = NULL;
1401 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1402 }
1403
1404 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1405 {
1406 asus_hides_smbus_lpc_ich6_suspend(dev);
1407 asus_hides_smbus_lpc_ich6_resume_early(dev);
1408 asus_hides_smbus_lpc_ich6_resume(dev);
1409 }
1410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1411 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1412 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1413 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1414
1415 /*
1416 * SiS 96x south bridge: BIOS typically hides SMBus device...
1417 */
1418 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1419 {
1420 u8 val = 0;
1421 pci_read_config_byte(dev, 0x77, &val);
1422 if (val & 0x10) {
1423 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1424 pci_write_config_byte(dev, 0x77, val & ~0x10);
1425 }
1426 }
1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1430 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1431 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1432 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1433 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1434 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1435
1436 /*
1437 * ... This is further complicated by the fact that some SiS96x south
1438 * bridges pretend to be 85C503/5513 instead. In that case see if we
1439 * spotted a compatible north bridge to make sure.
1440 * (pci_find_device doesn't work yet)
1441 *
1442 * We can also enable the sis96x bit in the discovery register..
1443 */
1444 #define SIS_DETECT_REGISTER 0x40
1445
1446 static void quirk_sis_503(struct pci_dev *dev)
1447 {
1448 u8 reg;
1449 u16 devid;
1450
1451 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1452 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1453 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1454 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1455 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1456 return;
1457 }
1458
1459 /*
1460 * Ok, it now shows up as a 96x.. run the 96x quirk by
1461 * hand in case it has already been processed.
1462 * (depends on link order, which is apparently not guaranteed)
1463 */
1464 dev->device = devid;
1465 quirk_sis_96x_smbus(dev);
1466 }
1467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1468 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1469
1470
1471 /*
1472 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1473 * and MC97 modem controller are disabled when a second PCI soundcard is
1474 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1475 * -- bjd
1476 */
1477 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1478 {
1479 u8 val;
1480 int asus_hides_ac97 = 0;
1481
1482 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1483 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1484 asus_hides_ac97 = 1;
1485 }
1486
1487 if (!asus_hides_ac97)
1488 return;
1489
1490 pci_read_config_byte(dev, 0x50, &val);
1491 if (val & 0xc0) {
1492 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1493 pci_read_config_byte(dev, 0x50, &val);
1494 if (val & 0xc0)
1495 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1496 val);
1497 else
1498 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1499 }
1500 }
1501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1502 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1503
1504 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1505
1506 /*
1507 * If we are using libata we can drive this chip properly but must
1508 * do this early on to make the additional device appear during
1509 * the PCI scanning.
1510 */
1511 static void quirk_jmicron_ata(struct pci_dev *pdev)
1512 {
1513 u32 conf1, conf5, class;
1514 u8 hdr;
1515
1516 /* Only poke fn 0 */
1517 if (PCI_FUNC(pdev->devfn))
1518 return;
1519
1520 pci_read_config_dword(pdev, 0x40, &conf1);
1521 pci_read_config_dword(pdev, 0x80, &conf5);
1522
1523 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1524 conf5 &= ~(1 << 24); /* Clear bit 24 */
1525
1526 switch (pdev->device) {
1527 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1528 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1529 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1530 /* The controller should be in single function ahci mode */
1531 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1532 break;
1533
1534 case PCI_DEVICE_ID_JMICRON_JMB365:
1535 case PCI_DEVICE_ID_JMICRON_JMB366:
1536 /* Redirect IDE second PATA port to the right spot */
1537 conf5 |= (1 << 24);
1538 /* Fall through */
1539 case PCI_DEVICE_ID_JMICRON_JMB361:
1540 case PCI_DEVICE_ID_JMICRON_JMB363:
1541 case PCI_DEVICE_ID_JMICRON_JMB369:
1542 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1543 /* Set the class codes correctly and then direct IDE 0 */
1544 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1545 break;
1546
1547 case PCI_DEVICE_ID_JMICRON_JMB368:
1548 /* The controller should be in single function IDE mode */
1549 conf1 |= 0x00C00000; /* Set 22, 23 */
1550 break;
1551 }
1552
1553 pci_write_config_dword(pdev, 0x40, conf1);
1554 pci_write_config_dword(pdev, 0x80, conf5);
1555
1556 /* Update pdev accordingly */
1557 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1558 pdev->hdr_type = hdr & 0x7f;
1559 pdev->multifunction = !!(hdr & 0x80);
1560
1561 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1562 pdev->class = class >> 8;
1563 }
1564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1567 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1568 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1569 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1570 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1571 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1572 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1576 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1577 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1582
1583 #endif
1584
1585 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1586 {
1587 if (dev->multifunction) {
1588 device_disable_async_suspend(&dev->dev);
1589 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1590 }
1591 }
1592 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1593 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1596
1597 #ifdef CONFIG_X86_IO_APIC
1598 static void quirk_alder_ioapic(struct pci_dev *pdev)
1599 {
1600 int i;
1601
1602 if ((pdev->class >> 8) != 0xff00)
1603 return;
1604
1605 /* the first BAR is the location of the IO APIC...we must
1606 * not touch this (and it's already covered by the fixmap), so
1607 * forcibly insert it into the resource tree */
1608 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1609 insert_resource(&iomem_resource, &pdev->resource[0]);
1610
1611 /* The next five BARs all seem to be rubbish, so just clean
1612 * them out */
1613 for (i = 1; i < 6; i++)
1614 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1615 }
1616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1617 #endif
1618
1619 static void quirk_pcie_mch(struct pci_dev *pdev)
1620 {
1621 pdev->no_msi = 1;
1622 }
1623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1626
1627
1628 /*
1629 * It's possible for the MSI to get corrupted if shpc and acpi
1630 * are used together on certain PXH-based systems.
1631 */
1632 static void quirk_pcie_pxh(struct pci_dev *dev)
1633 {
1634 dev->no_msi = 1;
1635 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1636 }
1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1638 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1639 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1641 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1642
1643 /*
1644 * Some Intel PCI Express chipsets have trouble with downstream
1645 * device power management.
1646 */
1647 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1648 {
1649 pci_pm_d3_delay = 120;
1650 dev->no_d1d2 = 1;
1651 }
1652
1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1674
1675 #ifdef CONFIG_X86_IO_APIC
1676 /*
1677 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1678 * remap the original interrupt in the linux kernel to the boot interrupt, so
1679 * that a PCI device's interrupt handler is installed on the boot interrupt
1680 * line instead.
1681 */
1682 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1683 {
1684 if (noioapicquirk || noioapicreroute)
1685 return;
1686
1687 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1688 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1689 dev->vendor, dev->device);
1690 }
1691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1699 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1700 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1701 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1702 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1703 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1704 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1705 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1706 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1707
1708 /*
1709 * On some chipsets we can disable the generation of legacy INTx boot
1710 * interrupts.
1711 */
1712
1713 /*
1714 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1715 * 300641-004US, section 5.7.3.
1716 */
1717 #define INTEL_6300_IOAPIC_ABAR 0x40
1718 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1719
1720 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1721 {
1722 u16 pci_config_word;
1723
1724 if (noioapicquirk)
1725 return;
1726
1727 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1728 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1729 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1730
1731 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1732 dev->vendor, dev->device);
1733 }
1734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1735 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1736
1737 /*
1738 * disable boot interrupts on HT-1000
1739 */
1740 #define BC_HT1000_FEATURE_REG 0x64
1741 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1742 #define BC_HT1000_MAP_IDX 0xC00
1743 #define BC_HT1000_MAP_DATA 0xC01
1744
1745 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1746 {
1747 u32 pci_config_dword;
1748 u8 irq;
1749
1750 if (noioapicquirk)
1751 return;
1752
1753 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1754 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1755 BC_HT1000_PIC_REGS_ENABLE);
1756
1757 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1758 outb(irq, BC_HT1000_MAP_IDX);
1759 outb(0x00, BC_HT1000_MAP_DATA);
1760 }
1761
1762 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1763
1764 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1765 dev->vendor, dev->device);
1766 }
1767 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1768 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1769
1770 /*
1771 * disable boot interrupts on AMD and ATI chipsets
1772 */
1773 /*
1774 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1775 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1776 * (due to an erratum).
1777 */
1778 #define AMD_813X_MISC 0x40
1779 #define AMD_813X_NOIOAMODE (1<<0)
1780 #define AMD_813X_REV_B1 0x12
1781 #define AMD_813X_REV_B2 0x13
1782
1783 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1784 {
1785 u32 pci_config_dword;
1786
1787 if (noioapicquirk)
1788 return;
1789 if ((dev->revision == AMD_813X_REV_B1) ||
1790 (dev->revision == AMD_813X_REV_B2))
1791 return;
1792
1793 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1794 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1795 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1796
1797 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1798 dev->vendor, dev->device);
1799 }
1800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1801 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1803 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1804
1805 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1806
1807 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1808 {
1809 u16 pci_config_word;
1810
1811 if (noioapicquirk)
1812 return;
1813
1814 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1815 if (!pci_config_word) {
1816 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1817 dev->vendor, dev->device);
1818 return;
1819 }
1820 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1821 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1822 dev->vendor, dev->device);
1823 }
1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1825 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1826 #endif /* CONFIG_X86_IO_APIC */
1827
1828 /*
1829 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1830 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1831 * Re-allocate the region if needed...
1832 */
1833 static void quirk_tc86c001_ide(struct pci_dev *dev)
1834 {
1835 struct resource *r = &dev->resource[0];
1836
1837 if (r->start & 0x8) {
1838 r->flags |= IORESOURCE_UNSET;
1839 r->start = 0;
1840 r->end = 0xf;
1841 }
1842 }
1843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1844 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1845 quirk_tc86c001_ide);
1846
1847 /*
1848 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1849 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1850 * being read correctly if bit 7 of the base address is set.
1851 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1852 * Re-allocate the regions to a 256-byte boundary if necessary.
1853 */
1854 static void quirk_plx_pci9050(struct pci_dev *dev)
1855 {
1856 unsigned int bar;
1857
1858 /* Fixed in revision 2 (PCI 9052). */
1859 if (dev->revision >= 2)
1860 return;
1861 for (bar = 0; bar <= 1; bar++)
1862 if (pci_resource_len(dev, bar) == 0x80 &&
1863 (pci_resource_start(dev, bar) & 0x80)) {
1864 struct resource *r = &dev->resource[bar];
1865 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1866 bar);
1867 r->flags |= IORESOURCE_UNSET;
1868 r->start = 0;
1869 r->end = 0xff;
1870 }
1871 }
1872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1873 quirk_plx_pci9050);
1874 /*
1875 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1876 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1877 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1878 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1879 *
1880 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1881 * driver.
1882 */
1883 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1884 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1885
1886 static void quirk_netmos(struct pci_dev *dev)
1887 {
1888 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1889 unsigned int num_serial = dev->subsystem_device & 0xf;
1890
1891 /*
1892 * These Netmos parts are multiport serial devices with optional
1893 * parallel ports. Even when parallel ports are present, they
1894 * are identified as class SERIAL, which means the serial driver
1895 * will claim them. To prevent this, mark them as class OTHER.
1896 * These combo devices should be claimed by parport_serial.
1897 *
1898 * The subdevice ID is of the form 0x00PS, where <P> is the number
1899 * of parallel ports and <S> is the number of serial ports.
1900 */
1901 switch (dev->device) {
1902 case PCI_DEVICE_ID_NETMOS_9835:
1903 /* Well, this rule doesn't hold for the following 9835 device */
1904 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1905 dev->subsystem_device == 0x0299)
1906 return;
1907 case PCI_DEVICE_ID_NETMOS_9735:
1908 case PCI_DEVICE_ID_NETMOS_9745:
1909 case PCI_DEVICE_ID_NETMOS_9845:
1910 case PCI_DEVICE_ID_NETMOS_9855:
1911 if (num_parallel) {
1912 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1913 dev->device, num_parallel, num_serial);
1914 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1915 (dev->class & 0xff);
1916 }
1917 }
1918 }
1919 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1920 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1921
1922 /*
1923 * Quirk non-zero PCI functions to route VPD access through function 0 for
1924 * devices that share VPD resources between functions. The functions are
1925 * expected to be identical devices.
1926 */
1927 static void quirk_f0_vpd_link(struct pci_dev *dev)
1928 {
1929 struct pci_dev *f0;
1930
1931 if (!PCI_FUNC(dev->devfn))
1932 return;
1933
1934 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1935 if (!f0)
1936 return;
1937
1938 if (f0->vpd && dev->class == f0->class &&
1939 dev->vendor == f0->vendor && dev->device == f0->device)
1940 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1941
1942 pci_dev_put(f0);
1943 }
1944 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1945 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1946
1947 static void quirk_e100_interrupt(struct pci_dev *dev)
1948 {
1949 u16 command, pmcsr;
1950 u8 __iomem *csr;
1951 u8 cmd_hi;
1952
1953 switch (dev->device) {
1954 /* PCI IDs taken from drivers/net/e100.c */
1955 case 0x1029:
1956 case 0x1030 ... 0x1034:
1957 case 0x1038 ... 0x103E:
1958 case 0x1050 ... 0x1057:
1959 case 0x1059:
1960 case 0x1064 ... 0x106B:
1961 case 0x1091 ... 0x1095:
1962 case 0x1209:
1963 case 0x1229:
1964 case 0x2449:
1965 case 0x2459:
1966 case 0x245D:
1967 case 0x27DC:
1968 break;
1969 default:
1970 return;
1971 }
1972
1973 /*
1974 * Some firmware hands off the e100 with interrupts enabled,
1975 * which can cause a flood of interrupts if packets are
1976 * received before the driver attaches to the device. So
1977 * disable all e100 interrupts here. The driver will
1978 * re-enable them when it's ready.
1979 */
1980 pci_read_config_word(dev, PCI_COMMAND, &command);
1981
1982 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1983 return;
1984
1985 /*
1986 * Check that the device is in the D0 power state. If it's not,
1987 * there is no point to look any further.
1988 */
1989 if (dev->pm_cap) {
1990 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1991 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1992 return;
1993 }
1994
1995 /* Convert from PCI bus to resource space. */
1996 csr = ioremap(pci_resource_start(dev, 0), 8);
1997 if (!csr) {
1998 dev_warn(&dev->dev, "Can't map e100 registers\n");
1999 return;
2000 }
2001
2002 cmd_hi = readb(csr + 3);
2003 if (cmd_hi == 0) {
2004 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2005 writeb(1, csr + 3);
2006 }
2007
2008 iounmap(csr);
2009 }
2010 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2011 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2012
2013 /*
2014 * The 82575 and 82598 may experience data corruption issues when transitioning
2015 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2016 */
2017 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2018 {
2019 dev_info(&dev->dev, "Disabling L0s\n");
2020 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2021 }
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2036
2037 static void fixup_rev1_53c810(struct pci_dev *dev)
2038 {
2039 u32 class = dev->class;
2040
2041 /*
2042 * rev 1 ncr53c810 chips don't set the class at all which means
2043 * they don't get their resources remapped. Fix that here.
2044 */
2045 if (class)
2046 return;
2047
2048 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2049 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2050 class, dev->class);
2051 }
2052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2053
2054 /* Enable 1k I/O space granularity on the Intel P64H2 */
2055 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2056 {
2057 u16 en1k;
2058
2059 pci_read_config_word(dev, 0x40, &en1k);
2060
2061 if (en1k & 0x200) {
2062 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2063 dev->io_window_1k = 1;
2064 }
2065 }
2066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2067
2068 /* Under some circumstances, AER is not linked with extended capabilities.
2069 * Force it to be linked by setting the corresponding control bit in the
2070 * config space.
2071 */
2072 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2073 {
2074 uint8_t b;
2075 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2076 if (!(b & 0x20)) {
2077 pci_write_config_byte(dev, 0xf41, b | 0x20);
2078 dev_info(&dev->dev, "Linking AER extended capability\n");
2079 }
2080 }
2081 }
2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2083 quirk_nvidia_ck804_pcie_aer_ext_cap);
2084 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2085 quirk_nvidia_ck804_pcie_aer_ext_cap);
2086
2087 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2088 {
2089 /*
2090 * Disable PCI Bus Parking and PCI Master read caching on CX700
2091 * which causes unspecified timing errors with a VT6212L on the PCI
2092 * bus leading to USB2.0 packet loss.
2093 *
2094 * This quirk is only enabled if a second (on the external PCI bus)
2095 * VT6212L is found -- the CX700 core itself also contains a USB
2096 * host controller with the same PCI ID as the VT6212L.
2097 */
2098
2099 /* Count VT6212L instances */
2100 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2101 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2102 uint8_t b;
2103
2104 /* p should contain the first (internal) VT6212L -- see if we have
2105 an external one by searching again */
2106 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2107 if (!p)
2108 return;
2109 pci_dev_put(p);
2110
2111 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2112 if (b & 0x40) {
2113 /* Turn off PCI Bus Parking */
2114 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2115
2116 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2117 }
2118 }
2119
2120 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2121 if (b != 0) {
2122 /* Turn off PCI Master read caching */
2123 pci_write_config_byte(dev, 0x72, 0x0);
2124
2125 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2126 pci_write_config_byte(dev, 0x75, 0x1);
2127
2128 /* Disable "Read FIFO Timer" */
2129 pci_write_config_byte(dev, 0x77, 0x0);
2130
2131 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2132 }
2133 }
2134 }
2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2136
2137 /*
2138 * If a device follows the VPD format spec, the PCI core will not read or
2139 * write past the VPD End Tag. But some vendors do not follow the VPD
2140 * format spec, so we can't tell how much data is safe to access. Devices
2141 * may behave unpredictably if we access too much. Blacklist these devices
2142 * so we don't touch VPD at all.
2143 */
2144 static void quirk_blacklist_vpd(struct pci_dev *dev)
2145 {
2146 if (dev->vpd) {
2147 dev->vpd->len = 0;
2148 dev_warn(&dev->dev, FW_BUG "VPD access disabled\n");
2149 }
2150 }
2151
2152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2164 quirk_blacklist_vpd);
2165
2166 /*
2167 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2168 * VPD end tag will hang the device. This problem was initially
2169 * observed when a vpd entry was created in sysfs
2170 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2171 * will dump 32k of data. Reading a full 32k will cause an access
2172 * beyond the VPD end tag causing the device to hang. Once the device
2173 * is hung, the bnx2 driver will not be able to reset the device.
2174 * We believe that it is legal to read beyond the end tag and
2175 * therefore the solution is to limit the read/write length.
2176 */
2177 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2178 {
2179 /*
2180 * Only disable the VPD capability for 5706, 5706S, 5708,
2181 * 5708S and 5709 rev. A
2182 */
2183 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2184 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2185 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2186 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2187 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2188 (dev->revision & 0xf0) == 0x0)) {
2189 if (dev->vpd)
2190 dev->vpd->len = 0x80;
2191 }
2192 }
2193
2194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2195 PCI_DEVICE_ID_NX2_5706,
2196 quirk_brcm_570x_limit_vpd);
2197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2198 PCI_DEVICE_ID_NX2_5706S,
2199 quirk_brcm_570x_limit_vpd);
2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2201 PCI_DEVICE_ID_NX2_5708,
2202 quirk_brcm_570x_limit_vpd);
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2204 PCI_DEVICE_ID_NX2_5708S,
2205 quirk_brcm_570x_limit_vpd);
2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2207 PCI_DEVICE_ID_NX2_5709,
2208 quirk_brcm_570x_limit_vpd);
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2210 PCI_DEVICE_ID_NX2_5709S,
2211 quirk_brcm_570x_limit_vpd);
2212
2213 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2214 {
2215 u32 rev;
2216
2217 pci_read_config_dword(dev, 0xf4, &rev);
2218
2219 /* Only CAP the MRRS if the device is a 5719 A0 */
2220 if (rev == 0x05719000) {
2221 int readrq = pcie_get_readrq(dev);
2222 if (readrq > 2048)
2223 pcie_set_readrq(dev, 2048);
2224 }
2225 }
2226
2227 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2228 PCI_DEVICE_ID_TIGON3_5719,
2229 quirk_brcm_5719_limit_mrrs);
2230
2231 /* Originally in EDAC sources for i82875P:
2232 * Intel tells BIOS developers to hide device 6 which
2233 * configures the overflow device access containing
2234 * the DRBs - this is where we expose device 6.
2235 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2236 */
2237 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2238 {
2239 u8 reg;
2240
2241 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2242 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2243 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2244 }
2245 }
2246
2247 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2248 quirk_unhide_mch_dev6);
2249 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2250 quirk_unhide_mch_dev6);
2251
2252 #ifdef CONFIG_TILEPRO
2253 /*
2254 * The Tilera TILEmpower tilepro platform needs to set the link speed
2255 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2256 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2257 * capability register of the PEX8624 PCIe switch. The switch
2258 * supports link speed auto negotiation, but falsely sets
2259 * the link speed to 5GT/s.
2260 */
2261 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2262 {
2263 if (tile_plx_gen1) {
2264 pci_write_config_dword(dev, 0x98, 0x1);
2265 mdelay(50);
2266 }
2267 }
2268 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2269 #endif /* CONFIG_TILEPRO */
2270
2271 #ifdef CONFIG_PCI_MSI
2272 /* Some chipsets do not support MSI. We cannot easily rely on setting
2273 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2274 * some other buses controlled by the chipset even if Linux is not
2275 * aware of it. Instead of setting the flag on all buses in the
2276 * machine, simply disable MSI globally.
2277 */
2278 static void quirk_disable_all_msi(struct pci_dev *dev)
2279 {
2280 pci_no_msi();
2281 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2282 }
2283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2291
2292 /* Disable MSI on chipsets that are known to not support it */
2293 static void quirk_disable_msi(struct pci_dev *dev)
2294 {
2295 if (dev->subordinate) {
2296 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2297 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2298 }
2299 }
2300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2303
2304 /*
2305 * The APC bridge device in AMD 780 family northbridges has some random
2306 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2307 * we use the possible vendor/device IDs of the host bridge for the
2308 * declared quirk, and search for the APC bridge by slot number.
2309 */
2310 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2311 {
2312 struct pci_dev *apc_bridge;
2313
2314 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2315 if (apc_bridge) {
2316 if (apc_bridge->device == 0x9602)
2317 quirk_disable_msi(apc_bridge);
2318 pci_dev_put(apc_bridge);
2319 }
2320 }
2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2323
2324 /* Go through the list of Hypertransport capabilities and
2325 * return 1 if a HT MSI capability is found and enabled */
2326 static int msi_ht_cap_enabled(struct pci_dev *dev)
2327 {
2328 int pos, ttl = PCI_FIND_CAP_TTL;
2329
2330 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2331 while (pos && ttl--) {
2332 u8 flags;
2333
2334 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2335 &flags) == 0) {
2336 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2337 flags & HT_MSI_FLAGS_ENABLE ?
2338 "enabled" : "disabled");
2339 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2340 }
2341
2342 pos = pci_find_next_ht_capability(dev, pos,
2343 HT_CAPTYPE_MSI_MAPPING);
2344 }
2345 return 0;
2346 }
2347
2348 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2349 static void quirk_msi_ht_cap(struct pci_dev *dev)
2350 {
2351 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2352 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2353 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2354 }
2355 }
2356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2357 quirk_msi_ht_cap);
2358
2359 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2360 * MSI are supported if the MSI capability set in any of these mappings.
2361 */
2362 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2363 {
2364 struct pci_dev *pdev;
2365
2366 if (!dev->subordinate)
2367 return;
2368
2369 /* check HT MSI cap on this chipset and the root one.
2370 * a single one having MSI is enough to be sure that MSI are supported.
2371 */
2372 pdev = pci_get_slot(dev->bus, 0);
2373 if (!pdev)
2374 return;
2375 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2376 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2377 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2378 }
2379 pci_dev_put(pdev);
2380 }
2381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2382 quirk_nvidia_ck804_msi_ht_cap);
2383
2384 /* Force enable MSI mapping capability on HT bridges */
2385 static void ht_enable_msi_mapping(struct pci_dev *dev)
2386 {
2387 int pos, ttl = PCI_FIND_CAP_TTL;
2388
2389 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2390 while (pos && ttl--) {
2391 u8 flags;
2392
2393 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2394 &flags) == 0) {
2395 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2396
2397 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2398 flags | HT_MSI_FLAGS_ENABLE);
2399 }
2400 pos = pci_find_next_ht_capability(dev, pos,
2401 HT_CAPTYPE_MSI_MAPPING);
2402 }
2403 }
2404 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2405 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2406 ht_enable_msi_mapping);
2407
2408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2409 ht_enable_msi_mapping);
2410
2411 /* The P5N32-SLI motherboards from Asus have a problem with msi
2412 * for the MCP55 NIC. It is not yet determined whether the msi problem
2413 * also affects other devices. As for now, turn off msi for this device.
2414 */
2415 static void nvenet_msi_disable(struct pci_dev *dev)
2416 {
2417 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2418
2419 if (board_name &&
2420 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2421 strstr(board_name, "P5N32-E SLI"))) {
2422 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2423 dev->no_msi = 1;
2424 }
2425 }
2426 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2427 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2428 nvenet_msi_disable);
2429
2430 /*
2431 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2432 * config register. This register controls the routing of legacy
2433 * interrupts from devices that route through the MCP55. If this register
2434 * is misprogrammed, interrupts are only sent to the BSP, unlike
2435 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2436 * having this register set properly prevents kdump from booting up
2437 * properly, so let's make sure that we have it set correctly.
2438 * Note that this is an undocumented register.
2439 */
2440 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2441 {
2442 u32 cfg;
2443
2444 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2445 return;
2446
2447 pci_read_config_dword(dev, 0x74, &cfg);
2448
2449 if (cfg & ((1 << 2) | (1 << 15))) {
2450 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2451 cfg &= ~((1 << 2) | (1 << 15));
2452 pci_write_config_dword(dev, 0x74, cfg);
2453 }
2454 }
2455
2456 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2457 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2458 nvbridge_check_legacy_irq_routing);
2459
2460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2461 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2462 nvbridge_check_legacy_irq_routing);
2463
2464 static int ht_check_msi_mapping(struct pci_dev *dev)
2465 {
2466 int pos, ttl = PCI_FIND_CAP_TTL;
2467 int found = 0;
2468
2469 /* check if there is HT MSI cap or enabled on this device */
2470 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2471 while (pos && ttl--) {
2472 u8 flags;
2473
2474 if (found < 1)
2475 found = 1;
2476 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2477 &flags) == 0) {
2478 if (flags & HT_MSI_FLAGS_ENABLE) {
2479 if (found < 2) {
2480 found = 2;
2481 break;
2482 }
2483 }
2484 }
2485 pos = pci_find_next_ht_capability(dev, pos,
2486 HT_CAPTYPE_MSI_MAPPING);
2487 }
2488
2489 return found;
2490 }
2491
2492 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2493 {
2494 struct pci_dev *dev;
2495 int pos;
2496 int i, dev_no;
2497 int found = 0;
2498
2499 dev_no = host_bridge->devfn >> 3;
2500 for (i = dev_no + 1; i < 0x20; i++) {
2501 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2502 if (!dev)
2503 continue;
2504
2505 /* found next host bridge ?*/
2506 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2507 if (pos != 0) {
2508 pci_dev_put(dev);
2509 break;
2510 }
2511
2512 if (ht_check_msi_mapping(dev)) {
2513 found = 1;
2514 pci_dev_put(dev);
2515 break;
2516 }
2517 pci_dev_put(dev);
2518 }
2519
2520 return found;
2521 }
2522
2523 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2524 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2525
2526 static int is_end_of_ht_chain(struct pci_dev *dev)
2527 {
2528 int pos, ctrl_off;
2529 int end = 0;
2530 u16 flags, ctrl;
2531
2532 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2533
2534 if (!pos)
2535 goto out;
2536
2537 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2538
2539 ctrl_off = ((flags >> 10) & 1) ?
2540 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2541 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2542
2543 if (ctrl & (1 << 6))
2544 end = 1;
2545
2546 out:
2547 return end;
2548 }
2549
2550 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2551 {
2552 struct pci_dev *host_bridge;
2553 int pos;
2554 int i, dev_no;
2555 int found = 0;
2556
2557 dev_no = dev->devfn >> 3;
2558 for (i = dev_no; i >= 0; i--) {
2559 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2560 if (!host_bridge)
2561 continue;
2562
2563 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2564 if (pos != 0) {
2565 found = 1;
2566 break;
2567 }
2568 pci_dev_put(host_bridge);
2569 }
2570
2571 if (!found)
2572 return;
2573
2574 /* don't enable end_device/host_bridge with leaf directly here */
2575 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2576 host_bridge_with_leaf(host_bridge))
2577 goto out;
2578
2579 /* root did that ! */
2580 if (msi_ht_cap_enabled(host_bridge))
2581 goto out;
2582
2583 ht_enable_msi_mapping(dev);
2584
2585 out:
2586 pci_dev_put(host_bridge);
2587 }
2588
2589 static void ht_disable_msi_mapping(struct pci_dev *dev)
2590 {
2591 int pos, ttl = PCI_FIND_CAP_TTL;
2592
2593 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2594 while (pos && ttl--) {
2595 u8 flags;
2596
2597 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2598 &flags) == 0) {
2599 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2600
2601 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2602 flags & ~HT_MSI_FLAGS_ENABLE);
2603 }
2604 pos = pci_find_next_ht_capability(dev, pos,
2605 HT_CAPTYPE_MSI_MAPPING);
2606 }
2607 }
2608
2609 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2610 {
2611 struct pci_dev *host_bridge;
2612 int pos;
2613 int found;
2614
2615 if (!pci_msi_enabled())
2616 return;
2617
2618 /* check if there is HT MSI cap or enabled on this device */
2619 found = ht_check_msi_mapping(dev);
2620
2621 /* no HT MSI CAP */
2622 if (found == 0)
2623 return;
2624
2625 /*
2626 * HT MSI mapping should be disabled on devices that are below
2627 * a non-Hypertransport host bridge. Locate the host bridge...
2628 */
2629 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2630 if (host_bridge == NULL) {
2631 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2632 return;
2633 }
2634
2635 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2636 if (pos != 0) {
2637 /* Host bridge is to HT */
2638 if (found == 1) {
2639 /* it is not enabled, try to enable it */
2640 if (all)
2641 ht_enable_msi_mapping(dev);
2642 else
2643 nv_ht_enable_msi_mapping(dev);
2644 }
2645 goto out;
2646 }
2647
2648 /* HT MSI is not enabled */
2649 if (found == 1)
2650 goto out;
2651
2652 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2653 ht_disable_msi_mapping(dev);
2654
2655 out:
2656 pci_dev_put(host_bridge);
2657 }
2658
2659 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2660 {
2661 return __nv_msi_ht_cap_quirk(dev, 1);
2662 }
2663
2664 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2665 {
2666 return __nv_msi_ht_cap_quirk(dev, 0);
2667 }
2668
2669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2670 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2671
2672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2673 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2674
2675 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2676 {
2677 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2678 }
2679 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2680 {
2681 struct pci_dev *p;
2682
2683 /* SB700 MSI issue will be fixed at HW level from revision A21,
2684 * we need check PCI REVISION ID of SMBus controller to get SB700
2685 * revision.
2686 */
2687 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2688 NULL);
2689 if (!p)
2690 return;
2691
2692 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2693 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2694 pci_dev_put(p);
2695 }
2696 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2697 {
2698 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2699 if (dev->revision < 0x18) {
2700 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2701 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2702 }
2703 }
2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2705 PCI_DEVICE_ID_TIGON3_5780,
2706 quirk_msi_intx_disable_bug);
2707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2708 PCI_DEVICE_ID_TIGON3_5780S,
2709 quirk_msi_intx_disable_bug);
2710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2711 PCI_DEVICE_ID_TIGON3_5714,
2712 quirk_msi_intx_disable_bug);
2713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2714 PCI_DEVICE_ID_TIGON3_5714S,
2715 quirk_msi_intx_disable_bug);
2716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2717 PCI_DEVICE_ID_TIGON3_5715,
2718 quirk_msi_intx_disable_bug);
2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2720 PCI_DEVICE_ID_TIGON3_5715S,
2721 quirk_msi_intx_disable_bug);
2722
2723 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2724 quirk_msi_intx_disable_ati_bug);
2725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2726 quirk_msi_intx_disable_ati_bug);
2727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2728 quirk_msi_intx_disable_ati_bug);
2729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2730 quirk_msi_intx_disable_ati_bug);
2731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2732 quirk_msi_intx_disable_ati_bug);
2733
2734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2735 quirk_msi_intx_disable_bug);
2736 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2737 quirk_msi_intx_disable_bug);
2738 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2739 quirk_msi_intx_disable_bug);
2740
2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2742 quirk_msi_intx_disable_bug);
2743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2744 quirk_msi_intx_disable_bug);
2745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2746 quirk_msi_intx_disable_bug);
2747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2748 quirk_msi_intx_disable_bug);
2749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2750 quirk_msi_intx_disable_bug);
2751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2752 quirk_msi_intx_disable_bug);
2753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2754 quirk_msi_intx_disable_qca_bug);
2755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2756 quirk_msi_intx_disable_qca_bug);
2757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2758 quirk_msi_intx_disable_qca_bug);
2759 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2760 quirk_msi_intx_disable_qca_bug);
2761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2762 quirk_msi_intx_disable_qca_bug);
2763 #endif /* CONFIG_PCI_MSI */
2764
2765 /* Allow manual resource allocation for PCI hotplug bridges
2766 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2767 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2768 * kernel fails to allocate resources when hotplug device is
2769 * inserted and PCI bus is rescanned.
2770 */
2771 static void quirk_hotplug_bridge(struct pci_dev *dev)
2772 {
2773 dev->is_hotplug_bridge = 1;
2774 }
2775
2776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2777
2778 /*
2779 * This is a quirk for the Ricoh MMC controller found as a part of
2780 * some mulifunction chips.
2781
2782 * This is very similar and based on the ricoh_mmc driver written by
2783 * Philip Langdale. Thank you for these magic sequences.
2784 *
2785 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2786 * and one or both of cardbus or firewire.
2787 *
2788 * It happens that they implement SD and MMC
2789 * support as separate controllers (and PCI functions). The linux SDHCI
2790 * driver supports MMC cards but the chip detects MMC cards in hardware
2791 * and directs them to the MMC controller - so the SDHCI driver never sees
2792 * them.
2793 *
2794 * To get around this, we must disable the useless MMC controller.
2795 * At that point, the SDHCI controller will start seeing them
2796 * It seems to be the case that the relevant PCI registers to deactivate the
2797 * MMC controller live on PCI function 0, which might be the cardbus controller
2798 * or the firewire controller, depending on the particular chip in question
2799 *
2800 * This has to be done early, because as soon as we disable the MMC controller
2801 * other pci functions shift up one level, e.g. function #2 becomes function
2802 * #1, and this will confuse the pci core.
2803 */
2804
2805 #ifdef CONFIG_MMC_RICOH_MMC
2806 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2807 {
2808 /* disable via cardbus interface */
2809 u8 write_enable;
2810 u8 write_target;
2811 u8 disable;
2812
2813 /* disable must be done via function #0 */
2814 if (PCI_FUNC(dev->devfn))
2815 return;
2816
2817 pci_read_config_byte(dev, 0xB7, &disable);
2818 if (disable & 0x02)
2819 return;
2820
2821 pci_read_config_byte(dev, 0x8E, &write_enable);
2822 pci_write_config_byte(dev, 0x8E, 0xAA);
2823 pci_read_config_byte(dev, 0x8D, &write_target);
2824 pci_write_config_byte(dev, 0x8D, 0xB7);
2825 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2826 pci_write_config_byte(dev, 0x8E, write_enable);
2827 pci_write_config_byte(dev, 0x8D, write_target);
2828
2829 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2830 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2831 }
2832 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2833 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2834
2835 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2836 {
2837 /* disable via firewire interface */
2838 u8 write_enable;
2839 u8 disable;
2840
2841 /* disable must be done via function #0 */
2842 if (PCI_FUNC(dev->devfn))
2843 return;
2844 /*
2845 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2846 * certain types of SD/MMC cards. Lowering the SD base
2847 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2848 *
2849 * 0x150 - SD2.0 mode enable for changing base clock
2850 * frequency to 50Mhz
2851 * 0xe1 - Base clock frequency
2852 * 0x32 - 50Mhz new clock frequency
2853 * 0xf9 - Key register for 0x150
2854 * 0xfc - key register for 0xe1
2855 */
2856 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2857 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2858 pci_write_config_byte(dev, 0xf9, 0xfc);
2859 pci_write_config_byte(dev, 0x150, 0x10);
2860 pci_write_config_byte(dev, 0xf9, 0x00);
2861 pci_write_config_byte(dev, 0xfc, 0x01);
2862 pci_write_config_byte(dev, 0xe1, 0x32);
2863 pci_write_config_byte(dev, 0xfc, 0x00);
2864
2865 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2866 }
2867
2868 pci_read_config_byte(dev, 0xCB, &disable);
2869
2870 if (disable & 0x02)
2871 return;
2872
2873 pci_read_config_byte(dev, 0xCA, &write_enable);
2874 pci_write_config_byte(dev, 0xCA, 0x57);
2875 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2876 pci_write_config_byte(dev, 0xCA, write_enable);
2877
2878 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2879 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2880
2881 }
2882 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2883 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2884 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2885 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2886 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2887 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2888 #endif /*CONFIG_MMC_RICOH_MMC*/
2889
2890 #ifdef CONFIG_DMAR_TABLE
2891 #define VTUNCERRMSK_REG 0x1ac
2892 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2893 /*
2894 * This is a quirk for masking vt-d spec defined errors to platform error
2895 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2896 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2897 * on the RAS config settings of the platform) when a vt-d fault happens.
2898 * The resulting SMI caused the system to hang.
2899 *
2900 * VT-d spec related errors are already handled by the VT-d OS code, so no
2901 * need to report the same error through other channels.
2902 */
2903 static void vtd_mask_spec_errors(struct pci_dev *dev)
2904 {
2905 u32 word;
2906
2907 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2908 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2909 }
2910 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2911 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2912 #endif
2913
2914 static void fixup_ti816x_class(struct pci_dev *dev)
2915 {
2916 u32 class = dev->class;
2917
2918 /* TI 816x devices do not have class code set when in PCIe boot mode */
2919 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2920 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2921 class, dev->class);
2922 }
2923 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2924 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2925
2926 /* Some PCIe devices do not work reliably with the claimed maximum
2927 * payload size supported.
2928 */
2929 static void fixup_mpss_256(struct pci_dev *dev)
2930 {
2931 dev->pcie_mpss = 1; /* 256 bytes */
2932 }
2933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2934 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2936 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2938 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2939
2940 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2941 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2942 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2943 * until all of the devices are discovered and buses walked, read completion
2944 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2945 * it is possible to hotplug a device with MPS of 256B.
2946 */
2947 static void quirk_intel_mc_errata(struct pci_dev *dev)
2948 {
2949 int err;
2950 u16 rcc;
2951
2952 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2953 pcie_bus_config == PCIE_BUS_DEFAULT)
2954 return;
2955
2956 /* Intel errata specifies bits to change but does not say what they are.
2957 * Keeping them magical until such time as the registers and values can
2958 * be explained.
2959 */
2960 err = pci_read_config_word(dev, 0x48, &rcc);
2961 if (err) {
2962 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
2963 return;
2964 }
2965
2966 if (!(rcc & (1 << 10)))
2967 return;
2968
2969 rcc &= ~(1 << 10);
2970
2971 err = pci_write_config_word(dev, 0x48, rcc);
2972 if (err) {
2973 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
2974 return;
2975 }
2976
2977 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2978 }
2979 /* Intel 5000 series memory controllers and ports 2-7 */
2980 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2983 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2994 /* Intel 5100 series memory controllers and ports 2-7 */
2995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3006
3007
3008 /*
3009 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3010 * work around this, query the size it should be configured to by the device and
3011 * modify the resource end to correspond to this new size.
3012 */
3013 static void quirk_intel_ntb(struct pci_dev *dev)
3014 {
3015 int rc;
3016 u8 val;
3017
3018 rc = pci_read_config_byte(dev, 0x00D0, &val);
3019 if (rc)
3020 return;
3021
3022 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3023
3024 rc = pci_read_config_byte(dev, 0x00D1, &val);
3025 if (rc)
3026 return;
3027
3028 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3029 }
3030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3032
3033 static ktime_t fixup_debug_start(struct pci_dev *dev,
3034 void (*fn)(struct pci_dev *dev))
3035 {
3036 ktime_t calltime = ktime_set(0, 0);
3037
3038 dev_dbg(&dev->dev, "calling %pF\n", fn);
3039 if (initcall_debug) {
3040 pr_debug("calling %pF @ %i for %s\n",
3041 fn, task_pid_nr(current), dev_name(&dev->dev));
3042 calltime = ktime_get();
3043 }
3044
3045 return calltime;
3046 }
3047
3048 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3049 void (*fn)(struct pci_dev *dev))
3050 {
3051 ktime_t delta, rettime;
3052 unsigned long long duration;
3053
3054 if (initcall_debug) {
3055 rettime = ktime_get();
3056 delta = ktime_sub(rettime, calltime);
3057 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3058 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3059 fn, duration, dev_name(&dev->dev));
3060 }
3061 }
3062
3063 /*
3064 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3065 * even though no one is handling them (f.e. i915 driver is never loaded).
3066 * Additionally the interrupt destination is not set up properly
3067 * and the interrupt ends up -somewhere-.
3068 *
3069 * These spurious interrupts are "sticky" and the kernel disables
3070 * the (shared) interrupt line after 100.000+ generated interrupts.
3071 *
3072 * Fix it by disabling the still enabled interrupts.
3073 * This resolves crashes often seen on monitor unplug.
3074 */
3075 #define I915_DEIER_REG 0x4400c
3076 static void disable_igfx_irq(struct pci_dev *dev)
3077 {
3078 void __iomem *regs = pci_iomap(dev, 0, 0);
3079 if (regs == NULL) {
3080 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3081 return;
3082 }
3083
3084 /* Check if any interrupt line is still enabled */
3085 if (readl(regs + I915_DEIER_REG) != 0) {
3086 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3087
3088 writel(0, regs + I915_DEIER_REG);
3089 }
3090
3091 pci_iounmap(dev, regs);
3092 }
3093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3096
3097 /*
3098 * PCI devices which are on Intel chips can skip the 10ms delay
3099 * before entering D3 mode.
3100 */
3101 static void quirk_remove_d3_delay(struct pci_dev *dev)
3102 {
3103 dev->d3_delay = 0;
3104 }
3105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3119 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3121 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3122 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3129 /*
3130 * Some devices may pass our check in pci_intx_mask_supported if
3131 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3132 * support this feature.
3133 */
3134 static void quirk_broken_intx_masking(struct pci_dev *dev)
3135 {
3136 dev->broken_intx_masking = 1;
3137 }
3138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
3139 quirk_broken_intx_masking);
3140 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3141 quirk_broken_intx_masking);
3142 /*
3143 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3144 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3145 *
3146 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3147 */
3148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3149 quirk_broken_intx_masking);
3150 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3151 quirk_broken_intx_masking);
3152
3153 /*
3154 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3155 * DisINTx can be set but the interrupt status bit is non-functional.
3156 */
3157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1572,
3158 quirk_broken_intx_masking);
3159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1574,
3160 quirk_broken_intx_masking);
3161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1580,
3162 quirk_broken_intx_masking);
3163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1581,
3164 quirk_broken_intx_masking);
3165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1583,
3166 quirk_broken_intx_masking);
3167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1584,
3168 quirk_broken_intx_masking);
3169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1585,
3170 quirk_broken_intx_masking);
3171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1586,
3172 quirk_broken_intx_masking);
3173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1587,
3174 quirk_broken_intx_masking);
3175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1588,
3176 quirk_broken_intx_masking);
3177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1589,
3178 quirk_broken_intx_masking);
3179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x37d0,
3180 quirk_broken_intx_masking);
3181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x37d1,
3182 quirk_broken_intx_masking);
3183 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x37d2,
3184 quirk_broken_intx_masking);
3185
3186 static void quirk_no_bus_reset(struct pci_dev *dev)
3187 {
3188 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3189 }
3190
3191 /*
3192 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3193 * The device will throw a Link Down error on AER-capable systems and
3194 * regardless of AER, config space of the device is never accessible again
3195 * and typically causes the system to hang or reset when access is attempted.
3196 * http://www.spinics.net/lists/linux-pci/msg34797.html
3197 */
3198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3201
3202 static void quirk_no_pm_reset(struct pci_dev *dev)
3203 {
3204 /*
3205 * We can't do a bus reset on root bus devices, but an ineffective
3206 * PM reset may be better than nothing.
3207 */
3208 if (!pci_is_root_bus(dev->bus))
3209 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3210 }
3211
3212 /*
3213 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3214 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3215 * to have no effect on the device: it retains the framebuffer contents and
3216 * monitor sync. Advertising this support makes other layers, like VFIO,
3217 * assume pci_reset_function() is viable for this device. Mark it as
3218 * unavailable to skip it when testing reset methods.
3219 */
3220 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3221 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3222
3223 /*
3224 * Thunderbolt controllers with broken MSI hotplug signaling:
3225 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3226 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3227 */
3228 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3229 {
3230 if (pdev->is_hotplug_bridge &&
3231 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3232 pdev->revision <= 1))
3233 pdev->no_msi = 1;
3234 }
3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3236 quirk_thunderbolt_hotplug_msi);
3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3238 quirk_thunderbolt_hotplug_msi);
3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3240 quirk_thunderbolt_hotplug_msi);
3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3242 quirk_thunderbolt_hotplug_msi);
3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3244 quirk_thunderbolt_hotplug_msi);
3245
3246 #ifdef CONFIG_ACPI
3247 /*
3248 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3249 *
3250 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3251 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3252 * be present after resume if a device was plugged in before suspend.
3253 *
3254 * The thunderbolt controller consists of a pcie switch with downstream
3255 * bridges leading to the NHI and to the tunnel pci bridges.
3256 *
3257 * This quirk cuts power to the whole chip. Therefore we have to apply it
3258 * during suspend_noirq of the upstream bridge.
3259 *
3260 * Power is automagically restored before resume. No action is needed.
3261 */
3262 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3263 {
3264 acpi_handle bridge, SXIO, SXFP, SXLV;
3265
3266 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3267 return;
3268 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3269 return;
3270 bridge = ACPI_HANDLE(&dev->dev);
3271 if (!bridge)
3272 return;
3273 /*
3274 * SXIO and SXLV are present only on machines requiring this quirk.
3275 * TB bridges in external devices might have the same device id as those
3276 * on the host, but they will not have the associated ACPI methods. This
3277 * implicitly checks that we are at the right bridge.
3278 */
3279 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3280 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3281 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3282 return;
3283 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3284
3285 /* magic sequence */
3286 acpi_execute_simple_method(SXIO, NULL, 1);
3287 acpi_execute_simple_method(SXFP, NULL, 0);
3288 msleep(300);
3289 acpi_execute_simple_method(SXLV, NULL, 0);
3290 acpi_execute_simple_method(SXIO, NULL, 0);
3291 acpi_execute_simple_method(SXLV, NULL, 0);
3292 }
3293 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3294 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3295 quirk_apple_poweroff_thunderbolt);
3296
3297 /*
3298 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3299 *
3300 * During suspend the thunderbolt controller is reset and all pci
3301 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3302 * during resume. We have to manually wait for the NHI since there is
3303 * no parent child relationship between the NHI and the tunneled
3304 * bridges.
3305 */
3306 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3307 {
3308 struct pci_dev *sibling = NULL;
3309 struct pci_dev *nhi = NULL;
3310
3311 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3312 return;
3313 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3314 return;
3315 /*
3316 * Find the NHI and confirm that we are a bridge on the tb host
3317 * controller and not on a tb endpoint.
3318 */
3319 sibling = pci_get_slot(dev->bus, 0x0);
3320 if (sibling == dev)
3321 goto out; /* we are the downstream bridge to the NHI */
3322 if (!sibling || !sibling->subordinate)
3323 goto out;
3324 nhi = pci_get_slot(sibling->subordinate, 0x0);
3325 if (!nhi)
3326 goto out;
3327 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3328 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3329 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3330 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3331 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3332 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3333 goto out;
3334 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3335 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3336 out:
3337 pci_dev_put(nhi);
3338 pci_dev_put(sibling);
3339 }
3340 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3341 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3342 quirk_apple_wait_for_thunderbolt);
3343 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3344 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3345 quirk_apple_wait_for_thunderbolt);
3346 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3347 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3348 quirk_apple_wait_for_thunderbolt);
3349 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3350 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3351 quirk_apple_wait_for_thunderbolt);
3352 #endif
3353
3354 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3355 struct pci_fixup *end)
3356 {
3357 ktime_t calltime;
3358
3359 for (; f < end; f++)
3360 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3361 f->class == (u32) PCI_ANY_ID) &&
3362 (f->vendor == dev->vendor ||
3363 f->vendor == (u16) PCI_ANY_ID) &&
3364 (f->device == dev->device ||
3365 f->device == (u16) PCI_ANY_ID)) {
3366 calltime = fixup_debug_start(dev, f->hook);
3367 f->hook(dev);
3368 fixup_debug_report(dev, calltime, f->hook);
3369 }
3370 }
3371
3372 extern struct pci_fixup __start_pci_fixups_early[];
3373 extern struct pci_fixup __end_pci_fixups_early[];
3374 extern struct pci_fixup __start_pci_fixups_header[];
3375 extern struct pci_fixup __end_pci_fixups_header[];
3376 extern struct pci_fixup __start_pci_fixups_final[];
3377 extern struct pci_fixup __end_pci_fixups_final[];
3378 extern struct pci_fixup __start_pci_fixups_enable[];
3379 extern struct pci_fixup __end_pci_fixups_enable[];
3380 extern struct pci_fixup __start_pci_fixups_resume[];
3381 extern struct pci_fixup __end_pci_fixups_resume[];
3382 extern struct pci_fixup __start_pci_fixups_resume_early[];
3383 extern struct pci_fixup __end_pci_fixups_resume_early[];
3384 extern struct pci_fixup __start_pci_fixups_suspend[];
3385 extern struct pci_fixup __end_pci_fixups_suspend[];
3386 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3387 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3388
3389 static bool pci_apply_fixup_final_quirks;
3390
3391 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3392 {
3393 struct pci_fixup *start, *end;
3394
3395 switch (pass) {
3396 case pci_fixup_early:
3397 start = __start_pci_fixups_early;
3398 end = __end_pci_fixups_early;
3399 break;
3400
3401 case pci_fixup_header:
3402 start = __start_pci_fixups_header;
3403 end = __end_pci_fixups_header;
3404 break;
3405
3406 case pci_fixup_final:
3407 if (!pci_apply_fixup_final_quirks)
3408 return;
3409 start = __start_pci_fixups_final;
3410 end = __end_pci_fixups_final;
3411 break;
3412
3413 case pci_fixup_enable:
3414 start = __start_pci_fixups_enable;
3415 end = __end_pci_fixups_enable;
3416 break;
3417
3418 case pci_fixup_resume:
3419 start = __start_pci_fixups_resume;
3420 end = __end_pci_fixups_resume;
3421 break;
3422
3423 case pci_fixup_resume_early:
3424 start = __start_pci_fixups_resume_early;
3425 end = __end_pci_fixups_resume_early;
3426 break;
3427
3428 case pci_fixup_suspend:
3429 start = __start_pci_fixups_suspend;
3430 end = __end_pci_fixups_suspend;
3431 break;
3432
3433 case pci_fixup_suspend_late:
3434 start = __start_pci_fixups_suspend_late;
3435 end = __end_pci_fixups_suspend_late;
3436 break;
3437
3438 default:
3439 /* stupid compiler warning, you would think with an enum... */
3440 return;
3441 }
3442 pci_do_fixups(dev, start, end);
3443 }
3444 EXPORT_SYMBOL(pci_fixup_device);
3445
3446
3447 static int __init pci_apply_final_quirks(void)
3448 {
3449 struct pci_dev *dev = NULL;
3450 u8 cls = 0;
3451 u8 tmp;
3452
3453 if (pci_cache_line_size)
3454 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3455 pci_cache_line_size << 2);
3456
3457 pci_apply_fixup_final_quirks = true;
3458 for_each_pci_dev(dev) {
3459 pci_fixup_device(pci_fixup_final, dev);
3460 /*
3461 * If arch hasn't set it explicitly yet, use the CLS
3462 * value shared by all PCI devices. If there's a
3463 * mismatch, fall back to the default value.
3464 */
3465 if (!pci_cache_line_size) {
3466 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3467 if (!cls)
3468 cls = tmp;
3469 if (!tmp || cls == tmp)
3470 continue;
3471
3472 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3473 cls << 2, tmp << 2,
3474 pci_dfl_cache_line_size << 2);
3475 pci_cache_line_size = pci_dfl_cache_line_size;
3476 }
3477 }
3478
3479 if (!pci_cache_line_size) {
3480 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3481 cls << 2, pci_dfl_cache_line_size << 2);
3482 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3483 }
3484
3485 return 0;
3486 }
3487
3488 fs_initcall_sync(pci_apply_final_quirks);
3489
3490 /*
3491 * Followings are device-specific reset methods which can be used to
3492 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3493 * not available.
3494 */
3495 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3496 {
3497 /*
3498 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3499 *
3500 * The 82599 supports FLR on VFs, but FLR support is reported only
3501 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3502 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3503 */
3504
3505 if (probe)
3506 return 0;
3507
3508 if (!pci_wait_for_pending_transaction(dev))
3509 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3510
3511 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3512
3513 msleep(100);
3514
3515 return 0;
3516 }
3517
3518 #define SOUTH_CHICKEN2 0xc2004
3519 #define PCH_PP_STATUS 0xc7200
3520 #define PCH_PP_CONTROL 0xc7204
3521 #define MSG_CTL 0x45010
3522 #define NSDE_PWR_STATE 0xd0100
3523 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3524
3525 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3526 {
3527 void __iomem *mmio_base;
3528 unsigned long timeout;
3529 u32 val;
3530
3531 if (probe)
3532 return 0;
3533
3534 mmio_base = pci_iomap(dev, 0, 0);
3535 if (!mmio_base)
3536 return -ENOMEM;
3537
3538 iowrite32(0x00000002, mmio_base + MSG_CTL);
3539
3540 /*
3541 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3542 * driver loaded sets the right bits. However, this's a reset and
3543 * the bits have been set by i915 previously, so we clobber
3544 * SOUTH_CHICKEN2 register directly here.
3545 */
3546 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3547
3548 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3549 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3550
3551 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3552 do {
3553 val = ioread32(mmio_base + PCH_PP_STATUS);
3554 if ((val & 0xb0000000) == 0)
3555 goto reset_complete;
3556 msleep(10);
3557 } while (time_before(jiffies, timeout));
3558 dev_warn(&dev->dev, "timeout during reset\n");
3559
3560 reset_complete:
3561 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3562
3563 pci_iounmap(dev, mmio_base);
3564 return 0;
3565 }
3566
3567 /*
3568 * Device-specific reset method for Chelsio T4-based adapters.
3569 */
3570 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3571 {
3572 u16 old_command;
3573 u16 msix_flags;
3574
3575 /*
3576 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3577 * that we have no device-specific reset method.
3578 */
3579 if ((dev->device & 0xf000) != 0x4000)
3580 return -ENOTTY;
3581
3582 /*
3583 * If this is the "probe" phase, return 0 indicating that we can
3584 * reset this device.
3585 */
3586 if (probe)
3587 return 0;
3588
3589 /*
3590 * T4 can wedge if there are DMAs in flight within the chip and Bus
3591 * Master has been disabled. We need to have it on till the Function
3592 * Level Reset completes. (BUS_MASTER is disabled in
3593 * pci_reset_function()).
3594 */
3595 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3596 pci_write_config_word(dev, PCI_COMMAND,
3597 old_command | PCI_COMMAND_MASTER);
3598
3599 /*
3600 * Perform the actual device function reset, saving and restoring
3601 * configuration information around the reset.
3602 */
3603 pci_save_state(dev);
3604
3605 /*
3606 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3607 * are disabled when an MSI-X interrupt message needs to be delivered.
3608 * So we briefly re-enable MSI-X interrupts for the duration of the
3609 * FLR. The pci_restore_state() below will restore the original
3610 * MSI-X state.
3611 */
3612 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3613 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3614 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3615 msix_flags |
3616 PCI_MSIX_FLAGS_ENABLE |
3617 PCI_MSIX_FLAGS_MASKALL);
3618
3619 /*
3620 * Start of pcie_flr() code sequence. This reset code is a copy of
3621 * the guts of pcie_flr() because that's not an exported function.
3622 */
3623
3624 if (!pci_wait_for_pending_transaction(dev))
3625 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3626
3627 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3628 msleep(100);
3629
3630 /*
3631 * End of pcie_flr() code sequence.
3632 */
3633
3634 /*
3635 * Restore the configuration information (BAR values, etc.) including
3636 * the original PCI Configuration Space Command word, and return
3637 * success.
3638 */
3639 pci_restore_state(dev);
3640 pci_write_config_word(dev, PCI_COMMAND, old_command);
3641 return 0;
3642 }
3643
3644 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3645 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3646 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3647
3648 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3649 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3650 reset_intel_82599_sfp_virtfn },
3651 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3652 reset_ivb_igd },
3653 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3654 reset_ivb_igd },
3655 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3656 reset_chelsio_generic_dev },
3657 { 0 }
3658 };
3659
3660 /*
3661 * These device-specific reset methods are here rather than in a driver
3662 * because when a host assigns a device to a guest VM, the host may need
3663 * to reset the device but probably doesn't have a driver for it.
3664 */
3665 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3666 {
3667 const struct pci_dev_reset_methods *i;
3668
3669 for (i = pci_dev_reset_methods; i->reset; i++) {
3670 if ((i->vendor == dev->vendor ||
3671 i->vendor == (u16)PCI_ANY_ID) &&
3672 (i->device == dev->device ||
3673 i->device == (u16)PCI_ANY_ID))
3674 return i->reset(dev, probe);
3675 }
3676
3677 return -ENOTTY;
3678 }
3679
3680 static void quirk_dma_func0_alias(struct pci_dev *dev)
3681 {
3682 if (PCI_FUNC(dev->devfn) != 0)
3683 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3684 }
3685
3686 /*
3687 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3688 *
3689 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3690 */
3691 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3693
3694 static void quirk_dma_func1_alias(struct pci_dev *dev)
3695 {
3696 if (PCI_FUNC(dev->devfn) != 1)
3697 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3698 }
3699
3700 /*
3701 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3702 * SKUs function 1 is present and is a legacy IDE controller, in other
3703 * SKUs this function is not present, making this a ghost requester.
3704 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3705 */
3706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3707 quirk_dma_func1_alias);
3708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3709 quirk_dma_func1_alias);
3710 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3711 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3712 quirk_dma_func1_alias);
3713 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3715 quirk_dma_func1_alias);
3716 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3718 quirk_dma_func1_alias);
3719 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3721 quirk_dma_func1_alias);
3722 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3724 quirk_dma_func1_alias);
3725 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3726 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3727 quirk_dma_func1_alias);
3728 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3729 quirk_dma_func1_alias);
3730 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3731 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3732 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3733 quirk_dma_func1_alias);
3734 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3735 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3736 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3737 quirk_dma_func1_alias);
3738
3739 /*
3740 * Some devices DMA with the wrong devfn, not just the wrong function.
3741 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3742 * the alias is "fixed" and independent of the device devfn.
3743 *
3744 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3745 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3746 * single device on the secondary bus. In reality, the single exposed
3747 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3748 * that provides a bridge to the internal bus of the I/O processor. The
3749 * controller supports private devices, which can be hidden from PCI config
3750 * space. In the case of the Adaptec 3405, a private device at 01.0
3751 * appears to be the DMA engine, which therefore needs to become a DMA
3752 * alias for the device.
3753 */
3754 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3755 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3756 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3757 .driver_data = PCI_DEVFN(1, 0) },
3758 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3759 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3760 .driver_data = PCI_DEVFN(1, 0) },
3761 { 0 }
3762 };
3763
3764 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3765 {
3766 const struct pci_device_id *id;
3767
3768 id = pci_match_id(fixed_dma_alias_tbl, dev);
3769 if (id)
3770 pci_add_dma_alias(dev, id->driver_data);
3771 }
3772
3773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3774
3775 /*
3776 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3777 * using the wrong DMA alias for the device. Some of these devices can be
3778 * used as either forward or reverse bridges, so we need to test whether the
3779 * device is operating in the correct mode. We could probably apply this
3780 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3781 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3782 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3783 */
3784 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3785 {
3786 if (!pci_is_root_bus(pdev->bus) &&
3787 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3788 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3789 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3790 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3791 }
3792 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3794 quirk_use_pcie_bridge_dma_alias);
3795 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3796 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3797 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3798 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3799 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3800 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3801
3802 /*
3803 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3804 * be added as aliases to the DMA device in order to allow buffer access
3805 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3806 * programmed in the EEPROM.
3807 */
3808 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3809 {
3810 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3811 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3812 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3813 }
3814 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3815 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3816
3817 /*
3818 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3819 * class code. Fix it.
3820 */
3821 static void quirk_tw686x_class(struct pci_dev *pdev)
3822 {
3823 u32 class = pdev->class;
3824
3825 /* Use "Multimedia controller" class */
3826 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3827 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3828 class, pdev->class);
3829 }
3830 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3831 quirk_tw686x_class);
3832 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3833 quirk_tw686x_class);
3834 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3835 quirk_tw686x_class);
3836 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3837 quirk_tw686x_class);
3838
3839 /*
3840 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3841 * values for the Attribute as were supplied in the header of the
3842 * corresponding Request, except as explicitly allowed when IDO is used."
3843 *
3844 * If a non-compliant device generates a completion with a different
3845 * attribute than the request, the receiver may accept it (which itself
3846 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3847 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3848 * device access timeout.
3849 *
3850 * If the non-compliant device generates completions with zero attributes
3851 * (instead of copying the attributes from the request), we can work around
3852 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3853 * upstream devices so they always generate requests with zero attributes.
3854 *
3855 * This affects other devices under the same Root Port, but since these
3856 * attributes are performance hints, there should be no functional problem.
3857 *
3858 * Note that Configuration Space accesses are never supposed to have TLP
3859 * Attributes, so we're safe waiting till after any Configuration Space
3860 * accesses to do the Root Port fixup.
3861 */
3862 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
3863 {
3864 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
3865
3866 if (!root_port) {
3867 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
3868 return;
3869 }
3870
3871 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
3872 dev_name(&pdev->dev));
3873 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
3874 PCI_EXP_DEVCTL_RELAX_EN |
3875 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
3876 }
3877
3878 /*
3879 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
3880 * Completion it generates.
3881 */
3882 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
3883 {
3884 /*
3885 * This mask/compare operation selects for Physical Function 4 on a
3886 * T5. We only need to fix up the Root Port once for any of the
3887 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
3888 * 0x54xx so we use that one,
3889 */
3890 if ((pdev->device & 0xff00) == 0x5400)
3891 quirk_disable_root_port_attributes(pdev);
3892 }
3893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3894 quirk_chelsio_T5_disable_root_port_attributes);
3895
3896 /*
3897 * AMD has indicated that the devices below do not support peer-to-peer
3898 * in any system where they are found in the southbridge with an AMD
3899 * IOMMU in the system. Multifunction devices that do not support
3900 * peer-to-peer between functions can claim to support a subset of ACS.
3901 * Such devices effectively enable request redirect (RR) and completion
3902 * redirect (CR) since all transactions are redirected to the upstream
3903 * root complex.
3904 *
3905 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3906 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3907 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3908 *
3909 * 1002:4385 SBx00 SMBus Controller
3910 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3911 * 1002:4383 SBx00 Azalia (Intel HDA)
3912 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3913 * 1002:4384 SBx00 PCI to PCI Bridge
3914 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3915 *
3916 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
3917 *
3918 * 1022:780f [AMD] FCH PCI Bridge
3919 * 1022:7809 [AMD] FCH USB OHCI Controller
3920 */
3921 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3922 {
3923 #ifdef CONFIG_ACPI
3924 struct acpi_table_header *header = NULL;
3925 acpi_status status;
3926
3927 /* Targeting multifunction devices on the SB (appears on root bus) */
3928 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3929 return -ENODEV;
3930
3931 /* The IVRS table describes the AMD IOMMU */
3932 status = acpi_get_table("IVRS", 0, &header);
3933 if (ACPI_FAILURE(status))
3934 return -ENODEV;
3935
3936 /* Filter out flags not applicable to multifunction */
3937 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3938
3939 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3940 #else
3941 return -ENODEV;
3942 #endif
3943 }
3944
3945 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
3946 {
3947 /*
3948 * Cavium devices matching this quirk do not perform peer-to-peer
3949 * with other functions, allowing masking out these bits as if they
3950 * were unimplemented in the ACS capability.
3951 */
3952 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3953 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
3954
3955 return acs_flags ? 0 : 1;
3956 }
3957
3958 /*
3959 * Many Intel PCH root ports do provide ACS-like features to disable peer
3960 * transactions and validate bus numbers in requests, but do not provide an
3961 * actual PCIe ACS capability. This is the list of device IDs known to fall
3962 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3963 */
3964 static const u16 pci_quirk_intel_pch_acs_ids[] = {
3965 /* Ibexpeak PCH */
3966 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3967 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3968 /* Cougarpoint PCH */
3969 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3970 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3971 /* Pantherpoint PCH */
3972 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3973 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3974 /* Lynxpoint-H PCH */
3975 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3976 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3977 /* Lynxpoint-LP PCH */
3978 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3979 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3980 /* Wildcat PCH */
3981 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3982 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3983 /* Patsburg (X79) PCH */
3984 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3985 /* Wellsburg (X99) PCH */
3986 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
3987 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
3988 /* Lynx Point (9 series) PCH */
3989 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
3990 };
3991
3992 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3993 {
3994 int i;
3995
3996 /* Filter out a few obvious non-matches first */
3997 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3998 return false;
3999
4000 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4001 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4002 return true;
4003
4004 return false;
4005 }
4006
4007 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4008
4009 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4010 {
4011 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4012 INTEL_PCH_ACS_FLAGS : 0;
4013
4014 if (!pci_quirk_intel_pch_acs_match(dev))
4015 return -ENOTTY;
4016
4017 return acs_flags & ~flags ? 0 : 1;
4018 }
4019
4020 /*
4021 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4022 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4023 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4024 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4025 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4026 * control register is at offset 8 instead of 6 and we should probably use
4027 * dword accesses to them. This applies to the following PCI Device IDs, as
4028 * found in volume 1 of the datasheet[2]:
4029 *
4030 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4031 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4032 *
4033 * N.B. This doesn't fix what lspci shows.
4034 *
4035 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4036 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4037 */
4038 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4039 {
4040 return pci_is_pcie(dev) &&
4041 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
4042 ((dev->device & ~0xf) == 0xa110 ||
4043 (dev->device >= 0xa167 && dev->device <= 0xa16a));
4044 }
4045
4046 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4047
4048 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4049 {
4050 int pos;
4051 u32 cap, ctrl;
4052
4053 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4054 return -ENOTTY;
4055
4056 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4057 if (!pos)
4058 return -ENOTTY;
4059
4060 /* see pci_acs_flags_enabled() */
4061 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4062 acs_flags &= (cap | PCI_ACS_EC);
4063
4064 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4065
4066 return acs_flags & ~ctrl ? 0 : 1;
4067 }
4068
4069 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4070 {
4071 /*
4072 * SV, TB, and UF are not relevant to multifunction endpoints.
4073 *
4074 * Multifunction devices are only required to implement RR, CR, and DT
4075 * in their ACS capability if they support peer-to-peer transactions.
4076 * Devices matching this quirk have been verified by the vendor to not
4077 * perform peer-to-peer with other functions, allowing us to mask out
4078 * these bits as if they were unimplemented in the ACS capability.
4079 */
4080 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4081 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4082
4083 return acs_flags ? 0 : 1;
4084 }
4085
4086 static const struct pci_dev_acs_enabled {
4087 u16 vendor;
4088 u16 device;
4089 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4090 } pci_dev_acs_enabled[] = {
4091 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4092 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4093 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4094 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4095 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4096 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4097 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4098 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4099 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4100 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4101 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4102 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4103 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4104 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4105 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4106 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4107 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4108 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4109 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4110 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4111 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4112 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4113 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4114 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4115 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4116 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4117 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4118 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4119 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4120 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4121 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4122 /* 82580 */
4123 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4124 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4125 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4126 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4127 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4128 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4129 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4130 /* 82576 */
4131 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4132 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4133 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4134 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4135 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4136 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4137 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4138 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4139 /* 82575 */
4140 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4141 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4142 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4143 /* I350 */
4144 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4145 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4146 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4147 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4148 /* 82571 (Quads omitted due to non-ACS switch) */
4149 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4150 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4151 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4152 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4153 /* I219 */
4154 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4155 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4156 /* Intel PCH root ports */
4157 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4158 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4159 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4160 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4161 /* Cavium ThunderX */
4162 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4163 { 0 }
4164 };
4165
4166 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4167 {
4168 const struct pci_dev_acs_enabled *i;
4169 int ret;
4170
4171 /*
4172 * Allow devices that do not expose standard PCIe ACS capabilities
4173 * or control to indicate their support here. Multi-function express
4174 * devices which do not allow internal peer-to-peer between functions,
4175 * but do not implement PCIe ACS may wish to return true here.
4176 */
4177 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4178 if ((i->vendor == dev->vendor ||
4179 i->vendor == (u16)PCI_ANY_ID) &&
4180 (i->device == dev->device ||
4181 i->device == (u16)PCI_ANY_ID)) {
4182 ret = i->acs_enabled(dev, acs_flags);
4183 if (ret >= 0)
4184 return ret;
4185 }
4186 }
4187
4188 return -ENOTTY;
4189 }
4190
4191 /* Config space offset of Root Complex Base Address register */
4192 #define INTEL_LPC_RCBA_REG 0xf0
4193 /* 31:14 RCBA address */
4194 #define INTEL_LPC_RCBA_MASK 0xffffc000
4195 /* RCBA Enable */
4196 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4197
4198 /* Backbone Scratch Pad Register */
4199 #define INTEL_BSPR_REG 0x1104
4200 /* Backbone Peer Non-Posted Disable */
4201 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4202 /* Backbone Peer Posted Disable */
4203 #define INTEL_BSPR_REG_BPPD (1 << 9)
4204
4205 /* Upstream Peer Decode Configuration Register */
4206 #define INTEL_UPDCR_REG 0x1114
4207 /* 5:0 Peer Decode Enable bits */
4208 #define INTEL_UPDCR_REG_MASK 0x3f
4209
4210 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4211 {
4212 u32 rcba, bspr, updcr;
4213 void __iomem *rcba_mem;
4214
4215 /*
4216 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4217 * are D28:F* and therefore get probed before LPC, thus we can't
4218 * use pci_get_slot/pci_read_config_dword here.
4219 */
4220 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4221 INTEL_LPC_RCBA_REG, &rcba);
4222 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4223 return -EINVAL;
4224
4225 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4226 PAGE_ALIGN(INTEL_UPDCR_REG));
4227 if (!rcba_mem)
4228 return -ENOMEM;
4229
4230 /*
4231 * The BSPR can disallow peer cycles, but it's set by soft strap and
4232 * therefore read-only. If both posted and non-posted peer cycles are
4233 * disallowed, we're ok. If either are allowed, then we need to use
4234 * the UPDCR to disable peer decodes for each port. This provides the
4235 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4236 */
4237 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4238 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4239 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4240 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4241 if (updcr & INTEL_UPDCR_REG_MASK) {
4242 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4243 updcr &= ~INTEL_UPDCR_REG_MASK;
4244 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4245 }
4246 }
4247
4248 iounmap(rcba_mem);
4249 return 0;
4250 }
4251
4252 /* Miscellaneous Port Configuration register */
4253 #define INTEL_MPC_REG 0xd8
4254 /* MPC: Invalid Receive Bus Number Check Enable */
4255 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4256
4257 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4258 {
4259 u32 mpc;
4260
4261 /*
4262 * When enabled, the IRBNCE bit of the MPC register enables the
4263 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4264 * ensures that requester IDs fall within the bus number range
4265 * of the bridge. Enable if not already.
4266 */
4267 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4268 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4269 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4270 mpc |= INTEL_MPC_REG_IRBNCE;
4271 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4272 }
4273 }
4274
4275 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4276 {
4277 if (!pci_quirk_intel_pch_acs_match(dev))
4278 return -ENOTTY;
4279
4280 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4281 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4282 return 0;
4283 }
4284
4285 pci_quirk_enable_intel_rp_mpc_acs(dev);
4286
4287 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4288
4289 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4290
4291 return 0;
4292 }
4293
4294 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4295 {
4296 int pos;
4297 u32 cap, ctrl;
4298
4299 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4300 return -ENOTTY;
4301
4302 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4303 if (!pos)
4304 return -ENOTTY;
4305
4306 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4307 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4308
4309 ctrl |= (cap & PCI_ACS_SV);
4310 ctrl |= (cap & PCI_ACS_RR);
4311 ctrl |= (cap & PCI_ACS_CR);
4312 ctrl |= (cap & PCI_ACS_UF);
4313
4314 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4315
4316 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4317
4318 return 0;
4319 }
4320
4321 static const struct pci_dev_enable_acs {
4322 u16 vendor;
4323 u16 device;
4324 int (*enable_acs)(struct pci_dev *dev);
4325 } pci_dev_enable_acs[] = {
4326 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4327 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4328 { 0 }
4329 };
4330
4331 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4332 {
4333 const struct pci_dev_enable_acs *i;
4334 int ret;
4335
4336 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4337 if ((i->vendor == dev->vendor ||
4338 i->vendor == (u16)PCI_ANY_ID) &&
4339 (i->device == dev->device ||
4340 i->device == (u16)PCI_ANY_ID)) {
4341 ret = i->enable_acs(dev);
4342 if (ret >= 0)
4343 return ret;
4344 }
4345 }
4346
4347 return -ENOTTY;
4348 }
4349
4350 /*
4351 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4352 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4353 * Next Capability pointer in the MSI Capability Structure should point to
4354 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4355 * the list.
4356 */
4357 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4358 {
4359 int pos, i = 0;
4360 u8 next_cap;
4361 u16 reg16, *cap;
4362 struct pci_cap_saved_state *state;
4363
4364 /* Bail if the hardware bug is fixed */
4365 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4366 return;
4367
4368 /* Bail if MSI Capability Structure is not found for some reason */
4369 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4370 if (!pos)
4371 return;
4372
4373 /*
4374 * Bail if Next Capability pointer in the MSI Capability Structure
4375 * is not the expected incorrect 0x00.
4376 */
4377 pci_read_config_byte(pdev, pos + 1, &next_cap);
4378 if (next_cap)
4379 return;
4380
4381 /*
4382 * PCIe Capability Structure is expected to be at 0x50 and should
4383 * terminate the list (Next Capability pointer is 0x00). Verify
4384 * Capability Id and Next Capability pointer is as expected.
4385 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4386 * to correctly set kernel data structures which have already been
4387 * set incorrectly due to the hardware bug.
4388 */
4389 pos = 0x50;
4390 pci_read_config_word(pdev, pos, &reg16);
4391 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4392 u32 status;
4393 #ifndef PCI_EXP_SAVE_REGS
4394 #define PCI_EXP_SAVE_REGS 7
4395 #endif
4396 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4397
4398 pdev->pcie_cap = pos;
4399 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4400 pdev->pcie_flags_reg = reg16;
4401 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4402 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4403
4404 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4405 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4406 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4407 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4408
4409 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4410 return;
4411
4412 /*
4413 * Save PCIE cap
4414 */
4415 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4416 if (!state)
4417 return;
4418
4419 state->cap.cap_nr = PCI_CAP_ID_EXP;
4420 state->cap.cap_extended = 0;
4421 state->cap.size = size;
4422 cap = (u16 *)&state->cap.data[0];
4423 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4424 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4425 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4426 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4427 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4428 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4429 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4430 hlist_add_head(&state->next, &pdev->saved_cap_space);
4431 }
4432 }
4433 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
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