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[mirror_ubuntu-hirsute-kernel.git] / drivers / pci / quirks.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains work-arounds for many known PCI hardware
4 * bugs. Devices present only on certain architectures (host
5 * bridges et cetera) should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the
12 * USB quirks file, where their drivers can access reuse it.
13 */
14
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <asm/dma.h> /* isa_dma_bridge_buggy */
30 #include "pci.h"
31
32 /*
33 * Decoding should be disabled for a PCI device during BAR sizing to avoid
34 * conflict. But doing so may cause problems on host bridge and perhaps other
35 * key system devices. For devices that need to have mmio decoding always-on,
36 * we need to set the dev->mmio_always_on bit.
37 */
38 static void quirk_mmio_always_on(struct pci_dev *dev)
39 {
40 dev->mmio_always_on = 1;
41 }
42 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
43 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
44
45 /* The Mellanox Tavor device gives false positive parity errors
46 * Mark this device with a broken_parity_status, to allow
47 * PCI scanning code to "skip" this now blacklisted device.
48 */
49 static void quirk_mellanox_tavor(struct pci_dev *dev)
50 {
51 dev->broken_parity_status = 1; /* This device gives false positives */
52 }
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
54 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
55
56 /* Deal with broken BIOSes that neglect to enable passive release,
57 which can cause problems in combination with the 82441FX/PPro MTRRs */
58 static void quirk_passive_release(struct pci_dev *dev)
59 {
60 struct pci_dev *d = NULL;
61 unsigned char dlc;
62
63 /* We have to make sure a particular bit is set in the PIIX3
64 ISA bridge, so we have to go out and find it. */
65 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
66 pci_read_config_byte(d, 0x82, &dlc);
67 if (!(dlc & 1<<1)) {
68 pci_info(d, "PIIX3: Enabling Passive Release\n");
69 dlc |= 1<<1;
70 pci_write_config_byte(d, 0x82, dlc);
71 }
72 }
73 }
74 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
75 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76
77 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
78 but VIA don't answer queries. If you happen to have good contacts at VIA
79 ask them for me please -- Alan
80
81 This appears to be BIOS not version dependent. So presumably there is a
82 chipset level fix */
83
84 static void quirk_isa_dma_hangs(struct pci_dev *dev)
85 {
86 if (!isa_dma_bridge_buggy) {
87 isa_dma_bridge_buggy = 1;
88 pci_info(dev, "Activating ISA DMA hang workarounds\n");
89 }
90 }
91 /*
92 * Its not totally clear which chipsets are the problematic ones
93 * We know 82C586 and 82C596 variants are affected.
94 */
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
102
103 /*
104 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
105 * for some HT machines to use C4 w/o hanging.
106 */
107 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
108 {
109 u32 pmbase;
110 u16 pm1a;
111
112 pci_read_config_dword(dev, 0x40, &pmbase);
113 pmbase = pmbase & 0xff80;
114 pm1a = inw(pmbase);
115
116 if (pm1a & 0x10) {
117 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
118 outw(0x10, pmbase);
119 }
120 }
121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
122
123 /*
124 * Chipsets where PCI->PCI transfers vanish or hang
125 */
126 static void quirk_nopcipci(struct pci_dev *dev)
127 {
128 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
129 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
130 pci_pci_problems |= PCIPCI_FAIL;
131 }
132 }
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
135
136 static void quirk_nopciamd(struct pci_dev *dev)
137 {
138 u8 rev;
139 pci_read_config_byte(dev, 0x08, &rev);
140 if (rev == 0x13) {
141 /* Erratum 24 */
142 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
143 pci_pci_problems |= PCIAGP_FAIL;
144 }
145 }
146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
147
148 /*
149 * Triton requires workarounds to be used by the drivers
150 */
151 static void quirk_triton(struct pci_dev *dev)
152 {
153 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
154 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
155 pci_pci_problems |= PCIPCI_TRITON;
156 }
157 }
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
162
163 /*
164 * VIA Apollo KT133 needs PCI latency patch
165 * Made according to a windows driver based patch by George E. Breese
166 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
167 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
168 * the info on which Mr Breese based his work.
169 *
170 * Updated based on further information from the site and also on
171 * information provided by VIA
172 */
173 static void quirk_vialatency(struct pci_dev *dev)
174 {
175 struct pci_dev *p;
176 u8 busarb;
177 /* Ok we have a potential problem chipset here. Now see if we have
178 a buggy southbridge */
179
180 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
181 if (p != NULL) {
182 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
183 /* Check for buggy part revisions */
184 if (p->revision < 0x40 || p->revision > 0x42)
185 goto exit;
186 } else {
187 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
188 if (p == NULL) /* No problem parts */
189 goto exit;
190 /* Check for buggy part revisions */
191 if (p->revision < 0x10 || p->revision > 0x12)
192 goto exit;
193 }
194
195 /*
196 * Ok we have the problem. Now set the PCI master grant to
197 * occur every master grant. The apparent bug is that under high
198 * PCI load (quite common in Linux of course) you can get data
199 * loss when the CPU is held off the bus for 3 bus master requests
200 * This happens to include the IDE controllers....
201 *
202 * VIA only apply this fix when an SB Live! is present but under
203 * both Linux and Windows this isn't enough, and we have seen
204 * corruption without SB Live! but with things like 3 UDMA IDE
205 * controllers. So we ignore that bit of the VIA recommendation..
206 */
207
208 pci_read_config_byte(dev, 0x76, &busarb);
209 /* Set bit 4 and bi 5 of byte 76 to 0x01
210 "Master priority rotation on every PCI master grant */
211 busarb &= ~(1<<5);
212 busarb |= (1<<4);
213 pci_write_config_byte(dev, 0x76, busarb);
214 pci_info(dev, "Applying VIA southbridge workaround\n");
215 exit:
216 pci_dev_put(p);
217 }
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
221 /* Must restore this on a resume from RAM */
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
225
226 /*
227 * VIA Apollo VP3 needs ETBF on BT848/878
228 */
229 static void quirk_viaetbf(struct pci_dev *dev)
230 {
231 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
232 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
233 pci_pci_problems |= PCIPCI_VIAETBF;
234 }
235 }
236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
237
238 static void quirk_vsfx(struct pci_dev *dev)
239 {
240 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
241 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
242 pci_pci_problems |= PCIPCI_VSFX;
243 }
244 }
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
246
247 /*
248 * Ali Magik requires workarounds to be used by the drivers
249 * that DMA to AGP space. Latency must be set to 0xA and triton
250 * workaround applied too
251 * [Info kindly provided by ALi]
252 */
253 static void quirk_alimagik(struct pci_dev *dev)
254 {
255 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
256 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
257 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
258 }
259 }
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
262
263 /*
264 * Natoma has some interesting boundary conditions with Zoran stuff
265 * at least
266 */
267 static void quirk_natoma(struct pci_dev *dev)
268 {
269 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
270 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
271 pci_pci_problems |= PCIPCI_NATOMA;
272 }
273 }
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
280
281 /*
282 * This chip can cause PCI parity errors if config register 0xA0 is read
283 * while DMAs are occurring.
284 */
285 static void quirk_citrine(struct pci_dev *dev)
286 {
287 dev->cfg_size = 0xA0;
288 }
289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
290
291 /*
292 * This chip can cause bus lockups if config addresses above 0x600
293 * are read or written.
294 */
295 static void quirk_nfp6000(struct pci_dev *dev)
296 {
297 dev->cfg_size = 0x600;
298 }
299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
302
303 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
304 static void quirk_extend_bar_to_page(struct pci_dev *dev)
305 {
306 int i;
307
308 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
309 struct resource *r = &dev->resource[i];
310
311 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
312 r->end = PAGE_SIZE - 1;
313 r->start = 0;
314 r->flags |= IORESOURCE_UNSET;
315 pci_info(dev, "expanded BAR %d to page size: %pR\n",
316 i, r);
317 }
318 }
319 }
320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
321
322 /*
323 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
324 * If it's needed, re-allocate the region.
325 */
326 static void quirk_s3_64M(struct pci_dev *dev)
327 {
328 struct resource *r = &dev->resource[0];
329
330 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
331 r->flags |= IORESOURCE_UNSET;
332 r->start = 0;
333 r->end = 0x3ffffff;
334 }
335 }
336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
338
339 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
340 const char *name)
341 {
342 u32 region;
343 struct pci_bus_region bus_region;
344 struct resource *res = dev->resource + pos;
345
346 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
347
348 if (!region)
349 return;
350
351 res->name = pci_name(dev);
352 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
353 res->flags |=
354 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
355 region &= ~(size - 1);
356
357 /* Convert from PCI bus to resource space */
358 bus_region.start = region;
359 bus_region.end = region + size - 1;
360 pcibios_bus_to_resource(dev->bus, res, &bus_region);
361
362 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
363 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
364 }
365
366 /*
367 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
368 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
369 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
370 * (which conflicts w/ BAR1's memory range).
371 *
372 * CS553x's ISA PCI BARs may also be read-only (ref:
373 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
374 */
375 static void quirk_cs5536_vsa(struct pci_dev *dev)
376 {
377 static char *name = "CS5536 ISA bridge";
378
379 if (pci_resource_len(dev, 0) != 8) {
380 quirk_io(dev, 0, 8, name); /* SMB */
381 quirk_io(dev, 1, 256, name); /* GPIO */
382 quirk_io(dev, 2, 64, name); /* MFGPT */
383 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
384 name);
385 }
386 }
387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
388
389 static void quirk_io_region(struct pci_dev *dev, int port,
390 unsigned size, int nr, const char *name)
391 {
392 u16 region;
393 struct pci_bus_region bus_region;
394 struct resource *res = dev->resource + nr;
395
396 pci_read_config_word(dev, port, &region);
397 region &= ~(size - 1);
398
399 if (!region)
400 return;
401
402 res->name = pci_name(dev);
403 res->flags = IORESOURCE_IO;
404
405 /* Convert from PCI bus to resource space */
406 bus_region.start = region;
407 bus_region.end = region + size - 1;
408 pcibios_bus_to_resource(dev->bus, res, &bus_region);
409
410 if (!pci_claim_resource(dev, nr))
411 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
412 }
413
414 /*
415 * ATI Northbridge setups MCE the processor if you even
416 * read somewhere between 0x3b0->0x3bb or read 0x3d3
417 */
418 static void quirk_ati_exploding_mce(struct pci_dev *dev)
419 {
420 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
421 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
422 request_region(0x3b0, 0x0C, "RadeonIGP");
423 request_region(0x3d3, 0x01, "RadeonIGP");
424 }
425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
426
427 /*
428 * In the AMD NL platform, this device ([1022:7912]) has a class code of
429 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
430 * claim it.
431 * But the dwc3 driver is a more specific driver for this device, and we'd
432 * prefer to use it instead of xhci. To prevent xhci from claiming the
433 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
434 * defines as "USB device (not host controller)". The dwc3 driver can then
435 * claim it based on its Vendor and Device ID.
436 */
437 static void quirk_amd_nl_class(struct pci_dev *pdev)
438 {
439 u32 class = pdev->class;
440
441 /* Use "USB Device (not host controller)" class */
442 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
443 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
444 class, pdev->class);
445 }
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
447 quirk_amd_nl_class);
448
449 /*
450 * Let's make the southbridge information explicit instead
451 * of having to worry about people probing the ACPI areas,
452 * for example.. (Yes, it happens, and if you read the wrong
453 * ACPI register it will put the machine to sleep with no
454 * way of waking it up again. Bummer).
455 *
456 * ALI M7101: Two IO regions pointed to by words at
457 * 0xE0 (64 bytes of ACPI registers)
458 * 0xE2 (32 bytes of SMB registers)
459 */
460 static void quirk_ali7101_acpi(struct pci_dev *dev)
461 {
462 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
463 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
464 }
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
466
467 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
468 {
469 u32 devres;
470 u32 mask, size, base;
471
472 pci_read_config_dword(dev, port, &devres);
473 if ((devres & enable) != enable)
474 return;
475 mask = (devres >> 16) & 15;
476 base = devres & 0xffff;
477 size = 16;
478 for (;;) {
479 unsigned bit = size >> 1;
480 if ((bit & mask) == bit)
481 break;
482 size = bit;
483 }
484 /*
485 * For now we only print it out. Eventually we'll want to
486 * reserve it (at least if it's in the 0x1000+ range), but
487 * let's get enough confirmation reports first.
488 */
489 base &= -size;
490 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
491 }
492
493 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
494 {
495 u32 devres;
496 u32 mask, size, base;
497
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
500 return;
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
503 size = 128 << 16;
504 for (;;) {
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
507 break;
508 size = bit;
509 }
510 /*
511 * For now we only print it out. Eventually we'll want to
512 * reserve it, but let's get enough confirmation reports first.
513 */
514 base &= -size;
515 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
516 }
517
518 /*
519 * PIIX4 ACPI: Two IO regions pointed to by longwords at
520 * 0x40 (64 bytes of ACPI registers)
521 * 0x90 (16 bytes of SMB registers)
522 * and a few strange programmable PIIX4 device resources.
523 */
524 static void quirk_piix4_acpi(struct pci_dev *dev)
525 {
526 u32 res_a;
527
528 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
529 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
530
531 /* Device resource A has enables for some of the other ones */
532 pci_read_config_dword(dev, 0x5c, &res_a);
533
534 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
535 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
536
537 /* Device resource D is just bitfields for static resources */
538
539 /* Device 12 enabled? */
540 if (res_a & (1 << 29)) {
541 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
542 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
543 }
544 /* Device 13 enabled? */
545 if (res_a & (1 << 30)) {
546 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
547 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
548 }
549 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
550 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
551 }
552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
554
555 #define ICH_PMBASE 0x40
556 #define ICH_ACPI_CNTL 0x44
557 #define ICH4_ACPI_EN 0x10
558 #define ICH6_ACPI_EN 0x80
559 #define ICH4_GPIOBASE 0x58
560 #define ICH4_GPIO_CNTL 0x5c
561 #define ICH4_GPIO_EN 0x10
562 #define ICH6_GPIOBASE 0x48
563 #define ICH6_GPIO_CNTL 0x4c
564 #define ICH6_GPIO_EN 0x10
565
566 /*
567 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
568 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
569 * 0x58 (64 bytes of GPIO I/O space)
570 */
571 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
572 {
573 u8 enable;
574
575 /*
576 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
577 * with low legacy (and fixed) ports. We don't know the decoding
578 * priority and can't tell whether the legacy device or the one created
579 * here is really at that address. This happens on boards with broken
580 * BIOSes.
581 */
582
583 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
584 if (enable & ICH4_ACPI_EN)
585 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
586 "ICH4 ACPI/GPIO/TCO");
587
588 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
589 if (enable & ICH4_GPIO_EN)
590 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
591 "ICH4 GPIO");
592 }
593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
603
604 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
605 {
606 u8 enable;
607
608 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
609 if (enable & ICH6_ACPI_EN)
610 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
611 "ICH6 ACPI/GPIO/TCO");
612
613 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
614 if (enable & ICH6_GPIO_EN)
615 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
616 "ICH6 GPIO");
617 }
618
619 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
620 {
621 u32 val;
622 u32 size, base;
623
624 pci_read_config_dword(dev, reg, &val);
625
626 /* Enabled? */
627 if (!(val & 1))
628 return;
629 base = val & 0xfffc;
630 if (dynsize) {
631 /*
632 * This is not correct. It is 16, 32 or 64 bytes depending on
633 * register D31:F0:ADh bits 5:4.
634 *
635 * But this gets us at least _part_ of it.
636 */
637 size = 16;
638 } else {
639 size = 128;
640 }
641 base &= ~(size-1);
642
643 /* Just print it out for now. We should reserve it after more debugging */
644 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
645 }
646
647 static void quirk_ich6_lpc(struct pci_dev *dev)
648 {
649 /* Shared ACPI/GPIO decode with all ICH6+ */
650 ich6_lpc_acpi_gpio(dev);
651
652 /* ICH6-specific generic IO decode */
653 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
654 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
655 }
656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
658
659 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
660 {
661 u32 val;
662 u32 mask, base;
663
664 pci_read_config_dword(dev, reg, &val);
665
666 /* Enabled? */
667 if (!(val & 1))
668 return;
669
670 /*
671 * IO base in bits 15:2, mask in bits 23:18, both
672 * are dword-based
673 */
674 base = val & 0xfffc;
675 mask = (val >> 16) & 0xfc;
676 mask |= 3;
677
678 /* Just print it out for now. We should reserve it after more debugging */
679 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
680 }
681
682 /* ICH7-10 has the same common LPC generic IO decode registers */
683 static void quirk_ich7_lpc(struct pci_dev *dev)
684 {
685 /* We share the common ACPI/GPIO decode with ICH6 */
686 ich6_lpc_acpi_gpio(dev);
687
688 /* And have 4 ICH7+ generic decodes */
689 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
690 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
691 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
692 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
693 }
694 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
707
708 /*
709 * VIA ACPI: One IO region pointed to by longword at
710 * 0x48 or 0x20 (256 bytes of ACPI registers)
711 */
712 static void quirk_vt82c586_acpi(struct pci_dev *dev)
713 {
714 if (dev->revision & 0x10)
715 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
716 "vt82c586 ACPI");
717 }
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
719
720 /*
721 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
722 * 0x48 (256 bytes of ACPI registers)
723 * 0x70 (128 bytes of hardware monitoring register)
724 * 0x90 (16 bytes of SMB registers)
725 */
726 static void quirk_vt82c686_acpi(struct pci_dev *dev)
727 {
728 quirk_vt82c586_acpi(dev);
729
730 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
731 "vt82c686 HW-mon");
732
733 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
734 }
735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
736
737 /*
738 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
739 * 0x88 (128 bytes of power management registers)
740 * 0xd0 (16 bytes of SMB registers)
741 */
742 static void quirk_vt8235_acpi(struct pci_dev *dev)
743 {
744 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
745 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
746 }
747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
748
749 /*
750 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
751 * Disable fast back-to-back on the secondary bus segment
752 */
753 static void quirk_xio2000a(struct pci_dev *dev)
754 {
755 struct pci_dev *pdev;
756 u16 command;
757
758 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
759 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
760 pci_read_config_word(pdev, PCI_COMMAND, &command);
761 if (command & PCI_COMMAND_FAST_BACK)
762 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
763 }
764 }
765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
766 quirk_xio2000a);
767
768 #ifdef CONFIG_X86_IO_APIC
769
770 #include <asm/io_apic.h>
771
772 /*
773 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
774 * devices to the external APIC.
775 *
776 * TODO: When we have device-specific interrupt routers,
777 * this code will go away from quirks.
778 */
779 static void quirk_via_ioapic(struct pci_dev *dev)
780 {
781 u8 tmp;
782
783 if (nr_ioapics < 1)
784 tmp = 0; /* nothing routed to external APIC */
785 else
786 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
787
788 pci_info(dev, "%sbling VIA external APIC routing\n",
789 tmp == 0 ? "Disa" : "Ena");
790
791 /* Offset 0x58: External APIC IRQ output control */
792 pci_write_config_byte(dev, 0x58, tmp);
793 }
794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
795 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796
797 /*
798 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
799 * This leads to doubled level interrupt rates.
800 * Set this bit to get rid of cycle wastage.
801 * Otherwise uncritical.
802 */
803 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
804 {
805 u8 misc_control2;
806 #define BYPASS_APIC_DEASSERT 8
807
808 pci_read_config_byte(dev, 0x5B, &misc_control2);
809 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
810 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
811 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
812 }
813 }
814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
815 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816
817 /*
818 * The AMD io apic can hang the box when an apic irq is masked.
819 * We check all revs >= B0 (yet not in the pre production!) as the bug
820 * is currently marked NoFix
821 *
822 * We have multiple reports of hangs with this chipset that went away with
823 * noapic specified. For the moment we assume it's the erratum. We may be wrong
824 * of course. However the advice is demonstrably good even if so..
825 */
826 static void quirk_amd_ioapic(struct pci_dev *dev)
827 {
828 if (dev->revision >= 0x02) {
829 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
830 pci_warn(dev, " : booting with the \"noapic\" option\n");
831 }
832 }
833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
834 #endif /* CONFIG_X86_IO_APIC */
835
836 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
837
838 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
839 {
840 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
841 if (dev->subsystem_device == 0xa118)
842 dev->sriov->link = dev->devfn;
843 }
844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
845 #endif
846
847 /*
848 * Some settings of MMRBC can lead to data corruption so block changes.
849 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
850 */
851 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
852 {
853 if (dev->subordinate && dev->revision <= 0x12) {
854 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
855 dev->revision);
856 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
857 }
858 }
859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
860
861 /*
862 * FIXME: it is questionable that quirk_via_acpi
863 * is needed. It shows up as an ISA bridge, and does not
864 * support the PCI_INTERRUPT_LINE register at all. Therefore
865 * it seems like setting the pci_dev's 'irq' to the
866 * value of the ACPI SCI interrupt is only done for convenience.
867 * -jgarzik
868 */
869 static void quirk_via_acpi(struct pci_dev *d)
870 {
871 /*
872 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
873 */
874 u8 irq;
875 pci_read_config_byte(d, 0x42, &irq);
876 irq &= 0xf;
877 if (irq && (irq != 2))
878 d->irq = irq;
879 }
880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
882
883
884 /*
885 * VIA bridges which have VLink
886 */
887
888 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
889
890 static void quirk_via_bridge(struct pci_dev *dev)
891 {
892 /* See what bridge we have and find the device ranges */
893 switch (dev->device) {
894 case PCI_DEVICE_ID_VIA_82C686:
895 /* The VT82C686 is special, it attaches to PCI and can have
896 any device number. All its subdevices are functions of
897 that single device. */
898 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
899 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
900 break;
901 case PCI_DEVICE_ID_VIA_8237:
902 case PCI_DEVICE_ID_VIA_8237A:
903 via_vlink_dev_lo = 15;
904 break;
905 case PCI_DEVICE_ID_VIA_8235:
906 via_vlink_dev_lo = 16;
907 break;
908 case PCI_DEVICE_ID_VIA_8231:
909 case PCI_DEVICE_ID_VIA_8233_0:
910 case PCI_DEVICE_ID_VIA_8233A:
911 case PCI_DEVICE_ID_VIA_8233C_0:
912 via_vlink_dev_lo = 17;
913 break;
914 }
915 }
916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
924
925 /**
926 * quirk_via_vlink - VIA VLink IRQ number update
927 * @dev: PCI device
928 *
929 * If the device we are dealing with is on a PIC IRQ we need to
930 * ensure that the IRQ line register which usually is not relevant
931 * for PCI cards, is actually written so that interrupts get sent
932 * to the right place.
933 * We only do this on systems where a VIA south bridge was detected,
934 * and only for VIA devices on the motherboard (see quirk_via_bridge
935 * above).
936 */
937
938 static void quirk_via_vlink(struct pci_dev *dev)
939 {
940 u8 irq, new_irq;
941
942 /* Check if we have VLink at all */
943 if (via_vlink_dev_lo == -1)
944 return;
945
946 new_irq = dev->irq;
947
948 /* Don't quirk interrupts outside the legacy IRQ range */
949 if (!new_irq || new_irq > 15)
950 return;
951
952 /* Internal device ? */
953 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
954 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
955 return;
956
957 /* This is an internal VLink device on a PIC interrupt. The BIOS
958 ought to have set this but may not have, so we redo it */
959
960 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
961 if (new_irq != irq) {
962 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
963 irq, new_irq);
964 udelay(15); /* unknown if delay really needed */
965 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
966 }
967 }
968 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
969
970 /*
971 * VIA VT82C598 has its device ID settable and many BIOSes
972 * set it to the ID of VT82C597 for backward compatibility.
973 * We need to switch it off to be able to recognize the real
974 * type of the chip.
975 */
976 static void quirk_vt82c598_id(struct pci_dev *dev)
977 {
978 pci_write_config_byte(dev, 0xfc, 0);
979 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
980 }
981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
982
983 /*
984 * CardBus controllers have a legacy base address that enables them
985 * to respond as i82365 pcmcia controllers. We don't want them to
986 * do this even if the Linux CardBus driver is not loaded, because
987 * the Linux i82365 driver does not (and should not) handle CardBus.
988 */
989 static void quirk_cardbus_legacy(struct pci_dev *dev)
990 {
991 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
992 }
993 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
994 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
995 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
996 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
997
998 /*
999 * Following the PCI ordering rules is optional on the AMD762. I'm not
1000 * sure what the designers were smoking but let's not inhale...
1001 *
1002 * To be fair to AMD, it follows the spec by default, its BIOS people
1003 * who turn it off!
1004 */
1005 static void quirk_amd_ordering(struct pci_dev *dev)
1006 {
1007 u32 pcic;
1008 pci_read_config_dword(dev, 0x4C, &pcic);
1009 if ((pcic & 6) != 6) {
1010 pcic |= 6;
1011 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1012 pci_write_config_dword(dev, 0x4C, pcic);
1013 pci_read_config_dword(dev, 0x84, &pcic);
1014 pcic |= (1 << 23); /* Required in this mode */
1015 pci_write_config_dword(dev, 0x84, pcic);
1016 }
1017 }
1018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1019 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1020
1021 /*
1022 * DreamWorks provided workaround for Dunord I-3000 problem
1023 *
1024 * This card decodes and responds to addresses not apparently
1025 * assigned to it. We force a larger allocation to ensure that
1026 * nothing gets put too close to it.
1027 */
1028 static void quirk_dunord(struct pci_dev *dev)
1029 {
1030 struct resource *r = &dev->resource[1];
1031
1032 r->flags |= IORESOURCE_UNSET;
1033 r->start = 0;
1034 r->end = 0xffffff;
1035 }
1036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1037
1038 /*
1039 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1040 * is subtractive decoding (transparent), and does indicate this
1041 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1042 * instead of 0x01.
1043 */
1044 static void quirk_transparent_bridge(struct pci_dev *dev)
1045 {
1046 dev->transparent = 1;
1047 }
1048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1050
1051 /*
1052 * Common misconfiguration of the MediaGX/Geode PCI master that will
1053 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1054 * datasheets found at http://www.national.com/analog for info on what
1055 * these bits do. <christer@weinigel.se>
1056 */
1057 static void quirk_mediagx_master(struct pci_dev *dev)
1058 {
1059 u8 reg;
1060
1061 pci_read_config_byte(dev, 0x41, &reg);
1062 if (reg & 2) {
1063 reg &= ~2;
1064 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1065 reg);
1066 pci_write_config_byte(dev, 0x41, reg);
1067 }
1068 }
1069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1070 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1071
1072 /*
1073 * Ensure C0 rev restreaming is off. This is normally done by
1074 * the BIOS but in the odd case it is not the results are corruption
1075 * hence the presence of a Linux check
1076 */
1077 static void quirk_disable_pxb(struct pci_dev *pdev)
1078 {
1079 u16 config;
1080
1081 if (pdev->revision != 0x04) /* Only C0 requires this */
1082 return;
1083 pci_read_config_word(pdev, 0x40, &config);
1084 if (config & (1<<6)) {
1085 config &= ~(1<<6);
1086 pci_write_config_word(pdev, 0x40, config);
1087 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1088 }
1089 }
1090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1091 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1092
1093 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1094 {
1095 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1096 u8 tmp;
1097
1098 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1099 if (tmp == 0x01) {
1100 pci_read_config_byte(pdev, 0x40, &tmp);
1101 pci_write_config_byte(pdev, 0x40, tmp|1);
1102 pci_write_config_byte(pdev, 0x9, 1);
1103 pci_write_config_byte(pdev, 0xa, 6);
1104 pci_write_config_byte(pdev, 0x40, tmp);
1105
1106 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1107 pci_info(pdev, "set SATA to AHCI mode\n");
1108 }
1109 }
1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1111 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1113 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1117 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118
1119 /*
1120 * Serverworks CSB5 IDE does not fully support native mode
1121 */
1122 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1123 {
1124 u8 prog;
1125 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1126 if (prog & 5) {
1127 prog &= ~5;
1128 pdev->class &= ~5;
1129 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1130 /* PCI layer will sort out resources */
1131 }
1132 }
1133 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1134
1135 /*
1136 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1137 */
1138 static void quirk_ide_samemode(struct pci_dev *pdev)
1139 {
1140 u8 prog;
1141
1142 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1143
1144 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1145 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1146 prog &= ~5;
1147 pdev->class &= ~5;
1148 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1149 }
1150 }
1151 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1152
1153 /*
1154 * Some ATA devices break if put into D3
1155 */
1156
1157 static void quirk_no_ata_d3(struct pci_dev *pdev)
1158 {
1159 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1160 }
1161 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1162 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1163 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1164 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1165 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1166 /* ALi loses some register settings that we cannot then restore */
1167 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1168 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1169 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1170 occur when mode detecting */
1171 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1172 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1173
1174 /* This was originally an Alpha specific thing, but it really fits here.
1175 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1176 */
1177 static void quirk_eisa_bridge(struct pci_dev *dev)
1178 {
1179 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1180 }
1181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1182
1183
1184 /*
1185 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1186 * is not activated. The myth is that Asus said that they do not want the
1187 * users to be irritated by just another PCI Device in the Win98 device
1188 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1189 * package 2.7.0 for details)
1190 *
1191 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1192 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1193 * becomes necessary to do this tweak in two steps -- the chosen trigger
1194 * is either the Host bridge (preferred) or on-board VGA controller.
1195 *
1196 * Note that we used to unhide the SMBus that way on Toshiba laptops
1197 * (Satellite A40 and Tecra M2) but then found that the thermal management
1198 * was done by SMM code, which could cause unsynchronized concurrent
1199 * accesses to the SMBus registers, with potentially bad effects. Thus you
1200 * should be very careful when adding new entries: if SMM is accessing the
1201 * Intel SMBus, this is a very good reason to leave it hidden.
1202 *
1203 * Likewise, many recent laptops use ACPI for thermal management. If the
1204 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1205 * natively, and keeping the SMBus hidden is the right thing to do. If you
1206 * are about to add an entry in the table below, please first disassemble
1207 * the DSDT and double-check that there is no code accessing the SMBus.
1208 */
1209 static int asus_hides_smbus;
1210
1211 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1212 {
1213 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1214 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1215 switch (dev->subsystem_device) {
1216 case 0x8025: /* P4B-LX */
1217 case 0x8070: /* P4B */
1218 case 0x8088: /* P4B533 */
1219 case 0x1626: /* L3C notebook */
1220 asus_hides_smbus = 1;
1221 }
1222 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1223 switch (dev->subsystem_device) {
1224 case 0x80b1: /* P4GE-V */
1225 case 0x80b2: /* P4PE */
1226 case 0x8093: /* P4B533-V */
1227 asus_hides_smbus = 1;
1228 }
1229 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1230 switch (dev->subsystem_device) {
1231 case 0x8030: /* P4T533 */
1232 asus_hides_smbus = 1;
1233 }
1234 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1235 switch (dev->subsystem_device) {
1236 case 0x8070: /* P4G8X Deluxe */
1237 asus_hides_smbus = 1;
1238 }
1239 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1240 switch (dev->subsystem_device) {
1241 case 0x80c9: /* PU-DLS */
1242 asus_hides_smbus = 1;
1243 }
1244 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1245 switch (dev->subsystem_device) {
1246 case 0x1751: /* M2N notebook */
1247 case 0x1821: /* M5N notebook */
1248 case 0x1897: /* A6L notebook */
1249 asus_hides_smbus = 1;
1250 }
1251 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1252 switch (dev->subsystem_device) {
1253 case 0x184b: /* W1N notebook */
1254 case 0x186a: /* M6Ne notebook */
1255 asus_hides_smbus = 1;
1256 }
1257 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1258 switch (dev->subsystem_device) {
1259 case 0x80f2: /* P4P800-X */
1260 asus_hides_smbus = 1;
1261 }
1262 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1263 switch (dev->subsystem_device) {
1264 case 0x1882: /* M6V notebook */
1265 case 0x1977: /* A6VA notebook */
1266 asus_hides_smbus = 1;
1267 }
1268 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1269 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1270 switch (dev->subsystem_device) {
1271 case 0x088C: /* HP Compaq nc8000 */
1272 case 0x0890: /* HP Compaq nc6000 */
1273 asus_hides_smbus = 1;
1274 }
1275 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1276 switch (dev->subsystem_device) {
1277 case 0x12bc: /* HP D330L */
1278 case 0x12bd: /* HP D530 */
1279 case 0x006a: /* HP Compaq nx9500 */
1280 asus_hides_smbus = 1;
1281 }
1282 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1283 switch (dev->subsystem_device) {
1284 case 0x12bf: /* HP xw4100 */
1285 asus_hides_smbus = 1;
1286 }
1287 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1288 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1289 switch (dev->subsystem_device) {
1290 case 0xC00C: /* Samsung P35 notebook */
1291 asus_hides_smbus = 1;
1292 }
1293 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1294 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1295 switch (dev->subsystem_device) {
1296 case 0x0058: /* Compaq Evo N620c */
1297 asus_hides_smbus = 1;
1298 }
1299 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1300 switch (dev->subsystem_device) {
1301 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1302 /* Motherboard doesn't have Host bridge
1303 * subvendor/subdevice IDs, therefore checking
1304 * its on-board VGA controller */
1305 asus_hides_smbus = 1;
1306 }
1307 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1308 switch (dev->subsystem_device) {
1309 case 0x00b8: /* Compaq Evo D510 CMT */
1310 case 0x00b9: /* Compaq Evo D510 SFF */
1311 case 0x00ba: /* Compaq Evo D510 USDT */
1312 /* Motherboard doesn't have Host bridge
1313 * subvendor/subdevice IDs and on-board VGA
1314 * controller is disabled if an AGP card is
1315 * inserted, therefore checking USB UHCI
1316 * Controller #1 */
1317 asus_hides_smbus = 1;
1318 }
1319 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1320 switch (dev->subsystem_device) {
1321 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1322 /* Motherboard doesn't have host bridge
1323 * subvendor/subdevice IDs, therefore checking
1324 * its on-board VGA controller */
1325 asus_hides_smbus = 1;
1326 }
1327 }
1328 }
1329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1339
1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1343
1344 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1345 {
1346 u16 val;
1347
1348 if (likely(!asus_hides_smbus))
1349 return;
1350
1351 pci_read_config_word(dev, 0xF2, &val);
1352 if (val & 0x8) {
1353 pci_write_config_word(dev, 0xF2, val & (~0x8));
1354 pci_read_config_word(dev, 0xF2, &val);
1355 if (val & 0x8)
1356 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1357 val);
1358 else
1359 pci_info(dev, "Enabled i801 SMBus device\n");
1360 }
1361 }
1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1369 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1376
1377 /* It appears we just have one such device. If not, we have a warning */
1378 static void __iomem *asus_rcba_base;
1379 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1380 {
1381 u32 rcba;
1382
1383 if (likely(!asus_hides_smbus))
1384 return;
1385 WARN_ON(asus_rcba_base);
1386
1387 pci_read_config_dword(dev, 0xF0, &rcba);
1388 /* use bits 31:14, 16 kB aligned */
1389 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1390 if (asus_rcba_base == NULL)
1391 return;
1392 }
1393
1394 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1395 {
1396 u32 val;
1397
1398 if (likely(!asus_hides_smbus || !asus_rcba_base))
1399 return;
1400 /* read the Function Disable register, dword mode only */
1401 val = readl(asus_rcba_base + 0x3418);
1402 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1403 }
1404
1405 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1406 {
1407 if (likely(!asus_hides_smbus || !asus_rcba_base))
1408 return;
1409 iounmap(asus_rcba_base);
1410 asus_rcba_base = NULL;
1411 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1412 }
1413
1414 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1415 {
1416 asus_hides_smbus_lpc_ich6_suspend(dev);
1417 asus_hides_smbus_lpc_ich6_resume_early(dev);
1418 asus_hides_smbus_lpc_ich6_resume(dev);
1419 }
1420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1421 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1422 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1423 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1424
1425 /*
1426 * SiS 96x south bridge: BIOS typically hides SMBus device...
1427 */
1428 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1429 {
1430 u8 val = 0;
1431 pci_read_config_byte(dev, 0x77, &val);
1432 if (val & 0x10) {
1433 pci_info(dev, "Enabling SiS 96x SMBus\n");
1434 pci_write_config_byte(dev, 0x77, val & ~0x10);
1435 }
1436 }
1437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1441 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1442 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1445
1446 /*
1447 * ... This is further complicated by the fact that some SiS96x south
1448 * bridges pretend to be 85C503/5513 instead. In that case see if we
1449 * spotted a compatible north bridge to make sure.
1450 * (pci_find_device doesn't work yet)
1451 *
1452 * We can also enable the sis96x bit in the discovery register..
1453 */
1454 #define SIS_DETECT_REGISTER 0x40
1455
1456 static void quirk_sis_503(struct pci_dev *dev)
1457 {
1458 u8 reg;
1459 u16 devid;
1460
1461 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1462 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1463 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1464 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1465 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1466 return;
1467 }
1468
1469 /*
1470 * Ok, it now shows up as a 96x.. run the 96x quirk by
1471 * hand in case it has already been processed.
1472 * (depends on link order, which is apparently not guaranteed)
1473 */
1474 dev->device = devid;
1475 quirk_sis_96x_smbus(dev);
1476 }
1477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1478 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1479
1480
1481 /*
1482 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1483 * and MC97 modem controller are disabled when a second PCI soundcard is
1484 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1485 * -- bjd
1486 */
1487 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1488 {
1489 u8 val;
1490 int asus_hides_ac97 = 0;
1491
1492 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1493 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1494 asus_hides_ac97 = 1;
1495 }
1496
1497 if (!asus_hides_ac97)
1498 return;
1499
1500 pci_read_config_byte(dev, 0x50, &val);
1501 if (val & 0xc0) {
1502 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1503 pci_read_config_byte(dev, 0x50, &val);
1504 if (val & 0xc0)
1505 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1506 val);
1507 else
1508 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1509 }
1510 }
1511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1512 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1513
1514 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1515
1516 /*
1517 * If we are using libata we can drive this chip properly but must
1518 * do this early on to make the additional device appear during
1519 * the PCI scanning.
1520 */
1521 static void quirk_jmicron_ata(struct pci_dev *pdev)
1522 {
1523 u32 conf1, conf5, class;
1524 u8 hdr;
1525
1526 /* Only poke fn 0 */
1527 if (PCI_FUNC(pdev->devfn))
1528 return;
1529
1530 pci_read_config_dword(pdev, 0x40, &conf1);
1531 pci_read_config_dword(pdev, 0x80, &conf5);
1532
1533 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1534 conf5 &= ~(1 << 24); /* Clear bit 24 */
1535
1536 switch (pdev->device) {
1537 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1538 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1539 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1540 /* The controller should be in single function ahci mode */
1541 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1542 break;
1543
1544 case PCI_DEVICE_ID_JMICRON_JMB365:
1545 case PCI_DEVICE_ID_JMICRON_JMB366:
1546 /* Redirect IDE second PATA port to the right spot */
1547 conf5 |= (1 << 24);
1548 /* Fall through */
1549 case PCI_DEVICE_ID_JMICRON_JMB361:
1550 case PCI_DEVICE_ID_JMICRON_JMB363:
1551 case PCI_DEVICE_ID_JMICRON_JMB369:
1552 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1553 /* Set the class codes correctly and then direct IDE 0 */
1554 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1555 break;
1556
1557 case PCI_DEVICE_ID_JMICRON_JMB368:
1558 /* The controller should be in single function IDE mode */
1559 conf1 |= 0x00C00000; /* Set 22, 23 */
1560 break;
1561 }
1562
1563 pci_write_config_dword(pdev, 0x40, conf1);
1564 pci_write_config_dword(pdev, 0x80, conf5);
1565
1566 /* Update pdev accordingly */
1567 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1568 pdev->hdr_type = hdr & 0x7f;
1569 pdev->multifunction = !!(hdr & 0x80);
1570
1571 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1572 pdev->class = class >> 8;
1573 }
1574 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1583 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1584 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1592
1593 #endif
1594
1595 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1596 {
1597 if (dev->multifunction) {
1598 device_disable_async_suspend(&dev->dev);
1599 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1600 }
1601 }
1602 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1603 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1606
1607 #ifdef CONFIG_X86_IO_APIC
1608 static void quirk_alder_ioapic(struct pci_dev *pdev)
1609 {
1610 int i;
1611
1612 if ((pdev->class >> 8) != 0xff00)
1613 return;
1614
1615 /* the first BAR is the location of the IO APIC...we must
1616 * not touch this (and it's already covered by the fixmap), so
1617 * forcibly insert it into the resource tree */
1618 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1619 insert_resource(&iomem_resource, &pdev->resource[0]);
1620
1621 /* The next five BARs all seem to be rubbish, so just clean
1622 * them out */
1623 for (i = 1; i < 6; i++)
1624 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1625 }
1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1627 #endif
1628
1629 static void quirk_pcie_mch(struct pci_dev *pdev)
1630 {
1631 pdev->no_msi = 1;
1632 }
1633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1636
1637 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1638
1639 /*
1640 * It's possible for the MSI to get corrupted if shpc and acpi
1641 * are used together on certain PXH-based systems.
1642 */
1643 static void quirk_pcie_pxh(struct pci_dev *dev)
1644 {
1645 dev->no_msi = 1;
1646 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1647 }
1648 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1653
1654 /*
1655 * Some Intel PCI Express chipsets have trouble with downstream
1656 * device power management.
1657 */
1658 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1659 {
1660 pci_pm_d3_delay = 120;
1661 dev->no_d1d2 = 1;
1662 }
1663
1664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1685
1686 static void quirk_radeon_pm(struct pci_dev *dev)
1687 {
1688 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1689 dev->subsystem_device == 0x00e2) {
1690 if (dev->d3_delay < 20) {
1691 dev->d3_delay = 20;
1692 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
1693 dev->d3_delay);
1694 }
1695 }
1696 }
1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1698
1699 #ifdef CONFIG_X86_IO_APIC
1700 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1701 {
1702 noioapicreroute = 1;
1703 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1704
1705 return 0;
1706 }
1707
1708 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1709 /*
1710 * Systems to exclude from boot interrupt reroute quirks
1711 */
1712 {
1713 .callback = dmi_disable_ioapicreroute,
1714 .ident = "ASUSTek Computer INC. M2N-LR",
1715 .matches = {
1716 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1717 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1718 },
1719 },
1720 {}
1721 };
1722
1723 /*
1724 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1725 * remap the original interrupt in the linux kernel to the boot interrupt, so
1726 * that a PCI device's interrupt handler is installed on the boot interrupt
1727 * line instead.
1728 */
1729 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1730 {
1731 dmi_check_system(boot_interrupt_dmi_table);
1732 if (noioapicquirk || noioapicreroute)
1733 return;
1734
1735 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1736 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1737 dev->vendor, dev->device);
1738 }
1739 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1747 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1748 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1749 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1754 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1755
1756 /*
1757 * On some chipsets we can disable the generation of legacy INTx boot
1758 * interrupts.
1759 */
1760
1761 /*
1762 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1763 * 300641-004US, section 5.7.3.
1764 */
1765 #define INTEL_6300_IOAPIC_ABAR 0x40
1766 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1767
1768 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1769 {
1770 u16 pci_config_word;
1771
1772 if (noioapicquirk)
1773 return;
1774
1775 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1776 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1777 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1778
1779 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1780 dev->vendor, dev->device);
1781 }
1782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1783 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1784
1785 /*
1786 * disable boot interrupts on HT-1000
1787 */
1788 #define BC_HT1000_FEATURE_REG 0x64
1789 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1790 #define BC_HT1000_MAP_IDX 0xC00
1791 #define BC_HT1000_MAP_DATA 0xC01
1792
1793 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1794 {
1795 u32 pci_config_dword;
1796 u8 irq;
1797
1798 if (noioapicquirk)
1799 return;
1800
1801 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1802 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1803 BC_HT1000_PIC_REGS_ENABLE);
1804
1805 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1806 outb(irq, BC_HT1000_MAP_IDX);
1807 outb(0x00, BC_HT1000_MAP_DATA);
1808 }
1809
1810 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1811
1812 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1813 dev->vendor, dev->device);
1814 }
1815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1816 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1817
1818 /*
1819 * disable boot interrupts on AMD and ATI chipsets
1820 */
1821 /*
1822 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1823 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1824 * (due to an erratum).
1825 */
1826 #define AMD_813X_MISC 0x40
1827 #define AMD_813X_NOIOAMODE (1<<0)
1828 #define AMD_813X_REV_B1 0x12
1829 #define AMD_813X_REV_B2 0x13
1830
1831 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1832 {
1833 u32 pci_config_dword;
1834
1835 if (noioapicquirk)
1836 return;
1837 if ((dev->revision == AMD_813X_REV_B1) ||
1838 (dev->revision == AMD_813X_REV_B2))
1839 return;
1840
1841 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1842 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1843 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1844
1845 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1846 dev->vendor, dev->device);
1847 }
1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1849 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1851 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1852
1853 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1854
1855 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1856 {
1857 u16 pci_config_word;
1858
1859 if (noioapicquirk)
1860 return;
1861
1862 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1863 if (!pci_config_word) {
1864 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1865 dev->vendor, dev->device);
1866 return;
1867 }
1868 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1869 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1870 dev->vendor, dev->device);
1871 }
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1873 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1874 #endif /* CONFIG_X86_IO_APIC */
1875
1876 /*
1877 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1878 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1879 * Re-allocate the region if needed...
1880 */
1881 static void quirk_tc86c001_ide(struct pci_dev *dev)
1882 {
1883 struct resource *r = &dev->resource[0];
1884
1885 if (r->start & 0x8) {
1886 r->flags |= IORESOURCE_UNSET;
1887 r->start = 0;
1888 r->end = 0xf;
1889 }
1890 }
1891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1892 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1893 quirk_tc86c001_ide);
1894
1895 /*
1896 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1897 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1898 * being read correctly if bit 7 of the base address is set.
1899 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1900 * Re-allocate the regions to a 256-byte boundary if necessary.
1901 */
1902 static void quirk_plx_pci9050(struct pci_dev *dev)
1903 {
1904 unsigned int bar;
1905
1906 /* Fixed in revision 2 (PCI 9052). */
1907 if (dev->revision >= 2)
1908 return;
1909 for (bar = 0; bar <= 1; bar++)
1910 if (pci_resource_len(dev, bar) == 0x80 &&
1911 (pci_resource_start(dev, bar) & 0x80)) {
1912 struct resource *r = &dev->resource[bar];
1913 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1914 bar);
1915 r->flags |= IORESOURCE_UNSET;
1916 r->start = 0;
1917 r->end = 0xff;
1918 }
1919 }
1920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1921 quirk_plx_pci9050);
1922 /*
1923 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1924 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1925 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1926 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1927 *
1928 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1929 * driver.
1930 */
1931 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1932 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1933
1934 static void quirk_netmos(struct pci_dev *dev)
1935 {
1936 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1937 unsigned int num_serial = dev->subsystem_device & 0xf;
1938
1939 /*
1940 * These Netmos parts are multiport serial devices with optional
1941 * parallel ports. Even when parallel ports are present, they
1942 * are identified as class SERIAL, which means the serial driver
1943 * will claim them. To prevent this, mark them as class OTHER.
1944 * These combo devices should be claimed by parport_serial.
1945 *
1946 * The subdevice ID is of the form 0x00PS, where <P> is the number
1947 * of parallel ports and <S> is the number of serial ports.
1948 */
1949 switch (dev->device) {
1950 case PCI_DEVICE_ID_NETMOS_9835:
1951 /* Well, this rule doesn't hold for the following 9835 device */
1952 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1953 dev->subsystem_device == 0x0299)
1954 return;
1955 case PCI_DEVICE_ID_NETMOS_9735:
1956 case PCI_DEVICE_ID_NETMOS_9745:
1957 case PCI_DEVICE_ID_NETMOS_9845:
1958 case PCI_DEVICE_ID_NETMOS_9855:
1959 if (num_parallel) {
1960 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1961 dev->device, num_parallel, num_serial);
1962 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1963 (dev->class & 0xff);
1964 }
1965 }
1966 }
1967 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1968 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1969
1970 /*
1971 * Quirk non-zero PCI functions to route VPD access through function 0 for
1972 * devices that share VPD resources between functions. The functions are
1973 * expected to be identical devices.
1974 */
1975 static void quirk_f0_vpd_link(struct pci_dev *dev)
1976 {
1977 struct pci_dev *f0;
1978
1979 if (!PCI_FUNC(dev->devfn))
1980 return;
1981
1982 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1983 if (!f0)
1984 return;
1985
1986 if (f0->vpd && dev->class == f0->class &&
1987 dev->vendor == f0->vendor && dev->device == f0->device)
1988 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1989
1990 pci_dev_put(f0);
1991 }
1992 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1993 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1994
1995 static void quirk_e100_interrupt(struct pci_dev *dev)
1996 {
1997 u16 command, pmcsr;
1998 u8 __iomem *csr;
1999 u8 cmd_hi;
2000
2001 switch (dev->device) {
2002 /* PCI IDs taken from drivers/net/e100.c */
2003 case 0x1029:
2004 case 0x1030 ... 0x1034:
2005 case 0x1038 ... 0x103E:
2006 case 0x1050 ... 0x1057:
2007 case 0x1059:
2008 case 0x1064 ... 0x106B:
2009 case 0x1091 ... 0x1095:
2010 case 0x1209:
2011 case 0x1229:
2012 case 0x2449:
2013 case 0x2459:
2014 case 0x245D:
2015 case 0x27DC:
2016 break;
2017 default:
2018 return;
2019 }
2020
2021 /*
2022 * Some firmware hands off the e100 with interrupts enabled,
2023 * which can cause a flood of interrupts if packets are
2024 * received before the driver attaches to the device. So
2025 * disable all e100 interrupts here. The driver will
2026 * re-enable them when it's ready.
2027 */
2028 pci_read_config_word(dev, PCI_COMMAND, &command);
2029
2030 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2031 return;
2032
2033 /*
2034 * Check that the device is in the D0 power state. If it's not,
2035 * there is no point to look any further.
2036 */
2037 if (dev->pm_cap) {
2038 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2039 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2040 return;
2041 }
2042
2043 /* Convert from PCI bus to resource space. */
2044 csr = ioremap(pci_resource_start(dev, 0), 8);
2045 if (!csr) {
2046 pci_warn(dev, "Can't map e100 registers\n");
2047 return;
2048 }
2049
2050 cmd_hi = readb(csr + 3);
2051 if (cmd_hi == 0) {
2052 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2053 writeb(1, csr + 3);
2054 }
2055
2056 iounmap(csr);
2057 }
2058 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2059 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2060
2061 /*
2062 * The 82575 and 82598 may experience data corruption issues when transitioning
2063 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2064 */
2065 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2066 {
2067 pci_info(dev, "Disabling L0s\n");
2068 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2069 }
2070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2084
2085 static void fixup_rev1_53c810(struct pci_dev *dev)
2086 {
2087 u32 class = dev->class;
2088
2089 /*
2090 * rev 1 ncr53c810 chips don't set the class at all which means
2091 * they don't get their resources remapped. Fix that here.
2092 */
2093 if (class)
2094 return;
2095
2096 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2097 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2098 class, dev->class);
2099 }
2100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2101
2102 /* Enable 1k I/O space granularity on the Intel P64H2 */
2103 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2104 {
2105 u16 en1k;
2106
2107 pci_read_config_word(dev, 0x40, &en1k);
2108
2109 if (en1k & 0x200) {
2110 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2111 dev->io_window_1k = 1;
2112 }
2113 }
2114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2115
2116 /* Under some circumstances, AER is not linked with extended capabilities.
2117 * Force it to be linked by setting the corresponding control bit in the
2118 * config space.
2119 */
2120 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2121 {
2122 uint8_t b;
2123 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2124 if (!(b & 0x20)) {
2125 pci_write_config_byte(dev, 0xf41, b | 0x20);
2126 pci_info(dev, "Linking AER extended capability\n");
2127 }
2128 }
2129 }
2130 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2131 quirk_nvidia_ck804_pcie_aer_ext_cap);
2132 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2133 quirk_nvidia_ck804_pcie_aer_ext_cap);
2134
2135 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2136 {
2137 /*
2138 * Disable PCI Bus Parking and PCI Master read caching on CX700
2139 * which causes unspecified timing errors with a VT6212L on the PCI
2140 * bus leading to USB2.0 packet loss.
2141 *
2142 * This quirk is only enabled if a second (on the external PCI bus)
2143 * VT6212L is found -- the CX700 core itself also contains a USB
2144 * host controller with the same PCI ID as the VT6212L.
2145 */
2146
2147 /* Count VT6212L instances */
2148 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2149 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2150 uint8_t b;
2151
2152 /* p should contain the first (internal) VT6212L -- see if we have
2153 an external one by searching again */
2154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2155 if (!p)
2156 return;
2157 pci_dev_put(p);
2158
2159 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2160 if (b & 0x40) {
2161 /* Turn off PCI Bus Parking */
2162 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2163
2164 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2165 }
2166 }
2167
2168 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2169 if (b != 0) {
2170 /* Turn off PCI Master read caching */
2171 pci_write_config_byte(dev, 0x72, 0x0);
2172
2173 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2174 pci_write_config_byte(dev, 0x75, 0x1);
2175
2176 /* Disable "Read FIFO Timer" */
2177 pci_write_config_byte(dev, 0x77, 0x0);
2178
2179 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2180 }
2181 }
2182 }
2183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2184
2185 /*
2186 * If a device follows the VPD format spec, the PCI core will not read or
2187 * write past the VPD End Tag. But some vendors do not follow the VPD
2188 * format spec, so we can't tell how much data is safe to access. Devices
2189 * may behave unpredictably if we access too much. Blacklist these devices
2190 * so we don't touch VPD at all.
2191 */
2192 static void quirk_blacklist_vpd(struct pci_dev *dev)
2193 {
2194 if (dev->vpd) {
2195 dev->vpd->len = 0;
2196 pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2197 }
2198 }
2199
2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2212 quirk_blacklist_vpd);
2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2214
2215 /*
2216 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2217 * VPD end tag will hang the device. This problem was initially
2218 * observed when a vpd entry was created in sysfs
2219 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2220 * will dump 32k of data. Reading a full 32k will cause an access
2221 * beyond the VPD end tag causing the device to hang. Once the device
2222 * is hung, the bnx2 driver will not be able to reset the device.
2223 * We believe that it is legal to read beyond the end tag and
2224 * therefore the solution is to limit the read/write length.
2225 */
2226 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2227 {
2228 /*
2229 * Only disable the VPD capability for 5706, 5706S, 5708,
2230 * 5708S and 5709 rev. A
2231 */
2232 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2233 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2234 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2235 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2236 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2237 (dev->revision & 0xf0) == 0x0)) {
2238 if (dev->vpd)
2239 dev->vpd->len = 0x80;
2240 }
2241 }
2242
2243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2244 PCI_DEVICE_ID_NX2_5706,
2245 quirk_brcm_570x_limit_vpd);
2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2247 PCI_DEVICE_ID_NX2_5706S,
2248 quirk_brcm_570x_limit_vpd);
2249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2250 PCI_DEVICE_ID_NX2_5708,
2251 quirk_brcm_570x_limit_vpd);
2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2253 PCI_DEVICE_ID_NX2_5708S,
2254 quirk_brcm_570x_limit_vpd);
2255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2256 PCI_DEVICE_ID_NX2_5709,
2257 quirk_brcm_570x_limit_vpd);
2258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2259 PCI_DEVICE_ID_NX2_5709S,
2260 quirk_brcm_570x_limit_vpd);
2261
2262 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2263 {
2264 u32 rev;
2265
2266 pci_read_config_dword(dev, 0xf4, &rev);
2267
2268 /* Only CAP the MRRS if the device is a 5719 A0 */
2269 if (rev == 0x05719000) {
2270 int readrq = pcie_get_readrq(dev);
2271 if (readrq > 2048)
2272 pcie_set_readrq(dev, 2048);
2273 }
2274 }
2275
2276 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2277 PCI_DEVICE_ID_TIGON3_5719,
2278 quirk_brcm_5719_limit_mrrs);
2279
2280 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2281 static void quirk_paxc_bridge(struct pci_dev *pdev)
2282 {
2283 /* The PCI config space is shared with the PAXC root port and the first
2284 * Ethernet device. So, we need to workaround this by telling the PCI
2285 * code that the bridge is not an Ethernet device.
2286 */
2287 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2288 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2289
2290 /* MPSS is not being set properly (as it is currently 0). This is
2291 * because that area of the PCI config space is hard coded to zero, and
2292 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2293 * so that the MPS can be set to the real max value.
2294 */
2295 pdev->pcie_mpss = 2;
2296 }
2297 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2298 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2299 #endif
2300
2301 /* Originally in EDAC sources for i82875P:
2302 * Intel tells BIOS developers to hide device 6 which
2303 * configures the overflow device access containing
2304 * the DRBs - this is where we expose device 6.
2305 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2306 */
2307 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2308 {
2309 u8 reg;
2310
2311 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2312 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2313 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2314 }
2315 }
2316
2317 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2318 quirk_unhide_mch_dev6);
2319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2320 quirk_unhide_mch_dev6);
2321
2322 #ifdef CONFIG_TILEPRO
2323 /*
2324 * The Tilera TILEmpower tilepro platform needs to set the link speed
2325 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2326 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2327 * capability register of the PEX8624 PCIe switch. The switch
2328 * supports link speed auto negotiation, but falsely sets
2329 * the link speed to 5GT/s.
2330 */
2331 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2332 {
2333 if (tile_plx_gen1) {
2334 pci_write_config_dword(dev, 0x98, 0x1);
2335 mdelay(50);
2336 }
2337 }
2338 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2339 #endif /* CONFIG_TILEPRO */
2340
2341 #ifdef CONFIG_PCI_MSI
2342 /* Some chipsets do not support MSI. We cannot easily rely on setting
2343 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2344 * some other buses controlled by the chipset even if Linux is not
2345 * aware of it. Instead of setting the flag on all buses in the
2346 * machine, simply disable MSI globally.
2347 */
2348 static void quirk_disable_all_msi(struct pci_dev *dev)
2349 {
2350 pci_no_msi();
2351 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2352 }
2353 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2361
2362 /* Disable MSI on chipsets that are known to not support it */
2363 static void quirk_disable_msi(struct pci_dev *dev)
2364 {
2365 if (dev->subordinate) {
2366 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2367 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2368 }
2369 }
2370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2373
2374 /*
2375 * The APC bridge device in AMD 780 family northbridges has some random
2376 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2377 * we use the possible vendor/device IDs of the host bridge for the
2378 * declared quirk, and search for the APC bridge by slot number.
2379 */
2380 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2381 {
2382 struct pci_dev *apc_bridge;
2383
2384 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2385 if (apc_bridge) {
2386 if (apc_bridge->device == 0x9602)
2387 quirk_disable_msi(apc_bridge);
2388 pci_dev_put(apc_bridge);
2389 }
2390 }
2391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2393
2394 /* Go through the list of Hypertransport capabilities and
2395 * return 1 if a HT MSI capability is found and enabled */
2396 static int msi_ht_cap_enabled(struct pci_dev *dev)
2397 {
2398 int pos, ttl = PCI_FIND_CAP_TTL;
2399
2400 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2401 while (pos && ttl--) {
2402 u8 flags;
2403
2404 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2405 &flags) == 0) {
2406 pci_info(dev, "Found %s HT MSI Mapping\n",
2407 flags & HT_MSI_FLAGS_ENABLE ?
2408 "enabled" : "disabled");
2409 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2410 }
2411
2412 pos = pci_find_next_ht_capability(dev, pos,
2413 HT_CAPTYPE_MSI_MAPPING);
2414 }
2415 return 0;
2416 }
2417
2418 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2419 static void quirk_msi_ht_cap(struct pci_dev *dev)
2420 {
2421 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2422 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2423 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2424 }
2425 }
2426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2427 quirk_msi_ht_cap);
2428
2429 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2430 * MSI are supported if the MSI capability set in any of these mappings.
2431 */
2432 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2433 {
2434 struct pci_dev *pdev;
2435
2436 if (!dev->subordinate)
2437 return;
2438
2439 /* check HT MSI cap on this chipset and the root one.
2440 * a single one having MSI is enough to be sure that MSI are supported.
2441 */
2442 pdev = pci_get_slot(dev->bus, 0);
2443 if (!pdev)
2444 return;
2445 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2446 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2447 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2448 }
2449 pci_dev_put(pdev);
2450 }
2451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2452 quirk_nvidia_ck804_msi_ht_cap);
2453
2454 /* Force enable MSI mapping capability on HT bridges */
2455 static void ht_enable_msi_mapping(struct pci_dev *dev)
2456 {
2457 int pos, ttl = PCI_FIND_CAP_TTL;
2458
2459 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2460 while (pos && ttl--) {
2461 u8 flags;
2462
2463 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2464 &flags) == 0) {
2465 pci_info(dev, "Enabling HT MSI Mapping\n");
2466
2467 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2468 flags | HT_MSI_FLAGS_ENABLE);
2469 }
2470 pos = pci_find_next_ht_capability(dev, pos,
2471 HT_CAPTYPE_MSI_MAPPING);
2472 }
2473 }
2474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2475 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2476 ht_enable_msi_mapping);
2477
2478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2479 ht_enable_msi_mapping);
2480
2481 /* The P5N32-SLI motherboards from Asus have a problem with msi
2482 * for the MCP55 NIC. It is not yet determined whether the msi problem
2483 * also affects other devices. As for now, turn off msi for this device.
2484 */
2485 static void nvenet_msi_disable(struct pci_dev *dev)
2486 {
2487 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2488
2489 if (board_name &&
2490 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2491 strstr(board_name, "P5N32-E SLI"))) {
2492 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2493 dev->no_msi = 1;
2494 }
2495 }
2496 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2497 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2498 nvenet_msi_disable);
2499
2500 /*
2501 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2502 * config register. This register controls the routing of legacy
2503 * interrupts from devices that route through the MCP55. If this register
2504 * is misprogrammed, interrupts are only sent to the BSP, unlike
2505 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2506 * having this register set properly prevents kdump from booting up
2507 * properly, so let's make sure that we have it set correctly.
2508 * Note that this is an undocumented register.
2509 */
2510 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2511 {
2512 u32 cfg;
2513
2514 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2515 return;
2516
2517 pci_read_config_dword(dev, 0x74, &cfg);
2518
2519 if (cfg & ((1 << 2) | (1 << 15))) {
2520 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2521 cfg &= ~((1 << 2) | (1 << 15));
2522 pci_write_config_dword(dev, 0x74, cfg);
2523 }
2524 }
2525
2526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2527 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2528 nvbridge_check_legacy_irq_routing);
2529
2530 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2531 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2532 nvbridge_check_legacy_irq_routing);
2533
2534 static int ht_check_msi_mapping(struct pci_dev *dev)
2535 {
2536 int pos, ttl = PCI_FIND_CAP_TTL;
2537 int found = 0;
2538
2539 /* check if there is HT MSI cap or enabled on this device */
2540 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2541 while (pos && ttl--) {
2542 u8 flags;
2543
2544 if (found < 1)
2545 found = 1;
2546 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2547 &flags) == 0) {
2548 if (flags & HT_MSI_FLAGS_ENABLE) {
2549 if (found < 2) {
2550 found = 2;
2551 break;
2552 }
2553 }
2554 }
2555 pos = pci_find_next_ht_capability(dev, pos,
2556 HT_CAPTYPE_MSI_MAPPING);
2557 }
2558
2559 return found;
2560 }
2561
2562 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2563 {
2564 struct pci_dev *dev;
2565 int pos;
2566 int i, dev_no;
2567 int found = 0;
2568
2569 dev_no = host_bridge->devfn >> 3;
2570 for (i = dev_no + 1; i < 0x20; i++) {
2571 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2572 if (!dev)
2573 continue;
2574
2575 /* found next host bridge ?*/
2576 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2577 if (pos != 0) {
2578 pci_dev_put(dev);
2579 break;
2580 }
2581
2582 if (ht_check_msi_mapping(dev)) {
2583 found = 1;
2584 pci_dev_put(dev);
2585 break;
2586 }
2587 pci_dev_put(dev);
2588 }
2589
2590 return found;
2591 }
2592
2593 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2594 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2595
2596 static int is_end_of_ht_chain(struct pci_dev *dev)
2597 {
2598 int pos, ctrl_off;
2599 int end = 0;
2600 u16 flags, ctrl;
2601
2602 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2603
2604 if (!pos)
2605 goto out;
2606
2607 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2608
2609 ctrl_off = ((flags >> 10) & 1) ?
2610 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2611 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2612
2613 if (ctrl & (1 << 6))
2614 end = 1;
2615
2616 out:
2617 return end;
2618 }
2619
2620 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2621 {
2622 struct pci_dev *host_bridge;
2623 int pos;
2624 int i, dev_no;
2625 int found = 0;
2626
2627 dev_no = dev->devfn >> 3;
2628 for (i = dev_no; i >= 0; i--) {
2629 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2630 if (!host_bridge)
2631 continue;
2632
2633 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2634 if (pos != 0) {
2635 found = 1;
2636 break;
2637 }
2638 pci_dev_put(host_bridge);
2639 }
2640
2641 if (!found)
2642 return;
2643
2644 /* don't enable end_device/host_bridge with leaf directly here */
2645 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2646 host_bridge_with_leaf(host_bridge))
2647 goto out;
2648
2649 /* root did that ! */
2650 if (msi_ht_cap_enabled(host_bridge))
2651 goto out;
2652
2653 ht_enable_msi_mapping(dev);
2654
2655 out:
2656 pci_dev_put(host_bridge);
2657 }
2658
2659 static void ht_disable_msi_mapping(struct pci_dev *dev)
2660 {
2661 int pos, ttl = PCI_FIND_CAP_TTL;
2662
2663 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2664 while (pos && ttl--) {
2665 u8 flags;
2666
2667 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2668 &flags) == 0) {
2669 pci_info(dev, "Disabling HT MSI Mapping\n");
2670
2671 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2672 flags & ~HT_MSI_FLAGS_ENABLE);
2673 }
2674 pos = pci_find_next_ht_capability(dev, pos,
2675 HT_CAPTYPE_MSI_MAPPING);
2676 }
2677 }
2678
2679 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2680 {
2681 struct pci_dev *host_bridge;
2682 int pos;
2683 int found;
2684
2685 if (!pci_msi_enabled())
2686 return;
2687
2688 /* check if there is HT MSI cap or enabled on this device */
2689 found = ht_check_msi_mapping(dev);
2690
2691 /* no HT MSI CAP */
2692 if (found == 0)
2693 return;
2694
2695 /*
2696 * HT MSI mapping should be disabled on devices that are below
2697 * a non-Hypertransport host bridge. Locate the host bridge...
2698 */
2699 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2700 PCI_DEVFN(0, 0));
2701 if (host_bridge == NULL) {
2702 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2703 return;
2704 }
2705
2706 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2707 if (pos != 0) {
2708 /* Host bridge is to HT */
2709 if (found == 1) {
2710 /* it is not enabled, try to enable it */
2711 if (all)
2712 ht_enable_msi_mapping(dev);
2713 else
2714 nv_ht_enable_msi_mapping(dev);
2715 }
2716 goto out;
2717 }
2718
2719 /* HT MSI is not enabled */
2720 if (found == 1)
2721 goto out;
2722
2723 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2724 ht_disable_msi_mapping(dev);
2725
2726 out:
2727 pci_dev_put(host_bridge);
2728 }
2729
2730 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2731 {
2732 return __nv_msi_ht_cap_quirk(dev, 1);
2733 }
2734
2735 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2736 {
2737 return __nv_msi_ht_cap_quirk(dev, 0);
2738 }
2739
2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2741 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2742
2743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2744 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2745
2746 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2747 {
2748 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2749 }
2750 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2751 {
2752 struct pci_dev *p;
2753
2754 /* SB700 MSI issue will be fixed at HW level from revision A21,
2755 * we need check PCI REVISION ID of SMBus controller to get SB700
2756 * revision.
2757 */
2758 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2759 NULL);
2760 if (!p)
2761 return;
2762
2763 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2764 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2765 pci_dev_put(p);
2766 }
2767 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2768 {
2769 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2770 if (dev->revision < 0x18) {
2771 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2772 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2773 }
2774 }
2775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2776 PCI_DEVICE_ID_TIGON3_5780,
2777 quirk_msi_intx_disable_bug);
2778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2779 PCI_DEVICE_ID_TIGON3_5780S,
2780 quirk_msi_intx_disable_bug);
2781 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2782 PCI_DEVICE_ID_TIGON3_5714,
2783 quirk_msi_intx_disable_bug);
2784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2785 PCI_DEVICE_ID_TIGON3_5714S,
2786 quirk_msi_intx_disable_bug);
2787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2788 PCI_DEVICE_ID_TIGON3_5715,
2789 quirk_msi_intx_disable_bug);
2790 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2791 PCI_DEVICE_ID_TIGON3_5715S,
2792 quirk_msi_intx_disable_bug);
2793
2794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2795 quirk_msi_intx_disable_ati_bug);
2796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2797 quirk_msi_intx_disable_ati_bug);
2798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2799 quirk_msi_intx_disable_ati_bug);
2800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2801 quirk_msi_intx_disable_ati_bug);
2802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2803 quirk_msi_intx_disable_ati_bug);
2804
2805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2806 quirk_msi_intx_disable_bug);
2807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2808 quirk_msi_intx_disable_bug);
2809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2810 quirk_msi_intx_disable_bug);
2811
2812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2813 quirk_msi_intx_disable_bug);
2814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2815 quirk_msi_intx_disable_bug);
2816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2817 quirk_msi_intx_disable_bug);
2818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2819 quirk_msi_intx_disable_bug);
2820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2821 quirk_msi_intx_disable_bug);
2822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2823 quirk_msi_intx_disable_bug);
2824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2825 quirk_msi_intx_disable_qca_bug);
2826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2827 quirk_msi_intx_disable_qca_bug);
2828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2829 quirk_msi_intx_disable_qca_bug);
2830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2831 quirk_msi_intx_disable_qca_bug);
2832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2833 quirk_msi_intx_disable_qca_bug);
2834 #endif /* CONFIG_PCI_MSI */
2835
2836 /* Allow manual resource allocation for PCI hotplug bridges
2837 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2838 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2839 * kernel fails to allocate resources when hotplug device is
2840 * inserted and PCI bus is rescanned.
2841 */
2842 static void quirk_hotplug_bridge(struct pci_dev *dev)
2843 {
2844 dev->is_hotplug_bridge = 1;
2845 }
2846
2847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2848
2849 /*
2850 * This is a quirk for the Ricoh MMC controller found as a part of
2851 * some mulifunction chips.
2852
2853 * This is very similar and based on the ricoh_mmc driver written by
2854 * Philip Langdale. Thank you for these magic sequences.
2855 *
2856 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2857 * and one or both of cardbus or firewire.
2858 *
2859 * It happens that they implement SD and MMC
2860 * support as separate controllers (and PCI functions). The linux SDHCI
2861 * driver supports MMC cards but the chip detects MMC cards in hardware
2862 * and directs them to the MMC controller - so the SDHCI driver never sees
2863 * them.
2864 *
2865 * To get around this, we must disable the useless MMC controller.
2866 * At that point, the SDHCI controller will start seeing them
2867 * It seems to be the case that the relevant PCI registers to deactivate the
2868 * MMC controller live on PCI function 0, which might be the cardbus controller
2869 * or the firewire controller, depending on the particular chip in question
2870 *
2871 * This has to be done early, because as soon as we disable the MMC controller
2872 * other pci functions shift up one level, e.g. function #2 becomes function
2873 * #1, and this will confuse the pci core.
2874 */
2875
2876 #ifdef CONFIG_MMC_RICOH_MMC
2877 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2878 {
2879 /* disable via cardbus interface */
2880 u8 write_enable;
2881 u8 write_target;
2882 u8 disable;
2883
2884 /* disable must be done via function #0 */
2885 if (PCI_FUNC(dev->devfn))
2886 return;
2887
2888 pci_read_config_byte(dev, 0xB7, &disable);
2889 if (disable & 0x02)
2890 return;
2891
2892 pci_read_config_byte(dev, 0x8E, &write_enable);
2893 pci_write_config_byte(dev, 0x8E, 0xAA);
2894 pci_read_config_byte(dev, 0x8D, &write_target);
2895 pci_write_config_byte(dev, 0x8D, 0xB7);
2896 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2897 pci_write_config_byte(dev, 0x8E, write_enable);
2898 pci_write_config_byte(dev, 0x8D, write_target);
2899
2900 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2901 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2902 }
2903 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2904 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2905
2906 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2907 {
2908 /* disable via firewire interface */
2909 u8 write_enable;
2910 u8 disable;
2911
2912 /* disable must be done via function #0 */
2913 if (PCI_FUNC(dev->devfn))
2914 return;
2915 /*
2916 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2917 * certain types of SD/MMC cards. Lowering the SD base
2918 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2919 *
2920 * 0x150 - SD2.0 mode enable for changing base clock
2921 * frequency to 50Mhz
2922 * 0xe1 - Base clock frequency
2923 * 0x32 - 50Mhz new clock frequency
2924 * 0xf9 - Key register for 0x150
2925 * 0xfc - key register for 0xe1
2926 */
2927 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2928 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2929 pci_write_config_byte(dev, 0xf9, 0xfc);
2930 pci_write_config_byte(dev, 0x150, 0x10);
2931 pci_write_config_byte(dev, 0xf9, 0x00);
2932 pci_write_config_byte(dev, 0xfc, 0x01);
2933 pci_write_config_byte(dev, 0xe1, 0x32);
2934 pci_write_config_byte(dev, 0xfc, 0x00);
2935
2936 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
2937 }
2938
2939 pci_read_config_byte(dev, 0xCB, &disable);
2940
2941 if (disable & 0x02)
2942 return;
2943
2944 pci_read_config_byte(dev, 0xCA, &write_enable);
2945 pci_write_config_byte(dev, 0xCA, 0x57);
2946 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2947 pci_write_config_byte(dev, 0xCA, write_enable);
2948
2949 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2950 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2951
2952 }
2953 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2954 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2955 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2956 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2957 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2958 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2959 #endif /*CONFIG_MMC_RICOH_MMC*/
2960
2961 #ifdef CONFIG_DMAR_TABLE
2962 #define VTUNCERRMSK_REG 0x1ac
2963 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2964 /*
2965 * This is a quirk for masking vt-d spec defined errors to platform error
2966 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2967 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2968 * on the RAS config settings of the platform) when a vt-d fault happens.
2969 * The resulting SMI caused the system to hang.
2970 *
2971 * VT-d spec related errors are already handled by the VT-d OS code, so no
2972 * need to report the same error through other channels.
2973 */
2974 static void vtd_mask_spec_errors(struct pci_dev *dev)
2975 {
2976 u32 word;
2977
2978 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2979 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2980 }
2981 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2982 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2983 #endif
2984
2985 static void fixup_ti816x_class(struct pci_dev *dev)
2986 {
2987 u32 class = dev->class;
2988
2989 /* TI 816x devices do not have class code set when in PCIe boot mode */
2990 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2991 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
2992 class, dev->class);
2993 }
2994 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2995 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2996
2997 /* Some PCIe devices do not work reliably with the claimed maximum
2998 * payload size supported.
2999 */
3000 static void fixup_mpss_256(struct pci_dev *dev)
3001 {
3002 dev->pcie_mpss = 1; /* 256 bytes */
3003 }
3004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3005 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3007 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3009 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3010
3011 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
3012 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3013 * Since there is no way of knowing what the PCIE MPS on each fabric will be
3014 * until all of the devices are discovered and buses walked, read completion
3015 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3016 * it is possible to hotplug a device with MPS of 256B.
3017 */
3018 static void quirk_intel_mc_errata(struct pci_dev *dev)
3019 {
3020 int err;
3021 u16 rcc;
3022
3023 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3024 pcie_bus_config == PCIE_BUS_DEFAULT)
3025 return;
3026
3027 /* Intel errata specifies bits to change but does not say what they are.
3028 * Keeping them magical until such time as the registers and values can
3029 * be explained.
3030 */
3031 err = pci_read_config_word(dev, 0x48, &rcc);
3032 if (err) {
3033 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3034 return;
3035 }
3036
3037 if (!(rcc & (1 << 10)))
3038 return;
3039
3040 rcc &= ~(1 << 10);
3041
3042 err = pci_write_config_word(dev, 0x48, rcc);
3043 if (err) {
3044 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3045 return;
3046 }
3047
3048 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3049 }
3050 /* Intel 5000 series memory controllers and ports 2-7 */
3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3065 /* Intel 5100 series memory controllers and ports 2-7 */
3066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3077
3078
3079 /*
3080 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3081 * work around this, query the size it should be configured to by the device and
3082 * modify the resource end to correspond to this new size.
3083 */
3084 static void quirk_intel_ntb(struct pci_dev *dev)
3085 {
3086 int rc;
3087 u8 val;
3088
3089 rc = pci_read_config_byte(dev, 0x00D0, &val);
3090 if (rc)
3091 return;
3092
3093 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3094
3095 rc = pci_read_config_byte(dev, 0x00D1, &val);
3096 if (rc)
3097 return;
3098
3099 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3100 }
3101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3103
3104 static ktime_t fixup_debug_start(struct pci_dev *dev,
3105 void (*fn)(struct pci_dev *dev))
3106 {
3107 ktime_t calltime = 0;
3108
3109 pci_dbg(dev, "calling %pF\n", fn);
3110 if (initcall_debug) {
3111 pr_debug("calling %pF @ %i for %s\n",
3112 fn, task_pid_nr(current), dev_name(&dev->dev));
3113 calltime = ktime_get();
3114 }
3115
3116 return calltime;
3117 }
3118
3119 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3120 void (*fn)(struct pci_dev *dev))
3121 {
3122 ktime_t delta, rettime;
3123 unsigned long long duration;
3124
3125 if (initcall_debug) {
3126 rettime = ktime_get();
3127 delta = ktime_sub(rettime, calltime);
3128 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3129 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3130 fn, duration, dev_name(&dev->dev));
3131 }
3132 }
3133
3134 /*
3135 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3136 * even though no one is handling them (f.e. i915 driver is never loaded).
3137 * Additionally the interrupt destination is not set up properly
3138 * and the interrupt ends up -somewhere-.
3139 *
3140 * These spurious interrupts are "sticky" and the kernel disables
3141 * the (shared) interrupt line after 100.000+ generated interrupts.
3142 *
3143 * Fix it by disabling the still enabled interrupts.
3144 * This resolves crashes often seen on monitor unplug.
3145 */
3146 #define I915_DEIER_REG 0x4400c
3147 static void disable_igfx_irq(struct pci_dev *dev)
3148 {
3149 void __iomem *regs = pci_iomap(dev, 0, 0);
3150 if (regs == NULL) {
3151 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3152 return;
3153 }
3154
3155 /* Check if any interrupt line is still enabled */
3156 if (readl(regs + I915_DEIER_REG) != 0) {
3157 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3158
3159 writel(0, regs + I915_DEIER_REG);
3160 }
3161
3162 pci_iounmap(dev, regs);
3163 }
3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3167
3168 /*
3169 * PCI devices which are on Intel chips can skip the 10ms delay
3170 * before entering D3 mode.
3171 */
3172 static void quirk_remove_d3_delay(struct pci_dev *dev)
3173 {
3174 dev->d3_delay = 0;
3175 }
3176 /* C600 Series devices do not need 10ms d3_delay */
3177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3180 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3192 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3202
3203 /*
3204 * Some devices may pass our check in pci_intx_mask_supported() if
3205 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3206 * support this feature.
3207 */
3208 static void quirk_broken_intx_masking(struct pci_dev *dev)
3209 {
3210 dev->broken_intx_masking = 1;
3211 }
3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3213 quirk_broken_intx_masking);
3214 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3215 quirk_broken_intx_masking);
3216 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3217 quirk_broken_intx_masking);
3218
3219 /*
3220 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3221 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3222 *
3223 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3224 */
3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3226 quirk_broken_intx_masking);
3227
3228 /*
3229 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3230 * DisINTx can be set but the interrupt status bit is non-functional.
3231 */
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3233 quirk_broken_intx_masking);
3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3235 quirk_broken_intx_masking);
3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3237 quirk_broken_intx_masking);
3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3239 quirk_broken_intx_masking);
3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3241 quirk_broken_intx_masking);
3242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3243 quirk_broken_intx_masking);
3244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3245 quirk_broken_intx_masking);
3246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3247 quirk_broken_intx_masking);
3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3249 quirk_broken_intx_masking);
3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3251 quirk_broken_intx_masking);
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3253 quirk_broken_intx_masking);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3255 quirk_broken_intx_masking);
3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3257 quirk_broken_intx_masking);
3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3259 quirk_broken_intx_masking);
3260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3261 quirk_broken_intx_masking);
3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3263 quirk_broken_intx_masking);
3264
3265 static u16 mellanox_broken_intx_devs[] = {
3266 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3267 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3268 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3269 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3270 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3271 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3272 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3273 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3274 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3275 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3276 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3277 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3278 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3279 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3280 };
3281
3282 #define CONNECTX_4_CURR_MAX_MINOR 99
3283 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3284
3285 /*
3286 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3287 * If so, don't mark it as broken.
3288 * FW minor > 99 means older FW version format and no INTx masking support.
3289 * FW minor < 14 means new FW version format and no INTx masking support.
3290 */
3291 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3292 {
3293 __be32 __iomem *fw_ver;
3294 u16 fw_major;
3295 u16 fw_minor;
3296 u16 fw_subminor;
3297 u32 fw_maj_min;
3298 u32 fw_sub_min;
3299 int i;
3300
3301 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3302 if (pdev->device == mellanox_broken_intx_devs[i]) {
3303 pdev->broken_intx_masking = 1;
3304 return;
3305 }
3306 }
3307
3308 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3309 * support so shouldn't be checked further
3310 */
3311 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3312 return;
3313
3314 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3315 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3316 return;
3317
3318 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3319 if (pci_enable_device_mem(pdev)) {
3320 pci_warn(pdev, "Can't enable device memory\n");
3321 return;
3322 }
3323
3324 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3325 if (!fw_ver) {
3326 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3327 goto out;
3328 }
3329
3330 /* Reading from resource space should be 32b aligned */
3331 fw_maj_min = ioread32be(fw_ver);
3332 fw_sub_min = ioread32be(fw_ver + 1);
3333 fw_major = fw_maj_min & 0xffff;
3334 fw_minor = fw_maj_min >> 16;
3335 fw_subminor = fw_sub_min & 0xffff;
3336 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3337 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3338 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3339 fw_major, fw_minor, fw_subminor, pdev->device ==
3340 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3341 pdev->broken_intx_masking = 1;
3342 }
3343
3344 iounmap(fw_ver);
3345
3346 out:
3347 pci_disable_device(pdev);
3348 }
3349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3350 mellanox_check_broken_intx_masking);
3351
3352 static void quirk_no_bus_reset(struct pci_dev *dev)
3353 {
3354 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3355 }
3356
3357 /*
3358 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3359 * The device will throw a Link Down error on AER-capable systems and
3360 * regardless of AER, config space of the device is never accessible again
3361 * and typically causes the system to hang or reset when access is attempted.
3362 * http://www.spinics.net/lists/linux-pci/msg34797.html
3363 */
3364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3368
3369 /*
3370 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3371 * reset when used with certain child devices. After the reset, config
3372 * accesses to the child may fail.
3373 */
3374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3375
3376 static void quirk_no_pm_reset(struct pci_dev *dev)
3377 {
3378 /*
3379 * We can't do a bus reset on root bus devices, but an ineffective
3380 * PM reset may be better than nothing.
3381 */
3382 if (!pci_is_root_bus(dev->bus))
3383 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3384 }
3385
3386 /*
3387 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3388 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3389 * to have no effect on the device: it retains the framebuffer contents and
3390 * monitor sync. Advertising this support makes other layers, like VFIO,
3391 * assume pci_reset_function() is viable for this device. Mark it as
3392 * unavailable to skip it when testing reset methods.
3393 */
3394 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3395 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3396
3397 /*
3398 * Thunderbolt controllers with broken MSI hotplug signaling:
3399 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3400 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3401 */
3402 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3403 {
3404 if (pdev->is_hotplug_bridge &&
3405 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3406 pdev->revision <= 1))
3407 pdev->no_msi = 1;
3408 }
3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3410 quirk_thunderbolt_hotplug_msi);
3411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3412 quirk_thunderbolt_hotplug_msi);
3413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3414 quirk_thunderbolt_hotplug_msi);
3415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3416 quirk_thunderbolt_hotplug_msi);
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3418 quirk_thunderbolt_hotplug_msi);
3419
3420 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3421 {
3422 int chip = (dev->device & 0xf000) >> 12;
3423 int func = (dev->device & 0x0f00) >> 8;
3424 int prod = (dev->device & 0x00ff) >> 0;
3425
3426 /*
3427 * If this is a T3-based adapter, there's a 1KB VPD area at offset
3428 * 0xc00 which contains the preferred VPD values. If this is a T4 or
3429 * later based adapter, the special VPD is at offset 0x400 for the
3430 * Physical Functions (the SR-IOV Virtual Functions have no VPD
3431 * Capabilities). The PCI VPD Access core routines will normally
3432 * compute the size of the VPD by parsing the VPD Data Structure at
3433 * offset 0x000. This will result in silent failures when attempting
3434 * to accesses these other VPD areas which are beyond those computed
3435 * limits.
3436 */
3437 if (chip == 0x0 && prod >= 0x20)
3438 pci_set_vpd_size(dev, 8192);
3439 else if (chip >= 0x4 && func < 0x8)
3440 pci_set_vpd_size(dev, 2048);
3441 }
3442
3443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3444 quirk_chelsio_extend_vpd);
3445
3446 #ifdef CONFIG_ACPI
3447 /*
3448 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3449 *
3450 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3451 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3452 * be present after resume if a device was plugged in before suspend.
3453 *
3454 * The thunderbolt controller consists of a pcie switch with downstream
3455 * bridges leading to the NHI and to the tunnel pci bridges.
3456 *
3457 * This quirk cuts power to the whole chip. Therefore we have to apply it
3458 * during suspend_noirq of the upstream bridge.
3459 *
3460 * Power is automagically restored before resume. No action is needed.
3461 */
3462 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3463 {
3464 acpi_handle bridge, SXIO, SXFP, SXLV;
3465
3466 if (!x86_apple_machine)
3467 return;
3468 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3469 return;
3470 bridge = ACPI_HANDLE(&dev->dev);
3471 if (!bridge)
3472 return;
3473 /*
3474 * SXIO and SXLV are present only on machines requiring this quirk.
3475 * TB bridges in external devices might have the same device id as those
3476 * on the host, but they will not have the associated ACPI methods. This
3477 * implicitly checks that we are at the right bridge.
3478 */
3479 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3480 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3481 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3482 return;
3483 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n");
3484
3485 /* magic sequence */
3486 acpi_execute_simple_method(SXIO, NULL, 1);
3487 acpi_execute_simple_method(SXFP, NULL, 0);
3488 msleep(300);
3489 acpi_execute_simple_method(SXLV, NULL, 0);
3490 acpi_execute_simple_method(SXIO, NULL, 0);
3491 acpi_execute_simple_method(SXLV, NULL, 0);
3492 }
3493 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3494 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3495 quirk_apple_poweroff_thunderbolt);
3496
3497 /*
3498 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3499 *
3500 * During suspend the thunderbolt controller is reset and all pci
3501 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3502 * during resume. We have to manually wait for the NHI since there is
3503 * no parent child relationship between the NHI and the tunneled
3504 * bridges.
3505 */
3506 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3507 {
3508 struct pci_dev *sibling = NULL;
3509 struct pci_dev *nhi = NULL;
3510
3511 if (!x86_apple_machine)
3512 return;
3513 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3514 return;
3515 /*
3516 * Find the NHI and confirm that we are a bridge on the tb host
3517 * controller and not on a tb endpoint.
3518 */
3519 sibling = pci_get_slot(dev->bus, 0x0);
3520 if (sibling == dev)
3521 goto out; /* we are the downstream bridge to the NHI */
3522 if (!sibling || !sibling->subordinate)
3523 goto out;
3524 nhi = pci_get_slot(sibling->subordinate, 0x0);
3525 if (!nhi)
3526 goto out;
3527 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3528 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3529 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3530 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3531 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3532 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3533 goto out;
3534 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3535 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3536 out:
3537 pci_dev_put(nhi);
3538 pci_dev_put(sibling);
3539 }
3540 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3541 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3542 quirk_apple_wait_for_thunderbolt);
3543 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3544 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3545 quirk_apple_wait_for_thunderbolt);
3546 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3547 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3548 quirk_apple_wait_for_thunderbolt);
3549 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3550 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3551 quirk_apple_wait_for_thunderbolt);
3552 #endif
3553
3554 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3555 struct pci_fixup *end)
3556 {
3557 ktime_t calltime;
3558
3559 for (; f < end; f++)
3560 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3561 f->class == (u32) PCI_ANY_ID) &&
3562 (f->vendor == dev->vendor ||
3563 f->vendor == (u16) PCI_ANY_ID) &&
3564 (f->device == dev->device ||
3565 f->device == (u16) PCI_ANY_ID)) {
3566 calltime = fixup_debug_start(dev, f->hook);
3567 f->hook(dev);
3568 fixup_debug_report(dev, calltime, f->hook);
3569 }
3570 }
3571
3572 extern struct pci_fixup __start_pci_fixups_early[];
3573 extern struct pci_fixup __end_pci_fixups_early[];
3574 extern struct pci_fixup __start_pci_fixups_header[];
3575 extern struct pci_fixup __end_pci_fixups_header[];
3576 extern struct pci_fixup __start_pci_fixups_final[];
3577 extern struct pci_fixup __end_pci_fixups_final[];
3578 extern struct pci_fixup __start_pci_fixups_enable[];
3579 extern struct pci_fixup __end_pci_fixups_enable[];
3580 extern struct pci_fixup __start_pci_fixups_resume[];
3581 extern struct pci_fixup __end_pci_fixups_resume[];
3582 extern struct pci_fixup __start_pci_fixups_resume_early[];
3583 extern struct pci_fixup __end_pci_fixups_resume_early[];
3584 extern struct pci_fixup __start_pci_fixups_suspend[];
3585 extern struct pci_fixup __end_pci_fixups_suspend[];
3586 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3587 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3588
3589 static bool pci_apply_fixup_final_quirks;
3590
3591 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3592 {
3593 struct pci_fixup *start, *end;
3594
3595 switch (pass) {
3596 case pci_fixup_early:
3597 start = __start_pci_fixups_early;
3598 end = __end_pci_fixups_early;
3599 break;
3600
3601 case pci_fixup_header:
3602 start = __start_pci_fixups_header;
3603 end = __end_pci_fixups_header;
3604 break;
3605
3606 case pci_fixup_final:
3607 if (!pci_apply_fixup_final_quirks)
3608 return;
3609 start = __start_pci_fixups_final;
3610 end = __end_pci_fixups_final;
3611 break;
3612
3613 case pci_fixup_enable:
3614 start = __start_pci_fixups_enable;
3615 end = __end_pci_fixups_enable;
3616 break;
3617
3618 case pci_fixup_resume:
3619 start = __start_pci_fixups_resume;
3620 end = __end_pci_fixups_resume;
3621 break;
3622
3623 case pci_fixup_resume_early:
3624 start = __start_pci_fixups_resume_early;
3625 end = __end_pci_fixups_resume_early;
3626 break;
3627
3628 case pci_fixup_suspend:
3629 start = __start_pci_fixups_suspend;
3630 end = __end_pci_fixups_suspend;
3631 break;
3632
3633 case pci_fixup_suspend_late:
3634 start = __start_pci_fixups_suspend_late;
3635 end = __end_pci_fixups_suspend_late;
3636 break;
3637
3638 default:
3639 /* stupid compiler warning, you would think with an enum... */
3640 return;
3641 }
3642 pci_do_fixups(dev, start, end);
3643 }
3644 EXPORT_SYMBOL(pci_fixup_device);
3645
3646
3647 static int __init pci_apply_final_quirks(void)
3648 {
3649 struct pci_dev *dev = NULL;
3650 u8 cls = 0;
3651 u8 tmp;
3652
3653 if (pci_cache_line_size)
3654 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3655 pci_cache_line_size << 2);
3656
3657 pci_apply_fixup_final_quirks = true;
3658 for_each_pci_dev(dev) {
3659 pci_fixup_device(pci_fixup_final, dev);
3660 /*
3661 * If arch hasn't set it explicitly yet, use the CLS
3662 * value shared by all PCI devices. If there's a
3663 * mismatch, fall back to the default value.
3664 */
3665 if (!pci_cache_line_size) {
3666 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3667 if (!cls)
3668 cls = tmp;
3669 if (!tmp || cls == tmp)
3670 continue;
3671
3672 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3673 cls << 2, tmp << 2,
3674 pci_dfl_cache_line_size << 2);
3675 pci_cache_line_size = pci_dfl_cache_line_size;
3676 }
3677 }
3678
3679 if (!pci_cache_line_size) {
3680 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3681 cls << 2, pci_dfl_cache_line_size << 2);
3682 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3683 }
3684
3685 return 0;
3686 }
3687
3688 fs_initcall_sync(pci_apply_final_quirks);
3689
3690 /*
3691 * Following are device-specific reset methods which can be used to
3692 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3693 * not available.
3694 */
3695 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3696 {
3697 /*
3698 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3699 *
3700 * The 82599 supports FLR on VFs, but FLR support is reported only
3701 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3702 * Thus we must call pcie_flr() directly without first checking if it is
3703 * supported.
3704 */
3705 if (!probe)
3706 pcie_flr(dev);
3707 return 0;
3708 }
3709
3710 #define SOUTH_CHICKEN2 0xc2004
3711 #define PCH_PP_STATUS 0xc7200
3712 #define PCH_PP_CONTROL 0xc7204
3713 #define MSG_CTL 0x45010
3714 #define NSDE_PWR_STATE 0xd0100
3715 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3716
3717 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3718 {
3719 void __iomem *mmio_base;
3720 unsigned long timeout;
3721 u32 val;
3722
3723 if (probe)
3724 return 0;
3725
3726 mmio_base = pci_iomap(dev, 0, 0);
3727 if (!mmio_base)
3728 return -ENOMEM;
3729
3730 iowrite32(0x00000002, mmio_base + MSG_CTL);
3731
3732 /*
3733 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3734 * driver loaded sets the right bits. However, this's a reset and
3735 * the bits have been set by i915 previously, so we clobber
3736 * SOUTH_CHICKEN2 register directly here.
3737 */
3738 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3739
3740 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3741 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3742
3743 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3744 do {
3745 val = ioread32(mmio_base + PCH_PP_STATUS);
3746 if ((val & 0xb0000000) == 0)
3747 goto reset_complete;
3748 msleep(10);
3749 } while (time_before(jiffies, timeout));
3750 pci_warn(dev, "timeout during reset\n");
3751
3752 reset_complete:
3753 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3754
3755 pci_iounmap(dev, mmio_base);
3756 return 0;
3757 }
3758
3759 /*
3760 * Device-specific reset method for Chelsio T4-based adapters.
3761 */
3762 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3763 {
3764 u16 old_command;
3765 u16 msix_flags;
3766
3767 /*
3768 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3769 * that we have no device-specific reset method.
3770 */
3771 if ((dev->device & 0xf000) != 0x4000)
3772 return -ENOTTY;
3773
3774 /*
3775 * If this is the "probe" phase, return 0 indicating that we can
3776 * reset this device.
3777 */
3778 if (probe)
3779 return 0;
3780
3781 /*
3782 * T4 can wedge if there are DMAs in flight within the chip and Bus
3783 * Master has been disabled. We need to have it on till the Function
3784 * Level Reset completes. (BUS_MASTER is disabled in
3785 * pci_reset_function()).
3786 */
3787 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3788 pci_write_config_word(dev, PCI_COMMAND,
3789 old_command | PCI_COMMAND_MASTER);
3790
3791 /*
3792 * Perform the actual device function reset, saving and restoring
3793 * configuration information around the reset.
3794 */
3795 pci_save_state(dev);
3796
3797 /*
3798 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3799 * are disabled when an MSI-X interrupt message needs to be delivered.
3800 * So we briefly re-enable MSI-X interrupts for the duration of the
3801 * FLR. The pci_restore_state() below will restore the original
3802 * MSI-X state.
3803 */
3804 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3805 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3806 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3807 msix_flags |
3808 PCI_MSIX_FLAGS_ENABLE |
3809 PCI_MSIX_FLAGS_MASKALL);
3810
3811 pcie_flr(dev);
3812
3813 /*
3814 * Restore the configuration information (BAR values, etc.) including
3815 * the original PCI Configuration Space Command word, and return
3816 * success.
3817 */
3818 pci_restore_state(dev);
3819 pci_write_config_word(dev, PCI_COMMAND, old_command);
3820 return 0;
3821 }
3822
3823 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3824 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3825 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3826
3827 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3828 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3829 reset_intel_82599_sfp_virtfn },
3830 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3831 reset_ivb_igd },
3832 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3833 reset_ivb_igd },
3834 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3835 reset_chelsio_generic_dev },
3836 { 0 }
3837 };
3838
3839 /*
3840 * These device-specific reset methods are here rather than in a driver
3841 * because when a host assigns a device to a guest VM, the host may need
3842 * to reset the device but probably doesn't have a driver for it.
3843 */
3844 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3845 {
3846 const struct pci_dev_reset_methods *i;
3847
3848 for (i = pci_dev_reset_methods; i->reset; i++) {
3849 if ((i->vendor == dev->vendor ||
3850 i->vendor == (u16)PCI_ANY_ID) &&
3851 (i->device == dev->device ||
3852 i->device == (u16)PCI_ANY_ID))
3853 return i->reset(dev, probe);
3854 }
3855
3856 return -ENOTTY;
3857 }
3858
3859 static void quirk_dma_func0_alias(struct pci_dev *dev)
3860 {
3861 if (PCI_FUNC(dev->devfn) != 0)
3862 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3863 }
3864
3865 /*
3866 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3867 *
3868 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3869 */
3870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3872
3873 static void quirk_dma_func1_alias(struct pci_dev *dev)
3874 {
3875 if (PCI_FUNC(dev->devfn) != 1)
3876 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3877 }
3878
3879 /*
3880 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3881 * SKUs function 1 is present and is a legacy IDE controller, in other
3882 * SKUs this function is not present, making this a ghost requester.
3883 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3884 */
3885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3886 quirk_dma_func1_alias);
3887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3888 quirk_dma_func1_alias);
3889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3890 quirk_dma_func1_alias);
3891 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3893 quirk_dma_func1_alias);
3894 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3896 quirk_dma_func1_alias);
3897 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3899 quirk_dma_func1_alias);
3900 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3902 quirk_dma_func1_alias);
3903 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3904 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3905 quirk_dma_func1_alias);
3906 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3908 quirk_dma_func1_alias);
3909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3910 quirk_dma_func1_alias);
3911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3912 quirk_dma_func1_alias);
3913 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3915 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3916 quirk_dma_func1_alias);
3917 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3918 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3919 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3920 quirk_dma_func1_alias);
3921
3922 /*
3923 * Some devices DMA with the wrong devfn, not just the wrong function.
3924 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3925 * the alias is "fixed" and independent of the device devfn.
3926 *
3927 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3928 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3929 * single device on the secondary bus. In reality, the single exposed
3930 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3931 * that provides a bridge to the internal bus of the I/O processor. The
3932 * controller supports private devices, which can be hidden from PCI config
3933 * space. In the case of the Adaptec 3405, a private device at 01.0
3934 * appears to be the DMA engine, which therefore needs to become a DMA
3935 * alias for the device.
3936 */
3937 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3938 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3939 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3940 .driver_data = PCI_DEVFN(1, 0) },
3941 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3942 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3943 .driver_data = PCI_DEVFN(1, 0) },
3944 { 0 }
3945 };
3946
3947 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3948 {
3949 const struct pci_device_id *id;
3950
3951 id = pci_match_id(fixed_dma_alias_tbl, dev);
3952 if (id)
3953 pci_add_dma_alias(dev, id->driver_data);
3954 }
3955
3956 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3957
3958 /*
3959 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3960 * using the wrong DMA alias for the device. Some of these devices can be
3961 * used as either forward or reverse bridges, so we need to test whether the
3962 * device is operating in the correct mode. We could probably apply this
3963 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3964 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3965 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3966 */
3967 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3968 {
3969 if (!pci_is_root_bus(pdev->bus) &&
3970 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3971 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3972 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3973 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3974 }
3975 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3977 quirk_use_pcie_bridge_dma_alias);
3978 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3979 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3980 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3981 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3982 /* ITE 8893 has the same problem as the 8892 */
3983 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
3984 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3985 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3986
3987 /*
3988 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3989 * be added as aliases to the DMA device in order to allow buffer access
3990 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3991 * programmed in the EEPROM.
3992 */
3993 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3994 {
3995 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3996 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3997 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3998 }
3999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4001
4002 /*
4003 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4004 * associated not at the root bus, but at a bridge below. This quirk avoids
4005 * generating invalid DMA aliases.
4006 */
4007 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4008 {
4009 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4010 }
4011 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4012 quirk_bridge_cavm_thrx2_pcie_root);
4013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4014 quirk_bridge_cavm_thrx2_pcie_root);
4015
4016 /*
4017 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4018 * class code. Fix it.
4019 */
4020 static void quirk_tw686x_class(struct pci_dev *pdev)
4021 {
4022 u32 class = pdev->class;
4023
4024 /* Use "Multimedia controller" class */
4025 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4026 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4027 class, pdev->class);
4028 }
4029 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4030 quirk_tw686x_class);
4031 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4032 quirk_tw686x_class);
4033 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4034 quirk_tw686x_class);
4035 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4036 quirk_tw686x_class);
4037
4038 /*
4039 * Some devices have problems with Transaction Layer Packets with the Relaxed
4040 * Ordering Attribute set. Such devices should mark themselves and other
4041 * Device Drivers should check before sending TLPs with RO set.
4042 */
4043 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4044 {
4045 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4046 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4047 }
4048
4049 /*
4050 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4051 * Complex has a Flow Control Credit issue which can cause performance
4052 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4053 */
4054 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4055 quirk_relaxedordering_disable);
4056 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4057 quirk_relaxedordering_disable);
4058 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4059 quirk_relaxedordering_disable);
4060 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4061 quirk_relaxedordering_disable);
4062 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4063 quirk_relaxedordering_disable);
4064 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4065 quirk_relaxedordering_disable);
4066 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4067 quirk_relaxedordering_disable);
4068 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4069 quirk_relaxedordering_disable);
4070 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4071 quirk_relaxedordering_disable);
4072 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4073 quirk_relaxedordering_disable);
4074 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4075 quirk_relaxedordering_disable);
4076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4077 quirk_relaxedordering_disable);
4078 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4079 quirk_relaxedordering_disable);
4080 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4081 quirk_relaxedordering_disable);
4082 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4083 quirk_relaxedordering_disable);
4084 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4085 quirk_relaxedordering_disable);
4086 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4087 quirk_relaxedordering_disable);
4088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4089 quirk_relaxedordering_disable);
4090 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4091 quirk_relaxedordering_disable);
4092 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4093 quirk_relaxedordering_disable);
4094 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4095 quirk_relaxedordering_disable);
4096 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4097 quirk_relaxedordering_disable);
4098 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4099 quirk_relaxedordering_disable);
4100 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4101 quirk_relaxedordering_disable);
4102 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4103 quirk_relaxedordering_disable);
4104 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4105 quirk_relaxedordering_disable);
4106 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4107 quirk_relaxedordering_disable);
4108 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4109 quirk_relaxedordering_disable);
4110
4111 /*
4112 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4113 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4114 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4115 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4116 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4117 * November 10, 2010). As a result, on this platform we can't use Relaxed
4118 * Ordering for Upstream TLPs.
4119 */
4120 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4121 quirk_relaxedordering_disable);
4122 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4123 quirk_relaxedordering_disable);
4124 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4125 quirk_relaxedordering_disable);
4126
4127 /*
4128 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4129 * values for the Attribute as were supplied in the header of the
4130 * corresponding Request, except as explicitly allowed when IDO is used."
4131 *
4132 * If a non-compliant device generates a completion with a different
4133 * attribute than the request, the receiver may accept it (which itself
4134 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4135 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4136 * device access timeout.
4137 *
4138 * If the non-compliant device generates completions with zero attributes
4139 * (instead of copying the attributes from the request), we can work around
4140 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4141 * upstream devices so they always generate requests with zero attributes.
4142 *
4143 * This affects other devices under the same Root Port, but since these
4144 * attributes are performance hints, there should be no functional problem.
4145 *
4146 * Note that Configuration Space accesses are never supposed to have TLP
4147 * Attributes, so we're safe waiting till after any Configuration Space
4148 * accesses to do the Root Port fixup.
4149 */
4150 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4151 {
4152 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4153
4154 if (!root_port) {
4155 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4156 return;
4157 }
4158
4159 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4160 dev_name(&pdev->dev));
4161 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4162 PCI_EXP_DEVCTL_RELAX_EN |
4163 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4164 }
4165
4166 /*
4167 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4168 * Completion it generates.
4169 */
4170 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4171 {
4172 /*
4173 * This mask/compare operation selects for Physical Function 4 on a
4174 * T5. We only need to fix up the Root Port once for any of the
4175 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4176 * 0x54xx so we use that one,
4177 */
4178 if ((pdev->device & 0xff00) == 0x5400)
4179 quirk_disable_root_port_attributes(pdev);
4180 }
4181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4182 quirk_chelsio_T5_disable_root_port_attributes);
4183
4184 /*
4185 * AMD has indicated that the devices below do not support peer-to-peer
4186 * in any system where they are found in the southbridge with an AMD
4187 * IOMMU in the system. Multifunction devices that do not support
4188 * peer-to-peer between functions can claim to support a subset of ACS.
4189 * Such devices effectively enable request redirect (RR) and completion
4190 * redirect (CR) since all transactions are redirected to the upstream
4191 * root complex.
4192 *
4193 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4194 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4195 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4196 *
4197 * 1002:4385 SBx00 SMBus Controller
4198 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4199 * 1002:4383 SBx00 Azalia (Intel HDA)
4200 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4201 * 1002:4384 SBx00 PCI to PCI Bridge
4202 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4203 *
4204 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4205 *
4206 * 1022:780f [AMD] FCH PCI Bridge
4207 * 1022:7809 [AMD] FCH USB OHCI Controller
4208 */
4209 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4210 {
4211 #ifdef CONFIG_ACPI
4212 struct acpi_table_header *header = NULL;
4213 acpi_status status;
4214
4215 /* Targeting multifunction devices on the SB (appears on root bus) */
4216 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4217 return -ENODEV;
4218
4219 /* The IVRS table describes the AMD IOMMU */
4220 status = acpi_get_table("IVRS", 0, &header);
4221 if (ACPI_FAILURE(status))
4222 return -ENODEV;
4223
4224 /* Filter out flags not applicable to multifunction */
4225 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4226
4227 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4228 #else
4229 return -ENODEV;
4230 #endif
4231 }
4232
4233 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4234 {
4235 /*
4236 * Effectively selects all downstream ports for whole ThunderX 1
4237 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4238 * bits of device ID are used to indicate which subdevice is used
4239 * within the SoC.
4240 */
4241 return (pci_is_pcie(dev) &&
4242 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4243 ((dev->device & 0xf800) == 0xa000));
4244 }
4245
4246 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4247 {
4248 /*
4249 * Cavium root ports don't advertise an ACS capability. However,
4250 * the RTL internally implements similar protection as if ACS had
4251 * Request Redirection, Completion Redirection, Source Validation,
4252 * and Upstream Forwarding features enabled. Assert that the
4253 * hardware implements and enables equivalent ACS functionality for
4254 * these flags.
4255 */
4256 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4257
4258 if (!pci_quirk_cavium_acs_match(dev))
4259 return -ENOTTY;
4260
4261 return acs_flags ? 0 : 1;
4262 }
4263
4264 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4265 {
4266 /*
4267 * X-Gene root matching this quirk do not allow peer-to-peer
4268 * transactions with others, allowing masking out these bits as if they
4269 * were unimplemented in the ACS capability.
4270 */
4271 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4272
4273 return acs_flags ? 0 : 1;
4274 }
4275
4276 /*
4277 * Many Intel PCH root ports do provide ACS-like features to disable peer
4278 * transactions and validate bus numbers in requests, but do not provide an
4279 * actual PCIe ACS capability. This is the list of device IDs known to fall
4280 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4281 */
4282 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4283 /* Ibexpeak PCH */
4284 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4285 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4286 /* Cougarpoint PCH */
4287 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4288 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4289 /* Pantherpoint PCH */
4290 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4291 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4292 /* Lynxpoint-H PCH */
4293 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4294 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4295 /* Lynxpoint-LP PCH */
4296 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4297 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4298 /* Wildcat PCH */
4299 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4300 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4301 /* Patsburg (X79) PCH */
4302 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4303 /* Wellsburg (X99) PCH */
4304 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4305 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4306 /* Lynx Point (9 series) PCH */
4307 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4308 };
4309
4310 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4311 {
4312 int i;
4313
4314 /* Filter out a few obvious non-matches first */
4315 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4316 return false;
4317
4318 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4319 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4320 return true;
4321
4322 return false;
4323 }
4324
4325 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4326
4327 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4328 {
4329 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4330 INTEL_PCH_ACS_FLAGS : 0;
4331
4332 if (!pci_quirk_intel_pch_acs_match(dev))
4333 return -ENOTTY;
4334
4335 return acs_flags & ~flags ? 0 : 1;
4336 }
4337
4338 /*
4339 * These QCOM root ports do provide ACS-like features to disable peer
4340 * transactions and validate bus numbers in requests, but do not provide an
4341 * actual PCIe ACS capability. Hardware supports source validation but it
4342 * will report the issue as Completer Abort instead of ACS Violation.
4343 * Hardware doesn't support peer-to-peer and each root port is a root
4344 * complex with unique segment numbers. It is not possible for one root
4345 * port to pass traffic to another root port. All PCIe transactions are
4346 * terminated inside the root port.
4347 */
4348 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4349 {
4350 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4351 int ret = acs_flags & ~flags ? 0 : 1;
4352
4353 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
4354
4355 return ret;
4356 }
4357
4358 /*
4359 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4360 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4361 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4362 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4363 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4364 * control register is at offset 8 instead of 6 and we should probably use
4365 * dword accesses to them. This applies to the following PCI Device IDs, as
4366 * found in volume 1 of the datasheet[2]:
4367 *
4368 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4369 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4370 *
4371 * N.B. This doesn't fix what lspci shows.
4372 *
4373 * The 100 series chipset specification update includes this as errata #23[3].
4374 *
4375 * The 200 series chipset (Union Point) has the same bug according to the
4376 * specification update (Intel 200 Series Chipset Family Platform Controller
4377 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4378 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4379 * chipset include:
4380 *
4381 * 0xa290-0xa29f PCI Express Root port #{0-16}
4382 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4383 *
4384 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4385 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4386 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4387 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4388 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4389 */
4390 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4391 {
4392 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4393 return false;
4394
4395 switch (dev->device) {
4396 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4397 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4398 return true;
4399 }
4400
4401 return false;
4402 }
4403
4404 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4405
4406 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4407 {
4408 int pos;
4409 u32 cap, ctrl;
4410
4411 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4412 return -ENOTTY;
4413
4414 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4415 if (!pos)
4416 return -ENOTTY;
4417
4418 /* see pci_acs_flags_enabled() */
4419 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4420 acs_flags &= (cap | PCI_ACS_EC);
4421
4422 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4423
4424 return acs_flags & ~ctrl ? 0 : 1;
4425 }
4426
4427 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4428 {
4429 /*
4430 * SV, TB, and UF are not relevant to multifunction endpoints.
4431 *
4432 * Multifunction devices are only required to implement RR, CR, and DT
4433 * in their ACS capability if they support peer-to-peer transactions.
4434 * Devices matching this quirk have been verified by the vendor to not
4435 * perform peer-to-peer with other functions, allowing us to mask out
4436 * these bits as if they were unimplemented in the ACS capability.
4437 */
4438 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4439 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4440
4441 return acs_flags ? 0 : 1;
4442 }
4443
4444 static const struct pci_dev_acs_enabled {
4445 u16 vendor;
4446 u16 device;
4447 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4448 } pci_dev_acs_enabled[] = {
4449 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4450 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4451 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4452 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4453 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4454 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4455 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4456 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4457 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4458 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4459 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4460 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4461 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4462 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4463 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4464 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4465 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4466 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4467 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4468 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4469 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4470 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4471 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4472 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4473 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4474 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4475 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4476 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4477 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4478 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4479 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4480 /* 82580 */
4481 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4482 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4483 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4484 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4485 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4486 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4487 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4488 /* 82576 */
4489 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4490 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4491 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4492 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4493 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4494 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4495 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4496 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4497 /* 82575 */
4498 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4499 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4500 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4501 /* I350 */
4502 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4503 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4504 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4505 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4506 /* 82571 (Quads omitted due to non-ACS switch) */
4507 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4508 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4509 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4510 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4511 /* I219 */
4512 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4513 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4514 /* QCOM QDF2xxx root ports */
4515 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4516 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4517 /* Intel PCH root ports */
4518 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4519 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4520 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4521 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4522 /* Cavium ThunderX */
4523 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4524 /* APM X-Gene */
4525 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4526 { 0 }
4527 };
4528
4529 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4530 {
4531 const struct pci_dev_acs_enabled *i;
4532 int ret;
4533
4534 /*
4535 * Allow devices that do not expose standard PCIe ACS capabilities
4536 * or control to indicate their support here. Multi-function express
4537 * devices which do not allow internal peer-to-peer between functions,
4538 * but do not implement PCIe ACS may wish to return true here.
4539 */
4540 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4541 if ((i->vendor == dev->vendor ||
4542 i->vendor == (u16)PCI_ANY_ID) &&
4543 (i->device == dev->device ||
4544 i->device == (u16)PCI_ANY_ID)) {
4545 ret = i->acs_enabled(dev, acs_flags);
4546 if (ret >= 0)
4547 return ret;
4548 }
4549 }
4550
4551 return -ENOTTY;
4552 }
4553
4554 /* Config space offset of Root Complex Base Address register */
4555 #define INTEL_LPC_RCBA_REG 0xf0
4556 /* 31:14 RCBA address */
4557 #define INTEL_LPC_RCBA_MASK 0xffffc000
4558 /* RCBA Enable */
4559 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4560
4561 /* Backbone Scratch Pad Register */
4562 #define INTEL_BSPR_REG 0x1104
4563 /* Backbone Peer Non-Posted Disable */
4564 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4565 /* Backbone Peer Posted Disable */
4566 #define INTEL_BSPR_REG_BPPD (1 << 9)
4567
4568 /* Upstream Peer Decode Configuration Register */
4569 #define INTEL_UPDCR_REG 0x1114
4570 /* 5:0 Peer Decode Enable bits */
4571 #define INTEL_UPDCR_REG_MASK 0x3f
4572
4573 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4574 {
4575 u32 rcba, bspr, updcr;
4576 void __iomem *rcba_mem;
4577
4578 /*
4579 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4580 * are D28:F* and therefore get probed before LPC, thus we can't
4581 * use pci_get_slot/pci_read_config_dword here.
4582 */
4583 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4584 INTEL_LPC_RCBA_REG, &rcba);
4585 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4586 return -EINVAL;
4587
4588 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4589 PAGE_ALIGN(INTEL_UPDCR_REG));
4590 if (!rcba_mem)
4591 return -ENOMEM;
4592
4593 /*
4594 * The BSPR can disallow peer cycles, but it's set by soft strap and
4595 * therefore read-only. If both posted and non-posted peer cycles are
4596 * disallowed, we're ok. If either are allowed, then we need to use
4597 * the UPDCR to disable peer decodes for each port. This provides the
4598 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4599 */
4600 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4601 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4602 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4603 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4604 if (updcr & INTEL_UPDCR_REG_MASK) {
4605 pci_info(dev, "Disabling UPDCR peer decodes\n");
4606 updcr &= ~INTEL_UPDCR_REG_MASK;
4607 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4608 }
4609 }
4610
4611 iounmap(rcba_mem);
4612 return 0;
4613 }
4614
4615 /* Miscellaneous Port Configuration register */
4616 #define INTEL_MPC_REG 0xd8
4617 /* MPC: Invalid Receive Bus Number Check Enable */
4618 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4619
4620 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4621 {
4622 u32 mpc;
4623
4624 /*
4625 * When enabled, the IRBNCE bit of the MPC register enables the
4626 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4627 * ensures that requester IDs fall within the bus number range
4628 * of the bridge. Enable if not already.
4629 */
4630 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4631 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4632 pci_info(dev, "Enabling MPC IRBNCE\n");
4633 mpc |= INTEL_MPC_REG_IRBNCE;
4634 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4635 }
4636 }
4637
4638 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4639 {
4640 if (!pci_quirk_intel_pch_acs_match(dev))
4641 return -ENOTTY;
4642
4643 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4644 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4645 return 0;
4646 }
4647
4648 pci_quirk_enable_intel_rp_mpc_acs(dev);
4649
4650 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4651
4652 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4653
4654 return 0;
4655 }
4656
4657 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4658 {
4659 int pos;
4660 u32 cap, ctrl;
4661
4662 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4663 return -ENOTTY;
4664
4665 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4666 if (!pos)
4667 return -ENOTTY;
4668
4669 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4670 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4671
4672 ctrl |= (cap & PCI_ACS_SV);
4673 ctrl |= (cap & PCI_ACS_RR);
4674 ctrl |= (cap & PCI_ACS_CR);
4675 ctrl |= (cap & PCI_ACS_UF);
4676
4677 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4678
4679 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4680
4681 return 0;
4682 }
4683
4684 static const struct pci_dev_enable_acs {
4685 u16 vendor;
4686 u16 device;
4687 int (*enable_acs)(struct pci_dev *dev);
4688 } pci_dev_enable_acs[] = {
4689 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4690 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4691 { 0 }
4692 };
4693
4694 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4695 {
4696 const struct pci_dev_enable_acs *i;
4697 int ret;
4698
4699 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4700 if ((i->vendor == dev->vendor ||
4701 i->vendor == (u16)PCI_ANY_ID) &&
4702 (i->device == dev->device ||
4703 i->device == (u16)PCI_ANY_ID)) {
4704 ret = i->enable_acs(dev);
4705 if (ret >= 0)
4706 return ret;
4707 }
4708 }
4709
4710 return -ENOTTY;
4711 }
4712
4713 /*
4714 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4715 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4716 * Next Capability pointer in the MSI Capability Structure should point to
4717 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4718 * the list.
4719 */
4720 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4721 {
4722 int pos, i = 0;
4723 u8 next_cap;
4724 u16 reg16, *cap;
4725 struct pci_cap_saved_state *state;
4726
4727 /* Bail if the hardware bug is fixed */
4728 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4729 return;
4730
4731 /* Bail if MSI Capability Structure is not found for some reason */
4732 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4733 if (!pos)
4734 return;
4735
4736 /*
4737 * Bail if Next Capability pointer in the MSI Capability Structure
4738 * is not the expected incorrect 0x00.
4739 */
4740 pci_read_config_byte(pdev, pos + 1, &next_cap);
4741 if (next_cap)
4742 return;
4743
4744 /*
4745 * PCIe Capability Structure is expected to be at 0x50 and should
4746 * terminate the list (Next Capability pointer is 0x00). Verify
4747 * Capability Id and Next Capability pointer is as expected.
4748 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4749 * to correctly set kernel data structures which have already been
4750 * set incorrectly due to the hardware bug.
4751 */
4752 pos = 0x50;
4753 pci_read_config_word(pdev, pos, &reg16);
4754 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4755 u32 status;
4756 #ifndef PCI_EXP_SAVE_REGS
4757 #define PCI_EXP_SAVE_REGS 7
4758 #endif
4759 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4760
4761 pdev->pcie_cap = pos;
4762 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4763 pdev->pcie_flags_reg = reg16;
4764 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4765 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4766
4767 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4768 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4769 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4770 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4771
4772 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4773 return;
4774
4775 /*
4776 * Save PCIE cap
4777 */
4778 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4779 if (!state)
4780 return;
4781
4782 state->cap.cap_nr = PCI_CAP_ID_EXP;
4783 state->cap.cap_extended = 0;
4784 state->cap.size = size;
4785 cap = (u16 *)&state->cap.data[0];
4786 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4787 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4788 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4789 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4790 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4791 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4792 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4793 hlist_add_head(&state->next, &pdev->saved_cap_space);
4794 }
4795 }
4796 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4797
4798 /* FLR may cause some 82579 devices to hang. */
4799 static void quirk_intel_no_flr(struct pci_dev *dev)
4800 {
4801 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4802 }
4803 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4804 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4805
4806 static void quirk_no_ext_tags(struct pci_dev *pdev)
4807 {
4808 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4809
4810 if (!bridge)
4811 return;
4812
4813 bridge->no_ext_tags = 1;
4814 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
4815
4816 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4817 }
4818 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
4819 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
4820 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
4821
4822 #ifdef CONFIG_PCI_ATS
4823 /*
4824 * Some devices have a broken ATS implementation causing IOMMU stalls.
4825 * Don't use ATS for those devices.
4826 */
4827 static void quirk_no_ats(struct pci_dev *pdev)
4828 {
4829 pci_info(pdev, "disabling ATS (broken on this device)\n");
4830 pdev->ats_cap = 0;
4831 }
4832
4833 /* AMD Stoney platform GPU */
4834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
4835 #endif /* CONFIG_PCI_ATS */
4836
4837 /* Freescale PCIe doesn't support MSI in RC mode */
4838 static void quirk_fsl_no_msi(struct pci_dev *pdev)
4839 {
4840 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
4841 pdev->no_msi = 1;
4842 }
4843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
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