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PCI: Add ACS quirk for Intel Union Point
[mirror_ubuntu-zesty-kernel.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29 #include "pci.h"
30
31 /*
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
37 static void quirk_mmio_always_on(struct pci_dev *dev)
38 {
39 dev->mmio_always_on = 1;
40 }
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
43
44 /* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed
45 * by IO resource file, and need to skip the files
46 */
47 static void quirk_marvell_mask_bar(struct pci_dev *dev)
48 {
49 int i;
50
51 for (i = 0; i < 5; i++)
52 if (dev->resource[i].start)
53 dev->resource[i].start =
54 dev->resource[i].end = 0;
55 }
56 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
57 quirk_marvell_mask_bar);
58
59 /* The Mellanox Tavor device gives false positive parity errors
60 * Mark this device with a broken_parity_status, to allow
61 * PCI scanning code to "skip" this now blacklisted device.
62 */
63 static void quirk_mellanox_tavor(struct pci_dev *dev)
64 {
65 dev->broken_parity_status = 1; /* This device gives false positives */
66 }
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
69
70 /* Deal with broken BIOSes that neglect to enable passive release,
71 which can cause problems in combination with the 82441FX/PPro MTRRs */
72 static void quirk_passive_release(struct pci_dev *dev)
73 {
74 struct pci_dev *d = NULL;
75 unsigned char dlc;
76
77 /* We have to make sure a particular bit is set in the PIIX3
78 ISA bridge, so we have to go out and find it. */
79 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
80 pci_read_config_byte(d, 0x82, &dlc);
81 if (!(dlc & 1<<1)) {
82 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
83 dlc |= 1<<1;
84 pci_write_config_byte(d, 0x82, dlc);
85 }
86 }
87 }
88 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
89 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
90
91 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
92 but VIA don't answer queries. If you happen to have good contacts at VIA
93 ask them for me please -- Alan
94
95 This appears to be BIOS not version dependent. So presumably there is a
96 chipset level fix */
97
98 static void quirk_isa_dma_hangs(struct pci_dev *dev)
99 {
100 if (!isa_dma_bridge_buggy) {
101 isa_dma_bridge_buggy = 1;
102 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
103 }
104 }
105 /*
106 * Its not totally clear which chipsets are the problematic ones
107 * We know 82C586 and 82C596 variants are affected.
108 */
109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
116
117 /*
118 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
119 * for some HT machines to use C4 w/o hanging.
120 */
121 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
122 {
123 u32 pmbase;
124 u16 pm1a;
125
126 pci_read_config_dword(dev, 0x40, &pmbase);
127 pmbase = pmbase & 0xff80;
128 pm1a = inw(pmbase);
129
130 if (pm1a & 0x10) {
131 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
132 outw(0x10, pmbase);
133 }
134 }
135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
136
137 /*
138 * Chipsets where PCI->PCI transfers vanish or hang
139 */
140 static void quirk_nopcipci(struct pci_dev *dev)
141 {
142 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
143 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
144 pci_pci_problems |= PCIPCI_FAIL;
145 }
146 }
147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
149
150 static void quirk_nopciamd(struct pci_dev *dev)
151 {
152 u8 rev;
153 pci_read_config_byte(dev, 0x08, &rev);
154 if (rev == 0x13) {
155 /* Erratum 24 */
156 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
157 pci_pci_problems |= PCIAGP_FAIL;
158 }
159 }
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
161
162 /*
163 * Triton requires workarounds to be used by the drivers
164 */
165 static void quirk_triton(struct pci_dev *dev)
166 {
167 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
168 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
169 pci_pci_problems |= PCIPCI_TRITON;
170 }
171 }
172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
176
177 /*
178 * VIA Apollo KT133 needs PCI latency patch
179 * Made according to a windows driver based patch by George E. Breese
180 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
181 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
182 * the info on which Mr Breese based his work.
183 *
184 * Updated based on further information from the site and also on
185 * information provided by VIA
186 */
187 static void quirk_vialatency(struct pci_dev *dev)
188 {
189 struct pci_dev *p;
190 u8 busarb;
191 /* Ok we have a potential problem chipset here. Now see if we have
192 a buggy southbridge */
193
194 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
195 if (p != NULL) {
196 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
197 /* Check for buggy part revisions */
198 if (p->revision < 0x40 || p->revision > 0x42)
199 goto exit;
200 } else {
201 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
202 if (p == NULL) /* No problem parts */
203 goto exit;
204 /* Check for buggy part revisions */
205 if (p->revision < 0x10 || p->revision > 0x12)
206 goto exit;
207 }
208
209 /*
210 * Ok we have the problem. Now set the PCI master grant to
211 * occur every master grant. The apparent bug is that under high
212 * PCI load (quite common in Linux of course) you can get data
213 * loss when the CPU is held off the bus for 3 bus master requests
214 * This happens to include the IDE controllers....
215 *
216 * VIA only apply this fix when an SB Live! is present but under
217 * both Linux and Windows this isn't enough, and we have seen
218 * corruption without SB Live! but with things like 3 UDMA IDE
219 * controllers. So we ignore that bit of the VIA recommendation..
220 */
221
222 pci_read_config_byte(dev, 0x76, &busarb);
223 /* Set bit 4 and bi 5 of byte 76 to 0x01
224 "Master priority rotation on every PCI master grant */
225 busarb &= ~(1<<5);
226 busarb |= (1<<4);
227 pci_write_config_byte(dev, 0x76, busarb);
228 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
229 exit:
230 pci_dev_put(p);
231 }
232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
235 /* Must restore this on a resume from RAM */
236 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
238 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
239
240 /*
241 * VIA Apollo VP3 needs ETBF on BT848/878
242 */
243 static void quirk_viaetbf(struct pci_dev *dev)
244 {
245 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
246 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
247 pci_pci_problems |= PCIPCI_VIAETBF;
248 }
249 }
250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
251
252 static void quirk_vsfx(struct pci_dev *dev)
253 {
254 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_VSFX;
257 }
258 }
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
260
261 /*
262 * Ali Magik requires workarounds to be used by the drivers
263 * that DMA to AGP space. Latency must be set to 0xA and triton
264 * workaround applied too
265 * [Info kindly provided by ALi]
266 */
267 static void quirk_alimagik(struct pci_dev *dev)
268 {
269 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
270 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
271 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
272 }
273 }
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
276
277 /*
278 * Natoma has some interesting boundary conditions with Zoran stuff
279 * at least
280 */
281 static void quirk_natoma(struct pci_dev *dev)
282 {
283 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
284 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
285 pci_pci_problems |= PCIPCI_NATOMA;
286 }
287 }
288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
294
295 /*
296 * This chip can cause PCI parity errors if config register 0xA0 is read
297 * while DMAs are occurring.
298 */
299 static void quirk_citrine(struct pci_dev *dev)
300 {
301 dev->cfg_size = 0xA0;
302 }
303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
304
305 /*
306 * This chip can cause bus lockups if config addresses above 0x600
307 * are read or written.
308 */
309 static void quirk_nfp6000(struct pci_dev *dev)
310 {
311 dev->cfg_size = 0x600;
312 }
313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
316
317 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
318 static void quirk_extend_bar_to_page(struct pci_dev *dev)
319 {
320 int i;
321
322 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
323 struct resource *r = &dev->resource[i];
324
325 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
326 r->end = PAGE_SIZE - 1;
327 r->start = 0;
328 r->flags |= IORESOURCE_UNSET;
329 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
330 i, r);
331 }
332 }
333 }
334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
335
336 /*
337 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
338 * If it's needed, re-allocate the region.
339 */
340 static void quirk_s3_64M(struct pci_dev *dev)
341 {
342 struct resource *r = &dev->resource[0];
343
344 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
345 r->flags |= IORESOURCE_UNSET;
346 r->start = 0;
347 r->end = 0x3ffffff;
348 }
349 }
350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
352
353 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
354 const char *name)
355 {
356 u32 region;
357 struct pci_bus_region bus_region;
358 struct resource *res = dev->resource + pos;
359
360 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
361
362 if (!region)
363 return;
364
365 res->name = pci_name(dev);
366 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
367 res->flags |=
368 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
369 region &= ~(size - 1);
370
371 /* Convert from PCI bus to resource space */
372 bus_region.start = region;
373 bus_region.end = region + size - 1;
374 pcibios_bus_to_resource(dev->bus, res, &bus_region);
375
376 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
377 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
378 }
379
380 /*
381 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
382 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
383 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
384 * (which conflicts w/ BAR1's memory range).
385 *
386 * CS553x's ISA PCI BARs may also be read-only (ref:
387 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
388 */
389 static void quirk_cs5536_vsa(struct pci_dev *dev)
390 {
391 static char *name = "CS5536 ISA bridge";
392
393 if (pci_resource_len(dev, 0) != 8) {
394 quirk_io(dev, 0, 8, name); /* SMB */
395 quirk_io(dev, 1, 256, name); /* GPIO */
396 quirk_io(dev, 2, 64, name); /* MFGPT */
397 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
398 name);
399 }
400 }
401 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
402
403 static void quirk_io_region(struct pci_dev *dev, int port,
404 unsigned size, int nr, const char *name)
405 {
406 u16 region;
407 struct pci_bus_region bus_region;
408 struct resource *res = dev->resource + nr;
409
410 pci_read_config_word(dev, port, &region);
411 region &= ~(size - 1);
412
413 if (!region)
414 return;
415
416 res->name = pci_name(dev);
417 res->flags = IORESOURCE_IO;
418
419 /* Convert from PCI bus to resource space */
420 bus_region.start = region;
421 bus_region.end = region + size - 1;
422 pcibios_bus_to_resource(dev->bus, res, &bus_region);
423
424 if (!pci_claim_resource(dev, nr))
425 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
426 }
427
428 /*
429 * ATI Northbridge setups MCE the processor if you even
430 * read somewhere between 0x3b0->0x3bb or read 0x3d3
431 */
432 static void quirk_ati_exploding_mce(struct pci_dev *dev)
433 {
434 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
435 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
436 request_region(0x3b0, 0x0C, "RadeonIGP");
437 request_region(0x3d3, 0x01, "RadeonIGP");
438 }
439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
440
441 /*
442 * In the AMD NL platform, this device ([1022:7912]) has a class code of
443 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
444 * claim it.
445 * But the dwc3 driver is a more specific driver for this device, and we'd
446 * prefer to use it instead of xhci. To prevent xhci from claiming the
447 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
448 * defines as "USB device (not host controller)". The dwc3 driver can then
449 * claim it based on its Vendor and Device ID.
450 */
451 static void quirk_amd_nl_class(struct pci_dev *pdev)
452 {
453 u32 class = pdev->class;
454
455 /* Use "USB Device (not host controller)" class */
456 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
457 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
458 class, pdev->class);
459 }
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
461 quirk_amd_nl_class);
462
463 /*
464 * Let's make the southbridge information explicit instead
465 * of having to worry about people probing the ACPI areas,
466 * for example.. (Yes, it happens, and if you read the wrong
467 * ACPI register it will put the machine to sleep with no
468 * way of waking it up again. Bummer).
469 *
470 * ALI M7101: Two IO regions pointed to by words at
471 * 0xE0 (64 bytes of ACPI registers)
472 * 0xE2 (32 bytes of SMB registers)
473 */
474 static void quirk_ali7101_acpi(struct pci_dev *dev)
475 {
476 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
477 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
478 }
479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
480
481 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
482 {
483 u32 devres;
484 u32 mask, size, base;
485
486 pci_read_config_dword(dev, port, &devres);
487 if ((devres & enable) != enable)
488 return;
489 mask = (devres >> 16) & 15;
490 base = devres & 0xffff;
491 size = 16;
492 for (;;) {
493 unsigned bit = size >> 1;
494 if ((bit & mask) == bit)
495 break;
496 size = bit;
497 }
498 /*
499 * For now we only print it out. Eventually we'll want to
500 * reserve it (at least if it's in the 0x1000+ range), but
501 * let's get enough confirmation reports first.
502 */
503 base &= -size;
504 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
505 base + size - 1);
506 }
507
508 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
509 {
510 u32 devres;
511 u32 mask, size, base;
512
513 pci_read_config_dword(dev, port, &devres);
514 if ((devres & enable) != enable)
515 return;
516 base = devres & 0xffff0000;
517 mask = (devres & 0x3f) << 16;
518 size = 128 << 16;
519 for (;;) {
520 unsigned bit = size >> 1;
521 if ((bit & mask) == bit)
522 break;
523 size = bit;
524 }
525 /*
526 * For now we only print it out. Eventually we'll want to
527 * reserve it, but let's get enough confirmation reports first.
528 */
529 base &= -size;
530 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
531 base + size - 1);
532 }
533
534 /*
535 * PIIX4 ACPI: Two IO regions pointed to by longwords at
536 * 0x40 (64 bytes of ACPI registers)
537 * 0x90 (16 bytes of SMB registers)
538 * and a few strange programmable PIIX4 device resources.
539 */
540 static void quirk_piix4_acpi(struct pci_dev *dev)
541 {
542 u32 res_a;
543
544 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
545 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
546
547 /* Device resource A has enables for some of the other ones */
548 pci_read_config_dword(dev, 0x5c, &res_a);
549
550 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
551 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
552
553 /* Device resource D is just bitfields for static resources */
554
555 /* Device 12 enabled? */
556 if (res_a & (1 << 29)) {
557 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
558 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
559 }
560 /* Device 13 enabled? */
561 if (res_a & (1 << 30)) {
562 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
563 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
564 }
565 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
566 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
567 }
568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
570
571 #define ICH_PMBASE 0x40
572 #define ICH_ACPI_CNTL 0x44
573 #define ICH4_ACPI_EN 0x10
574 #define ICH6_ACPI_EN 0x80
575 #define ICH4_GPIOBASE 0x58
576 #define ICH4_GPIO_CNTL 0x5c
577 #define ICH4_GPIO_EN 0x10
578 #define ICH6_GPIOBASE 0x48
579 #define ICH6_GPIO_CNTL 0x4c
580 #define ICH6_GPIO_EN 0x10
581
582 /*
583 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
584 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
585 * 0x58 (64 bytes of GPIO I/O space)
586 */
587 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
588 {
589 u8 enable;
590
591 /*
592 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
593 * with low legacy (and fixed) ports. We don't know the decoding
594 * priority and can't tell whether the legacy device or the one created
595 * here is really at that address. This happens on boards with broken
596 * BIOSes.
597 */
598
599 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
600 if (enable & ICH4_ACPI_EN)
601 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
602 "ICH4 ACPI/GPIO/TCO");
603
604 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
605 if (enable & ICH4_GPIO_EN)
606 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
607 "ICH4 GPIO");
608 }
609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
619
620 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
621 {
622 u8 enable;
623
624 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
625 if (enable & ICH6_ACPI_EN)
626 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
627 "ICH6 ACPI/GPIO/TCO");
628
629 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
630 if (enable & ICH6_GPIO_EN)
631 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
632 "ICH6 GPIO");
633 }
634
635 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
636 {
637 u32 val;
638 u32 size, base;
639
640 pci_read_config_dword(dev, reg, &val);
641
642 /* Enabled? */
643 if (!(val & 1))
644 return;
645 base = val & 0xfffc;
646 if (dynsize) {
647 /*
648 * This is not correct. It is 16, 32 or 64 bytes depending on
649 * register D31:F0:ADh bits 5:4.
650 *
651 * But this gets us at least _part_ of it.
652 */
653 size = 16;
654 } else {
655 size = 128;
656 }
657 base &= ~(size-1);
658
659 /* Just print it out for now. We should reserve it after more debugging */
660 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
661 }
662
663 static void quirk_ich6_lpc(struct pci_dev *dev)
664 {
665 /* Shared ACPI/GPIO decode with all ICH6+ */
666 ich6_lpc_acpi_gpio(dev);
667
668 /* ICH6-specific generic IO decode */
669 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
670 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
671 }
672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
674
675 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
676 {
677 u32 val;
678 u32 mask, base;
679
680 pci_read_config_dword(dev, reg, &val);
681
682 /* Enabled? */
683 if (!(val & 1))
684 return;
685
686 /*
687 * IO base in bits 15:2, mask in bits 23:18, both
688 * are dword-based
689 */
690 base = val & 0xfffc;
691 mask = (val >> 16) & 0xfc;
692 mask |= 3;
693
694 /* Just print it out for now. We should reserve it after more debugging */
695 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
696 }
697
698 /* ICH7-10 has the same common LPC generic IO decode registers */
699 static void quirk_ich7_lpc(struct pci_dev *dev)
700 {
701 /* We share the common ACPI/GPIO decode with ICH6 */
702 ich6_lpc_acpi_gpio(dev);
703
704 /* And have 4 ICH7+ generic decodes */
705 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
706 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
707 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
708 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
709 }
710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
711 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
713 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
723
724 /*
725 * VIA ACPI: One IO region pointed to by longword at
726 * 0x48 or 0x20 (256 bytes of ACPI registers)
727 */
728 static void quirk_vt82c586_acpi(struct pci_dev *dev)
729 {
730 if (dev->revision & 0x10)
731 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
732 "vt82c586 ACPI");
733 }
734 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
735
736 /*
737 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
738 * 0x48 (256 bytes of ACPI registers)
739 * 0x70 (128 bytes of hardware monitoring register)
740 * 0x90 (16 bytes of SMB registers)
741 */
742 static void quirk_vt82c686_acpi(struct pci_dev *dev)
743 {
744 quirk_vt82c586_acpi(dev);
745
746 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
747 "vt82c686 HW-mon");
748
749 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
750 }
751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
752
753 /*
754 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
755 * 0x88 (128 bytes of power management registers)
756 * 0xd0 (16 bytes of SMB registers)
757 */
758 static void quirk_vt8235_acpi(struct pci_dev *dev)
759 {
760 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
761 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
762 }
763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
764
765 /*
766 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
767 * Disable fast back-to-back on the secondary bus segment
768 */
769 static void quirk_xio2000a(struct pci_dev *dev)
770 {
771 struct pci_dev *pdev;
772 u16 command;
773
774 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
775 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
776 pci_read_config_word(pdev, PCI_COMMAND, &command);
777 if (command & PCI_COMMAND_FAST_BACK)
778 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
779 }
780 }
781 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
782 quirk_xio2000a);
783
784 #ifdef CONFIG_X86_IO_APIC
785
786 #include <asm/io_apic.h>
787
788 /*
789 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
790 * devices to the external APIC.
791 *
792 * TODO: When we have device-specific interrupt routers,
793 * this code will go away from quirks.
794 */
795 static void quirk_via_ioapic(struct pci_dev *dev)
796 {
797 u8 tmp;
798
799 if (nr_ioapics < 1)
800 tmp = 0; /* nothing routed to external APIC */
801 else
802 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
803
804 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
805 tmp == 0 ? "Disa" : "Ena");
806
807 /* Offset 0x58: External APIC IRQ output control */
808 pci_write_config_byte(dev, 0x58, tmp);
809 }
810 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
811 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
812
813 /*
814 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
815 * This leads to doubled level interrupt rates.
816 * Set this bit to get rid of cycle wastage.
817 * Otherwise uncritical.
818 */
819 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
820 {
821 u8 misc_control2;
822 #define BYPASS_APIC_DEASSERT 8
823
824 pci_read_config_byte(dev, 0x5B, &misc_control2);
825 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
826 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
827 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
828 }
829 }
830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
831 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
832
833 /*
834 * The AMD io apic can hang the box when an apic irq is masked.
835 * We check all revs >= B0 (yet not in the pre production!) as the bug
836 * is currently marked NoFix
837 *
838 * We have multiple reports of hangs with this chipset that went away with
839 * noapic specified. For the moment we assume it's the erratum. We may be wrong
840 * of course. However the advice is demonstrably good even if so..
841 */
842 static void quirk_amd_ioapic(struct pci_dev *dev)
843 {
844 if (dev->revision >= 0x02) {
845 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
846 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
847 }
848 }
849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
850 #endif /* CONFIG_X86_IO_APIC */
851
852 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
853
854 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
855 {
856 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
857 if (dev->subsystem_device == 0xa118)
858 dev->sriov->link = dev->devfn;
859 }
860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
861 #endif
862
863 /*
864 * Some settings of MMRBC can lead to data corruption so block changes.
865 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
866 */
867 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
868 {
869 if (dev->subordinate && dev->revision <= 0x12) {
870 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
871 dev->revision);
872 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
873 }
874 }
875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
876
877 /*
878 * FIXME: it is questionable that quirk_via_acpi
879 * is needed. It shows up as an ISA bridge, and does not
880 * support the PCI_INTERRUPT_LINE register at all. Therefore
881 * it seems like setting the pci_dev's 'irq' to the
882 * value of the ACPI SCI interrupt is only done for convenience.
883 * -jgarzik
884 */
885 static void quirk_via_acpi(struct pci_dev *d)
886 {
887 /*
888 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
889 */
890 u8 irq;
891 pci_read_config_byte(d, 0x42, &irq);
892 irq &= 0xf;
893 if (irq && (irq != 2))
894 d->irq = irq;
895 }
896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
898
899
900 /*
901 * VIA bridges which have VLink
902 */
903
904 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
905
906 static void quirk_via_bridge(struct pci_dev *dev)
907 {
908 /* See what bridge we have and find the device ranges */
909 switch (dev->device) {
910 case PCI_DEVICE_ID_VIA_82C686:
911 /* The VT82C686 is special, it attaches to PCI and can have
912 any device number. All its subdevices are functions of
913 that single device. */
914 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
915 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
916 break;
917 case PCI_DEVICE_ID_VIA_8237:
918 case PCI_DEVICE_ID_VIA_8237A:
919 via_vlink_dev_lo = 15;
920 break;
921 case PCI_DEVICE_ID_VIA_8235:
922 via_vlink_dev_lo = 16;
923 break;
924 case PCI_DEVICE_ID_VIA_8231:
925 case PCI_DEVICE_ID_VIA_8233_0:
926 case PCI_DEVICE_ID_VIA_8233A:
927 case PCI_DEVICE_ID_VIA_8233C_0:
928 via_vlink_dev_lo = 17;
929 break;
930 }
931 }
932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
940
941 /**
942 * quirk_via_vlink - VIA VLink IRQ number update
943 * @dev: PCI device
944 *
945 * If the device we are dealing with is on a PIC IRQ we need to
946 * ensure that the IRQ line register which usually is not relevant
947 * for PCI cards, is actually written so that interrupts get sent
948 * to the right place.
949 * We only do this on systems where a VIA south bridge was detected,
950 * and only for VIA devices on the motherboard (see quirk_via_bridge
951 * above).
952 */
953
954 static void quirk_via_vlink(struct pci_dev *dev)
955 {
956 u8 irq, new_irq;
957
958 /* Check if we have VLink at all */
959 if (via_vlink_dev_lo == -1)
960 return;
961
962 new_irq = dev->irq;
963
964 /* Don't quirk interrupts outside the legacy IRQ range */
965 if (!new_irq || new_irq > 15)
966 return;
967
968 /* Internal device ? */
969 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
970 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
971 return;
972
973 /* This is an internal VLink device on a PIC interrupt. The BIOS
974 ought to have set this but may not have, so we redo it */
975
976 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
977 if (new_irq != irq) {
978 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
979 irq, new_irq);
980 udelay(15); /* unknown if delay really needed */
981 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
982 }
983 }
984 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
985
986 /*
987 * VIA VT82C598 has its device ID settable and many BIOSes
988 * set it to the ID of VT82C597 for backward compatibility.
989 * We need to switch it off to be able to recognize the real
990 * type of the chip.
991 */
992 static void quirk_vt82c598_id(struct pci_dev *dev)
993 {
994 pci_write_config_byte(dev, 0xfc, 0);
995 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
996 }
997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
998
999 /*
1000 * CardBus controllers have a legacy base address that enables them
1001 * to respond as i82365 pcmcia controllers. We don't want them to
1002 * do this even if the Linux CardBus driver is not loaded, because
1003 * the Linux i82365 driver does not (and should not) handle CardBus.
1004 */
1005 static void quirk_cardbus_legacy(struct pci_dev *dev)
1006 {
1007 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1008 }
1009 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1010 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1011 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1012 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1013
1014 /*
1015 * Following the PCI ordering rules is optional on the AMD762. I'm not
1016 * sure what the designers were smoking but let's not inhale...
1017 *
1018 * To be fair to AMD, it follows the spec by default, its BIOS people
1019 * who turn it off!
1020 */
1021 static void quirk_amd_ordering(struct pci_dev *dev)
1022 {
1023 u32 pcic;
1024 pci_read_config_dword(dev, 0x4C, &pcic);
1025 if ((pcic & 6) != 6) {
1026 pcic |= 6;
1027 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1028 pci_write_config_dword(dev, 0x4C, pcic);
1029 pci_read_config_dword(dev, 0x84, &pcic);
1030 pcic |= (1 << 23); /* Required in this mode */
1031 pci_write_config_dword(dev, 0x84, pcic);
1032 }
1033 }
1034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1035 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1036
1037 /*
1038 * DreamWorks provided workaround for Dunord I-3000 problem
1039 *
1040 * This card decodes and responds to addresses not apparently
1041 * assigned to it. We force a larger allocation to ensure that
1042 * nothing gets put too close to it.
1043 */
1044 static void quirk_dunord(struct pci_dev *dev)
1045 {
1046 struct resource *r = &dev->resource[1];
1047
1048 r->flags |= IORESOURCE_UNSET;
1049 r->start = 0;
1050 r->end = 0xffffff;
1051 }
1052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1053
1054 /*
1055 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1056 * is subtractive decoding (transparent), and does indicate this
1057 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1058 * instead of 0x01.
1059 */
1060 static void quirk_transparent_bridge(struct pci_dev *dev)
1061 {
1062 dev->transparent = 1;
1063 }
1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1066
1067 /*
1068 * Common misconfiguration of the MediaGX/Geode PCI master that will
1069 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1070 * datasheets found at http://www.national.com/analog for info on what
1071 * these bits do. <christer@weinigel.se>
1072 */
1073 static void quirk_mediagx_master(struct pci_dev *dev)
1074 {
1075 u8 reg;
1076
1077 pci_read_config_byte(dev, 0x41, &reg);
1078 if (reg & 2) {
1079 reg &= ~2;
1080 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1081 reg);
1082 pci_write_config_byte(dev, 0x41, reg);
1083 }
1084 }
1085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1086 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1087
1088 /*
1089 * Ensure C0 rev restreaming is off. This is normally done by
1090 * the BIOS but in the odd case it is not the results are corruption
1091 * hence the presence of a Linux check
1092 */
1093 static void quirk_disable_pxb(struct pci_dev *pdev)
1094 {
1095 u16 config;
1096
1097 if (pdev->revision != 0x04) /* Only C0 requires this */
1098 return;
1099 pci_read_config_word(pdev, 0x40, &config);
1100 if (config & (1<<6)) {
1101 config &= ~(1<<6);
1102 pci_write_config_word(pdev, 0x40, config);
1103 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1104 }
1105 }
1106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1107 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1108
1109 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1110 {
1111 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1112 u8 tmp;
1113
1114 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1115 if (tmp == 0x01) {
1116 pci_read_config_byte(pdev, 0x40, &tmp);
1117 pci_write_config_byte(pdev, 0x40, tmp|1);
1118 pci_write_config_byte(pdev, 0x9, 1);
1119 pci_write_config_byte(pdev, 0xa, 6);
1120 pci_write_config_byte(pdev, 0x40, tmp);
1121
1122 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1123 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1124 }
1125 }
1126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1127 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1129 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1131 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1133 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1134
1135 /*
1136 * Serverworks CSB5 IDE does not fully support native mode
1137 */
1138 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1139 {
1140 u8 prog;
1141 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1142 if (prog & 5) {
1143 prog &= ~5;
1144 pdev->class &= ~5;
1145 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1146 /* PCI layer will sort out resources */
1147 }
1148 }
1149 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1150
1151 /*
1152 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1153 */
1154 static void quirk_ide_samemode(struct pci_dev *pdev)
1155 {
1156 u8 prog;
1157
1158 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1159
1160 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1161 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1162 prog &= ~5;
1163 pdev->class &= ~5;
1164 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1165 }
1166 }
1167 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1168
1169 /*
1170 * Some ATA devices break if put into D3
1171 */
1172
1173 static void quirk_no_ata_d3(struct pci_dev *pdev)
1174 {
1175 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1176 }
1177 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1178 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1179 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1180 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1181 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1182 /* ALi loses some register settings that we cannot then restore */
1183 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1184 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1185 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1186 occur when mode detecting */
1187 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1188 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1189
1190 /* This was originally an Alpha specific thing, but it really fits here.
1191 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1192 */
1193 static void quirk_eisa_bridge(struct pci_dev *dev)
1194 {
1195 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1196 }
1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1198
1199
1200 /*
1201 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1202 * is not activated. The myth is that Asus said that they do not want the
1203 * users to be irritated by just another PCI Device in the Win98 device
1204 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1205 * package 2.7.0 for details)
1206 *
1207 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1208 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1209 * becomes necessary to do this tweak in two steps -- the chosen trigger
1210 * is either the Host bridge (preferred) or on-board VGA controller.
1211 *
1212 * Note that we used to unhide the SMBus that way on Toshiba laptops
1213 * (Satellite A40 and Tecra M2) but then found that the thermal management
1214 * was done by SMM code, which could cause unsynchronized concurrent
1215 * accesses to the SMBus registers, with potentially bad effects. Thus you
1216 * should be very careful when adding new entries: if SMM is accessing the
1217 * Intel SMBus, this is a very good reason to leave it hidden.
1218 *
1219 * Likewise, many recent laptops use ACPI for thermal management. If the
1220 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1221 * natively, and keeping the SMBus hidden is the right thing to do. If you
1222 * are about to add an entry in the table below, please first disassemble
1223 * the DSDT and double-check that there is no code accessing the SMBus.
1224 */
1225 static int asus_hides_smbus;
1226
1227 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1228 {
1229 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1230 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1231 switch (dev->subsystem_device) {
1232 case 0x8025: /* P4B-LX */
1233 case 0x8070: /* P4B */
1234 case 0x8088: /* P4B533 */
1235 case 0x1626: /* L3C notebook */
1236 asus_hides_smbus = 1;
1237 }
1238 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1239 switch (dev->subsystem_device) {
1240 case 0x80b1: /* P4GE-V */
1241 case 0x80b2: /* P4PE */
1242 case 0x8093: /* P4B533-V */
1243 asus_hides_smbus = 1;
1244 }
1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1246 switch (dev->subsystem_device) {
1247 case 0x8030: /* P4T533 */
1248 asus_hides_smbus = 1;
1249 }
1250 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1251 switch (dev->subsystem_device) {
1252 case 0x8070: /* P4G8X Deluxe */
1253 asus_hides_smbus = 1;
1254 }
1255 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1256 switch (dev->subsystem_device) {
1257 case 0x80c9: /* PU-DLS */
1258 asus_hides_smbus = 1;
1259 }
1260 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1261 switch (dev->subsystem_device) {
1262 case 0x1751: /* M2N notebook */
1263 case 0x1821: /* M5N notebook */
1264 case 0x1897: /* A6L notebook */
1265 asus_hides_smbus = 1;
1266 }
1267 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1268 switch (dev->subsystem_device) {
1269 case 0x184b: /* W1N notebook */
1270 case 0x186a: /* M6Ne notebook */
1271 asus_hides_smbus = 1;
1272 }
1273 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1274 switch (dev->subsystem_device) {
1275 case 0x80f2: /* P4P800-X */
1276 asus_hides_smbus = 1;
1277 }
1278 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1279 switch (dev->subsystem_device) {
1280 case 0x1882: /* M6V notebook */
1281 case 0x1977: /* A6VA notebook */
1282 asus_hides_smbus = 1;
1283 }
1284 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1285 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1286 switch (dev->subsystem_device) {
1287 case 0x088C: /* HP Compaq nc8000 */
1288 case 0x0890: /* HP Compaq nc6000 */
1289 asus_hides_smbus = 1;
1290 }
1291 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1292 switch (dev->subsystem_device) {
1293 case 0x12bc: /* HP D330L */
1294 case 0x12bd: /* HP D530 */
1295 case 0x006a: /* HP Compaq nx9500 */
1296 asus_hides_smbus = 1;
1297 }
1298 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1299 switch (dev->subsystem_device) {
1300 case 0x12bf: /* HP xw4100 */
1301 asus_hides_smbus = 1;
1302 }
1303 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1304 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1305 switch (dev->subsystem_device) {
1306 case 0xC00C: /* Samsung P35 notebook */
1307 asus_hides_smbus = 1;
1308 }
1309 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1310 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1311 switch (dev->subsystem_device) {
1312 case 0x0058: /* Compaq Evo N620c */
1313 asus_hides_smbus = 1;
1314 }
1315 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1316 switch (dev->subsystem_device) {
1317 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1318 /* Motherboard doesn't have Host bridge
1319 * subvendor/subdevice IDs, therefore checking
1320 * its on-board VGA controller */
1321 asus_hides_smbus = 1;
1322 }
1323 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1324 switch (dev->subsystem_device) {
1325 case 0x00b8: /* Compaq Evo D510 CMT */
1326 case 0x00b9: /* Compaq Evo D510 SFF */
1327 case 0x00ba: /* Compaq Evo D510 USDT */
1328 /* Motherboard doesn't have Host bridge
1329 * subvendor/subdevice IDs and on-board VGA
1330 * controller is disabled if an AGP card is
1331 * inserted, therefore checking USB UHCI
1332 * Controller #1 */
1333 asus_hides_smbus = 1;
1334 }
1335 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1336 switch (dev->subsystem_device) {
1337 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1338 /* Motherboard doesn't have host bridge
1339 * subvendor/subdevice IDs, therefore checking
1340 * its on-board VGA controller */
1341 asus_hides_smbus = 1;
1342 }
1343 }
1344 }
1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1355
1356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1359
1360 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1361 {
1362 u16 val;
1363
1364 if (likely(!asus_hides_smbus))
1365 return;
1366
1367 pci_read_config_word(dev, 0xF2, &val);
1368 if (val & 0x8) {
1369 pci_write_config_word(dev, 0xF2, val & (~0x8));
1370 pci_read_config_word(dev, 0xF2, &val);
1371 if (val & 0x8)
1372 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1373 val);
1374 else
1375 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1376 }
1377 }
1378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1385 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1386 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1387 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1388 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1389 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1390 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1392
1393 /* It appears we just have one such device. If not, we have a warning */
1394 static void __iomem *asus_rcba_base;
1395 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1396 {
1397 u32 rcba;
1398
1399 if (likely(!asus_hides_smbus))
1400 return;
1401 WARN_ON(asus_rcba_base);
1402
1403 pci_read_config_dword(dev, 0xF0, &rcba);
1404 /* use bits 31:14, 16 kB aligned */
1405 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1406 if (asus_rcba_base == NULL)
1407 return;
1408 }
1409
1410 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1411 {
1412 u32 val;
1413
1414 if (likely(!asus_hides_smbus || !asus_rcba_base))
1415 return;
1416 /* read the Function Disable register, dword mode only */
1417 val = readl(asus_rcba_base + 0x3418);
1418 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1419 }
1420
1421 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1422 {
1423 if (likely(!asus_hides_smbus || !asus_rcba_base))
1424 return;
1425 iounmap(asus_rcba_base);
1426 asus_rcba_base = NULL;
1427 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1428 }
1429
1430 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1431 {
1432 asus_hides_smbus_lpc_ich6_suspend(dev);
1433 asus_hides_smbus_lpc_ich6_resume_early(dev);
1434 asus_hides_smbus_lpc_ich6_resume(dev);
1435 }
1436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1437 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1438 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1439 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1440
1441 /*
1442 * SiS 96x south bridge: BIOS typically hides SMBus device...
1443 */
1444 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1445 {
1446 u8 val = 0;
1447 pci_read_config_byte(dev, 0x77, &val);
1448 if (val & 0x10) {
1449 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1450 pci_write_config_byte(dev, 0x77, val & ~0x10);
1451 }
1452 }
1453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1457 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1458 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1459 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1460 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1461
1462 /*
1463 * ... This is further complicated by the fact that some SiS96x south
1464 * bridges pretend to be 85C503/5513 instead. In that case see if we
1465 * spotted a compatible north bridge to make sure.
1466 * (pci_find_device doesn't work yet)
1467 *
1468 * We can also enable the sis96x bit in the discovery register..
1469 */
1470 #define SIS_DETECT_REGISTER 0x40
1471
1472 static void quirk_sis_503(struct pci_dev *dev)
1473 {
1474 u8 reg;
1475 u16 devid;
1476
1477 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1478 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1479 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1480 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1481 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1482 return;
1483 }
1484
1485 /*
1486 * Ok, it now shows up as a 96x.. run the 96x quirk by
1487 * hand in case it has already been processed.
1488 * (depends on link order, which is apparently not guaranteed)
1489 */
1490 dev->device = devid;
1491 quirk_sis_96x_smbus(dev);
1492 }
1493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1494 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1495
1496
1497 /*
1498 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1499 * and MC97 modem controller are disabled when a second PCI soundcard is
1500 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1501 * -- bjd
1502 */
1503 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1504 {
1505 u8 val;
1506 int asus_hides_ac97 = 0;
1507
1508 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1509 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1510 asus_hides_ac97 = 1;
1511 }
1512
1513 if (!asus_hides_ac97)
1514 return;
1515
1516 pci_read_config_byte(dev, 0x50, &val);
1517 if (val & 0xc0) {
1518 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1519 pci_read_config_byte(dev, 0x50, &val);
1520 if (val & 0xc0)
1521 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1522 val);
1523 else
1524 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1525 }
1526 }
1527 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1529
1530 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1531
1532 /*
1533 * If we are using libata we can drive this chip properly but must
1534 * do this early on to make the additional device appear during
1535 * the PCI scanning.
1536 */
1537 static void quirk_jmicron_ata(struct pci_dev *pdev)
1538 {
1539 u32 conf1, conf5, class;
1540 u8 hdr;
1541
1542 /* Only poke fn 0 */
1543 if (PCI_FUNC(pdev->devfn))
1544 return;
1545
1546 pci_read_config_dword(pdev, 0x40, &conf1);
1547 pci_read_config_dword(pdev, 0x80, &conf5);
1548
1549 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1550 conf5 &= ~(1 << 24); /* Clear bit 24 */
1551
1552 switch (pdev->device) {
1553 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1554 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1555 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1556 /* The controller should be in single function ahci mode */
1557 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1558 break;
1559
1560 case PCI_DEVICE_ID_JMICRON_JMB365:
1561 case PCI_DEVICE_ID_JMICRON_JMB366:
1562 /* Redirect IDE second PATA port to the right spot */
1563 conf5 |= (1 << 24);
1564 /* Fall through */
1565 case PCI_DEVICE_ID_JMICRON_JMB361:
1566 case PCI_DEVICE_ID_JMICRON_JMB363:
1567 case PCI_DEVICE_ID_JMICRON_JMB369:
1568 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1569 /* Set the class codes correctly and then direct IDE 0 */
1570 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1571 break;
1572
1573 case PCI_DEVICE_ID_JMICRON_JMB368:
1574 /* The controller should be in single function IDE mode */
1575 conf1 |= 0x00C00000; /* Set 22, 23 */
1576 break;
1577 }
1578
1579 pci_write_config_dword(pdev, 0x40, conf1);
1580 pci_write_config_dword(pdev, 0x80, conf5);
1581
1582 /* Update pdev accordingly */
1583 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1584 pdev->hdr_type = hdr & 0x7f;
1585 pdev->multifunction = !!(hdr & 0x80);
1586
1587 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1588 pdev->class = class >> 8;
1589 }
1590 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1593 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1594 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1595 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1596 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1597 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1598 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1599 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1600 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1601 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1602 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1603 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1604 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1605 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1606 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1608
1609 #endif
1610
1611 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1612 {
1613 if (dev->multifunction) {
1614 device_disable_async_suspend(&dev->dev);
1615 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1616 }
1617 }
1618 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1619 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1622
1623 #ifdef CONFIG_X86_IO_APIC
1624 static void quirk_alder_ioapic(struct pci_dev *pdev)
1625 {
1626 int i;
1627
1628 if ((pdev->class >> 8) != 0xff00)
1629 return;
1630
1631 /* the first BAR is the location of the IO APIC...we must
1632 * not touch this (and it's already covered by the fixmap), so
1633 * forcibly insert it into the resource tree */
1634 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1635 insert_resource(&iomem_resource, &pdev->resource[0]);
1636
1637 /* The next five BARs all seem to be rubbish, so just clean
1638 * them out */
1639 for (i = 1; i < 6; i++)
1640 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1641 }
1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1643 #endif
1644
1645 static void quirk_pcie_mch(struct pci_dev *pdev)
1646 {
1647 pdev->no_msi = 1;
1648 }
1649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1652
1653
1654 /*
1655 * It's possible for the MSI to get corrupted if shpc and acpi
1656 * are used together on certain PXH-based systems.
1657 */
1658 static void quirk_pcie_pxh(struct pci_dev *dev)
1659 {
1660 dev->no_msi = 1;
1661 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1662 }
1663 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1664 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1666 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1667 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1668
1669 /*
1670 * Some Intel PCI Express chipsets have trouble with downstream
1671 * device power management.
1672 */
1673 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1674 {
1675 pci_pm_d3_delay = 120;
1676 dev->no_d1d2 = 1;
1677 }
1678
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1700
1701 #ifdef CONFIG_X86_IO_APIC
1702 /*
1703 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1704 * remap the original interrupt in the linux kernel to the boot interrupt, so
1705 * that a PCI device's interrupt handler is installed on the boot interrupt
1706 * line instead.
1707 */
1708 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1709 {
1710 if (noioapicquirk || noioapicreroute)
1711 return;
1712
1713 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1714 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1715 dev->vendor, dev->device);
1716 }
1717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1723 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1724 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1725 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1726 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1727 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1728 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1729 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1730 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1731 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1732 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1733
1734 /*
1735 * On some chipsets we can disable the generation of legacy INTx boot
1736 * interrupts.
1737 */
1738
1739 /*
1740 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1741 * 300641-004US, section 5.7.3.
1742 */
1743 #define INTEL_6300_IOAPIC_ABAR 0x40
1744 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1745
1746 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1747 {
1748 u16 pci_config_word;
1749
1750 if (noioapicquirk)
1751 return;
1752
1753 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1754 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1755 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1756
1757 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1758 dev->vendor, dev->device);
1759 }
1760 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1761 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1762
1763 /*
1764 * disable boot interrupts on HT-1000
1765 */
1766 #define BC_HT1000_FEATURE_REG 0x64
1767 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1768 #define BC_HT1000_MAP_IDX 0xC00
1769 #define BC_HT1000_MAP_DATA 0xC01
1770
1771 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1772 {
1773 u32 pci_config_dword;
1774 u8 irq;
1775
1776 if (noioapicquirk)
1777 return;
1778
1779 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1780 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1781 BC_HT1000_PIC_REGS_ENABLE);
1782
1783 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1784 outb(irq, BC_HT1000_MAP_IDX);
1785 outb(0x00, BC_HT1000_MAP_DATA);
1786 }
1787
1788 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1789
1790 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1791 dev->vendor, dev->device);
1792 }
1793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1794 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1795
1796 /*
1797 * disable boot interrupts on AMD and ATI chipsets
1798 */
1799 /*
1800 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1801 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1802 * (due to an erratum).
1803 */
1804 #define AMD_813X_MISC 0x40
1805 #define AMD_813X_NOIOAMODE (1<<0)
1806 #define AMD_813X_REV_B1 0x12
1807 #define AMD_813X_REV_B2 0x13
1808
1809 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1810 {
1811 u32 pci_config_dword;
1812
1813 if (noioapicquirk)
1814 return;
1815 if ((dev->revision == AMD_813X_REV_B1) ||
1816 (dev->revision == AMD_813X_REV_B2))
1817 return;
1818
1819 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1820 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1821 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1822
1823 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1824 dev->vendor, dev->device);
1825 }
1826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1827 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1829 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1830
1831 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1832
1833 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1834 {
1835 u16 pci_config_word;
1836
1837 if (noioapicquirk)
1838 return;
1839
1840 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1841 if (!pci_config_word) {
1842 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1843 dev->vendor, dev->device);
1844 return;
1845 }
1846 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1847 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1848 dev->vendor, dev->device);
1849 }
1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1851 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1852 #endif /* CONFIG_X86_IO_APIC */
1853
1854 /*
1855 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1856 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1857 * Re-allocate the region if needed...
1858 */
1859 static void quirk_tc86c001_ide(struct pci_dev *dev)
1860 {
1861 struct resource *r = &dev->resource[0];
1862
1863 if (r->start & 0x8) {
1864 r->flags |= IORESOURCE_UNSET;
1865 r->start = 0;
1866 r->end = 0xf;
1867 }
1868 }
1869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1870 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1871 quirk_tc86c001_ide);
1872
1873 /*
1874 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1875 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1876 * being read correctly if bit 7 of the base address is set.
1877 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1878 * Re-allocate the regions to a 256-byte boundary if necessary.
1879 */
1880 static void quirk_plx_pci9050(struct pci_dev *dev)
1881 {
1882 unsigned int bar;
1883
1884 /* Fixed in revision 2 (PCI 9052). */
1885 if (dev->revision >= 2)
1886 return;
1887 for (bar = 0; bar <= 1; bar++)
1888 if (pci_resource_len(dev, bar) == 0x80 &&
1889 (pci_resource_start(dev, bar) & 0x80)) {
1890 struct resource *r = &dev->resource[bar];
1891 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1892 bar);
1893 r->flags |= IORESOURCE_UNSET;
1894 r->start = 0;
1895 r->end = 0xff;
1896 }
1897 }
1898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1899 quirk_plx_pci9050);
1900 /*
1901 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1902 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1903 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1904 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1905 *
1906 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1907 * driver.
1908 */
1909 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1910 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1911
1912 static void quirk_netmos(struct pci_dev *dev)
1913 {
1914 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1915 unsigned int num_serial = dev->subsystem_device & 0xf;
1916
1917 /*
1918 * These Netmos parts are multiport serial devices with optional
1919 * parallel ports. Even when parallel ports are present, they
1920 * are identified as class SERIAL, which means the serial driver
1921 * will claim them. To prevent this, mark them as class OTHER.
1922 * These combo devices should be claimed by parport_serial.
1923 *
1924 * The subdevice ID is of the form 0x00PS, where <P> is the number
1925 * of parallel ports and <S> is the number of serial ports.
1926 */
1927 switch (dev->device) {
1928 case PCI_DEVICE_ID_NETMOS_9835:
1929 /* Well, this rule doesn't hold for the following 9835 device */
1930 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1931 dev->subsystem_device == 0x0299)
1932 return;
1933 case PCI_DEVICE_ID_NETMOS_9735:
1934 case PCI_DEVICE_ID_NETMOS_9745:
1935 case PCI_DEVICE_ID_NETMOS_9845:
1936 case PCI_DEVICE_ID_NETMOS_9855:
1937 if (num_parallel) {
1938 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1939 dev->device, num_parallel, num_serial);
1940 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1941 (dev->class & 0xff);
1942 }
1943 }
1944 }
1945 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1946 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1947
1948 /*
1949 * Quirk non-zero PCI functions to route VPD access through function 0 for
1950 * devices that share VPD resources between functions. The functions are
1951 * expected to be identical devices.
1952 */
1953 static void quirk_f0_vpd_link(struct pci_dev *dev)
1954 {
1955 struct pci_dev *f0;
1956
1957 if (!PCI_FUNC(dev->devfn))
1958 return;
1959
1960 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1961 if (!f0)
1962 return;
1963
1964 if (f0->vpd && dev->class == f0->class &&
1965 dev->vendor == f0->vendor && dev->device == f0->device)
1966 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1967
1968 pci_dev_put(f0);
1969 }
1970 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1971 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1972
1973 static void quirk_e100_interrupt(struct pci_dev *dev)
1974 {
1975 u16 command, pmcsr;
1976 u8 __iomem *csr;
1977 u8 cmd_hi;
1978
1979 switch (dev->device) {
1980 /* PCI IDs taken from drivers/net/e100.c */
1981 case 0x1029:
1982 case 0x1030 ... 0x1034:
1983 case 0x1038 ... 0x103E:
1984 case 0x1050 ... 0x1057:
1985 case 0x1059:
1986 case 0x1064 ... 0x106B:
1987 case 0x1091 ... 0x1095:
1988 case 0x1209:
1989 case 0x1229:
1990 case 0x2449:
1991 case 0x2459:
1992 case 0x245D:
1993 case 0x27DC:
1994 break;
1995 default:
1996 return;
1997 }
1998
1999 /*
2000 * Some firmware hands off the e100 with interrupts enabled,
2001 * which can cause a flood of interrupts if packets are
2002 * received before the driver attaches to the device. So
2003 * disable all e100 interrupts here. The driver will
2004 * re-enable them when it's ready.
2005 */
2006 pci_read_config_word(dev, PCI_COMMAND, &command);
2007
2008 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2009 return;
2010
2011 /*
2012 * Check that the device is in the D0 power state. If it's not,
2013 * there is no point to look any further.
2014 */
2015 if (dev->pm_cap) {
2016 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2017 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2018 return;
2019 }
2020
2021 /* Convert from PCI bus to resource space. */
2022 csr = ioremap(pci_resource_start(dev, 0), 8);
2023 if (!csr) {
2024 dev_warn(&dev->dev, "Can't map e100 registers\n");
2025 return;
2026 }
2027
2028 cmd_hi = readb(csr + 3);
2029 if (cmd_hi == 0) {
2030 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2031 writeb(1, csr + 3);
2032 }
2033
2034 iounmap(csr);
2035 }
2036 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2037 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2038
2039 /*
2040 * The 82575 and 82598 may experience data corruption issues when transitioning
2041 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2042 */
2043 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2044 {
2045 dev_info(&dev->dev, "Disabling L0s\n");
2046 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2047 }
2048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2062
2063 static void fixup_rev1_53c810(struct pci_dev *dev)
2064 {
2065 u32 class = dev->class;
2066
2067 /*
2068 * rev 1 ncr53c810 chips don't set the class at all which means
2069 * they don't get their resources remapped. Fix that here.
2070 */
2071 if (class)
2072 return;
2073
2074 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2075 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2076 class, dev->class);
2077 }
2078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2079
2080 /* Enable 1k I/O space granularity on the Intel P64H2 */
2081 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2082 {
2083 u16 en1k;
2084
2085 pci_read_config_word(dev, 0x40, &en1k);
2086
2087 if (en1k & 0x200) {
2088 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2089 dev->io_window_1k = 1;
2090 }
2091 }
2092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2093
2094 /* Under some circumstances, AER is not linked with extended capabilities.
2095 * Force it to be linked by setting the corresponding control bit in the
2096 * config space.
2097 */
2098 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2099 {
2100 uint8_t b;
2101 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2102 if (!(b & 0x20)) {
2103 pci_write_config_byte(dev, 0xf41, b | 0x20);
2104 dev_info(&dev->dev, "Linking AER extended capability\n");
2105 }
2106 }
2107 }
2108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2109 quirk_nvidia_ck804_pcie_aer_ext_cap);
2110 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2111 quirk_nvidia_ck804_pcie_aer_ext_cap);
2112
2113 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2114 {
2115 /*
2116 * Disable PCI Bus Parking and PCI Master read caching on CX700
2117 * which causes unspecified timing errors with a VT6212L on the PCI
2118 * bus leading to USB2.0 packet loss.
2119 *
2120 * This quirk is only enabled if a second (on the external PCI bus)
2121 * VT6212L is found -- the CX700 core itself also contains a USB
2122 * host controller with the same PCI ID as the VT6212L.
2123 */
2124
2125 /* Count VT6212L instances */
2126 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2127 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2128 uint8_t b;
2129
2130 /* p should contain the first (internal) VT6212L -- see if we have
2131 an external one by searching again */
2132 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2133 if (!p)
2134 return;
2135 pci_dev_put(p);
2136
2137 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2138 if (b & 0x40) {
2139 /* Turn off PCI Bus Parking */
2140 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2141
2142 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2143 }
2144 }
2145
2146 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2147 if (b != 0) {
2148 /* Turn off PCI Master read caching */
2149 pci_write_config_byte(dev, 0x72, 0x0);
2150
2151 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2152 pci_write_config_byte(dev, 0x75, 0x1);
2153
2154 /* Disable "Read FIFO Timer" */
2155 pci_write_config_byte(dev, 0x77, 0x0);
2156
2157 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2158 }
2159 }
2160 }
2161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2162
2163 /*
2164 * If a device follows the VPD format spec, the PCI core will not read or
2165 * write past the VPD End Tag. But some vendors do not follow the VPD
2166 * format spec, so we can't tell how much data is safe to access. Devices
2167 * may behave unpredictably if we access too much. Blacklist these devices
2168 * so we don't touch VPD at all.
2169 */
2170 static void quirk_blacklist_vpd(struct pci_dev *dev)
2171 {
2172 if (dev->vpd) {
2173 dev->vpd->len = 0;
2174 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2175 }
2176 }
2177
2178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2190 quirk_blacklist_vpd);
2191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2192
2193 /*
2194 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2195 * VPD end tag will hang the device. This problem was initially
2196 * observed when a vpd entry was created in sysfs
2197 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2198 * will dump 32k of data. Reading a full 32k will cause an access
2199 * beyond the VPD end tag causing the device to hang. Once the device
2200 * is hung, the bnx2 driver will not be able to reset the device.
2201 * We believe that it is legal to read beyond the end tag and
2202 * therefore the solution is to limit the read/write length.
2203 */
2204 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2205 {
2206 /*
2207 * Only disable the VPD capability for 5706, 5706S, 5708,
2208 * 5708S and 5709 rev. A
2209 */
2210 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2211 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2212 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2213 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2214 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2215 (dev->revision & 0xf0) == 0x0)) {
2216 if (dev->vpd)
2217 dev->vpd->len = 0x80;
2218 }
2219 }
2220
2221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2222 PCI_DEVICE_ID_NX2_5706,
2223 quirk_brcm_570x_limit_vpd);
2224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2225 PCI_DEVICE_ID_NX2_5706S,
2226 quirk_brcm_570x_limit_vpd);
2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2228 PCI_DEVICE_ID_NX2_5708,
2229 quirk_brcm_570x_limit_vpd);
2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2231 PCI_DEVICE_ID_NX2_5708S,
2232 quirk_brcm_570x_limit_vpd);
2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2234 PCI_DEVICE_ID_NX2_5709,
2235 quirk_brcm_570x_limit_vpd);
2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2237 PCI_DEVICE_ID_NX2_5709S,
2238 quirk_brcm_570x_limit_vpd);
2239
2240 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2241 {
2242 u32 rev;
2243
2244 pci_read_config_dword(dev, 0xf4, &rev);
2245
2246 /* Only CAP the MRRS if the device is a 5719 A0 */
2247 if (rev == 0x05719000) {
2248 int readrq = pcie_get_readrq(dev);
2249 if (readrq > 2048)
2250 pcie_set_readrq(dev, 2048);
2251 }
2252 }
2253
2254 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2255 PCI_DEVICE_ID_TIGON3_5719,
2256 quirk_brcm_5719_limit_mrrs);
2257
2258 /* Originally in EDAC sources for i82875P:
2259 * Intel tells BIOS developers to hide device 6 which
2260 * configures the overflow device access containing
2261 * the DRBs - this is where we expose device 6.
2262 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2263 */
2264 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2265 {
2266 u8 reg;
2267
2268 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2269 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2270 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2271 }
2272 }
2273
2274 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2275 quirk_unhide_mch_dev6);
2276 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2277 quirk_unhide_mch_dev6);
2278
2279 #ifdef CONFIG_TILEPRO
2280 /*
2281 * The Tilera TILEmpower tilepro platform needs to set the link speed
2282 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2283 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2284 * capability register of the PEX8624 PCIe switch. The switch
2285 * supports link speed auto negotiation, but falsely sets
2286 * the link speed to 5GT/s.
2287 */
2288 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2289 {
2290 if (tile_plx_gen1) {
2291 pci_write_config_dword(dev, 0x98, 0x1);
2292 mdelay(50);
2293 }
2294 }
2295 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2296 #endif /* CONFIG_TILEPRO */
2297
2298 #ifdef CONFIG_PCI_MSI
2299 /* Some chipsets do not support MSI. We cannot easily rely on setting
2300 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2301 * some other buses controlled by the chipset even if Linux is not
2302 * aware of it. Instead of setting the flag on all buses in the
2303 * machine, simply disable MSI globally.
2304 */
2305 static void quirk_disable_all_msi(struct pci_dev *dev)
2306 {
2307 pci_no_msi();
2308 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2309 }
2310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2311 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2312 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2318
2319 /* Disable MSI on chipsets that are known to not support it */
2320 static void quirk_disable_msi(struct pci_dev *dev)
2321 {
2322 if (dev->subordinate) {
2323 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2324 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2325 }
2326 }
2327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2330
2331 /*
2332 * The APC bridge device in AMD 780 family northbridges has some random
2333 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2334 * we use the possible vendor/device IDs of the host bridge for the
2335 * declared quirk, and search for the APC bridge by slot number.
2336 */
2337 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2338 {
2339 struct pci_dev *apc_bridge;
2340
2341 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2342 if (apc_bridge) {
2343 if (apc_bridge->device == 0x9602)
2344 quirk_disable_msi(apc_bridge);
2345 pci_dev_put(apc_bridge);
2346 }
2347 }
2348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2350
2351 /* Go through the list of Hypertransport capabilities and
2352 * return 1 if a HT MSI capability is found and enabled */
2353 static int msi_ht_cap_enabled(struct pci_dev *dev)
2354 {
2355 int pos, ttl = PCI_FIND_CAP_TTL;
2356
2357 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2358 while (pos && ttl--) {
2359 u8 flags;
2360
2361 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2362 &flags) == 0) {
2363 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2364 flags & HT_MSI_FLAGS_ENABLE ?
2365 "enabled" : "disabled");
2366 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2367 }
2368
2369 pos = pci_find_next_ht_capability(dev, pos,
2370 HT_CAPTYPE_MSI_MAPPING);
2371 }
2372 return 0;
2373 }
2374
2375 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2376 static void quirk_msi_ht_cap(struct pci_dev *dev)
2377 {
2378 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2379 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2380 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2381 }
2382 }
2383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2384 quirk_msi_ht_cap);
2385
2386 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2387 * MSI are supported if the MSI capability set in any of these mappings.
2388 */
2389 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2390 {
2391 struct pci_dev *pdev;
2392
2393 if (!dev->subordinate)
2394 return;
2395
2396 /* check HT MSI cap on this chipset and the root one.
2397 * a single one having MSI is enough to be sure that MSI are supported.
2398 */
2399 pdev = pci_get_slot(dev->bus, 0);
2400 if (!pdev)
2401 return;
2402 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2403 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2404 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2405 }
2406 pci_dev_put(pdev);
2407 }
2408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2409 quirk_nvidia_ck804_msi_ht_cap);
2410
2411 /* Force enable MSI mapping capability on HT bridges */
2412 static void ht_enable_msi_mapping(struct pci_dev *dev)
2413 {
2414 int pos, ttl = PCI_FIND_CAP_TTL;
2415
2416 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2417 while (pos && ttl--) {
2418 u8 flags;
2419
2420 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2421 &flags) == 0) {
2422 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2423
2424 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2425 flags | HT_MSI_FLAGS_ENABLE);
2426 }
2427 pos = pci_find_next_ht_capability(dev, pos,
2428 HT_CAPTYPE_MSI_MAPPING);
2429 }
2430 }
2431 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2432 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2433 ht_enable_msi_mapping);
2434
2435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2436 ht_enable_msi_mapping);
2437
2438 /* The P5N32-SLI motherboards from Asus have a problem with msi
2439 * for the MCP55 NIC. It is not yet determined whether the msi problem
2440 * also affects other devices. As for now, turn off msi for this device.
2441 */
2442 static void nvenet_msi_disable(struct pci_dev *dev)
2443 {
2444 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2445
2446 if (board_name &&
2447 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2448 strstr(board_name, "P5N32-E SLI"))) {
2449 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2450 dev->no_msi = 1;
2451 }
2452 }
2453 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2454 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2455 nvenet_msi_disable);
2456
2457 /*
2458 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2459 * config register. This register controls the routing of legacy
2460 * interrupts from devices that route through the MCP55. If this register
2461 * is misprogrammed, interrupts are only sent to the BSP, unlike
2462 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2463 * having this register set properly prevents kdump from booting up
2464 * properly, so let's make sure that we have it set correctly.
2465 * Note that this is an undocumented register.
2466 */
2467 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2468 {
2469 u32 cfg;
2470
2471 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2472 return;
2473
2474 pci_read_config_dword(dev, 0x74, &cfg);
2475
2476 if (cfg & ((1 << 2) | (1 << 15))) {
2477 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2478 cfg &= ~((1 << 2) | (1 << 15));
2479 pci_write_config_dword(dev, 0x74, cfg);
2480 }
2481 }
2482
2483 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2484 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2485 nvbridge_check_legacy_irq_routing);
2486
2487 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2488 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2489 nvbridge_check_legacy_irq_routing);
2490
2491 static int ht_check_msi_mapping(struct pci_dev *dev)
2492 {
2493 int pos, ttl = PCI_FIND_CAP_TTL;
2494 int found = 0;
2495
2496 /* check if there is HT MSI cap or enabled on this device */
2497 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2498 while (pos && ttl--) {
2499 u8 flags;
2500
2501 if (found < 1)
2502 found = 1;
2503 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2504 &flags) == 0) {
2505 if (flags & HT_MSI_FLAGS_ENABLE) {
2506 if (found < 2) {
2507 found = 2;
2508 break;
2509 }
2510 }
2511 }
2512 pos = pci_find_next_ht_capability(dev, pos,
2513 HT_CAPTYPE_MSI_MAPPING);
2514 }
2515
2516 return found;
2517 }
2518
2519 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2520 {
2521 struct pci_dev *dev;
2522 int pos;
2523 int i, dev_no;
2524 int found = 0;
2525
2526 dev_no = host_bridge->devfn >> 3;
2527 for (i = dev_no + 1; i < 0x20; i++) {
2528 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2529 if (!dev)
2530 continue;
2531
2532 /* found next host bridge ?*/
2533 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2534 if (pos != 0) {
2535 pci_dev_put(dev);
2536 break;
2537 }
2538
2539 if (ht_check_msi_mapping(dev)) {
2540 found = 1;
2541 pci_dev_put(dev);
2542 break;
2543 }
2544 pci_dev_put(dev);
2545 }
2546
2547 return found;
2548 }
2549
2550 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2551 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2552
2553 static int is_end_of_ht_chain(struct pci_dev *dev)
2554 {
2555 int pos, ctrl_off;
2556 int end = 0;
2557 u16 flags, ctrl;
2558
2559 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2560
2561 if (!pos)
2562 goto out;
2563
2564 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2565
2566 ctrl_off = ((flags >> 10) & 1) ?
2567 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2568 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2569
2570 if (ctrl & (1 << 6))
2571 end = 1;
2572
2573 out:
2574 return end;
2575 }
2576
2577 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2578 {
2579 struct pci_dev *host_bridge;
2580 int pos;
2581 int i, dev_no;
2582 int found = 0;
2583
2584 dev_no = dev->devfn >> 3;
2585 for (i = dev_no; i >= 0; i--) {
2586 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2587 if (!host_bridge)
2588 continue;
2589
2590 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2591 if (pos != 0) {
2592 found = 1;
2593 break;
2594 }
2595 pci_dev_put(host_bridge);
2596 }
2597
2598 if (!found)
2599 return;
2600
2601 /* don't enable end_device/host_bridge with leaf directly here */
2602 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2603 host_bridge_with_leaf(host_bridge))
2604 goto out;
2605
2606 /* root did that ! */
2607 if (msi_ht_cap_enabled(host_bridge))
2608 goto out;
2609
2610 ht_enable_msi_mapping(dev);
2611
2612 out:
2613 pci_dev_put(host_bridge);
2614 }
2615
2616 static void ht_disable_msi_mapping(struct pci_dev *dev)
2617 {
2618 int pos, ttl = PCI_FIND_CAP_TTL;
2619
2620 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2621 while (pos && ttl--) {
2622 u8 flags;
2623
2624 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2625 &flags) == 0) {
2626 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2627
2628 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2629 flags & ~HT_MSI_FLAGS_ENABLE);
2630 }
2631 pos = pci_find_next_ht_capability(dev, pos,
2632 HT_CAPTYPE_MSI_MAPPING);
2633 }
2634 }
2635
2636 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2637 {
2638 struct pci_dev *host_bridge;
2639 int pos;
2640 int found;
2641
2642 if (!pci_msi_enabled())
2643 return;
2644
2645 /* check if there is HT MSI cap or enabled on this device */
2646 found = ht_check_msi_mapping(dev);
2647
2648 /* no HT MSI CAP */
2649 if (found == 0)
2650 return;
2651
2652 /*
2653 * HT MSI mapping should be disabled on devices that are below
2654 * a non-Hypertransport host bridge. Locate the host bridge...
2655 */
2656 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2657 if (host_bridge == NULL) {
2658 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2659 return;
2660 }
2661
2662 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2663 if (pos != 0) {
2664 /* Host bridge is to HT */
2665 if (found == 1) {
2666 /* it is not enabled, try to enable it */
2667 if (all)
2668 ht_enable_msi_mapping(dev);
2669 else
2670 nv_ht_enable_msi_mapping(dev);
2671 }
2672 goto out;
2673 }
2674
2675 /* HT MSI is not enabled */
2676 if (found == 1)
2677 goto out;
2678
2679 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2680 ht_disable_msi_mapping(dev);
2681
2682 out:
2683 pci_dev_put(host_bridge);
2684 }
2685
2686 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2687 {
2688 return __nv_msi_ht_cap_quirk(dev, 1);
2689 }
2690
2691 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2692 {
2693 return __nv_msi_ht_cap_quirk(dev, 0);
2694 }
2695
2696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2697 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2698
2699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2700 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2701
2702 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2703 {
2704 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2705 }
2706 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2707 {
2708 struct pci_dev *p;
2709
2710 /* SB700 MSI issue will be fixed at HW level from revision A21,
2711 * we need check PCI REVISION ID of SMBus controller to get SB700
2712 * revision.
2713 */
2714 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2715 NULL);
2716 if (!p)
2717 return;
2718
2719 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2720 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2721 pci_dev_put(p);
2722 }
2723 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2724 {
2725 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2726 if (dev->revision < 0x18) {
2727 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2728 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2729 }
2730 }
2731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2732 PCI_DEVICE_ID_TIGON3_5780,
2733 quirk_msi_intx_disable_bug);
2734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2735 PCI_DEVICE_ID_TIGON3_5780S,
2736 quirk_msi_intx_disable_bug);
2737 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2738 PCI_DEVICE_ID_TIGON3_5714,
2739 quirk_msi_intx_disable_bug);
2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2741 PCI_DEVICE_ID_TIGON3_5714S,
2742 quirk_msi_intx_disable_bug);
2743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2744 PCI_DEVICE_ID_TIGON3_5715,
2745 quirk_msi_intx_disable_bug);
2746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2747 PCI_DEVICE_ID_TIGON3_5715S,
2748 quirk_msi_intx_disable_bug);
2749
2750 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2751 quirk_msi_intx_disable_ati_bug);
2752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2753 quirk_msi_intx_disable_ati_bug);
2754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2755 quirk_msi_intx_disable_ati_bug);
2756 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2757 quirk_msi_intx_disable_ati_bug);
2758 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2759 quirk_msi_intx_disable_ati_bug);
2760
2761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2762 quirk_msi_intx_disable_bug);
2763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2764 quirk_msi_intx_disable_bug);
2765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2766 quirk_msi_intx_disable_bug);
2767
2768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2769 quirk_msi_intx_disable_bug);
2770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2771 quirk_msi_intx_disable_bug);
2772 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2773 quirk_msi_intx_disable_bug);
2774 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2775 quirk_msi_intx_disable_bug);
2776 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2777 quirk_msi_intx_disable_bug);
2778 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2779 quirk_msi_intx_disable_bug);
2780 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2781 quirk_msi_intx_disable_qca_bug);
2782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2783 quirk_msi_intx_disable_qca_bug);
2784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2785 quirk_msi_intx_disable_qca_bug);
2786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2787 quirk_msi_intx_disable_qca_bug);
2788 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2789 quirk_msi_intx_disable_qca_bug);
2790 #endif /* CONFIG_PCI_MSI */
2791
2792 /* Allow manual resource allocation for PCI hotplug bridges
2793 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2794 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2795 * kernel fails to allocate resources when hotplug device is
2796 * inserted and PCI bus is rescanned.
2797 */
2798 static void quirk_hotplug_bridge(struct pci_dev *dev)
2799 {
2800 dev->is_hotplug_bridge = 1;
2801 }
2802
2803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2804
2805 /*
2806 * Apple: Avoid programming the memory/io aperture of 00:1c.0
2807 *
2808 * BIOS does not declare any resource for 00:1c.0, but with
2809 * hotplug flag set, thus the OS allocates:
2810 * [mem 0x7fa00000 - 0x7fbfffff]
2811 * [mem 0x7fc00000-0x7fdfffff 64bit pref]
2812 * which is conflict with an unreported device, which
2813 * causes unpredictable result such as accessing io port.
2814 * So clear the hotplug flag to work around it.
2815 */
2816 static void quirk_apple_mbp_poweroff(struct pci_dev *dev)
2817 {
2818 if (dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") ||
2819 dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5"))
2820 dev->is_hotplug_bridge = 0;
2821 }
2822
2823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
2824
2825 /*
2826 * This is a quirk for the Ricoh MMC controller found as a part of
2827 * some mulifunction chips.
2828
2829 * This is very similar and based on the ricoh_mmc driver written by
2830 * Philip Langdale. Thank you for these magic sequences.
2831 *
2832 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2833 * and one or both of cardbus or firewire.
2834 *
2835 * It happens that they implement SD and MMC
2836 * support as separate controllers (and PCI functions). The linux SDHCI
2837 * driver supports MMC cards but the chip detects MMC cards in hardware
2838 * and directs them to the MMC controller - so the SDHCI driver never sees
2839 * them.
2840 *
2841 * To get around this, we must disable the useless MMC controller.
2842 * At that point, the SDHCI controller will start seeing them
2843 * It seems to be the case that the relevant PCI registers to deactivate the
2844 * MMC controller live on PCI function 0, which might be the cardbus controller
2845 * or the firewire controller, depending on the particular chip in question
2846 *
2847 * This has to be done early, because as soon as we disable the MMC controller
2848 * other pci functions shift up one level, e.g. function #2 becomes function
2849 * #1, and this will confuse the pci core.
2850 */
2851
2852 #ifdef CONFIG_MMC_RICOH_MMC
2853 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2854 {
2855 /* disable via cardbus interface */
2856 u8 write_enable;
2857 u8 write_target;
2858 u8 disable;
2859
2860 /* disable must be done via function #0 */
2861 if (PCI_FUNC(dev->devfn))
2862 return;
2863
2864 pci_read_config_byte(dev, 0xB7, &disable);
2865 if (disable & 0x02)
2866 return;
2867
2868 pci_read_config_byte(dev, 0x8E, &write_enable);
2869 pci_write_config_byte(dev, 0x8E, 0xAA);
2870 pci_read_config_byte(dev, 0x8D, &write_target);
2871 pci_write_config_byte(dev, 0x8D, 0xB7);
2872 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2873 pci_write_config_byte(dev, 0x8E, write_enable);
2874 pci_write_config_byte(dev, 0x8D, write_target);
2875
2876 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2877 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2878 }
2879 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2880 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2881
2882 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2883 {
2884 /* disable via firewire interface */
2885 u8 write_enable;
2886 u8 disable;
2887
2888 /* disable must be done via function #0 */
2889 if (PCI_FUNC(dev->devfn))
2890 return;
2891 /*
2892 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2893 * certain types of SD/MMC cards. Lowering the SD base
2894 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2895 *
2896 * 0x150 - SD2.0 mode enable for changing base clock
2897 * frequency to 50Mhz
2898 * 0xe1 - Base clock frequency
2899 * 0x32 - 50Mhz new clock frequency
2900 * 0xf9 - Key register for 0x150
2901 * 0xfc - key register for 0xe1
2902 */
2903 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2904 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2905 pci_write_config_byte(dev, 0xf9, 0xfc);
2906 pci_write_config_byte(dev, 0x150, 0x10);
2907 pci_write_config_byte(dev, 0xf9, 0x00);
2908 pci_write_config_byte(dev, 0xfc, 0x01);
2909 pci_write_config_byte(dev, 0xe1, 0x32);
2910 pci_write_config_byte(dev, 0xfc, 0x00);
2911
2912 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2913 }
2914
2915 pci_read_config_byte(dev, 0xCB, &disable);
2916
2917 if (disable & 0x02)
2918 return;
2919
2920 pci_read_config_byte(dev, 0xCA, &write_enable);
2921 pci_write_config_byte(dev, 0xCA, 0x57);
2922 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2923 pci_write_config_byte(dev, 0xCA, write_enable);
2924
2925 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2926 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2927
2928 }
2929 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2930 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2931 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2932 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2933 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2934 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2935 #endif /*CONFIG_MMC_RICOH_MMC*/
2936
2937 #ifdef CONFIG_DMAR_TABLE
2938 #define VTUNCERRMSK_REG 0x1ac
2939 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2940 /*
2941 * This is a quirk for masking vt-d spec defined errors to platform error
2942 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2943 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2944 * on the RAS config settings of the platform) when a vt-d fault happens.
2945 * The resulting SMI caused the system to hang.
2946 *
2947 * VT-d spec related errors are already handled by the VT-d OS code, so no
2948 * need to report the same error through other channels.
2949 */
2950 static void vtd_mask_spec_errors(struct pci_dev *dev)
2951 {
2952 u32 word;
2953
2954 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2955 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2956 }
2957 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2958 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2959 #endif
2960
2961 static void fixup_ti816x_class(struct pci_dev *dev)
2962 {
2963 u32 class = dev->class;
2964
2965 /* TI 816x devices do not have class code set when in PCIe boot mode */
2966 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2967 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2968 class, dev->class);
2969 }
2970 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2971 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2972
2973 /* Some PCIe devices do not work reliably with the claimed maximum
2974 * payload size supported.
2975 */
2976 static void fixup_mpss_256(struct pci_dev *dev)
2977 {
2978 dev->pcie_mpss = 1; /* 256 bytes */
2979 }
2980 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2981 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2983 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2985 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2986
2987 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2988 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2989 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2990 * until all of the devices are discovered and buses walked, read completion
2991 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2992 * it is possible to hotplug a device with MPS of 256B.
2993 */
2994 static void quirk_intel_mc_errata(struct pci_dev *dev)
2995 {
2996 int err;
2997 u16 rcc;
2998
2999 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3000 pcie_bus_config == PCIE_BUS_DEFAULT)
3001 return;
3002
3003 /* Intel errata specifies bits to change but does not say what they are.
3004 * Keeping them magical until such time as the registers and values can
3005 * be explained.
3006 */
3007 err = pci_read_config_word(dev, 0x48, &rcc);
3008 if (err) {
3009 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3010 return;
3011 }
3012
3013 if (!(rcc & (1 << 10)))
3014 return;
3015
3016 rcc &= ~(1 << 10);
3017
3018 err = pci_write_config_word(dev, 0x48, rcc);
3019 if (err) {
3020 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3021 return;
3022 }
3023
3024 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3025 }
3026 /* Intel 5000 series memory controllers and ports 2-7 */
3027 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3035 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3040 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3041 /* Intel 5100 series memory controllers and ports 2-7 */
3042 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3043 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3044 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3045 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3046 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3053
3054
3055 /*
3056 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3057 * work around this, query the size it should be configured to by the device and
3058 * modify the resource end to correspond to this new size.
3059 */
3060 static void quirk_intel_ntb(struct pci_dev *dev)
3061 {
3062 int rc;
3063 u8 val;
3064
3065 rc = pci_read_config_byte(dev, 0x00D0, &val);
3066 if (rc)
3067 return;
3068
3069 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3070
3071 rc = pci_read_config_byte(dev, 0x00D1, &val);
3072 if (rc)
3073 return;
3074
3075 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3076 }
3077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3079
3080 static ktime_t fixup_debug_start(struct pci_dev *dev,
3081 void (*fn)(struct pci_dev *dev))
3082 {
3083 ktime_t calltime = 0;
3084
3085 dev_dbg(&dev->dev, "calling %pF\n", fn);
3086 if (initcall_debug) {
3087 pr_debug("calling %pF @ %i for %s\n",
3088 fn, task_pid_nr(current), dev_name(&dev->dev));
3089 calltime = ktime_get();
3090 }
3091
3092 return calltime;
3093 }
3094
3095 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3096 void (*fn)(struct pci_dev *dev))
3097 {
3098 ktime_t delta, rettime;
3099 unsigned long long duration;
3100
3101 if (initcall_debug) {
3102 rettime = ktime_get();
3103 delta = ktime_sub(rettime, calltime);
3104 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3105 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3106 fn, duration, dev_name(&dev->dev));
3107 }
3108 }
3109
3110 /*
3111 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3112 * even though no one is handling them (f.e. i915 driver is never loaded).
3113 * Additionally the interrupt destination is not set up properly
3114 * and the interrupt ends up -somewhere-.
3115 *
3116 * These spurious interrupts are "sticky" and the kernel disables
3117 * the (shared) interrupt line after 100.000+ generated interrupts.
3118 *
3119 * Fix it by disabling the still enabled interrupts.
3120 * This resolves crashes often seen on monitor unplug.
3121 */
3122 #define I915_DEIER_REG 0x4400c
3123 static void disable_igfx_irq(struct pci_dev *dev)
3124 {
3125 void __iomem *regs = pci_iomap(dev, 0, 0);
3126 if (regs == NULL) {
3127 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3128 return;
3129 }
3130
3131 /* Check if any interrupt line is still enabled */
3132 if (readl(regs + I915_DEIER_REG) != 0) {
3133 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3134
3135 writel(0, regs + I915_DEIER_REG);
3136 }
3137
3138 pci_iounmap(dev, regs);
3139 }
3140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3143
3144 /*
3145 * PCI devices which are on Intel chips can skip the 10ms delay
3146 * before entering D3 mode.
3147 */
3148 static void quirk_remove_d3_delay(struct pci_dev *dev)
3149 {
3150 dev->d3_delay = 0;
3151 }
3152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3155 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3166 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3169 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3176
3177 /*
3178 * Some devices may pass our check in pci_intx_mask_supported() if
3179 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3180 * support this feature.
3181 */
3182 static void quirk_broken_intx_masking(struct pci_dev *dev)
3183 {
3184 dev->broken_intx_masking = 1;
3185 }
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3187 quirk_broken_intx_masking);
3188 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3189 quirk_broken_intx_masking);
3190
3191 /*
3192 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3193 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3194 *
3195 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3196 */
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3198 quirk_broken_intx_masking);
3199
3200 /*
3201 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3202 * DisINTx can be set but the interrupt status bit is non-functional.
3203 */
3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3205 quirk_broken_intx_masking);
3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3207 quirk_broken_intx_masking);
3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3209 quirk_broken_intx_masking);
3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3211 quirk_broken_intx_masking);
3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3213 quirk_broken_intx_masking);
3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3215 quirk_broken_intx_masking);
3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3217 quirk_broken_intx_masking);
3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3219 quirk_broken_intx_masking);
3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3221 quirk_broken_intx_masking);
3222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3223 quirk_broken_intx_masking);
3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3225 quirk_broken_intx_masking);
3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3227 quirk_broken_intx_masking);
3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3229 quirk_broken_intx_masking);
3230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3231 quirk_broken_intx_masking);
3232
3233 static u16 mellanox_broken_intx_devs[] = {
3234 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3235 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3236 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3237 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3238 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3239 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3240 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3241 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3242 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3243 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3244 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3245 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3246 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3247 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3248 };
3249
3250 #define CONNECTX_4_CURR_MAX_MINOR 99
3251 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3252
3253 /*
3254 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3255 * If so, don't mark it as broken.
3256 * FW minor > 99 means older FW version format and no INTx masking support.
3257 * FW minor < 14 means new FW version format and no INTx masking support.
3258 */
3259 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3260 {
3261 __be32 __iomem *fw_ver;
3262 u16 fw_major;
3263 u16 fw_minor;
3264 u16 fw_subminor;
3265 u32 fw_maj_min;
3266 u32 fw_sub_min;
3267 int i;
3268
3269 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3270 if (pdev->device == mellanox_broken_intx_devs[i]) {
3271 pdev->broken_intx_masking = 1;
3272 return;
3273 }
3274 }
3275
3276 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3277 * support so shouldn't be checked further
3278 */
3279 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3280 return;
3281
3282 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3283 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3284 return;
3285
3286 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3287 if (pci_enable_device_mem(pdev)) {
3288 dev_warn(&pdev->dev, "Can't enable device memory\n");
3289 return;
3290 }
3291
3292 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3293 if (!fw_ver) {
3294 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3295 goto out;
3296 }
3297
3298 /* Reading from resource space should be 32b aligned */
3299 fw_maj_min = ioread32be(fw_ver);
3300 fw_sub_min = ioread32be(fw_ver + 1);
3301 fw_major = fw_maj_min & 0xffff;
3302 fw_minor = fw_maj_min >> 16;
3303 fw_subminor = fw_sub_min & 0xffff;
3304 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3305 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3306 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3307 fw_major, fw_minor, fw_subminor, pdev->device ==
3308 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3309 pdev->broken_intx_masking = 1;
3310 }
3311
3312 iounmap(fw_ver);
3313
3314 out:
3315 pci_disable_device(pdev);
3316 }
3317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3318 mellanox_check_broken_intx_masking);
3319
3320 static void quirk_no_bus_reset(struct pci_dev *dev)
3321 {
3322 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3323 }
3324
3325 /*
3326 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3327 * The device will throw a Link Down error on AER-capable systems and
3328 * regardless of AER, config space of the device is never accessible again
3329 * and typically causes the system to hang or reset when access is attempted.
3330 * http://www.spinics.net/lists/linux-pci/msg34797.html
3331 */
3332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3336
3337 static void quirk_no_pm_reset(struct pci_dev *dev)
3338 {
3339 /*
3340 * We can't do a bus reset on root bus devices, but an ineffective
3341 * PM reset may be better than nothing.
3342 */
3343 if (!pci_is_root_bus(dev->bus))
3344 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3345 }
3346
3347 /*
3348 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3349 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3350 * to have no effect on the device: it retains the framebuffer contents and
3351 * monitor sync. Advertising this support makes other layers, like VFIO,
3352 * assume pci_reset_function() is viable for this device. Mark it as
3353 * unavailable to skip it when testing reset methods.
3354 */
3355 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3356 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3357
3358 /*
3359 * Thunderbolt controllers with broken MSI hotplug signaling:
3360 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3361 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3362 */
3363 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3364 {
3365 if (pdev->is_hotplug_bridge &&
3366 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3367 pdev->revision <= 1))
3368 pdev->no_msi = 1;
3369 }
3370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3371 quirk_thunderbolt_hotplug_msi);
3372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3373 quirk_thunderbolt_hotplug_msi);
3374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3375 quirk_thunderbolt_hotplug_msi);
3376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3377 quirk_thunderbolt_hotplug_msi);
3378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3379 quirk_thunderbolt_hotplug_msi);
3380
3381 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3382 {
3383 pci_set_vpd_size(dev, 8192);
3384 }
3385
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
3388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
3389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
3390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
3392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
3393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
3394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
3399
3400 #ifdef CONFIG_ACPI
3401 /*
3402 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3403 *
3404 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3405 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3406 * be present after resume if a device was plugged in before suspend.
3407 *
3408 * The thunderbolt controller consists of a pcie switch with downstream
3409 * bridges leading to the NHI and to the tunnel pci bridges.
3410 *
3411 * This quirk cuts power to the whole chip. Therefore we have to apply it
3412 * during suspend_noirq of the upstream bridge.
3413 *
3414 * Power is automagically restored before resume. No action is needed.
3415 */
3416 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3417 {
3418 acpi_handle bridge, SXIO, SXFP, SXLV;
3419
3420 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3421 return;
3422 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3423 return;
3424 bridge = ACPI_HANDLE(&dev->dev);
3425 if (!bridge)
3426 return;
3427 /*
3428 * SXIO and SXLV are present only on machines requiring this quirk.
3429 * TB bridges in external devices might have the same device id as those
3430 * on the host, but they will not have the associated ACPI methods. This
3431 * implicitly checks that we are at the right bridge.
3432 */
3433 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3434 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3435 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3436 return;
3437 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3438
3439 /* magic sequence */
3440 acpi_execute_simple_method(SXIO, NULL, 1);
3441 acpi_execute_simple_method(SXFP, NULL, 0);
3442 msleep(300);
3443 acpi_execute_simple_method(SXLV, NULL, 0);
3444 acpi_execute_simple_method(SXIO, NULL, 0);
3445 acpi_execute_simple_method(SXLV, NULL, 0);
3446 }
3447 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3448 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3449 quirk_apple_poweroff_thunderbolt);
3450
3451 /*
3452 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3453 *
3454 * During suspend the thunderbolt controller is reset and all pci
3455 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3456 * during resume. We have to manually wait for the NHI since there is
3457 * no parent child relationship between the NHI and the tunneled
3458 * bridges.
3459 */
3460 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3461 {
3462 struct pci_dev *sibling = NULL;
3463 struct pci_dev *nhi = NULL;
3464
3465 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3466 return;
3467 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3468 return;
3469 /*
3470 * Find the NHI and confirm that we are a bridge on the tb host
3471 * controller and not on a tb endpoint.
3472 */
3473 sibling = pci_get_slot(dev->bus, 0x0);
3474 if (sibling == dev)
3475 goto out; /* we are the downstream bridge to the NHI */
3476 if (!sibling || !sibling->subordinate)
3477 goto out;
3478 nhi = pci_get_slot(sibling->subordinate, 0x0);
3479 if (!nhi)
3480 goto out;
3481 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3482 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3483 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3484 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3485 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3486 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3487 goto out;
3488 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3489 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3490 out:
3491 pci_dev_put(nhi);
3492 pci_dev_put(sibling);
3493 }
3494 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3495 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3496 quirk_apple_wait_for_thunderbolt);
3497 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3498 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3499 quirk_apple_wait_for_thunderbolt);
3500 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3501 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3502 quirk_apple_wait_for_thunderbolt);
3503 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3504 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3505 quirk_apple_wait_for_thunderbolt);
3506 #endif
3507
3508 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3509 struct pci_fixup *end)
3510 {
3511 ktime_t calltime;
3512
3513 for (; f < end; f++)
3514 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3515 f->class == (u32) PCI_ANY_ID) &&
3516 (f->vendor == dev->vendor ||
3517 f->vendor == (u16) PCI_ANY_ID) &&
3518 (f->device == dev->device ||
3519 f->device == (u16) PCI_ANY_ID)) {
3520 calltime = fixup_debug_start(dev, f->hook);
3521 f->hook(dev);
3522 fixup_debug_report(dev, calltime, f->hook);
3523 }
3524 }
3525
3526 extern struct pci_fixup __start_pci_fixups_early[];
3527 extern struct pci_fixup __end_pci_fixups_early[];
3528 extern struct pci_fixup __start_pci_fixups_header[];
3529 extern struct pci_fixup __end_pci_fixups_header[];
3530 extern struct pci_fixup __start_pci_fixups_final[];
3531 extern struct pci_fixup __end_pci_fixups_final[];
3532 extern struct pci_fixup __start_pci_fixups_enable[];
3533 extern struct pci_fixup __end_pci_fixups_enable[];
3534 extern struct pci_fixup __start_pci_fixups_resume[];
3535 extern struct pci_fixup __end_pci_fixups_resume[];
3536 extern struct pci_fixup __start_pci_fixups_resume_early[];
3537 extern struct pci_fixup __end_pci_fixups_resume_early[];
3538 extern struct pci_fixup __start_pci_fixups_suspend[];
3539 extern struct pci_fixup __end_pci_fixups_suspend[];
3540 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3541 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3542
3543 static bool pci_apply_fixup_final_quirks;
3544
3545 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3546 {
3547 struct pci_fixup *start, *end;
3548
3549 switch (pass) {
3550 case pci_fixup_early:
3551 start = __start_pci_fixups_early;
3552 end = __end_pci_fixups_early;
3553 break;
3554
3555 case pci_fixup_header:
3556 start = __start_pci_fixups_header;
3557 end = __end_pci_fixups_header;
3558 break;
3559
3560 case pci_fixup_final:
3561 if (!pci_apply_fixup_final_quirks)
3562 return;
3563 start = __start_pci_fixups_final;
3564 end = __end_pci_fixups_final;
3565 break;
3566
3567 case pci_fixup_enable:
3568 start = __start_pci_fixups_enable;
3569 end = __end_pci_fixups_enable;
3570 break;
3571
3572 case pci_fixup_resume:
3573 start = __start_pci_fixups_resume;
3574 end = __end_pci_fixups_resume;
3575 break;
3576
3577 case pci_fixup_resume_early:
3578 start = __start_pci_fixups_resume_early;
3579 end = __end_pci_fixups_resume_early;
3580 break;
3581
3582 case pci_fixup_suspend:
3583 start = __start_pci_fixups_suspend;
3584 end = __end_pci_fixups_suspend;
3585 break;
3586
3587 case pci_fixup_suspend_late:
3588 start = __start_pci_fixups_suspend_late;
3589 end = __end_pci_fixups_suspend_late;
3590 break;
3591
3592 default:
3593 /* stupid compiler warning, you would think with an enum... */
3594 return;
3595 }
3596 pci_do_fixups(dev, start, end);
3597 }
3598 EXPORT_SYMBOL(pci_fixup_device);
3599
3600
3601 static int __init pci_apply_final_quirks(void)
3602 {
3603 struct pci_dev *dev = NULL;
3604 u8 cls = 0;
3605 u8 tmp;
3606
3607 if (pci_cache_line_size)
3608 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3609 pci_cache_line_size << 2);
3610
3611 pci_apply_fixup_final_quirks = true;
3612 for_each_pci_dev(dev) {
3613 pci_fixup_device(pci_fixup_final, dev);
3614 /*
3615 * If arch hasn't set it explicitly yet, use the CLS
3616 * value shared by all PCI devices. If there's a
3617 * mismatch, fall back to the default value.
3618 */
3619 if (!pci_cache_line_size) {
3620 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3621 if (!cls)
3622 cls = tmp;
3623 if (!tmp || cls == tmp)
3624 continue;
3625
3626 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3627 cls << 2, tmp << 2,
3628 pci_dfl_cache_line_size << 2);
3629 pci_cache_line_size = pci_dfl_cache_line_size;
3630 }
3631 }
3632
3633 if (!pci_cache_line_size) {
3634 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3635 cls << 2, pci_dfl_cache_line_size << 2);
3636 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3637 }
3638
3639 return 0;
3640 }
3641
3642 fs_initcall_sync(pci_apply_final_quirks);
3643
3644 /*
3645 * Followings are device-specific reset methods which can be used to
3646 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3647 * not available.
3648 */
3649 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3650 {
3651 /*
3652 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3653 *
3654 * The 82599 supports FLR on VFs, but FLR support is reported only
3655 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3656 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3657 */
3658
3659 if (probe)
3660 return 0;
3661
3662 if (!pci_wait_for_pending_transaction(dev))
3663 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3664
3665 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3666
3667 msleep(100);
3668
3669 return 0;
3670 }
3671
3672 #define SOUTH_CHICKEN2 0xc2004
3673 #define PCH_PP_STATUS 0xc7200
3674 #define PCH_PP_CONTROL 0xc7204
3675 #define MSG_CTL 0x45010
3676 #define NSDE_PWR_STATE 0xd0100
3677 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3678
3679 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3680 {
3681 void __iomem *mmio_base;
3682 unsigned long timeout;
3683 u32 val;
3684
3685 if (probe)
3686 return 0;
3687
3688 mmio_base = pci_iomap(dev, 0, 0);
3689 if (!mmio_base)
3690 return -ENOMEM;
3691
3692 iowrite32(0x00000002, mmio_base + MSG_CTL);
3693
3694 /*
3695 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3696 * driver loaded sets the right bits. However, this's a reset and
3697 * the bits have been set by i915 previously, so we clobber
3698 * SOUTH_CHICKEN2 register directly here.
3699 */
3700 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3701
3702 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3703 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3704
3705 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3706 do {
3707 val = ioread32(mmio_base + PCH_PP_STATUS);
3708 if ((val & 0xb0000000) == 0)
3709 goto reset_complete;
3710 msleep(10);
3711 } while (time_before(jiffies, timeout));
3712 dev_warn(&dev->dev, "timeout during reset\n");
3713
3714 reset_complete:
3715 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3716
3717 pci_iounmap(dev, mmio_base);
3718 return 0;
3719 }
3720
3721 /*
3722 * Device-specific reset method for Chelsio T4-based adapters.
3723 */
3724 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3725 {
3726 u16 old_command;
3727 u16 msix_flags;
3728
3729 /*
3730 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3731 * that we have no device-specific reset method.
3732 */
3733 if ((dev->device & 0xf000) != 0x4000)
3734 return -ENOTTY;
3735
3736 /*
3737 * If this is the "probe" phase, return 0 indicating that we can
3738 * reset this device.
3739 */
3740 if (probe)
3741 return 0;
3742
3743 /*
3744 * T4 can wedge if there are DMAs in flight within the chip and Bus
3745 * Master has been disabled. We need to have it on till the Function
3746 * Level Reset completes. (BUS_MASTER is disabled in
3747 * pci_reset_function()).
3748 */
3749 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3750 pci_write_config_word(dev, PCI_COMMAND,
3751 old_command | PCI_COMMAND_MASTER);
3752
3753 /*
3754 * Perform the actual device function reset, saving and restoring
3755 * configuration information around the reset.
3756 */
3757 pci_save_state(dev);
3758
3759 /*
3760 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3761 * are disabled when an MSI-X interrupt message needs to be delivered.
3762 * So we briefly re-enable MSI-X interrupts for the duration of the
3763 * FLR. The pci_restore_state() below will restore the original
3764 * MSI-X state.
3765 */
3766 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3767 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3768 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3769 msix_flags |
3770 PCI_MSIX_FLAGS_ENABLE |
3771 PCI_MSIX_FLAGS_MASKALL);
3772
3773 /*
3774 * Start of pcie_flr() code sequence. This reset code is a copy of
3775 * the guts of pcie_flr() because that's not an exported function.
3776 */
3777
3778 if (!pci_wait_for_pending_transaction(dev))
3779 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3780
3781 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3782 msleep(100);
3783
3784 /*
3785 * End of pcie_flr() code sequence.
3786 */
3787
3788 /*
3789 * Restore the configuration information (BAR values, etc.) including
3790 * the original PCI Configuration Space Command word, and return
3791 * success.
3792 */
3793 pci_restore_state(dev);
3794 pci_write_config_word(dev, PCI_COMMAND, old_command);
3795 return 0;
3796 }
3797
3798 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3799 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3800 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3801
3802 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3803 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3804 reset_intel_82599_sfp_virtfn },
3805 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3806 reset_ivb_igd },
3807 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3808 reset_ivb_igd },
3809 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3810 reset_chelsio_generic_dev },
3811 { 0 }
3812 };
3813
3814 /*
3815 * These device-specific reset methods are here rather than in a driver
3816 * because when a host assigns a device to a guest VM, the host may need
3817 * to reset the device but probably doesn't have a driver for it.
3818 */
3819 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3820 {
3821 const struct pci_dev_reset_methods *i;
3822
3823 for (i = pci_dev_reset_methods; i->reset; i++) {
3824 if ((i->vendor == dev->vendor ||
3825 i->vendor == (u16)PCI_ANY_ID) &&
3826 (i->device == dev->device ||
3827 i->device == (u16)PCI_ANY_ID))
3828 return i->reset(dev, probe);
3829 }
3830
3831 return -ENOTTY;
3832 }
3833
3834 static void quirk_dma_func0_alias(struct pci_dev *dev)
3835 {
3836 if (PCI_FUNC(dev->devfn) != 0)
3837 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3838 }
3839
3840 /*
3841 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3842 *
3843 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3844 */
3845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3847
3848 static void quirk_dma_func1_alias(struct pci_dev *dev)
3849 {
3850 if (PCI_FUNC(dev->devfn) != 1)
3851 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3852 }
3853
3854 /*
3855 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3856 * SKUs function 1 is present and is a legacy IDE controller, in other
3857 * SKUs this function is not present, making this a ghost requester.
3858 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3859 */
3860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3861 quirk_dma_func1_alias);
3862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3863 quirk_dma_func1_alias);
3864 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3866 quirk_dma_func1_alias);
3867 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3869 quirk_dma_func1_alias);
3870 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3872 quirk_dma_func1_alias);
3873 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3875 quirk_dma_func1_alias);
3876 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3877 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3878 quirk_dma_func1_alias);
3879 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3881 quirk_dma_func1_alias);
3882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3883 quirk_dma_func1_alias);
3884 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3886 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3887 quirk_dma_func1_alias);
3888 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3889 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3890 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3891 quirk_dma_func1_alias);
3892
3893 /*
3894 * Some devices DMA with the wrong devfn, not just the wrong function.
3895 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3896 * the alias is "fixed" and independent of the device devfn.
3897 *
3898 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3899 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3900 * single device on the secondary bus. In reality, the single exposed
3901 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3902 * that provides a bridge to the internal bus of the I/O processor. The
3903 * controller supports private devices, which can be hidden from PCI config
3904 * space. In the case of the Adaptec 3405, a private device at 01.0
3905 * appears to be the DMA engine, which therefore needs to become a DMA
3906 * alias for the device.
3907 */
3908 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3909 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3910 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3911 .driver_data = PCI_DEVFN(1, 0) },
3912 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3913 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3914 .driver_data = PCI_DEVFN(1, 0) },
3915 { 0 }
3916 };
3917
3918 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3919 {
3920 const struct pci_device_id *id;
3921
3922 id = pci_match_id(fixed_dma_alias_tbl, dev);
3923 if (id)
3924 pci_add_dma_alias(dev, id->driver_data);
3925 }
3926
3927 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3928
3929 /*
3930 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3931 * using the wrong DMA alias for the device. Some of these devices can be
3932 * used as either forward or reverse bridges, so we need to test whether the
3933 * device is operating in the correct mode. We could probably apply this
3934 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3935 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3936 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3937 */
3938 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3939 {
3940 if (!pci_is_root_bus(pdev->bus) &&
3941 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3942 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3943 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3944 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3945 }
3946 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3948 quirk_use_pcie_bridge_dma_alias);
3949 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3950 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3951 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3952 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3953 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3954 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3955
3956 /*
3957 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3958 * be added as aliases to the DMA device in order to allow buffer access
3959 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3960 * programmed in the EEPROM.
3961 */
3962 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3963 {
3964 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3965 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3966 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3967 }
3968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3969 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3970
3971 /*
3972 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3973 * class code. Fix it.
3974 */
3975 static void quirk_tw686x_class(struct pci_dev *pdev)
3976 {
3977 u32 class = pdev->class;
3978
3979 /* Use "Multimedia controller" class */
3980 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3981 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3982 class, pdev->class);
3983 }
3984 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3985 quirk_tw686x_class);
3986 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3987 quirk_tw686x_class);
3988 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3989 quirk_tw686x_class);
3990 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3991 quirk_tw686x_class);
3992
3993 /*
3994 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3995 * values for the Attribute as were supplied in the header of the
3996 * corresponding Request, except as explicitly allowed when IDO is used."
3997 *
3998 * If a non-compliant device generates a completion with a different
3999 * attribute than the request, the receiver may accept it (which itself
4000 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4001 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4002 * device access timeout.
4003 *
4004 * If the non-compliant device generates completions with zero attributes
4005 * (instead of copying the attributes from the request), we can work around
4006 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4007 * upstream devices so they always generate requests with zero attributes.
4008 *
4009 * This affects other devices under the same Root Port, but since these
4010 * attributes are performance hints, there should be no functional problem.
4011 *
4012 * Note that Configuration Space accesses are never supposed to have TLP
4013 * Attributes, so we're safe waiting till after any Configuration Space
4014 * accesses to do the Root Port fixup.
4015 */
4016 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4017 {
4018 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4019
4020 if (!root_port) {
4021 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4022 return;
4023 }
4024
4025 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4026 dev_name(&pdev->dev));
4027 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4028 PCI_EXP_DEVCTL_RELAX_EN |
4029 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4030 }
4031
4032 /*
4033 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4034 * Completion it generates.
4035 */
4036 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4037 {
4038 /*
4039 * This mask/compare operation selects for Physical Function 4 on a
4040 * T5. We only need to fix up the Root Port once for any of the
4041 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4042 * 0x54xx so we use that one,
4043 */
4044 if ((pdev->device & 0xff00) == 0x5400)
4045 quirk_disable_root_port_attributes(pdev);
4046 }
4047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4048 quirk_chelsio_T5_disable_root_port_attributes);
4049
4050 /*
4051 * AMD has indicated that the devices below do not support peer-to-peer
4052 * in any system where they are found in the southbridge with an AMD
4053 * IOMMU in the system. Multifunction devices that do not support
4054 * peer-to-peer between functions can claim to support a subset of ACS.
4055 * Such devices effectively enable request redirect (RR) and completion
4056 * redirect (CR) since all transactions are redirected to the upstream
4057 * root complex.
4058 *
4059 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4060 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4061 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4062 *
4063 * 1002:4385 SBx00 SMBus Controller
4064 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4065 * 1002:4383 SBx00 Azalia (Intel HDA)
4066 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4067 * 1002:4384 SBx00 PCI to PCI Bridge
4068 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4069 *
4070 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4071 *
4072 * 1022:780f [AMD] FCH PCI Bridge
4073 * 1022:7809 [AMD] FCH USB OHCI Controller
4074 */
4075 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4076 {
4077 #ifdef CONFIG_ACPI
4078 struct acpi_table_header *header = NULL;
4079 acpi_status status;
4080
4081 /* Targeting multifunction devices on the SB (appears on root bus) */
4082 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4083 return -ENODEV;
4084
4085 /* The IVRS table describes the AMD IOMMU */
4086 status = acpi_get_table("IVRS", 0, &header);
4087 if (ACPI_FAILURE(status))
4088 return -ENODEV;
4089
4090 /* Filter out flags not applicable to multifunction */
4091 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4092
4093 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4094 #else
4095 return -ENODEV;
4096 #endif
4097 }
4098
4099 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4100 {
4101 /*
4102 * Cavium devices matching this quirk do not perform peer-to-peer
4103 * with other functions, allowing masking out these bits as if they
4104 * were unimplemented in the ACS capability.
4105 */
4106 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4107 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4108
4109 return acs_flags ? 0 : 1;
4110 }
4111
4112 /*
4113 * Many Intel PCH root ports do provide ACS-like features to disable peer
4114 * transactions and validate bus numbers in requests, but do not provide an
4115 * actual PCIe ACS capability. This is the list of device IDs known to fall
4116 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4117 */
4118 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4119 /* Ibexpeak PCH */
4120 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4121 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4122 /* Cougarpoint PCH */
4123 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4124 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4125 /* Pantherpoint PCH */
4126 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4127 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4128 /* Lynxpoint-H PCH */
4129 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4130 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4131 /* Lynxpoint-LP PCH */
4132 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4133 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4134 /* Wildcat PCH */
4135 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4136 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4137 /* Patsburg (X79) PCH */
4138 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4139 /* Wellsburg (X99) PCH */
4140 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4141 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4142 /* Lynx Point (9 series) PCH */
4143 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4144 };
4145
4146 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4147 {
4148 int i;
4149
4150 /* Filter out a few obvious non-matches first */
4151 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4152 return false;
4153
4154 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4155 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4156 return true;
4157
4158 return false;
4159 }
4160
4161 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4162
4163 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4164 {
4165 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4166 INTEL_PCH_ACS_FLAGS : 0;
4167
4168 if (!pci_quirk_intel_pch_acs_match(dev))
4169 return -ENOTTY;
4170
4171 return acs_flags & ~flags ? 0 : 1;
4172 }
4173
4174 /*
4175 * These QCOM root ports do provide ACS-like features to disable peer
4176 * transactions and validate bus numbers in requests, but do not provide an
4177 * actual PCIe ACS capability. Hardware supports source validation but it
4178 * will report the issue as Completer Abort instead of ACS Violation.
4179 * Hardware doesn't support peer-to-peer and each root port is a root
4180 * complex with unique segment numbers. It is not possible for one root
4181 * port to pass traffic to another root port. All PCIe transactions are
4182 * terminated inside the root port.
4183 */
4184 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4185 {
4186 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4187 int ret = acs_flags & ~flags ? 0 : 1;
4188
4189 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4190
4191 return ret;
4192 }
4193
4194 /*
4195 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4196 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4197 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4198 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4199 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4200 * control register is at offset 8 instead of 6 and we should probably use
4201 * dword accesses to them. This applies to the following PCI Device IDs, as
4202 * found in volume 1 of the datasheet[2]:
4203 *
4204 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4205 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4206 *
4207 * N.B. This doesn't fix what lspci shows.
4208 *
4209 * The 100 series chipset specification update includes this as errata #23[3].
4210 *
4211 * The 200 series chipset (Union Point) has the same bug according to the
4212 * specification update (Intel 200 Series Chipset Family Platform Controller
4213 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4214 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4215 * chipset include:
4216 *
4217 * 0xa290-0xa29f PCI Express Root port #{0-16}
4218 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4219 *
4220 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4221 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4222 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4223 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4224 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4225 */
4226 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4227 {
4228 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4229 return false;
4230
4231 switch (dev->device) {
4232 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4233 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4234 return true;
4235 }
4236
4237 return false;
4238 }
4239
4240 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4241
4242 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4243 {
4244 int pos;
4245 u32 cap, ctrl;
4246
4247 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4248 return -ENOTTY;
4249
4250 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4251 if (!pos)
4252 return -ENOTTY;
4253
4254 /* see pci_acs_flags_enabled() */
4255 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4256 acs_flags &= (cap | PCI_ACS_EC);
4257
4258 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4259
4260 return acs_flags & ~ctrl ? 0 : 1;
4261 }
4262
4263 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4264 {
4265 /*
4266 * SV, TB, and UF are not relevant to multifunction endpoints.
4267 *
4268 * Multifunction devices are only required to implement RR, CR, and DT
4269 * in their ACS capability if they support peer-to-peer transactions.
4270 * Devices matching this quirk have been verified by the vendor to not
4271 * perform peer-to-peer with other functions, allowing us to mask out
4272 * these bits as if they were unimplemented in the ACS capability.
4273 */
4274 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4275 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4276
4277 return acs_flags ? 0 : 1;
4278 }
4279
4280 static const struct pci_dev_acs_enabled {
4281 u16 vendor;
4282 u16 device;
4283 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4284 } pci_dev_acs_enabled[] = {
4285 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4286 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4287 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4288 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4289 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4290 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4291 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4292 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4293 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4294 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4295 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4296 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4297 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4298 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4299 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4300 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4301 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4302 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4303 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4304 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4305 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4306 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4307 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4308 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4309 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4310 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4311 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4312 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4313 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4314 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4315 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4316 /* 82580 */
4317 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4318 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4319 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4320 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4321 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4322 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4323 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4324 /* 82576 */
4325 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4326 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4327 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4328 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4329 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4330 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4331 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4332 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4333 /* 82575 */
4334 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4335 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4336 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4337 /* I350 */
4338 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4339 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4340 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4341 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4342 /* 82571 (Quads omitted due to non-ACS switch) */
4343 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4344 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4345 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4346 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4347 /* I219 */
4348 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4349 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4350 /* QCOM QDF2xxx root ports */
4351 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4352 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4353 /* Intel PCH root ports */
4354 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4355 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4356 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4357 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4358 /* Cavium ThunderX */
4359 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4360 { 0 }
4361 };
4362
4363 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4364 {
4365 const struct pci_dev_acs_enabled *i;
4366 int ret;
4367
4368 /*
4369 * Allow devices that do not expose standard PCIe ACS capabilities
4370 * or control to indicate their support here. Multi-function express
4371 * devices which do not allow internal peer-to-peer between functions,
4372 * but do not implement PCIe ACS may wish to return true here.
4373 */
4374 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4375 if ((i->vendor == dev->vendor ||
4376 i->vendor == (u16)PCI_ANY_ID) &&
4377 (i->device == dev->device ||
4378 i->device == (u16)PCI_ANY_ID)) {
4379 ret = i->acs_enabled(dev, acs_flags);
4380 if (ret >= 0)
4381 return ret;
4382 }
4383 }
4384
4385 return -ENOTTY;
4386 }
4387
4388 /* Config space offset of Root Complex Base Address register */
4389 #define INTEL_LPC_RCBA_REG 0xf0
4390 /* 31:14 RCBA address */
4391 #define INTEL_LPC_RCBA_MASK 0xffffc000
4392 /* RCBA Enable */
4393 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4394
4395 /* Backbone Scratch Pad Register */
4396 #define INTEL_BSPR_REG 0x1104
4397 /* Backbone Peer Non-Posted Disable */
4398 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4399 /* Backbone Peer Posted Disable */
4400 #define INTEL_BSPR_REG_BPPD (1 << 9)
4401
4402 /* Upstream Peer Decode Configuration Register */
4403 #define INTEL_UPDCR_REG 0x1114
4404 /* 5:0 Peer Decode Enable bits */
4405 #define INTEL_UPDCR_REG_MASK 0x3f
4406
4407 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4408 {
4409 u32 rcba, bspr, updcr;
4410 void __iomem *rcba_mem;
4411
4412 /*
4413 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4414 * are D28:F* and therefore get probed before LPC, thus we can't
4415 * use pci_get_slot/pci_read_config_dword here.
4416 */
4417 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4418 INTEL_LPC_RCBA_REG, &rcba);
4419 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4420 return -EINVAL;
4421
4422 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4423 PAGE_ALIGN(INTEL_UPDCR_REG));
4424 if (!rcba_mem)
4425 return -ENOMEM;
4426
4427 /*
4428 * The BSPR can disallow peer cycles, but it's set by soft strap and
4429 * therefore read-only. If both posted and non-posted peer cycles are
4430 * disallowed, we're ok. If either are allowed, then we need to use
4431 * the UPDCR to disable peer decodes for each port. This provides the
4432 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4433 */
4434 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4435 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4436 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4437 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4438 if (updcr & INTEL_UPDCR_REG_MASK) {
4439 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4440 updcr &= ~INTEL_UPDCR_REG_MASK;
4441 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4442 }
4443 }
4444
4445 iounmap(rcba_mem);
4446 return 0;
4447 }
4448
4449 /* Miscellaneous Port Configuration register */
4450 #define INTEL_MPC_REG 0xd8
4451 /* MPC: Invalid Receive Bus Number Check Enable */
4452 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4453
4454 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4455 {
4456 u32 mpc;
4457
4458 /*
4459 * When enabled, the IRBNCE bit of the MPC register enables the
4460 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4461 * ensures that requester IDs fall within the bus number range
4462 * of the bridge. Enable if not already.
4463 */
4464 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4465 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4466 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4467 mpc |= INTEL_MPC_REG_IRBNCE;
4468 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4469 }
4470 }
4471
4472 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4473 {
4474 if (!pci_quirk_intel_pch_acs_match(dev))
4475 return -ENOTTY;
4476
4477 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4478 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4479 return 0;
4480 }
4481
4482 pci_quirk_enable_intel_rp_mpc_acs(dev);
4483
4484 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4485
4486 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4487
4488 return 0;
4489 }
4490
4491 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4492 {
4493 int pos;
4494 u32 cap, ctrl;
4495
4496 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4497 return -ENOTTY;
4498
4499 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4500 if (!pos)
4501 return -ENOTTY;
4502
4503 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4504 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4505
4506 ctrl |= (cap & PCI_ACS_SV);
4507 ctrl |= (cap & PCI_ACS_RR);
4508 ctrl |= (cap & PCI_ACS_CR);
4509 ctrl |= (cap & PCI_ACS_UF);
4510
4511 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4512
4513 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4514
4515 return 0;
4516 }
4517
4518 static const struct pci_dev_enable_acs {
4519 u16 vendor;
4520 u16 device;
4521 int (*enable_acs)(struct pci_dev *dev);
4522 } pci_dev_enable_acs[] = {
4523 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4524 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4525 { 0 }
4526 };
4527
4528 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4529 {
4530 const struct pci_dev_enable_acs *i;
4531 int ret;
4532
4533 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4534 if ((i->vendor == dev->vendor ||
4535 i->vendor == (u16)PCI_ANY_ID) &&
4536 (i->device == dev->device ||
4537 i->device == (u16)PCI_ANY_ID)) {
4538 ret = i->enable_acs(dev);
4539 if (ret >= 0)
4540 return ret;
4541 }
4542 }
4543
4544 return -ENOTTY;
4545 }
4546
4547 /*
4548 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4549 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4550 * Next Capability pointer in the MSI Capability Structure should point to
4551 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4552 * the list.
4553 */
4554 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4555 {
4556 int pos, i = 0;
4557 u8 next_cap;
4558 u16 reg16, *cap;
4559 struct pci_cap_saved_state *state;
4560
4561 /* Bail if the hardware bug is fixed */
4562 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4563 return;
4564
4565 /* Bail if MSI Capability Structure is not found for some reason */
4566 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4567 if (!pos)
4568 return;
4569
4570 /*
4571 * Bail if Next Capability pointer in the MSI Capability Structure
4572 * is not the expected incorrect 0x00.
4573 */
4574 pci_read_config_byte(pdev, pos + 1, &next_cap);
4575 if (next_cap)
4576 return;
4577
4578 /*
4579 * PCIe Capability Structure is expected to be at 0x50 and should
4580 * terminate the list (Next Capability pointer is 0x00). Verify
4581 * Capability Id and Next Capability pointer is as expected.
4582 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4583 * to correctly set kernel data structures which have already been
4584 * set incorrectly due to the hardware bug.
4585 */
4586 pos = 0x50;
4587 pci_read_config_word(pdev, pos, &reg16);
4588 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4589 u32 status;
4590 #ifndef PCI_EXP_SAVE_REGS
4591 #define PCI_EXP_SAVE_REGS 7
4592 #endif
4593 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4594
4595 pdev->pcie_cap = pos;
4596 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4597 pdev->pcie_flags_reg = reg16;
4598 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4599 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4600
4601 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4602 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4603 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4604 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4605
4606 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4607 return;
4608
4609 /*
4610 * Save PCIE cap
4611 */
4612 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4613 if (!state)
4614 return;
4615
4616 state->cap.cap_nr = PCI_CAP_ID_EXP;
4617 state->cap.cap_extended = 0;
4618 state->cap.size = size;
4619 cap = (u16 *)&state->cap.data[0];
4620 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4621 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4622 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4623 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4624 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4625 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4626 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4627 hlist_add_head(&state->next, &pdev->saved_cap_space);
4628 }
4629 }
4630 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4631
4632 /*
4633 * VMD-enabled root ports will change the source ID for all messages
4634 * to the VMD device. Rather than doing device matching with the source
4635 * ID, the AER driver should traverse the child device tree, reading
4636 * AER registers to find the faulting device.
4637 */
4638 static void quirk_no_aersid(struct pci_dev *pdev)
4639 {
4640 /* VMD Domain */
4641 if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
4642 pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
4643 }
4644 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
4645 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
4646 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
4647 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
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