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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/efi/efi into...
[mirror_ubuntu-artful-kernel.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <asm/dma.h> /* isa_dma_bridge_buggy */
29 #include "pci.h"
30
31 /*
32 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
37 static void quirk_mmio_always_on(struct pci_dev *dev)
38 {
39 dev->mmio_always_on = 1;
40 }
41 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
43
44 /* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
48 static void quirk_mellanox_tavor(struct pci_dev *dev)
49 {
50 dev->broken_parity_status = 1; /* This device gives false positives */
51 }
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
54
55 /* Deal with broken BIOSes that neglect to enable passive release,
56 which can cause problems in combination with the 82441FX/PPro MTRRs */
57 static void quirk_passive_release(struct pci_dev *dev)
58 {
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
67 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
68 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72 }
73 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
75
76 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
78 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
81 chipset level fix */
82
83 static void quirk_isa_dma_hangs(struct pci_dev *dev)
84 {
85 if (!isa_dma_bridge_buggy) {
86 isa_dma_bridge_buggy = 1;
87 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
88 }
89 }
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
101
102 /*
103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
106 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
107 {
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119 }
120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122 /*
123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
125 static void quirk_nopcipci(struct pci_dev *dev)
126 {
127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131 }
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
134
135 static void quirk_nopciamd(struct pci_dev *dev)
136 {
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144 }
145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
146
147 /*
148 * Triton requires workarounds to be used by the drivers
149 */
150 static void quirk_triton(struct pci_dev *dev)
151 {
152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156 }
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
161
162 /*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172 static void quirk_vialatency(struct pci_dev *dev)
173 {
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p != NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p == NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214 exit:
215 pci_dev_put(p);
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220 /* Must restore this on a resume from RAM */
221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225 /*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228 static void quirk_viaetbf(struct pci_dev *dev)
229 {
230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234 }
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237 static void quirk_vsfx(struct pci_dev *dev)
238 {
239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243 }
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246 /*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252 static void quirk_alimagik(struct pci_dev *dev)
253 {
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258 }
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262 /*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266 static void quirk_natoma(struct pci_dev *dev)
267 {
268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272 }
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280 /*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284 static void quirk_citrine(struct pci_dev *dev)
285 {
286 dev->cfg_size = 0xA0;
287 }
288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290 /*
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
293 */
294 static void quirk_nfp6000(struct pci_dev *dev)
295 {
296 dev->cfg_size = 0x600;
297 }
298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
301
302 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
303 static void quirk_extend_bar_to_page(struct pci_dev *dev)
304 {
305 int i;
306
307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
308 struct resource *r = &dev->resource[i];
309
310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
311 r->end = PAGE_SIZE - 1;
312 r->start = 0;
313 r->flags |= IORESOURCE_UNSET;
314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
315 i, r);
316 }
317 }
318 }
319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
320
321 /*
322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
323 * If it's needed, re-allocate the region.
324 */
325 static void quirk_s3_64M(struct pci_dev *dev)
326 {
327 struct resource *r = &dev->resource[0];
328
329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
330 r->flags |= IORESOURCE_UNSET;
331 r->start = 0;
332 r->end = 0x3ffffff;
333 }
334 }
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
337
338 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
339 const char *name)
340 {
341 u32 region;
342 struct pci_bus_region bus_region;
343 struct resource *res = dev->resource + pos;
344
345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
346
347 if (!region)
348 return;
349
350 res->name = pci_name(dev);
351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
352 res->flags |=
353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
354 region &= ~(size - 1);
355
356 /* Convert from PCI bus to resource space */
357 bus_region.start = region;
358 bus_region.end = region + size - 1;
359 pcibios_bus_to_resource(dev->bus, res, &bus_region);
360
361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
363 }
364
365 /*
366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
369 * (which conflicts w/ BAR1's memory range).
370 *
371 * CS553x's ISA PCI BARs may also be read-only (ref:
372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
373 */
374 static void quirk_cs5536_vsa(struct pci_dev *dev)
375 {
376 static char *name = "CS5536 ISA bridge";
377
378 if (pci_resource_len(dev, 0) != 8) {
379 quirk_io(dev, 0, 8, name); /* SMB */
380 quirk_io(dev, 1, 256, name); /* GPIO */
381 quirk_io(dev, 2, 64, name); /* MFGPT */
382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
383 name);
384 }
385 }
386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
387
388 static void quirk_io_region(struct pci_dev *dev, int port,
389 unsigned size, int nr, const char *name)
390 {
391 u16 region;
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
394
395 pci_read_config_word(dev, port, &region);
396 region &= ~(size - 1);
397
398 if (!region)
399 return;
400
401 res->name = pci_name(dev);
402 res->flags = IORESOURCE_IO;
403
404 /* Convert from PCI bus to resource space */
405 bus_region.start = region;
406 bus_region.end = region + size - 1;
407 pcibios_bus_to_resource(dev->bus, res, &bus_region);
408
409 if (!pci_claim_resource(dev, nr))
410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
411 }
412
413 /*
414 * ATI Northbridge setups MCE the processor if you even
415 * read somewhere between 0x3b0->0x3bb or read 0x3d3
416 */
417 static void quirk_ati_exploding_mce(struct pci_dev *dev)
418 {
419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
421 request_region(0x3b0, 0x0C, "RadeonIGP");
422 request_region(0x3d3, 0x01, "RadeonIGP");
423 }
424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
425
426 /*
427 * In the AMD NL platform, this device ([1022:7912]) has a class code of
428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
429 * claim it.
430 * But the dwc3 driver is a more specific driver for this device, and we'd
431 * prefer to use it instead of xhci. To prevent xhci from claiming the
432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
433 * defines as "USB device (not host controller)". The dwc3 driver can then
434 * claim it based on its Vendor and Device ID.
435 */
436 static void quirk_amd_nl_class(struct pci_dev *pdev)
437 {
438 u32 class = pdev->class;
439
440 /* Use "USB Device (not host controller)" class */
441 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
443 class, pdev->class);
444 }
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
446 quirk_amd_nl_class);
447
448 /*
449 * Let's make the southbridge information explicit instead
450 * of having to worry about people probing the ACPI areas,
451 * for example.. (Yes, it happens, and if you read the wrong
452 * ACPI register it will put the machine to sleep with no
453 * way of waking it up again. Bummer).
454 *
455 * ALI M7101: Two IO regions pointed to by words at
456 * 0xE0 (64 bytes of ACPI registers)
457 * 0xE2 (32 bytes of SMB registers)
458 */
459 static void quirk_ali7101_acpi(struct pci_dev *dev)
460 {
461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
463 }
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
465
466 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
467 {
468 u32 devres;
469 u32 mask, size, base;
470
471 pci_read_config_dword(dev, port, &devres);
472 if ((devres & enable) != enable)
473 return;
474 mask = (devres >> 16) & 15;
475 base = devres & 0xffff;
476 size = 16;
477 for (;;) {
478 unsigned bit = size >> 1;
479 if ((bit & mask) == bit)
480 break;
481 size = bit;
482 }
483 /*
484 * For now we only print it out. Eventually we'll want to
485 * reserve it (at least if it's in the 0x1000+ range), but
486 * let's get enough confirmation reports first.
487 */
488 base &= -size;
489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
490 base + size - 1);
491 }
492
493 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
494 {
495 u32 devres;
496 u32 mask, size, base;
497
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
500 return;
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
503 size = 128 << 16;
504 for (;;) {
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
507 break;
508 size = bit;
509 }
510 /*
511 * For now we only print it out. Eventually we'll want to
512 * reserve it, but let's get enough confirmation reports first.
513 */
514 base &= -size;
515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
516 base + size - 1);
517 }
518
519 /*
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
522 * 0x90 (16 bytes of SMB registers)
523 * and a few strange programmable PIIX4 device resources.
524 */
525 static void quirk_piix4_acpi(struct pci_dev *dev)
526 {
527 u32 res_a;
528
529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
531
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538 /* Device resource D is just bitfields for static resources */
539
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
552 }
553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
555
556 #define ICH_PMBASE 0x40
557 #define ICH_ACPI_CNTL 0x44
558 #define ICH4_ACPI_EN 0x10
559 #define ICH6_ACPI_EN 0x80
560 #define ICH4_GPIOBASE 0x58
561 #define ICH4_GPIO_CNTL 0x5c
562 #define ICH4_GPIO_EN 0x10
563 #define ICH6_GPIOBASE 0x48
564 #define ICH6_GPIO_CNTL 0x4c
565 #define ICH6_GPIO_EN 0x10
566
567 /*
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
571 */
572 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
573 {
574 u8 enable;
575
576 /*
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
581 * BIOSes.
582 */
583
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
588
589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
593 }
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
604
605 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
606 {
607 u8 enable;
608
609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
613
614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
618 }
619
620 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
621 {
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627 /* Enabled? */
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632 /*
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
635 *
636 * But this gets us at least _part_ of it.
637 */
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644 /* Just print it out for now. We should reserve it after more debugging */
645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646 }
647
648 static void quirk_ich6_lpc(struct pci_dev *dev)
649 {
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
652
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656 }
657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
660 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
661 {
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667 /* Enabled? */
668 if (!(val & 1))
669 return;
670
671 /*
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679 /* Just print it out for now. We should reserve it after more debugging */
680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681 }
682
683 /* ICH7-10 has the same common LPC generic IO decode registers */
684 static void quirk_ich7_lpc(struct pci_dev *dev)
685 {
686 /* We share the common ACPI/GPIO decode with ICH6 */
687 ich6_lpc_acpi_gpio(dev);
688
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694 }
695 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
708
709 /*
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
712 */
713 static void quirk_vt82c586_acpi(struct pci_dev *dev)
714 {
715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
718 }
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
720
721 /*
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
726 */
727 static void quirk_vt82c686_acpi(struct pci_dev *dev)
728 {
729 quirk_vt82c586_acpi(dev);
730
731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
733
734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
735 }
736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
737
738 /*
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
742 */
743 static void quirk_vt8235_acpi(struct pci_dev *dev)
744 {
745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
747 }
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
750 /*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
753 */
754 static void quirk_xio2000a(struct pci_dev *dev)
755 {
756 struct pci_dev *pdev;
757 u16 command;
758
759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765 }
766 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
768
769 #ifdef CONFIG_X86_IO_APIC
770
771 #include <asm/io_apic.h>
772
773 /*
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
776 *
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
779 */
780 static void quirk_via_ioapic(struct pci_dev *dev)
781 {
782 u8 tmp;
783
784 if (nr_ioapics < 1)
785 tmp = 0; /* nothing routed to external APIC */
786 else
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
788
789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
790 tmp == 0 ? "Disa" : "Ena");
791
792 /* Offset 0x58: External APIC IRQ output control */
793 pci_write_config_byte(dev, 0x58, tmp);
794 }
795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
797
798 /*
799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
803 */
804 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
805 {
806 u8 misc_control2;
807 #define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814 }
815 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
817
818 /*
819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
822 *
823 * We have multiple reports of hangs with this chipset that went away with
824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
825 * of course. However the advice is demonstrably good even if so..
826 */
827 static void quirk_amd_ioapic(struct pci_dev *dev)
828 {
829 if (dev->revision >= 0x02) {
830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
832 }
833 }
834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
835 #endif /* CONFIG_X86_IO_APIC */
836
837 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
838
839 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
840 {
841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
842 if (dev->subsystem_device == 0xa118)
843 dev->sriov->link = dev->devfn;
844 }
845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
846 #endif
847
848 /*
849 * Some settings of MMRBC can lead to data corruption so block changes.
850 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
851 */
852 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
853 {
854 if (dev->subordinate && dev->revision <= 0x12) {
855 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
856 dev->revision);
857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
858 }
859 }
860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
861
862 /*
863 * FIXME: it is questionable that quirk_via_acpi
864 * is needed. It shows up as an ISA bridge, and does not
865 * support the PCI_INTERRUPT_LINE register at all. Therefore
866 * it seems like setting the pci_dev's 'irq' to the
867 * value of the ACPI SCI interrupt is only done for convenience.
868 * -jgarzik
869 */
870 static void quirk_via_acpi(struct pci_dev *d)
871 {
872 /*
873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
874 */
875 u8 irq;
876 pci_read_config_byte(d, 0x42, &irq);
877 irq &= 0xf;
878 if (irq && (irq != 2))
879 d->irq = irq;
880 }
881 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
882 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
883
884
885 /*
886 * VIA bridges which have VLink
887 */
888
889 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
890
891 static void quirk_via_bridge(struct pci_dev *dev)
892 {
893 /* See what bridge we have and find the device ranges */
894 switch (dev->device) {
895 case PCI_DEVICE_ID_VIA_82C686:
896 /* The VT82C686 is special, it attaches to PCI and can have
897 any device number. All its subdevices are functions of
898 that single device. */
899 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
900 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
901 break;
902 case PCI_DEVICE_ID_VIA_8237:
903 case PCI_DEVICE_ID_VIA_8237A:
904 via_vlink_dev_lo = 15;
905 break;
906 case PCI_DEVICE_ID_VIA_8235:
907 via_vlink_dev_lo = 16;
908 break;
909 case PCI_DEVICE_ID_VIA_8231:
910 case PCI_DEVICE_ID_VIA_8233_0:
911 case PCI_DEVICE_ID_VIA_8233A:
912 case PCI_DEVICE_ID_VIA_8233C_0:
913 via_vlink_dev_lo = 17;
914 break;
915 }
916 }
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
925
926 /**
927 * quirk_via_vlink - VIA VLink IRQ number update
928 * @dev: PCI device
929 *
930 * If the device we are dealing with is on a PIC IRQ we need to
931 * ensure that the IRQ line register which usually is not relevant
932 * for PCI cards, is actually written so that interrupts get sent
933 * to the right place.
934 * We only do this on systems where a VIA south bridge was detected,
935 * and only for VIA devices on the motherboard (see quirk_via_bridge
936 * above).
937 */
938
939 static void quirk_via_vlink(struct pci_dev *dev)
940 {
941 u8 irq, new_irq;
942
943 /* Check if we have VLink at all */
944 if (via_vlink_dev_lo == -1)
945 return;
946
947 new_irq = dev->irq;
948
949 /* Don't quirk interrupts outside the legacy IRQ range */
950 if (!new_irq || new_irq > 15)
951 return;
952
953 /* Internal device ? */
954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
956 return;
957
958 /* This is an internal VLink device on a PIC interrupt. The BIOS
959 ought to have set this but may not have, so we redo it */
960
961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
962 if (new_irq != irq) {
963 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
964 irq, new_irq);
965 udelay(15); /* unknown if delay really needed */
966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
967 }
968 }
969 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
970
971 /*
972 * VIA VT82C598 has its device ID settable and many BIOSes
973 * set it to the ID of VT82C597 for backward compatibility.
974 * We need to switch it off to be able to recognize the real
975 * type of the chip.
976 */
977 static void quirk_vt82c598_id(struct pci_dev *dev)
978 {
979 pci_write_config_byte(dev, 0xfc, 0);
980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
981 }
982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
983
984 /*
985 * CardBus controllers have a legacy base address that enables them
986 * to respond as i82365 pcmcia controllers. We don't want them to
987 * do this even if the Linux CardBus driver is not loaded, because
988 * the Linux i82365 driver does not (and should not) handle CardBus.
989 */
990 static void quirk_cardbus_legacy(struct pci_dev *dev)
991 {
992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
993 }
994 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
996 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
998
999 /*
1000 * Following the PCI ordering rules is optional on the AMD762. I'm not
1001 * sure what the designers were smoking but let's not inhale...
1002 *
1003 * To be fair to AMD, it follows the spec by default, its BIOS people
1004 * who turn it off!
1005 */
1006 static void quirk_amd_ordering(struct pci_dev *dev)
1007 {
1008 u32 pcic;
1009 pci_read_config_dword(dev, 0x4C, &pcic);
1010 if ((pcic & 6) != 6) {
1011 pcic |= 6;
1012 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1013 pci_write_config_dword(dev, 0x4C, pcic);
1014 pci_read_config_dword(dev, 0x84, &pcic);
1015 pcic |= (1 << 23); /* Required in this mode */
1016 pci_write_config_dword(dev, 0x84, pcic);
1017 }
1018 }
1019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1021
1022 /*
1023 * DreamWorks provided workaround for Dunord I-3000 problem
1024 *
1025 * This card decodes and responds to addresses not apparently
1026 * assigned to it. We force a larger allocation to ensure that
1027 * nothing gets put too close to it.
1028 */
1029 static void quirk_dunord(struct pci_dev *dev)
1030 {
1031 struct resource *r = &dev->resource[1];
1032
1033 r->flags |= IORESOURCE_UNSET;
1034 r->start = 0;
1035 r->end = 0xffffff;
1036 }
1037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1038
1039 /*
1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1041 * is subtractive decoding (transparent), and does indicate this
1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1043 * instead of 0x01.
1044 */
1045 static void quirk_transparent_bridge(struct pci_dev *dev)
1046 {
1047 dev->transparent = 1;
1048 }
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1050 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1051
1052 /*
1053 * Common misconfiguration of the MediaGX/Geode PCI master that will
1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1055 * datasheets found at http://www.national.com/analog for info on what
1056 * these bits do. <christer@weinigel.se>
1057 */
1058 static void quirk_mediagx_master(struct pci_dev *dev)
1059 {
1060 u8 reg;
1061
1062 pci_read_config_byte(dev, 0x41, &reg);
1063 if (reg & 2) {
1064 reg &= ~2;
1065 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1066 reg);
1067 pci_write_config_byte(dev, 0x41, reg);
1068 }
1069 }
1070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1071 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1072
1073 /*
1074 * Ensure C0 rev restreaming is off. This is normally done by
1075 * the BIOS but in the odd case it is not the results are corruption
1076 * hence the presence of a Linux check
1077 */
1078 static void quirk_disable_pxb(struct pci_dev *pdev)
1079 {
1080 u16 config;
1081
1082 if (pdev->revision != 0x04) /* Only C0 requires this */
1083 return;
1084 pci_read_config_word(pdev, 0x40, &config);
1085 if (config & (1<<6)) {
1086 config &= ~(1<<6);
1087 pci_write_config_word(pdev, 0x40, config);
1088 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1089 }
1090 }
1091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1092 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1093
1094 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1095 {
1096 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1097 u8 tmp;
1098
1099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1100 if (tmp == 0x01) {
1101 pci_read_config_byte(pdev, 0x40, &tmp);
1102 pci_write_config_byte(pdev, 0x40, tmp|1);
1103 pci_write_config_byte(pdev, 0x9, 1);
1104 pci_write_config_byte(pdev, 0xa, 6);
1105 pci_write_config_byte(pdev, 0x40, tmp);
1106
1107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1108 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1109 }
1110 }
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1112 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1119
1120 /*
1121 * Serverworks CSB5 IDE does not fully support native mode
1122 */
1123 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1124 {
1125 u8 prog;
1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1127 if (prog & 5) {
1128 prog &= ~5;
1129 pdev->class &= ~5;
1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1131 /* PCI layer will sort out resources */
1132 }
1133 }
1134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1135
1136 /*
1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1138 */
1139 static void quirk_ide_samemode(struct pci_dev *pdev)
1140 {
1141 u8 prog;
1142
1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1144
1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1146 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1147 prog &= ~5;
1148 pdev->class &= ~5;
1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1150 }
1151 }
1152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1153
1154 /*
1155 * Some ATA devices break if put into D3
1156 */
1157
1158 static void quirk_no_ata_d3(struct pci_dev *pdev)
1159 {
1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1161 }
1162 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1163 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1167 /* ALi loses some register settings that we cannot then restore */
1168 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1170 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1171 occur when mode detecting */
1172 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1174
1175 /* This was originally an Alpha specific thing, but it really fits here.
1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1177 */
1178 static void quirk_eisa_bridge(struct pci_dev *dev)
1179 {
1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1181 }
1182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1183
1184
1185 /*
1186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1187 * is not activated. The myth is that Asus said that they do not want the
1188 * users to be irritated by just another PCI Device in the Win98 device
1189 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1190 * package 2.7.0 for details)
1191 *
1192 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1193 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1194 * becomes necessary to do this tweak in two steps -- the chosen trigger
1195 * is either the Host bridge (preferred) or on-board VGA controller.
1196 *
1197 * Note that we used to unhide the SMBus that way on Toshiba laptops
1198 * (Satellite A40 and Tecra M2) but then found that the thermal management
1199 * was done by SMM code, which could cause unsynchronized concurrent
1200 * accesses to the SMBus registers, with potentially bad effects. Thus you
1201 * should be very careful when adding new entries: if SMM is accessing the
1202 * Intel SMBus, this is a very good reason to leave it hidden.
1203 *
1204 * Likewise, many recent laptops use ACPI for thermal management. If the
1205 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1206 * natively, and keeping the SMBus hidden is the right thing to do. If you
1207 * are about to add an entry in the table below, please first disassemble
1208 * the DSDT and double-check that there is no code accessing the SMBus.
1209 */
1210 static int asus_hides_smbus;
1211
1212 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1213 {
1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1216 switch (dev->subsystem_device) {
1217 case 0x8025: /* P4B-LX */
1218 case 0x8070: /* P4B */
1219 case 0x8088: /* P4B533 */
1220 case 0x1626: /* L3C notebook */
1221 asus_hides_smbus = 1;
1222 }
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1224 switch (dev->subsystem_device) {
1225 case 0x80b1: /* P4GE-V */
1226 case 0x80b2: /* P4PE */
1227 case 0x8093: /* P4B533-V */
1228 asus_hides_smbus = 1;
1229 }
1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1231 switch (dev->subsystem_device) {
1232 case 0x8030: /* P4T533 */
1233 asus_hides_smbus = 1;
1234 }
1235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1236 switch (dev->subsystem_device) {
1237 case 0x8070: /* P4G8X Deluxe */
1238 asus_hides_smbus = 1;
1239 }
1240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1241 switch (dev->subsystem_device) {
1242 case 0x80c9: /* PU-DLS */
1243 asus_hides_smbus = 1;
1244 }
1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1246 switch (dev->subsystem_device) {
1247 case 0x1751: /* M2N notebook */
1248 case 0x1821: /* M5N notebook */
1249 case 0x1897: /* A6L notebook */
1250 asus_hides_smbus = 1;
1251 }
1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1253 switch (dev->subsystem_device) {
1254 case 0x184b: /* W1N notebook */
1255 case 0x186a: /* M6Ne notebook */
1256 asus_hides_smbus = 1;
1257 }
1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1259 switch (dev->subsystem_device) {
1260 case 0x80f2: /* P4P800-X */
1261 asus_hides_smbus = 1;
1262 }
1263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1264 switch (dev->subsystem_device) {
1265 case 0x1882: /* M6V notebook */
1266 case 0x1977: /* A6VA notebook */
1267 asus_hides_smbus = 1;
1268 }
1269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1271 switch (dev->subsystem_device) {
1272 case 0x088C: /* HP Compaq nc8000 */
1273 case 0x0890: /* HP Compaq nc6000 */
1274 asus_hides_smbus = 1;
1275 }
1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1277 switch (dev->subsystem_device) {
1278 case 0x12bc: /* HP D330L */
1279 case 0x12bd: /* HP D530 */
1280 case 0x006a: /* HP Compaq nx9500 */
1281 asus_hides_smbus = 1;
1282 }
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x12bf: /* HP xw4100 */
1286 asus_hides_smbus = 1;
1287 }
1288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1290 switch (dev->subsystem_device) {
1291 case 0xC00C: /* Samsung P35 notebook */
1292 asus_hides_smbus = 1;
1293 }
1294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1296 switch (dev->subsystem_device) {
1297 case 0x0058: /* Compaq Evo N620c */
1298 asus_hides_smbus = 1;
1299 }
1300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1301 switch (dev->subsystem_device) {
1302 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1303 /* Motherboard doesn't have Host bridge
1304 * subvendor/subdevice IDs, therefore checking
1305 * its on-board VGA controller */
1306 asus_hides_smbus = 1;
1307 }
1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1309 switch (dev->subsystem_device) {
1310 case 0x00b8: /* Compaq Evo D510 CMT */
1311 case 0x00b9: /* Compaq Evo D510 SFF */
1312 case 0x00ba: /* Compaq Evo D510 USDT */
1313 /* Motherboard doesn't have Host bridge
1314 * subvendor/subdevice IDs and on-board VGA
1315 * controller is disabled if an AGP card is
1316 * inserted, therefore checking USB UHCI
1317 * Controller #1 */
1318 asus_hides_smbus = 1;
1319 }
1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1321 switch (dev->subsystem_device) {
1322 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1323 /* Motherboard doesn't have host bridge
1324 * subvendor/subdevice IDs, therefore checking
1325 * its on-board VGA controller */
1326 asus_hides_smbus = 1;
1327 }
1328 }
1329 }
1330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1340
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1344
1345 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1346 {
1347 u16 val;
1348
1349 if (likely(!asus_hides_smbus))
1350 return;
1351
1352 pci_read_config_word(dev, 0xF2, &val);
1353 if (val & 0x8) {
1354 pci_write_config_word(dev, 0xF2, val & (~0x8));
1355 pci_read_config_word(dev, 0xF2, &val);
1356 if (val & 0x8)
1357 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1358 val);
1359 else
1360 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1361 }
1362 }
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1370 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1371 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1377
1378 /* It appears we just have one such device. If not, we have a warning */
1379 static void __iomem *asus_rcba_base;
1380 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1381 {
1382 u32 rcba;
1383
1384 if (likely(!asus_hides_smbus))
1385 return;
1386 WARN_ON(asus_rcba_base);
1387
1388 pci_read_config_dword(dev, 0xF0, &rcba);
1389 /* use bits 31:14, 16 kB aligned */
1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1391 if (asus_rcba_base == NULL)
1392 return;
1393 }
1394
1395 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1396 {
1397 u32 val;
1398
1399 if (likely(!asus_hides_smbus || !asus_rcba_base))
1400 return;
1401 /* read the Function Disable register, dword mode only */
1402 val = readl(asus_rcba_base + 0x3418);
1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1404 }
1405
1406 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1407 {
1408 if (likely(!asus_hides_smbus || !asus_rcba_base))
1409 return;
1410 iounmap(asus_rcba_base);
1411 asus_rcba_base = NULL;
1412 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1413 }
1414
1415 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1416 {
1417 asus_hides_smbus_lpc_ich6_suspend(dev);
1418 asus_hides_smbus_lpc_ich6_resume_early(dev);
1419 asus_hides_smbus_lpc_ich6_resume(dev);
1420 }
1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1422 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1423 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1425
1426 /*
1427 * SiS 96x south bridge: BIOS typically hides SMBus device...
1428 */
1429 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1430 {
1431 u8 val = 0;
1432 pci_read_config_byte(dev, 0x77, &val);
1433 if (val & 0x10) {
1434 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1435 pci_write_config_byte(dev, 0x77, val & ~0x10);
1436 }
1437 }
1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1442 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1443 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1446
1447 /*
1448 * ... This is further complicated by the fact that some SiS96x south
1449 * bridges pretend to be 85C503/5513 instead. In that case see if we
1450 * spotted a compatible north bridge to make sure.
1451 * (pci_find_device doesn't work yet)
1452 *
1453 * We can also enable the sis96x bit in the discovery register..
1454 */
1455 #define SIS_DETECT_REGISTER 0x40
1456
1457 static void quirk_sis_503(struct pci_dev *dev)
1458 {
1459 u8 reg;
1460 u16 devid;
1461
1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1467 return;
1468 }
1469
1470 /*
1471 * Ok, it now shows up as a 96x.. run the 96x quirk by
1472 * hand in case it has already been processed.
1473 * (depends on link order, which is apparently not guaranteed)
1474 */
1475 dev->device = devid;
1476 quirk_sis_96x_smbus(dev);
1477 }
1478 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1479 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1480
1481
1482 /*
1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1484 * and MC97 modem controller are disabled when a second PCI soundcard is
1485 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1486 * -- bjd
1487 */
1488 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1489 {
1490 u8 val;
1491 int asus_hides_ac97 = 0;
1492
1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1494 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1495 asus_hides_ac97 = 1;
1496 }
1497
1498 if (!asus_hides_ac97)
1499 return;
1500
1501 pci_read_config_byte(dev, 0x50, &val);
1502 if (val & 0xc0) {
1503 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1504 pci_read_config_byte(dev, 0x50, &val);
1505 if (val & 0xc0)
1506 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1507 val);
1508 else
1509 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1510 }
1511 }
1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1513 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1514
1515 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1516
1517 /*
1518 * If we are using libata we can drive this chip properly but must
1519 * do this early on to make the additional device appear during
1520 * the PCI scanning.
1521 */
1522 static void quirk_jmicron_ata(struct pci_dev *pdev)
1523 {
1524 u32 conf1, conf5, class;
1525 u8 hdr;
1526
1527 /* Only poke fn 0 */
1528 if (PCI_FUNC(pdev->devfn))
1529 return;
1530
1531 pci_read_config_dword(pdev, 0x40, &conf1);
1532 pci_read_config_dword(pdev, 0x80, &conf5);
1533
1534 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1535 conf5 &= ~(1 << 24); /* Clear bit 24 */
1536
1537 switch (pdev->device) {
1538 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1539 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1540 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1541 /* The controller should be in single function ahci mode */
1542 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1543 break;
1544
1545 case PCI_DEVICE_ID_JMICRON_JMB365:
1546 case PCI_DEVICE_ID_JMICRON_JMB366:
1547 /* Redirect IDE second PATA port to the right spot */
1548 conf5 |= (1 << 24);
1549 /* Fall through */
1550 case PCI_DEVICE_ID_JMICRON_JMB361:
1551 case PCI_DEVICE_ID_JMICRON_JMB363:
1552 case PCI_DEVICE_ID_JMICRON_JMB369:
1553 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1554 /* Set the class codes correctly and then direct IDE 0 */
1555 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1556 break;
1557
1558 case PCI_DEVICE_ID_JMICRON_JMB368:
1559 /* The controller should be in single function IDE mode */
1560 conf1 |= 0x00C00000; /* Set 22, 23 */
1561 break;
1562 }
1563
1564 pci_write_config_dword(pdev, 0x40, conf1);
1565 pci_write_config_dword(pdev, 0x80, conf5);
1566
1567 /* Update pdev accordingly */
1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1569 pdev->hdr_type = hdr & 0x7f;
1570 pdev->multifunction = !!(hdr & 0x80);
1571
1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1573 pdev->class = class >> 8;
1574 }
1575 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1576 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1584 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1585 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1593
1594 #endif
1595
1596 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1597 {
1598 if (dev->multifunction) {
1599 device_disable_async_suspend(&dev->dev);
1600 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1601 }
1602 }
1603 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1604 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1607
1608 #ifdef CONFIG_X86_IO_APIC
1609 static void quirk_alder_ioapic(struct pci_dev *pdev)
1610 {
1611 int i;
1612
1613 if ((pdev->class >> 8) != 0xff00)
1614 return;
1615
1616 /* the first BAR is the location of the IO APIC...we must
1617 * not touch this (and it's already covered by the fixmap), so
1618 * forcibly insert it into the resource tree */
1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1620 insert_resource(&iomem_resource, &pdev->resource[0]);
1621
1622 /* The next five BARs all seem to be rubbish, so just clean
1623 * them out */
1624 for (i = 1; i < 6; i++)
1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1626 }
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1628 #endif
1629
1630 static void quirk_pcie_mch(struct pci_dev *pdev)
1631 {
1632 pdev->no_msi = 1;
1633 }
1634 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
1638
1639
1640 /*
1641 * It's possible for the MSI to get corrupted if shpc and acpi
1642 * are used together on certain PXH-based systems.
1643 */
1644 static void quirk_pcie_pxh(struct pci_dev *dev)
1645 {
1646 dev->no_msi = 1;
1647 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1648 }
1649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1654
1655 /*
1656 * Some Intel PCI Express chipsets have trouble with downstream
1657 * device power management.
1658 */
1659 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1660 {
1661 pci_pm_d3_delay = 120;
1662 dev->no_d1d2 = 1;
1663 }
1664
1665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1686
1687 #ifdef CONFIG_X86_IO_APIC
1688 /*
1689 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1690 * remap the original interrupt in the linux kernel to the boot interrupt, so
1691 * that a PCI device's interrupt handler is installed on the boot interrupt
1692 * line instead.
1693 */
1694 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1695 {
1696 if (noioapicquirk || noioapicreroute)
1697 return;
1698
1699 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1700 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1701 dev->vendor, dev->device);
1702 }
1703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1711 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1712 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1713 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1714 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1715 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1716 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1717 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1718 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1719
1720 /*
1721 * On some chipsets we can disable the generation of legacy INTx boot
1722 * interrupts.
1723 */
1724
1725 /*
1726 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1727 * 300641-004US, section 5.7.3.
1728 */
1729 #define INTEL_6300_IOAPIC_ABAR 0x40
1730 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1731
1732 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1733 {
1734 u16 pci_config_word;
1735
1736 if (noioapicquirk)
1737 return;
1738
1739 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1740 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1741 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1742
1743 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1744 dev->vendor, dev->device);
1745 }
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1747 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1748
1749 /*
1750 * disable boot interrupts on HT-1000
1751 */
1752 #define BC_HT1000_FEATURE_REG 0x64
1753 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1754 #define BC_HT1000_MAP_IDX 0xC00
1755 #define BC_HT1000_MAP_DATA 0xC01
1756
1757 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1758 {
1759 u32 pci_config_dword;
1760 u8 irq;
1761
1762 if (noioapicquirk)
1763 return;
1764
1765 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1766 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1767 BC_HT1000_PIC_REGS_ENABLE);
1768
1769 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1770 outb(irq, BC_HT1000_MAP_IDX);
1771 outb(0x00, BC_HT1000_MAP_DATA);
1772 }
1773
1774 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1775
1776 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1777 dev->vendor, dev->device);
1778 }
1779 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1780 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1781
1782 /*
1783 * disable boot interrupts on AMD and ATI chipsets
1784 */
1785 /*
1786 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1787 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1788 * (due to an erratum).
1789 */
1790 #define AMD_813X_MISC 0x40
1791 #define AMD_813X_NOIOAMODE (1<<0)
1792 #define AMD_813X_REV_B1 0x12
1793 #define AMD_813X_REV_B2 0x13
1794
1795 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1796 {
1797 u32 pci_config_dword;
1798
1799 if (noioapicquirk)
1800 return;
1801 if ((dev->revision == AMD_813X_REV_B1) ||
1802 (dev->revision == AMD_813X_REV_B2))
1803 return;
1804
1805 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1806 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1807 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1808
1809 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1810 dev->vendor, dev->device);
1811 }
1812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1813 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1815 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1816
1817 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1818
1819 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1820 {
1821 u16 pci_config_word;
1822
1823 if (noioapicquirk)
1824 return;
1825
1826 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1827 if (!pci_config_word) {
1828 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1829 dev->vendor, dev->device);
1830 return;
1831 }
1832 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1833 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1834 dev->vendor, dev->device);
1835 }
1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1837 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1838 #endif /* CONFIG_X86_IO_APIC */
1839
1840 /*
1841 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1842 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1843 * Re-allocate the region if needed...
1844 */
1845 static void quirk_tc86c001_ide(struct pci_dev *dev)
1846 {
1847 struct resource *r = &dev->resource[0];
1848
1849 if (r->start & 0x8) {
1850 r->flags |= IORESOURCE_UNSET;
1851 r->start = 0;
1852 r->end = 0xf;
1853 }
1854 }
1855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1856 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1857 quirk_tc86c001_ide);
1858
1859 /*
1860 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1861 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1862 * being read correctly if bit 7 of the base address is set.
1863 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1864 * Re-allocate the regions to a 256-byte boundary if necessary.
1865 */
1866 static void quirk_plx_pci9050(struct pci_dev *dev)
1867 {
1868 unsigned int bar;
1869
1870 /* Fixed in revision 2 (PCI 9052). */
1871 if (dev->revision >= 2)
1872 return;
1873 for (bar = 0; bar <= 1; bar++)
1874 if (pci_resource_len(dev, bar) == 0x80 &&
1875 (pci_resource_start(dev, bar) & 0x80)) {
1876 struct resource *r = &dev->resource[bar];
1877 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1878 bar);
1879 r->flags |= IORESOURCE_UNSET;
1880 r->start = 0;
1881 r->end = 0xff;
1882 }
1883 }
1884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1885 quirk_plx_pci9050);
1886 /*
1887 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1888 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1889 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1890 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1891 *
1892 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1893 * driver.
1894 */
1895 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1896 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1897
1898 static void quirk_netmos(struct pci_dev *dev)
1899 {
1900 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1901 unsigned int num_serial = dev->subsystem_device & 0xf;
1902
1903 /*
1904 * These Netmos parts are multiport serial devices with optional
1905 * parallel ports. Even when parallel ports are present, they
1906 * are identified as class SERIAL, which means the serial driver
1907 * will claim them. To prevent this, mark them as class OTHER.
1908 * These combo devices should be claimed by parport_serial.
1909 *
1910 * The subdevice ID is of the form 0x00PS, where <P> is the number
1911 * of parallel ports and <S> is the number of serial ports.
1912 */
1913 switch (dev->device) {
1914 case PCI_DEVICE_ID_NETMOS_9835:
1915 /* Well, this rule doesn't hold for the following 9835 device */
1916 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1917 dev->subsystem_device == 0x0299)
1918 return;
1919 case PCI_DEVICE_ID_NETMOS_9735:
1920 case PCI_DEVICE_ID_NETMOS_9745:
1921 case PCI_DEVICE_ID_NETMOS_9845:
1922 case PCI_DEVICE_ID_NETMOS_9855:
1923 if (num_parallel) {
1924 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1925 dev->device, num_parallel, num_serial);
1926 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1927 (dev->class & 0xff);
1928 }
1929 }
1930 }
1931 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1932 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1933
1934 /*
1935 * Quirk non-zero PCI functions to route VPD access through function 0 for
1936 * devices that share VPD resources between functions. The functions are
1937 * expected to be identical devices.
1938 */
1939 static void quirk_f0_vpd_link(struct pci_dev *dev)
1940 {
1941 struct pci_dev *f0;
1942
1943 if (!PCI_FUNC(dev->devfn))
1944 return;
1945
1946 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1947 if (!f0)
1948 return;
1949
1950 if (f0->vpd && dev->class == f0->class &&
1951 dev->vendor == f0->vendor && dev->device == f0->device)
1952 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1953
1954 pci_dev_put(f0);
1955 }
1956 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1957 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1958
1959 static void quirk_e100_interrupt(struct pci_dev *dev)
1960 {
1961 u16 command, pmcsr;
1962 u8 __iomem *csr;
1963 u8 cmd_hi;
1964
1965 switch (dev->device) {
1966 /* PCI IDs taken from drivers/net/e100.c */
1967 case 0x1029:
1968 case 0x1030 ... 0x1034:
1969 case 0x1038 ... 0x103E:
1970 case 0x1050 ... 0x1057:
1971 case 0x1059:
1972 case 0x1064 ... 0x106B:
1973 case 0x1091 ... 0x1095:
1974 case 0x1209:
1975 case 0x1229:
1976 case 0x2449:
1977 case 0x2459:
1978 case 0x245D:
1979 case 0x27DC:
1980 break;
1981 default:
1982 return;
1983 }
1984
1985 /*
1986 * Some firmware hands off the e100 with interrupts enabled,
1987 * which can cause a flood of interrupts if packets are
1988 * received before the driver attaches to the device. So
1989 * disable all e100 interrupts here. The driver will
1990 * re-enable them when it's ready.
1991 */
1992 pci_read_config_word(dev, PCI_COMMAND, &command);
1993
1994 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1995 return;
1996
1997 /*
1998 * Check that the device is in the D0 power state. If it's not,
1999 * there is no point to look any further.
2000 */
2001 if (dev->pm_cap) {
2002 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2003 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2004 return;
2005 }
2006
2007 /* Convert from PCI bus to resource space. */
2008 csr = ioremap(pci_resource_start(dev, 0), 8);
2009 if (!csr) {
2010 dev_warn(&dev->dev, "Can't map e100 registers\n");
2011 return;
2012 }
2013
2014 cmd_hi = readb(csr + 3);
2015 if (cmd_hi == 0) {
2016 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2017 writeb(1, csr + 3);
2018 }
2019
2020 iounmap(csr);
2021 }
2022 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2023 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2024
2025 /*
2026 * The 82575 and 82598 may experience data corruption issues when transitioning
2027 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2028 */
2029 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2030 {
2031 dev_info(&dev->dev, "Disabling L0s\n");
2032 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2033 }
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2048
2049 static void fixup_rev1_53c810(struct pci_dev *dev)
2050 {
2051 u32 class = dev->class;
2052
2053 /*
2054 * rev 1 ncr53c810 chips don't set the class at all which means
2055 * they don't get their resources remapped. Fix that here.
2056 */
2057 if (class)
2058 return;
2059
2060 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2061 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2062 class, dev->class);
2063 }
2064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2065
2066 /* Enable 1k I/O space granularity on the Intel P64H2 */
2067 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2068 {
2069 u16 en1k;
2070
2071 pci_read_config_word(dev, 0x40, &en1k);
2072
2073 if (en1k & 0x200) {
2074 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2075 dev->io_window_1k = 1;
2076 }
2077 }
2078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2079
2080 /* Under some circumstances, AER is not linked with extended capabilities.
2081 * Force it to be linked by setting the corresponding control bit in the
2082 * config space.
2083 */
2084 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2085 {
2086 uint8_t b;
2087 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2088 if (!(b & 0x20)) {
2089 pci_write_config_byte(dev, 0xf41, b | 0x20);
2090 dev_info(&dev->dev, "Linking AER extended capability\n");
2091 }
2092 }
2093 }
2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2095 quirk_nvidia_ck804_pcie_aer_ext_cap);
2096 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2097 quirk_nvidia_ck804_pcie_aer_ext_cap);
2098
2099 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2100 {
2101 /*
2102 * Disable PCI Bus Parking and PCI Master read caching on CX700
2103 * which causes unspecified timing errors with a VT6212L on the PCI
2104 * bus leading to USB2.0 packet loss.
2105 *
2106 * This quirk is only enabled if a second (on the external PCI bus)
2107 * VT6212L is found -- the CX700 core itself also contains a USB
2108 * host controller with the same PCI ID as the VT6212L.
2109 */
2110
2111 /* Count VT6212L instances */
2112 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2113 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2114 uint8_t b;
2115
2116 /* p should contain the first (internal) VT6212L -- see if we have
2117 an external one by searching again */
2118 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2119 if (!p)
2120 return;
2121 pci_dev_put(p);
2122
2123 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2124 if (b & 0x40) {
2125 /* Turn off PCI Bus Parking */
2126 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2127
2128 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2129 }
2130 }
2131
2132 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2133 if (b != 0) {
2134 /* Turn off PCI Master read caching */
2135 pci_write_config_byte(dev, 0x72, 0x0);
2136
2137 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2138 pci_write_config_byte(dev, 0x75, 0x1);
2139
2140 /* Disable "Read FIFO Timer" */
2141 pci_write_config_byte(dev, 0x77, 0x0);
2142
2143 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2144 }
2145 }
2146 }
2147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2148
2149 /*
2150 * If a device follows the VPD format spec, the PCI core will not read or
2151 * write past the VPD End Tag. But some vendors do not follow the VPD
2152 * format spec, so we can't tell how much data is safe to access. Devices
2153 * may behave unpredictably if we access too much. Blacklist these devices
2154 * so we don't touch VPD at all.
2155 */
2156 static void quirk_blacklist_vpd(struct pci_dev *dev)
2157 {
2158 if (dev->vpd) {
2159 dev->vpd->len = 0;
2160 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2161 }
2162 }
2163
2164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2169 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2170 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2176 quirk_blacklist_vpd);
2177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2178
2179 /*
2180 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2181 * VPD end tag will hang the device. This problem was initially
2182 * observed when a vpd entry was created in sysfs
2183 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2184 * will dump 32k of data. Reading a full 32k will cause an access
2185 * beyond the VPD end tag causing the device to hang. Once the device
2186 * is hung, the bnx2 driver will not be able to reset the device.
2187 * We believe that it is legal to read beyond the end tag and
2188 * therefore the solution is to limit the read/write length.
2189 */
2190 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2191 {
2192 /*
2193 * Only disable the VPD capability for 5706, 5706S, 5708,
2194 * 5708S and 5709 rev. A
2195 */
2196 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2197 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2198 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2199 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2200 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2201 (dev->revision & 0xf0) == 0x0)) {
2202 if (dev->vpd)
2203 dev->vpd->len = 0x80;
2204 }
2205 }
2206
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2208 PCI_DEVICE_ID_NX2_5706,
2209 quirk_brcm_570x_limit_vpd);
2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2211 PCI_DEVICE_ID_NX2_5706S,
2212 quirk_brcm_570x_limit_vpd);
2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2214 PCI_DEVICE_ID_NX2_5708,
2215 quirk_brcm_570x_limit_vpd);
2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2217 PCI_DEVICE_ID_NX2_5708S,
2218 quirk_brcm_570x_limit_vpd);
2219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2220 PCI_DEVICE_ID_NX2_5709,
2221 quirk_brcm_570x_limit_vpd);
2222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2223 PCI_DEVICE_ID_NX2_5709S,
2224 quirk_brcm_570x_limit_vpd);
2225
2226 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2227 {
2228 u32 rev;
2229
2230 pci_read_config_dword(dev, 0xf4, &rev);
2231
2232 /* Only CAP the MRRS if the device is a 5719 A0 */
2233 if (rev == 0x05719000) {
2234 int readrq = pcie_get_readrq(dev);
2235 if (readrq > 2048)
2236 pcie_set_readrq(dev, 2048);
2237 }
2238 }
2239
2240 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2241 PCI_DEVICE_ID_TIGON3_5719,
2242 quirk_brcm_5719_limit_mrrs);
2243
2244 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2245 static void quirk_paxc_bridge(struct pci_dev *pdev)
2246 {
2247 /* The PCI config space is shared with the PAXC root port and the first
2248 * Ethernet device. So, we need to workaround this by telling the PCI
2249 * code that the bridge is not an Ethernet device.
2250 */
2251 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2252 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2253
2254 /* MPSS is not being set properly (as it is currently 0). This is
2255 * because that area of the PCI config space is hard coded to zero, and
2256 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2257 * so that the MPS can be set to the real max value.
2258 */
2259 pdev->pcie_mpss = 2;
2260 }
2261 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2262 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2263 #endif
2264
2265 /* Originally in EDAC sources for i82875P:
2266 * Intel tells BIOS developers to hide device 6 which
2267 * configures the overflow device access containing
2268 * the DRBs - this is where we expose device 6.
2269 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2270 */
2271 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2272 {
2273 u8 reg;
2274
2275 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2276 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2277 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2278 }
2279 }
2280
2281 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2282 quirk_unhide_mch_dev6);
2283 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2284 quirk_unhide_mch_dev6);
2285
2286 #ifdef CONFIG_TILEPRO
2287 /*
2288 * The Tilera TILEmpower tilepro platform needs to set the link speed
2289 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2290 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2291 * capability register of the PEX8624 PCIe switch. The switch
2292 * supports link speed auto negotiation, but falsely sets
2293 * the link speed to 5GT/s.
2294 */
2295 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2296 {
2297 if (tile_plx_gen1) {
2298 pci_write_config_dword(dev, 0x98, 0x1);
2299 mdelay(50);
2300 }
2301 }
2302 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2303 #endif /* CONFIG_TILEPRO */
2304
2305 #ifdef CONFIG_PCI_MSI
2306 /* Some chipsets do not support MSI. We cannot easily rely on setting
2307 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2308 * some other buses controlled by the chipset even if Linux is not
2309 * aware of it. Instead of setting the flag on all buses in the
2310 * machine, simply disable MSI globally.
2311 */
2312 static void quirk_disable_all_msi(struct pci_dev *dev)
2313 {
2314 pci_no_msi();
2315 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2316 }
2317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2325
2326 /* Disable MSI on chipsets that are known to not support it */
2327 static void quirk_disable_msi(struct pci_dev *dev)
2328 {
2329 if (dev->subordinate) {
2330 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2331 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2332 }
2333 }
2334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2337
2338 /*
2339 * The APC bridge device in AMD 780 family northbridges has some random
2340 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2341 * we use the possible vendor/device IDs of the host bridge for the
2342 * declared quirk, and search for the APC bridge by slot number.
2343 */
2344 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2345 {
2346 struct pci_dev *apc_bridge;
2347
2348 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2349 if (apc_bridge) {
2350 if (apc_bridge->device == 0x9602)
2351 quirk_disable_msi(apc_bridge);
2352 pci_dev_put(apc_bridge);
2353 }
2354 }
2355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2357
2358 /* Go through the list of Hypertransport capabilities and
2359 * return 1 if a HT MSI capability is found and enabled */
2360 static int msi_ht_cap_enabled(struct pci_dev *dev)
2361 {
2362 int pos, ttl = PCI_FIND_CAP_TTL;
2363
2364 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2365 while (pos && ttl--) {
2366 u8 flags;
2367
2368 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2369 &flags) == 0) {
2370 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2371 flags & HT_MSI_FLAGS_ENABLE ?
2372 "enabled" : "disabled");
2373 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2374 }
2375
2376 pos = pci_find_next_ht_capability(dev, pos,
2377 HT_CAPTYPE_MSI_MAPPING);
2378 }
2379 return 0;
2380 }
2381
2382 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2383 static void quirk_msi_ht_cap(struct pci_dev *dev)
2384 {
2385 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2386 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2387 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2388 }
2389 }
2390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2391 quirk_msi_ht_cap);
2392
2393 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2394 * MSI are supported if the MSI capability set in any of these mappings.
2395 */
2396 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2397 {
2398 struct pci_dev *pdev;
2399
2400 if (!dev->subordinate)
2401 return;
2402
2403 /* check HT MSI cap on this chipset and the root one.
2404 * a single one having MSI is enough to be sure that MSI are supported.
2405 */
2406 pdev = pci_get_slot(dev->bus, 0);
2407 if (!pdev)
2408 return;
2409 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2410 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2411 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2412 }
2413 pci_dev_put(pdev);
2414 }
2415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2416 quirk_nvidia_ck804_msi_ht_cap);
2417
2418 /* Force enable MSI mapping capability on HT bridges */
2419 static void ht_enable_msi_mapping(struct pci_dev *dev)
2420 {
2421 int pos, ttl = PCI_FIND_CAP_TTL;
2422
2423 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2424 while (pos && ttl--) {
2425 u8 flags;
2426
2427 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2428 &flags) == 0) {
2429 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2430
2431 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2432 flags | HT_MSI_FLAGS_ENABLE);
2433 }
2434 pos = pci_find_next_ht_capability(dev, pos,
2435 HT_CAPTYPE_MSI_MAPPING);
2436 }
2437 }
2438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2439 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2440 ht_enable_msi_mapping);
2441
2442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2443 ht_enable_msi_mapping);
2444
2445 /* The P5N32-SLI motherboards from Asus have a problem with msi
2446 * for the MCP55 NIC. It is not yet determined whether the msi problem
2447 * also affects other devices. As for now, turn off msi for this device.
2448 */
2449 static void nvenet_msi_disable(struct pci_dev *dev)
2450 {
2451 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2452
2453 if (board_name &&
2454 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2455 strstr(board_name, "P5N32-E SLI"))) {
2456 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2457 dev->no_msi = 1;
2458 }
2459 }
2460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2461 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2462 nvenet_msi_disable);
2463
2464 /*
2465 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2466 * config register. This register controls the routing of legacy
2467 * interrupts from devices that route through the MCP55. If this register
2468 * is misprogrammed, interrupts are only sent to the BSP, unlike
2469 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2470 * having this register set properly prevents kdump from booting up
2471 * properly, so let's make sure that we have it set correctly.
2472 * Note that this is an undocumented register.
2473 */
2474 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2475 {
2476 u32 cfg;
2477
2478 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2479 return;
2480
2481 pci_read_config_dword(dev, 0x74, &cfg);
2482
2483 if (cfg & ((1 << 2) | (1 << 15))) {
2484 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2485 cfg &= ~((1 << 2) | (1 << 15));
2486 pci_write_config_dword(dev, 0x74, cfg);
2487 }
2488 }
2489
2490 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2491 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2492 nvbridge_check_legacy_irq_routing);
2493
2494 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2495 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2496 nvbridge_check_legacy_irq_routing);
2497
2498 static int ht_check_msi_mapping(struct pci_dev *dev)
2499 {
2500 int pos, ttl = PCI_FIND_CAP_TTL;
2501 int found = 0;
2502
2503 /* check if there is HT MSI cap or enabled on this device */
2504 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2505 while (pos && ttl--) {
2506 u8 flags;
2507
2508 if (found < 1)
2509 found = 1;
2510 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2511 &flags) == 0) {
2512 if (flags & HT_MSI_FLAGS_ENABLE) {
2513 if (found < 2) {
2514 found = 2;
2515 break;
2516 }
2517 }
2518 }
2519 pos = pci_find_next_ht_capability(dev, pos,
2520 HT_CAPTYPE_MSI_MAPPING);
2521 }
2522
2523 return found;
2524 }
2525
2526 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2527 {
2528 struct pci_dev *dev;
2529 int pos;
2530 int i, dev_no;
2531 int found = 0;
2532
2533 dev_no = host_bridge->devfn >> 3;
2534 for (i = dev_no + 1; i < 0x20; i++) {
2535 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2536 if (!dev)
2537 continue;
2538
2539 /* found next host bridge ?*/
2540 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2541 if (pos != 0) {
2542 pci_dev_put(dev);
2543 break;
2544 }
2545
2546 if (ht_check_msi_mapping(dev)) {
2547 found = 1;
2548 pci_dev_put(dev);
2549 break;
2550 }
2551 pci_dev_put(dev);
2552 }
2553
2554 return found;
2555 }
2556
2557 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2558 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2559
2560 static int is_end_of_ht_chain(struct pci_dev *dev)
2561 {
2562 int pos, ctrl_off;
2563 int end = 0;
2564 u16 flags, ctrl;
2565
2566 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2567
2568 if (!pos)
2569 goto out;
2570
2571 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2572
2573 ctrl_off = ((flags >> 10) & 1) ?
2574 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2575 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2576
2577 if (ctrl & (1 << 6))
2578 end = 1;
2579
2580 out:
2581 return end;
2582 }
2583
2584 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2585 {
2586 struct pci_dev *host_bridge;
2587 int pos;
2588 int i, dev_no;
2589 int found = 0;
2590
2591 dev_no = dev->devfn >> 3;
2592 for (i = dev_no; i >= 0; i--) {
2593 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2594 if (!host_bridge)
2595 continue;
2596
2597 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2598 if (pos != 0) {
2599 found = 1;
2600 break;
2601 }
2602 pci_dev_put(host_bridge);
2603 }
2604
2605 if (!found)
2606 return;
2607
2608 /* don't enable end_device/host_bridge with leaf directly here */
2609 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2610 host_bridge_with_leaf(host_bridge))
2611 goto out;
2612
2613 /* root did that ! */
2614 if (msi_ht_cap_enabled(host_bridge))
2615 goto out;
2616
2617 ht_enable_msi_mapping(dev);
2618
2619 out:
2620 pci_dev_put(host_bridge);
2621 }
2622
2623 static void ht_disable_msi_mapping(struct pci_dev *dev)
2624 {
2625 int pos, ttl = PCI_FIND_CAP_TTL;
2626
2627 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2628 while (pos && ttl--) {
2629 u8 flags;
2630
2631 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2632 &flags) == 0) {
2633 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2634
2635 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2636 flags & ~HT_MSI_FLAGS_ENABLE);
2637 }
2638 pos = pci_find_next_ht_capability(dev, pos,
2639 HT_CAPTYPE_MSI_MAPPING);
2640 }
2641 }
2642
2643 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2644 {
2645 struct pci_dev *host_bridge;
2646 int pos;
2647 int found;
2648
2649 if (!pci_msi_enabled())
2650 return;
2651
2652 /* check if there is HT MSI cap or enabled on this device */
2653 found = ht_check_msi_mapping(dev);
2654
2655 /* no HT MSI CAP */
2656 if (found == 0)
2657 return;
2658
2659 /*
2660 * HT MSI mapping should be disabled on devices that are below
2661 * a non-Hypertransport host bridge. Locate the host bridge...
2662 */
2663 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2664 if (host_bridge == NULL) {
2665 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2666 return;
2667 }
2668
2669 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2670 if (pos != 0) {
2671 /* Host bridge is to HT */
2672 if (found == 1) {
2673 /* it is not enabled, try to enable it */
2674 if (all)
2675 ht_enable_msi_mapping(dev);
2676 else
2677 nv_ht_enable_msi_mapping(dev);
2678 }
2679 goto out;
2680 }
2681
2682 /* HT MSI is not enabled */
2683 if (found == 1)
2684 goto out;
2685
2686 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2687 ht_disable_msi_mapping(dev);
2688
2689 out:
2690 pci_dev_put(host_bridge);
2691 }
2692
2693 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2694 {
2695 return __nv_msi_ht_cap_quirk(dev, 1);
2696 }
2697
2698 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2699 {
2700 return __nv_msi_ht_cap_quirk(dev, 0);
2701 }
2702
2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2704 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2705
2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2707 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2708
2709 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2710 {
2711 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2712 }
2713 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2714 {
2715 struct pci_dev *p;
2716
2717 /* SB700 MSI issue will be fixed at HW level from revision A21,
2718 * we need check PCI REVISION ID of SMBus controller to get SB700
2719 * revision.
2720 */
2721 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2722 NULL);
2723 if (!p)
2724 return;
2725
2726 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2727 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2728 pci_dev_put(p);
2729 }
2730 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2731 {
2732 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2733 if (dev->revision < 0x18) {
2734 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2735 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2736 }
2737 }
2738 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2739 PCI_DEVICE_ID_TIGON3_5780,
2740 quirk_msi_intx_disable_bug);
2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2742 PCI_DEVICE_ID_TIGON3_5780S,
2743 quirk_msi_intx_disable_bug);
2744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2745 PCI_DEVICE_ID_TIGON3_5714,
2746 quirk_msi_intx_disable_bug);
2747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2748 PCI_DEVICE_ID_TIGON3_5714S,
2749 quirk_msi_intx_disable_bug);
2750 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2751 PCI_DEVICE_ID_TIGON3_5715,
2752 quirk_msi_intx_disable_bug);
2753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2754 PCI_DEVICE_ID_TIGON3_5715S,
2755 quirk_msi_intx_disable_bug);
2756
2757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2758 quirk_msi_intx_disable_ati_bug);
2759 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2760 quirk_msi_intx_disable_ati_bug);
2761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2762 quirk_msi_intx_disable_ati_bug);
2763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2764 quirk_msi_intx_disable_ati_bug);
2765 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2766 quirk_msi_intx_disable_ati_bug);
2767
2768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2769 quirk_msi_intx_disable_bug);
2770 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2771 quirk_msi_intx_disable_bug);
2772 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2773 quirk_msi_intx_disable_bug);
2774
2775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2776 quirk_msi_intx_disable_bug);
2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2778 quirk_msi_intx_disable_bug);
2779 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2780 quirk_msi_intx_disable_bug);
2781 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2782 quirk_msi_intx_disable_bug);
2783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2784 quirk_msi_intx_disable_bug);
2785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2786 quirk_msi_intx_disable_bug);
2787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2788 quirk_msi_intx_disable_qca_bug);
2789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2790 quirk_msi_intx_disable_qca_bug);
2791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2792 quirk_msi_intx_disable_qca_bug);
2793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2794 quirk_msi_intx_disable_qca_bug);
2795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2796 quirk_msi_intx_disable_qca_bug);
2797 #endif /* CONFIG_PCI_MSI */
2798
2799 /* Allow manual resource allocation for PCI hotplug bridges
2800 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2801 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2802 * kernel fails to allocate resources when hotplug device is
2803 * inserted and PCI bus is rescanned.
2804 */
2805 static void quirk_hotplug_bridge(struct pci_dev *dev)
2806 {
2807 dev->is_hotplug_bridge = 1;
2808 }
2809
2810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2811
2812 /*
2813 * This is a quirk for the Ricoh MMC controller found as a part of
2814 * some mulifunction chips.
2815
2816 * This is very similar and based on the ricoh_mmc driver written by
2817 * Philip Langdale. Thank you for these magic sequences.
2818 *
2819 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2820 * and one or both of cardbus or firewire.
2821 *
2822 * It happens that they implement SD and MMC
2823 * support as separate controllers (and PCI functions). The linux SDHCI
2824 * driver supports MMC cards but the chip detects MMC cards in hardware
2825 * and directs them to the MMC controller - so the SDHCI driver never sees
2826 * them.
2827 *
2828 * To get around this, we must disable the useless MMC controller.
2829 * At that point, the SDHCI controller will start seeing them
2830 * It seems to be the case that the relevant PCI registers to deactivate the
2831 * MMC controller live on PCI function 0, which might be the cardbus controller
2832 * or the firewire controller, depending on the particular chip in question
2833 *
2834 * This has to be done early, because as soon as we disable the MMC controller
2835 * other pci functions shift up one level, e.g. function #2 becomes function
2836 * #1, and this will confuse the pci core.
2837 */
2838
2839 #ifdef CONFIG_MMC_RICOH_MMC
2840 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2841 {
2842 /* disable via cardbus interface */
2843 u8 write_enable;
2844 u8 write_target;
2845 u8 disable;
2846
2847 /* disable must be done via function #0 */
2848 if (PCI_FUNC(dev->devfn))
2849 return;
2850
2851 pci_read_config_byte(dev, 0xB7, &disable);
2852 if (disable & 0x02)
2853 return;
2854
2855 pci_read_config_byte(dev, 0x8E, &write_enable);
2856 pci_write_config_byte(dev, 0x8E, 0xAA);
2857 pci_read_config_byte(dev, 0x8D, &write_target);
2858 pci_write_config_byte(dev, 0x8D, 0xB7);
2859 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2860 pci_write_config_byte(dev, 0x8E, write_enable);
2861 pci_write_config_byte(dev, 0x8D, write_target);
2862
2863 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2864 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2865 }
2866 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2867 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2868
2869 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2870 {
2871 /* disable via firewire interface */
2872 u8 write_enable;
2873 u8 disable;
2874
2875 /* disable must be done via function #0 */
2876 if (PCI_FUNC(dev->devfn))
2877 return;
2878 /*
2879 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2880 * certain types of SD/MMC cards. Lowering the SD base
2881 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2882 *
2883 * 0x150 - SD2.0 mode enable for changing base clock
2884 * frequency to 50Mhz
2885 * 0xe1 - Base clock frequency
2886 * 0x32 - 50Mhz new clock frequency
2887 * 0xf9 - Key register for 0x150
2888 * 0xfc - key register for 0xe1
2889 */
2890 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2891 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2892 pci_write_config_byte(dev, 0xf9, 0xfc);
2893 pci_write_config_byte(dev, 0x150, 0x10);
2894 pci_write_config_byte(dev, 0xf9, 0x00);
2895 pci_write_config_byte(dev, 0xfc, 0x01);
2896 pci_write_config_byte(dev, 0xe1, 0x32);
2897 pci_write_config_byte(dev, 0xfc, 0x00);
2898
2899 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2900 }
2901
2902 pci_read_config_byte(dev, 0xCB, &disable);
2903
2904 if (disable & 0x02)
2905 return;
2906
2907 pci_read_config_byte(dev, 0xCA, &write_enable);
2908 pci_write_config_byte(dev, 0xCA, 0x57);
2909 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2910 pci_write_config_byte(dev, 0xCA, write_enable);
2911
2912 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2913 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2914
2915 }
2916 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2917 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2918 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2919 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2920 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2921 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2922 #endif /*CONFIG_MMC_RICOH_MMC*/
2923
2924 #ifdef CONFIG_DMAR_TABLE
2925 #define VTUNCERRMSK_REG 0x1ac
2926 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2927 /*
2928 * This is a quirk for masking vt-d spec defined errors to platform error
2929 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2930 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2931 * on the RAS config settings of the platform) when a vt-d fault happens.
2932 * The resulting SMI caused the system to hang.
2933 *
2934 * VT-d spec related errors are already handled by the VT-d OS code, so no
2935 * need to report the same error through other channels.
2936 */
2937 static void vtd_mask_spec_errors(struct pci_dev *dev)
2938 {
2939 u32 word;
2940
2941 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2942 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2943 }
2944 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2945 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2946 #endif
2947
2948 static void fixup_ti816x_class(struct pci_dev *dev)
2949 {
2950 u32 class = dev->class;
2951
2952 /* TI 816x devices do not have class code set when in PCIe boot mode */
2953 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2954 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2955 class, dev->class);
2956 }
2957 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2958 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2959
2960 /* Some PCIe devices do not work reliably with the claimed maximum
2961 * payload size supported.
2962 */
2963 static void fixup_mpss_256(struct pci_dev *dev)
2964 {
2965 dev->pcie_mpss = 1; /* 256 bytes */
2966 }
2967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2968 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2969 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2970 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2971 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2972 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2973
2974 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2975 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2976 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2977 * until all of the devices are discovered and buses walked, read completion
2978 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2979 * it is possible to hotplug a device with MPS of 256B.
2980 */
2981 static void quirk_intel_mc_errata(struct pci_dev *dev)
2982 {
2983 int err;
2984 u16 rcc;
2985
2986 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2987 pcie_bus_config == PCIE_BUS_DEFAULT)
2988 return;
2989
2990 /* Intel errata specifies bits to change but does not say what they are.
2991 * Keeping them magical until such time as the registers and values can
2992 * be explained.
2993 */
2994 err = pci_read_config_word(dev, 0x48, &rcc);
2995 if (err) {
2996 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
2997 return;
2998 }
2999
3000 if (!(rcc & (1 << 10)))
3001 return;
3002
3003 rcc &= ~(1 << 10);
3004
3005 err = pci_write_config_word(dev, 0x48, rcc);
3006 if (err) {
3007 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3008 return;
3009 }
3010
3011 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3012 }
3013 /* Intel 5000 series memory controllers and ports 2-7 */
3014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3027 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3028 /* Intel 5100 series memory controllers and ports 2-7 */
3029 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3030 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3032 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3035 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3040
3041
3042 /*
3043 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3044 * work around this, query the size it should be configured to by the device and
3045 * modify the resource end to correspond to this new size.
3046 */
3047 static void quirk_intel_ntb(struct pci_dev *dev)
3048 {
3049 int rc;
3050 u8 val;
3051
3052 rc = pci_read_config_byte(dev, 0x00D0, &val);
3053 if (rc)
3054 return;
3055
3056 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3057
3058 rc = pci_read_config_byte(dev, 0x00D1, &val);
3059 if (rc)
3060 return;
3061
3062 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3063 }
3064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3066
3067 static ktime_t fixup_debug_start(struct pci_dev *dev,
3068 void (*fn)(struct pci_dev *dev))
3069 {
3070 ktime_t calltime = 0;
3071
3072 dev_dbg(&dev->dev, "calling %pF\n", fn);
3073 if (initcall_debug) {
3074 pr_debug("calling %pF @ %i for %s\n",
3075 fn, task_pid_nr(current), dev_name(&dev->dev));
3076 calltime = ktime_get();
3077 }
3078
3079 return calltime;
3080 }
3081
3082 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3083 void (*fn)(struct pci_dev *dev))
3084 {
3085 ktime_t delta, rettime;
3086 unsigned long long duration;
3087
3088 if (initcall_debug) {
3089 rettime = ktime_get();
3090 delta = ktime_sub(rettime, calltime);
3091 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3092 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3093 fn, duration, dev_name(&dev->dev));
3094 }
3095 }
3096
3097 /*
3098 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3099 * even though no one is handling them (f.e. i915 driver is never loaded).
3100 * Additionally the interrupt destination is not set up properly
3101 * and the interrupt ends up -somewhere-.
3102 *
3103 * These spurious interrupts are "sticky" and the kernel disables
3104 * the (shared) interrupt line after 100.000+ generated interrupts.
3105 *
3106 * Fix it by disabling the still enabled interrupts.
3107 * This resolves crashes often seen on monitor unplug.
3108 */
3109 #define I915_DEIER_REG 0x4400c
3110 static void disable_igfx_irq(struct pci_dev *dev)
3111 {
3112 void __iomem *regs = pci_iomap(dev, 0, 0);
3113 if (regs == NULL) {
3114 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3115 return;
3116 }
3117
3118 /* Check if any interrupt line is still enabled */
3119 if (readl(regs + I915_DEIER_REG) != 0) {
3120 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3121
3122 writel(0, regs + I915_DEIER_REG);
3123 }
3124
3125 pci_iounmap(dev, regs);
3126 }
3127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3128 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3129 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3130
3131 /*
3132 * PCI devices which are on Intel chips can skip the 10ms delay
3133 * before entering D3 mode.
3134 */
3135 static void quirk_remove_d3_delay(struct pci_dev *dev)
3136 {
3137 dev->d3_delay = 0;
3138 }
3139 /* C600 Series devices do not need 10ms d3_delay */
3140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3143 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3151 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3155 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3165
3166 /*
3167 * Some devices may pass our check in pci_intx_mask_supported() if
3168 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3169 * support this feature.
3170 */
3171 static void quirk_broken_intx_masking(struct pci_dev *dev)
3172 {
3173 dev->broken_intx_masking = 1;
3174 }
3175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3176 quirk_broken_intx_masking);
3177 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3178 quirk_broken_intx_masking);
3179
3180 /*
3181 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3182 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3183 *
3184 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3185 */
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3187 quirk_broken_intx_masking);
3188
3189 /*
3190 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3191 * DisINTx can be set but the interrupt status bit is non-functional.
3192 */
3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3194 quirk_broken_intx_masking);
3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3196 quirk_broken_intx_masking);
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3198 quirk_broken_intx_masking);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3200 quirk_broken_intx_masking);
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3202 quirk_broken_intx_masking);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3204 quirk_broken_intx_masking);
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3206 quirk_broken_intx_masking);
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3208 quirk_broken_intx_masking);
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3210 quirk_broken_intx_masking);
3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3212 quirk_broken_intx_masking);
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3214 quirk_broken_intx_masking);
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3216 quirk_broken_intx_masking);
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3218 quirk_broken_intx_masking);
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3220 quirk_broken_intx_masking);
3221
3222 static u16 mellanox_broken_intx_devs[] = {
3223 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3224 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3225 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3226 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3227 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3228 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3229 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3230 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3231 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3232 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3233 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3234 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3235 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3236 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3237 };
3238
3239 #define CONNECTX_4_CURR_MAX_MINOR 99
3240 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3241
3242 /*
3243 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3244 * If so, don't mark it as broken.
3245 * FW minor > 99 means older FW version format and no INTx masking support.
3246 * FW minor < 14 means new FW version format and no INTx masking support.
3247 */
3248 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3249 {
3250 __be32 __iomem *fw_ver;
3251 u16 fw_major;
3252 u16 fw_minor;
3253 u16 fw_subminor;
3254 u32 fw_maj_min;
3255 u32 fw_sub_min;
3256 int i;
3257
3258 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3259 if (pdev->device == mellanox_broken_intx_devs[i]) {
3260 pdev->broken_intx_masking = 1;
3261 return;
3262 }
3263 }
3264
3265 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3266 * support so shouldn't be checked further
3267 */
3268 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3269 return;
3270
3271 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3272 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3273 return;
3274
3275 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3276 if (pci_enable_device_mem(pdev)) {
3277 dev_warn(&pdev->dev, "Can't enable device memory\n");
3278 return;
3279 }
3280
3281 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3282 if (!fw_ver) {
3283 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3284 goto out;
3285 }
3286
3287 /* Reading from resource space should be 32b aligned */
3288 fw_maj_min = ioread32be(fw_ver);
3289 fw_sub_min = ioread32be(fw_ver + 1);
3290 fw_major = fw_maj_min & 0xffff;
3291 fw_minor = fw_maj_min >> 16;
3292 fw_subminor = fw_sub_min & 0xffff;
3293 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3294 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3295 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3296 fw_major, fw_minor, fw_subminor, pdev->device ==
3297 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3298 pdev->broken_intx_masking = 1;
3299 }
3300
3301 iounmap(fw_ver);
3302
3303 out:
3304 pci_disable_device(pdev);
3305 }
3306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3307 mellanox_check_broken_intx_masking);
3308
3309 static void quirk_no_bus_reset(struct pci_dev *dev)
3310 {
3311 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3312 }
3313
3314 /*
3315 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3316 * The device will throw a Link Down error on AER-capable systems and
3317 * regardless of AER, config space of the device is never accessible again
3318 * and typically causes the system to hang or reset when access is attempted.
3319 * http://www.spinics.net/lists/linux-pci/msg34797.html
3320 */
3321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3325
3326 static void quirk_no_pm_reset(struct pci_dev *dev)
3327 {
3328 /*
3329 * We can't do a bus reset on root bus devices, but an ineffective
3330 * PM reset may be better than nothing.
3331 */
3332 if (!pci_is_root_bus(dev->bus))
3333 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3334 }
3335
3336 /*
3337 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3338 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3339 * to have no effect on the device: it retains the framebuffer contents and
3340 * monitor sync. Advertising this support makes other layers, like VFIO,
3341 * assume pci_reset_function() is viable for this device. Mark it as
3342 * unavailable to skip it when testing reset methods.
3343 */
3344 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3345 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3346
3347 /*
3348 * Thunderbolt controllers with broken MSI hotplug signaling:
3349 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3350 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3351 */
3352 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3353 {
3354 if (pdev->is_hotplug_bridge &&
3355 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3356 pdev->revision <= 1))
3357 pdev->no_msi = 1;
3358 }
3359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3360 quirk_thunderbolt_hotplug_msi);
3361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3362 quirk_thunderbolt_hotplug_msi);
3363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3364 quirk_thunderbolt_hotplug_msi);
3365 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3366 quirk_thunderbolt_hotplug_msi);
3367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3368 quirk_thunderbolt_hotplug_msi);
3369
3370 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3371 {
3372 pci_set_vpd_size(dev, 8192);
3373 }
3374
3375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
3376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
3377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
3378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
3379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
3380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
3381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
3382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
3383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
3384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
3388
3389 #ifdef CONFIG_ACPI
3390 /*
3391 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3392 *
3393 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3394 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3395 * be present after resume if a device was plugged in before suspend.
3396 *
3397 * The thunderbolt controller consists of a pcie switch with downstream
3398 * bridges leading to the NHI and to the tunnel pci bridges.
3399 *
3400 * This quirk cuts power to the whole chip. Therefore we have to apply it
3401 * during suspend_noirq of the upstream bridge.
3402 *
3403 * Power is automagically restored before resume. No action is needed.
3404 */
3405 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3406 {
3407 acpi_handle bridge, SXIO, SXFP, SXLV;
3408
3409 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3410 return;
3411 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3412 return;
3413 bridge = ACPI_HANDLE(&dev->dev);
3414 if (!bridge)
3415 return;
3416 /*
3417 * SXIO and SXLV are present only on machines requiring this quirk.
3418 * TB bridges in external devices might have the same device id as those
3419 * on the host, but they will not have the associated ACPI methods. This
3420 * implicitly checks that we are at the right bridge.
3421 */
3422 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3423 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3424 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3425 return;
3426 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3427
3428 /* magic sequence */
3429 acpi_execute_simple_method(SXIO, NULL, 1);
3430 acpi_execute_simple_method(SXFP, NULL, 0);
3431 msleep(300);
3432 acpi_execute_simple_method(SXLV, NULL, 0);
3433 acpi_execute_simple_method(SXIO, NULL, 0);
3434 acpi_execute_simple_method(SXLV, NULL, 0);
3435 }
3436 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3437 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3438 quirk_apple_poweroff_thunderbolt);
3439
3440 /*
3441 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3442 *
3443 * During suspend the thunderbolt controller is reset and all pci
3444 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3445 * during resume. We have to manually wait for the NHI since there is
3446 * no parent child relationship between the NHI and the tunneled
3447 * bridges.
3448 */
3449 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3450 {
3451 struct pci_dev *sibling = NULL;
3452 struct pci_dev *nhi = NULL;
3453
3454 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3455 return;
3456 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3457 return;
3458 /*
3459 * Find the NHI and confirm that we are a bridge on the tb host
3460 * controller and not on a tb endpoint.
3461 */
3462 sibling = pci_get_slot(dev->bus, 0x0);
3463 if (sibling == dev)
3464 goto out; /* we are the downstream bridge to the NHI */
3465 if (!sibling || !sibling->subordinate)
3466 goto out;
3467 nhi = pci_get_slot(sibling->subordinate, 0x0);
3468 if (!nhi)
3469 goto out;
3470 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3471 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3472 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3473 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3474 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3475 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3476 goto out;
3477 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3478 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3479 out:
3480 pci_dev_put(nhi);
3481 pci_dev_put(sibling);
3482 }
3483 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3484 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3485 quirk_apple_wait_for_thunderbolt);
3486 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3487 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3488 quirk_apple_wait_for_thunderbolt);
3489 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3490 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3491 quirk_apple_wait_for_thunderbolt);
3492 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3493 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3494 quirk_apple_wait_for_thunderbolt);
3495 #endif
3496
3497 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3498 struct pci_fixup *end)
3499 {
3500 ktime_t calltime;
3501
3502 for (; f < end; f++)
3503 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3504 f->class == (u32) PCI_ANY_ID) &&
3505 (f->vendor == dev->vendor ||
3506 f->vendor == (u16) PCI_ANY_ID) &&
3507 (f->device == dev->device ||
3508 f->device == (u16) PCI_ANY_ID)) {
3509 calltime = fixup_debug_start(dev, f->hook);
3510 f->hook(dev);
3511 fixup_debug_report(dev, calltime, f->hook);
3512 }
3513 }
3514
3515 extern struct pci_fixup __start_pci_fixups_early[];
3516 extern struct pci_fixup __end_pci_fixups_early[];
3517 extern struct pci_fixup __start_pci_fixups_header[];
3518 extern struct pci_fixup __end_pci_fixups_header[];
3519 extern struct pci_fixup __start_pci_fixups_final[];
3520 extern struct pci_fixup __end_pci_fixups_final[];
3521 extern struct pci_fixup __start_pci_fixups_enable[];
3522 extern struct pci_fixup __end_pci_fixups_enable[];
3523 extern struct pci_fixup __start_pci_fixups_resume[];
3524 extern struct pci_fixup __end_pci_fixups_resume[];
3525 extern struct pci_fixup __start_pci_fixups_resume_early[];
3526 extern struct pci_fixup __end_pci_fixups_resume_early[];
3527 extern struct pci_fixup __start_pci_fixups_suspend[];
3528 extern struct pci_fixup __end_pci_fixups_suspend[];
3529 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3530 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3531
3532 static bool pci_apply_fixup_final_quirks;
3533
3534 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3535 {
3536 struct pci_fixup *start, *end;
3537
3538 switch (pass) {
3539 case pci_fixup_early:
3540 start = __start_pci_fixups_early;
3541 end = __end_pci_fixups_early;
3542 break;
3543
3544 case pci_fixup_header:
3545 start = __start_pci_fixups_header;
3546 end = __end_pci_fixups_header;
3547 break;
3548
3549 case pci_fixup_final:
3550 if (!pci_apply_fixup_final_quirks)
3551 return;
3552 start = __start_pci_fixups_final;
3553 end = __end_pci_fixups_final;
3554 break;
3555
3556 case pci_fixup_enable:
3557 start = __start_pci_fixups_enable;
3558 end = __end_pci_fixups_enable;
3559 break;
3560
3561 case pci_fixup_resume:
3562 start = __start_pci_fixups_resume;
3563 end = __end_pci_fixups_resume;
3564 break;
3565
3566 case pci_fixup_resume_early:
3567 start = __start_pci_fixups_resume_early;
3568 end = __end_pci_fixups_resume_early;
3569 break;
3570
3571 case pci_fixup_suspend:
3572 start = __start_pci_fixups_suspend;
3573 end = __end_pci_fixups_suspend;
3574 break;
3575
3576 case pci_fixup_suspend_late:
3577 start = __start_pci_fixups_suspend_late;
3578 end = __end_pci_fixups_suspend_late;
3579 break;
3580
3581 default:
3582 /* stupid compiler warning, you would think with an enum... */
3583 return;
3584 }
3585 pci_do_fixups(dev, start, end);
3586 }
3587 EXPORT_SYMBOL(pci_fixup_device);
3588
3589
3590 static int __init pci_apply_final_quirks(void)
3591 {
3592 struct pci_dev *dev = NULL;
3593 u8 cls = 0;
3594 u8 tmp;
3595
3596 if (pci_cache_line_size)
3597 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3598 pci_cache_line_size << 2);
3599
3600 pci_apply_fixup_final_quirks = true;
3601 for_each_pci_dev(dev) {
3602 pci_fixup_device(pci_fixup_final, dev);
3603 /*
3604 * If arch hasn't set it explicitly yet, use the CLS
3605 * value shared by all PCI devices. If there's a
3606 * mismatch, fall back to the default value.
3607 */
3608 if (!pci_cache_line_size) {
3609 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3610 if (!cls)
3611 cls = tmp;
3612 if (!tmp || cls == tmp)
3613 continue;
3614
3615 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3616 cls << 2, tmp << 2,
3617 pci_dfl_cache_line_size << 2);
3618 pci_cache_line_size = pci_dfl_cache_line_size;
3619 }
3620 }
3621
3622 if (!pci_cache_line_size) {
3623 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3624 cls << 2, pci_dfl_cache_line_size << 2);
3625 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3626 }
3627
3628 return 0;
3629 }
3630
3631 fs_initcall_sync(pci_apply_final_quirks);
3632
3633 /*
3634 * Following are device-specific reset methods which can be used to
3635 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3636 * not available.
3637 */
3638 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3639 {
3640 /*
3641 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3642 *
3643 * The 82599 supports FLR on VFs, but FLR support is reported only
3644 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3645 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3646 */
3647
3648 if (probe)
3649 return 0;
3650
3651 if (!pci_wait_for_pending_transaction(dev))
3652 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3653
3654 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3655
3656 msleep(100);
3657
3658 return 0;
3659 }
3660
3661 #define SOUTH_CHICKEN2 0xc2004
3662 #define PCH_PP_STATUS 0xc7200
3663 #define PCH_PP_CONTROL 0xc7204
3664 #define MSG_CTL 0x45010
3665 #define NSDE_PWR_STATE 0xd0100
3666 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3667
3668 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3669 {
3670 void __iomem *mmio_base;
3671 unsigned long timeout;
3672 u32 val;
3673
3674 if (probe)
3675 return 0;
3676
3677 mmio_base = pci_iomap(dev, 0, 0);
3678 if (!mmio_base)
3679 return -ENOMEM;
3680
3681 iowrite32(0x00000002, mmio_base + MSG_CTL);
3682
3683 /*
3684 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3685 * driver loaded sets the right bits. However, this's a reset and
3686 * the bits have been set by i915 previously, so we clobber
3687 * SOUTH_CHICKEN2 register directly here.
3688 */
3689 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3690
3691 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3692 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3693
3694 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3695 do {
3696 val = ioread32(mmio_base + PCH_PP_STATUS);
3697 if ((val & 0xb0000000) == 0)
3698 goto reset_complete;
3699 msleep(10);
3700 } while (time_before(jiffies, timeout));
3701 dev_warn(&dev->dev, "timeout during reset\n");
3702
3703 reset_complete:
3704 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3705
3706 pci_iounmap(dev, mmio_base);
3707 return 0;
3708 }
3709
3710 /*
3711 * Device-specific reset method for Chelsio T4-based adapters.
3712 */
3713 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3714 {
3715 u16 old_command;
3716 u16 msix_flags;
3717
3718 /*
3719 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3720 * that we have no device-specific reset method.
3721 */
3722 if ((dev->device & 0xf000) != 0x4000)
3723 return -ENOTTY;
3724
3725 /*
3726 * If this is the "probe" phase, return 0 indicating that we can
3727 * reset this device.
3728 */
3729 if (probe)
3730 return 0;
3731
3732 /*
3733 * T4 can wedge if there are DMAs in flight within the chip and Bus
3734 * Master has been disabled. We need to have it on till the Function
3735 * Level Reset completes. (BUS_MASTER is disabled in
3736 * pci_reset_function()).
3737 */
3738 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3739 pci_write_config_word(dev, PCI_COMMAND,
3740 old_command | PCI_COMMAND_MASTER);
3741
3742 /*
3743 * Perform the actual device function reset, saving and restoring
3744 * configuration information around the reset.
3745 */
3746 pci_save_state(dev);
3747
3748 /*
3749 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3750 * are disabled when an MSI-X interrupt message needs to be delivered.
3751 * So we briefly re-enable MSI-X interrupts for the duration of the
3752 * FLR. The pci_restore_state() below will restore the original
3753 * MSI-X state.
3754 */
3755 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3756 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3757 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3758 msix_flags |
3759 PCI_MSIX_FLAGS_ENABLE |
3760 PCI_MSIX_FLAGS_MASKALL);
3761
3762 /*
3763 * Start of pcie_flr() code sequence. This reset code is a copy of
3764 * the guts of pcie_flr() because that's not an exported function.
3765 */
3766
3767 if (!pci_wait_for_pending_transaction(dev))
3768 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3769
3770 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3771 msleep(100);
3772
3773 /*
3774 * End of pcie_flr() code sequence.
3775 */
3776
3777 /*
3778 * Restore the configuration information (BAR values, etc.) including
3779 * the original PCI Configuration Space Command word, and return
3780 * success.
3781 */
3782 pci_restore_state(dev);
3783 pci_write_config_word(dev, PCI_COMMAND, old_command);
3784 return 0;
3785 }
3786
3787 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3788 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3789 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3790
3791 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3792 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3793 reset_intel_82599_sfp_virtfn },
3794 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3795 reset_ivb_igd },
3796 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3797 reset_ivb_igd },
3798 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3799 reset_chelsio_generic_dev },
3800 { 0 }
3801 };
3802
3803 /*
3804 * These device-specific reset methods are here rather than in a driver
3805 * because when a host assigns a device to a guest VM, the host may need
3806 * to reset the device but probably doesn't have a driver for it.
3807 */
3808 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3809 {
3810 const struct pci_dev_reset_methods *i;
3811
3812 for (i = pci_dev_reset_methods; i->reset; i++) {
3813 if ((i->vendor == dev->vendor ||
3814 i->vendor == (u16)PCI_ANY_ID) &&
3815 (i->device == dev->device ||
3816 i->device == (u16)PCI_ANY_ID))
3817 return i->reset(dev, probe);
3818 }
3819
3820 return -ENOTTY;
3821 }
3822
3823 static void quirk_dma_func0_alias(struct pci_dev *dev)
3824 {
3825 if (PCI_FUNC(dev->devfn) != 0)
3826 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3827 }
3828
3829 /*
3830 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3831 *
3832 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3833 */
3834 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3836
3837 static void quirk_dma_func1_alias(struct pci_dev *dev)
3838 {
3839 if (PCI_FUNC(dev->devfn) != 1)
3840 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3841 }
3842
3843 /*
3844 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3845 * SKUs function 1 is present and is a legacy IDE controller, in other
3846 * SKUs this function is not present, making this a ghost requester.
3847 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3848 */
3849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3850 quirk_dma_func1_alias);
3851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3852 quirk_dma_func1_alias);
3853 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3855 quirk_dma_func1_alias);
3856 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3858 quirk_dma_func1_alias);
3859 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3861 quirk_dma_func1_alias);
3862 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3864 quirk_dma_func1_alias);
3865 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3867 quirk_dma_func1_alias);
3868 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3870 quirk_dma_func1_alias);
3871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3872 quirk_dma_func1_alias);
3873 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3875 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3876 quirk_dma_func1_alias);
3877 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3878 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3879 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3880 quirk_dma_func1_alias);
3881
3882 /*
3883 * Some devices DMA with the wrong devfn, not just the wrong function.
3884 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3885 * the alias is "fixed" and independent of the device devfn.
3886 *
3887 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3888 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3889 * single device on the secondary bus. In reality, the single exposed
3890 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3891 * that provides a bridge to the internal bus of the I/O processor. The
3892 * controller supports private devices, which can be hidden from PCI config
3893 * space. In the case of the Adaptec 3405, a private device at 01.0
3894 * appears to be the DMA engine, which therefore needs to become a DMA
3895 * alias for the device.
3896 */
3897 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3898 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3899 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3900 .driver_data = PCI_DEVFN(1, 0) },
3901 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3902 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3903 .driver_data = PCI_DEVFN(1, 0) },
3904 { 0 }
3905 };
3906
3907 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3908 {
3909 const struct pci_device_id *id;
3910
3911 id = pci_match_id(fixed_dma_alias_tbl, dev);
3912 if (id)
3913 pci_add_dma_alias(dev, id->driver_data);
3914 }
3915
3916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3917
3918 /*
3919 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3920 * using the wrong DMA alias for the device. Some of these devices can be
3921 * used as either forward or reverse bridges, so we need to test whether the
3922 * device is operating in the correct mode. We could probably apply this
3923 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3924 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3925 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3926 */
3927 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3928 {
3929 if (!pci_is_root_bus(pdev->bus) &&
3930 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3931 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3932 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3933 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3934 }
3935 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3937 quirk_use_pcie_bridge_dma_alias);
3938 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3939 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3940 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3941 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3942 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3943 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3944
3945 /*
3946 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3947 * be added as aliases to the DMA device in order to allow buffer access
3948 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3949 * programmed in the EEPROM.
3950 */
3951 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3952 {
3953 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3954 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3955 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3956 }
3957 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3959
3960 /*
3961 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3962 * class code. Fix it.
3963 */
3964 static void quirk_tw686x_class(struct pci_dev *pdev)
3965 {
3966 u32 class = pdev->class;
3967
3968 /* Use "Multimedia controller" class */
3969 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3970 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3971 class, pdev->class);
3972 }
3973 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3974 quirk_tw686x_class);
3975 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3976 quirk_tw686x_class);
3977 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3978 quirk_tw686x_class);
3979 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3980 quirk_tw686x_class);
3981
3982 /*
3983 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
3984 * values for the Attribute as were supplied in the header of the
3985 * corresponding Request, except as explicitly allowed when IDO is used."
3986 *
3987 * If a non-compliant device generates a completion with a different
3988 * attribute than the request, the receiver may accept it (which itself
3989 * seems non-compliant based on sec 2.3.2), or it may handle it as a
3990 * Malformed TLP or an Unexpected Completion, which will probably lead to a
3991 * device access timeout.
3992 *
3993 * If the non-compliant device generates completions with zero attributes
3994 * (instead of copying the attributes from the request), we can work around
3995 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
3996 * upstream devices so they always generate requests with zero attributes.
3997 *
3998 * This affects other devices under the same Root Port, but since these
3999 * attributes are performance hints, there should be no functional problem.
4000 *
4001 * Note that Configuration Space accesses are never supposed to have TLP
4002 * Attributes, so we're safe waiting till after any Configuration Space
4003 * accesses to do the Root Port fixup.
4004 */
4005 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4006 {
4007 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4008
4009 if (!root_port) {
4010 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4011 return;
4012 }
4013
4014 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4015 dev_name(&pdev->dev));
4016 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4017 PCI_EXP_DEVCTL_RELAX_EN |
4018 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4019 }
4020
4021 /*
4022 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4023 * Completion it generates.
4024 */
4025 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4026 {
4027 /*
4028 * This mask/compare operation selects for Physical Function 4 on a
4029 * T5. We only need to fix up the Root Port once for any of the
4030 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4031 * 0x54xx so we use that one,
4032 */
4033 if ((pdev->device & 0xff00) == 0x5400)
4034 quirk_disable_root_port_attributes(pdev);
4035 }
4036 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4037 quirk_chelsio_T5_disable_root_port_attributes);
4038
4039 /*
4040 * AMD has indicated that the devices below do not support peer-to-peer
4041 * in any system where they are found in the southbridge with an AMD
4042 * IOMMU in the system. Multifunction devices that do not support
4043 * peer-to-peer between functions can claim to support a subset of ACS.
4044 * Such devices effectively enable request redirect (RR) and completion
4045 * redirect (CR) since all transactions are redirected to the upstream
4046 * root complex.
4047 *
4048 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4049 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4050 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4051 *
4052 * 1002:4385 SBx00 SMBus Controller
4053 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4054 * 1002:4383 SBx00 Azalia (Intel HDA)
4055 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4056 * 1002:4384 SBx00 PCI to PCI Bridge
4057 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4058 *
4059 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4060 *
4061 * 1022:780f [AMD] FCH PCI Bridge
4062 * 1022:7809 [AMD] FCH USB OHCI Controller
4063 */
4064 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4065 {
4066 #ifdef CONFIG_ACPI
4067 struct acpi_table_header *header = NULL;
4068 acpi_status status;
4069
4070 /* Targeting multifunction devices on the SB (appears on root bus) */
4071 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4072 return -ENODEV;
4073
4074 /* The IVRS table describes the AMD IOMMU */
4075 status = acpi_get_table("IVRS", 0, &header);
4076 if (ACPI_FAILURE(status))
4077 return -ENODEV;
4078
4079 /* Filter out flags not applicable to multifunction */
4080 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4081
4082 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4083 #else
4084 return -ENODEV;
4085 #endif
4086 }
4087
4088 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4089 {
4090 /*
4091 * Cavium devices matching this quirk do not perform peer-to-peer
4092 * with other functions, allowing masking out these bits as if they
4093 * were unimplemented in the ACS capability.
4094 */
4095 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4096 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4097
4098 return acs_flags ? 0 : 1;
4099 }
4100
4101 /*
4102 * Many Intel PCH root ports do provide ACS-like features to disable peer
4103 * transactions and validate bus numbers in requests, but do not provide an
4104 * actual PCIe ACS capability. This is the list of device IDs known to fall
4105 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4106 */
4107 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4108 /* Ibexpeak PCH */
4109 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4110 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4111 /* Cougarpoint PCH */
4112 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4113 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4114 /* Pantherpoint PCH */
4115 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4116 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4117 /* Lynxpoint-H PCH */
4118 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4119 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4120 /* Lynxpoint-LP PCH */
4121 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4122 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4123 /* Wildcat PCH */
4124 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4125 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4126 /* Patsburg (X79) PCH */
4127 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4128 /* Wellsburg (X99) PCH */
4129 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4130 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4131 /* Lynx Point (9 series) PCH */
4132 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4133 };
4134
4135 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4136 {
4137 int i;
4138
4139 /* Filter out a few obvious non-matches first */
4140 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4141 return false;
4142
4143 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4144 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4145 return true;
4146
4147 return false;
4148 }
4149
4150 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4151
4152 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4153 {
4154 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4155 INTEL_PCH_ACS_FLAGS : 0;
4156
4157 if (!pci_quirk_intel_pch_acs_match(dev))
4158 return -ENOTTY;
4159
4160 return acs_flags & ~flags ? 0 : 1;
4161 }
4162
4163 /*
4164 * These QCOM root ports do provide ACS-like features to disable peer
4165 * transactions and validate bus numbers in requests, but do not provide an
4166 * actual PCIe ACS capability. Hardware supports source validation but it
4167 * will report the issue as Completer Abort instead of ACS Violation.
4168 * Hardware doesn't support peer-to-peer and each root port is a root
4169 * complex with unique segment numbers. It is not possible for one root
4170 * port to pass traffic to another root port. All PCIe transactions are
4171 * terminated inside the root port.
4172 */
4173 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4174 {
4175 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4176 int ret = acs_flags & ~flags ? 0 : 1;
4177
4178 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4179
4180 return ret;
4181 }
4182
4183 /*
4184 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4185 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4186 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4187 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4188 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4189 * control register is at offset 8 instead of 6 and we should probably use
4190 * dword accesses to them. This applies to the following PCI Device IDs, as
4191 * found in volume 1 of the datasheet[2]:
4192 *
4193 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4194 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4195 *
4196 * N.B. This doesn't fix what lspci shows.
4197 *
4198 * The 100 series chipset specification update includes this as errata #23[3].
4199 *
4200 * The 200 series chipset (Union Point) has the same bug according to the
4201 * specification update (Intel 200 Series Chipset Family Platform Controller
4202 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4203 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4204 * chipset include:
4205 *
4206 * 0xa290-0xa29f PCI Express Root port #{0-16}
4207 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4208 *
4209 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4210 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4211 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4212 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4213 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4214 */
4215 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4216 {
4217 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4218 return false;
4219
4220 switch (dev->device) {
4221 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4222 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4223 return true;
4224 }
4225
4226 return false;
4227 }
4228
4229 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4230
4231 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4232 {
4233 int pos;
4234 u32 cap, ctrl;
4235
4236 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4237 return -ENOTTY;
4238
4239 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4240 if (!pos)
4241 return -ENOTTY;
4242
4243 /* see pci_acs_flags_enabled() */
4244 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4245 acs_flags &= (cap | PCI_ACS_EC);
4246
4247 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4248
4249 return acs_flags & ~ctrl ? 0 : 1;
4250 }
4251
4252 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4253 {
4254 /*
4255 * SV, TB, and UF are not relevant to multifunction endpoints.
4256 *
4257 * Multifunction devices are only required to implement RR, CR, and DT
4258 * in their ACS capability if they support peer-to-peer transactions.
4259 * Devices matching this quirk have been verified by the vendor to not
4260 * perform peer-to-peer with other functions, allowing us to mask out
4261 * these bits as if they were unimplemented in the ACS capability.
4262 */
4263 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4264 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4265
4266 return acs_flags ? 0 : 1;
4267 }
4268
4269 static const struct pci_dev_acs_enabled {
4270 u16 vendor;
4271 u16 device;
4272 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4273 } pci_dev_acs_enabled[] = {
4274 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4275 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4276 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4277 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4278 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4279 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4280 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4281 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4282 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4283 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4284 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4285 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4286 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4287 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4288 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4289 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4290 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4291 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4292 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4293 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4294 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4295 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4296 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4297 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4298 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4299 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4300 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4301 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4302 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4303 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4304 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4305 /* 82580 */
4306 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4307 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4308 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4309 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4310 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4311 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4312 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4313 /* 82576 */
4314 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4315 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4316 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4317 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4318 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4319 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4320 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4321 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4322 /* 82575 */
4323 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4324 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4325 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4326 /* I350 */
4327 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4328 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4329 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4330 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4331 /* 82571 (Quads omitted due to non-ACS switch) */
4332 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4333 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4334 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4335 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4336 /* I219 */
4337 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4338 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4339 /* QCOM QDF2xxx root ports */
4340 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4341 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4342 /* Intel PCH root ports */
4343 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4344 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4345 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4346 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4347 /* Cavium ThunderX */
4348 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4349 { 0 }
4350 };
4351
4352 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4353 {
4354 const struct pci_dev_acs_enabled *i;
4355 int ret;
4356
4357 /*
4358 * Allow devices that do not expose standard PCIe ACS capabilities
4359 * or control to indicate their support here. Multi-function express
4360 * devices which do not allow internal peer-to-peer between functions,
4361 * but do not implement PCIe ACS may wish to return true here.
4362 */
4363 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4364 if ((i->vendor == dev->vendor ||
4365 i->vendor == (u16)PCI_ANY_ID) &&
4366 (i->device == dev->device ||
4367 i->device == (u16)PCI_ANY_ID)) {
4368 ret = i->acs_enabled(dev, acs_flags);
4369 if (ret >= 0)
4370 return ret;
4371 }
4372 }
4373
4374 return -ENOTTY;
4375 }
4376
4377 /* Config space offset of Root Complex Base Address register */
4378 #define INTEL_LPC_RCBA_REG 0xf0
4379 /* 31:14 RCBA address */
4380 #define INTEL_LPC_RCBA_MASK 0xffffc000
4381 /* RCBA Enable */
4382 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4383
4384 /* Backbone Scratch Pad Register */
4385 #define INTEL_BSPR_REG 0x1104
4386 /* Backbone Peer Non-Posted Disable */
4387 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4388 /* Backbone Peer Posted Disable */
4389 #define INTEL_BSPR_REG_BPPD (1 << 9)
4390
4391 /* Upstream Peer Decode Configuration Register */
4392 #define INTEL_UPDCR_REG 0x1114
4393 /* 5:0 Peer Decode Enable bits */
4394 #define INTEL_UPDCR_REG_MASK 0x3f
4395
4396 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4397 {
4398 u32 rcba, bspr, updcr;
4399 void __iomem *rcba_mem;
4400
4401 /*
4402 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4403 * are D28:F* and therefore get probed before LPC, thus we can't
4404 * use pci_get_slot/pci_read_config_dword here.
4405 */
4406 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4407 INTEL_LPC_RCBA_REG, &rcba);
4408 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4409 return -EINVAL;
4410
4411 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4412 PAGE_ALIGN(INTEL_UPDCR_REG));
4413 if (!rcba_mem)
4414 return -ENOMEM;
4415
4416 /*
4417 * The BSPR can disallow peer cycles, but it's set by soft strap and
4418 * therefore read-only. If both posted and non-posted peer cycles are
4419 * disallowed, we're ok. If either are allowed, then we need to use
4420 * the UPDCR to disable peer decodes for each port. This provides the
4421 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4422 */
4423 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4424 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4425 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4426 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4427 if (updcr & INTEL_UPDCR_REG_MASK) {
4428 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4429 updcr &= ~INTEL_UPDCR_REG_MASK;
4430 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4431 }
4432 }
4433
4434 iounmap(rcba_mem);
4435 return 0;
4436 }
4437
4438 /* Miscellaneous Port Configuration register */
4439 #define INTEL_MPC_REG 0xd8
4440 /* MPC: Invalid Receive Bus Number Check Enable */
4441 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4442
4443 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4444 {
4445 u32 mpc;
4446
4447 /*
4448 * When enabled, the IRBNCE bit of the MPC register enables the
4449 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4450 * ensures that requester IDs fall within the bus number range
4451 * of the bridge. Enable if not already.
4452 */
4453 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4454 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4455 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4456 mpc |= INTEL_MPC_REG_IRBNCE;
4457 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4458 }
4459 }
4460
4461 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4462 {
4463 if (!pci_quirk_intel_pch_acs_match(dev))
4464 return -ENOTTY;
4465
4466 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4467 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4468 return 0;
4469 }
4470
4471 pci_quirk_enable_intel_rp_mpc_acs(dev);
4472
4473 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4474
4475 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4476
4477 return 0;
4478 }
4479
4480 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4481 {
4482 int pos;
4483 u32 cap, ctrl;
4484
4485 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4486 return -ENOTTY;
4487
4488 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4489 if (!pos)
4490 return -ENOTTY;
4491
4492 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4493 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4494
4495 ctrl |= (cap & PCI_ACS_SV);
4496 ctrl |= (cap & PCI_ACS_RR);
4497 ctrl |= (cap & PCI_ACS_CR);
4498 ctrl |= (cap & PCI_ACS_UF);
4499
4500 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4501
4502 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4503
4504 return 0;
4505 }
4506
4507 static const struct pci_dev_enable_acs {
4508 u16 vendor;
4509 u16 device;
4510 int (*enable_acs)(struct pci_dev *dev);
4511 } pci_dev_enable_acs[] = {
4512 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4513 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4514 { 0 }
4515 };
4516
4517 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4518 {
4519 const struct pci_dev_enable_acs *i;
4520 int ret;
4521
4522 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4523 if ((i->vendor == dev->vendor ||
4524 i->vendor == (u16)PCI_ANY_ID) &&
4525 (i->device == dev->device ||
4526 i->device == (u16)PCI_ANY_ID)) {
4527 ret = i->enable_acs(dev);
4528 if (ret >= 0)
4529 return ret;
4530 }
4531 }
4532
4533 return -ENOTTY;
4534 }
4535
4536 /*
4537 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4538 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4539 * Next Capability pointer in the MSI Capability Structure should point to
4540 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4541 * the list.
4542 */
4543 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4544 {
4545 int pos, i = 0;
4546 u8 next_cap;
4547 u16 reg16, *cap;
4548 struct pci_cap_saved_state *state;
4549
4550 /* Bail if the hardware bug is fixed */
4551 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4552 return;
4553
4554 /* Bail if MSI Capability Structure is not found for some reason */
4555 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4556 if (!pos)
4557 return;
4558
4559 /*
4560 * Bail if Next Capability pointer in the MSI Capability Structure
4561 * is not the expected incorrect 0x00.
4562 */
4563 pci_read_config_byte(pdev, pos + 1, &next_cap);
4564 if (next_cap)
4565 return;
4566
4567 /*
4568 * PCIe Capability Structure is expected to be at 0x50 and should
4569 * terminate the list (Next Capability pointer is 0x00). Verify
4570 * Capability Id and Next Capability pointer is as expected.
4571 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4572 * to correctly set kernel data structures which have already been
4573 * set incorrectly due to the hardware bug.
4574 */
4575 pos = 0x50;
4576 pci_read_config_word(pdev, pos, &reg16);
4577 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4578 u32 status;
4579 #ifndef PCI_EXP_SAVE_REGS
4580 #define PCI_EXP_SAVE_REGS 7
4581 #endif
4582 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4583
4584 pdev->pcie_cap = pos;
4585 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4586 pdev->pcie_flags_reg = reg16;
4587 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4588 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4589
4590 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4591 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4592 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4593 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4594
4595 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4596 return;
4597
4598 /*
4599 * Save PCIE cap
4600 */
4601 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4602 if (!state)
4603 return;
4604
4605 state->cap.cap_nr = PCI_CAP_ID_EXP;
4606 state->cap.cap_extended = 0;
4607 state->cap.size = size;
4608 cap = (u16 *)&state->cap.data[0];
4609 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4610 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4611 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4612 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4613 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4614 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4615 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4616 hlist_add_head(&state->next, &pdev->saved_cap_space);
4617 }
4618 }
4619 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4620
4621 /*
4622 * VMD-enabled root ports will change the source ID for all messages
4623 * to the VMD device. Rather than doing device matching with the source
4624 * ID, the AER driver should traverse the child device tree, reading
4625 * AER registers to find the faulting device.
4626 */
4627 static void quirk_no_aersid(struct pci_dev *pdev)
4628 {
4629 /* VMD Domain */
4630 if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
4631 pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
4632 }
4633 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
4634 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
4635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
4636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
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