1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/ktime.h>
27 #include <linux/nvme.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/switchtec.h>
31 #include <asm/dma.h> /* isa_dma_bridge_buggy */
34 static ktime_t
fixup_debug_start(struct pci_dev
*dev
,
35 void (*fn
)(struct pci_dev
*dev
))
38 pci_info(dev
, "calling %pS @ %i\n", fn
, task_pid_nr(current
));
43 static void fixup_debug_report(struct pci_dev
*dev
, ktime_t calltime
,
44 void (*fn
)(struct pci_dev
*dev
))
46 ktime_t delta
, rettime
;
47 unsigned long long duration
;
49 rettime
= ktime_get();
50 delta
= ktime_sub(rettime
, calltime
);
51 duration
= (unsigned long long) ktime_to_ns(delta
) >> 10;
52 if (initcall_debug
|| duration
> 10000)
53 pci_info(dev
, "%pS took %lld usecs\n", fn
, duration
);
56 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
57 struct pci_fixup
*end
)
62 if ((f
->class == (u32
) (dev
->class >> f
->class_shift
) ||
63 f
->class == (u32
) PCI_ANY_ID
) &&
64 (f
->vendor
== dev
->vendor
||
65 f
->vendor
== (u16
) PCI_ANY_ID
) &&
66 (f
->device
== dev
->device
||
67 f
->device
== (u16
) PCI_ANY_ID
)) {
68 void (*hook
)(struct pci_dev
*dev
);
69 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
70 hook
= offset_to_ptr(&f
->hook_offset
);
74 calltime
= fixup_debug_start(dev
, hook
);
76 fixup_debug_report(dev
, calltime
, hook
);
80 extern struct pci_fixup __start_pci_fixups_early
[];
81 extern struct pci_fixup __end_pci_fixups_early
[];
82 extern struct pci_fixup __start_pci_fixups_header
[];
83 extern struct pci_fixup __end_pci_fixups_header
[];
84 extern struct pci_fixup __start_pci_fixups_final
[];
85 extern struct pci_fixup __end_pci_fixups_final
[];
86 extern struct pci_fixup __start_pci_fixups_enable
[];
87 extern struct pci_fixup __end_pci_fixups_enable
[];
88 extern struct pci_fixup __start_pci_fixups_resume
[];
89 extern struct pci_fixup __end_pci_fixups_resume
[];
90 extern struct pci_fixup __start_pci_fixups_resume_early
[];
91 extern struct pci_fixup __end_pci_fixups_resume_early
[];
92 extern struct pci_fixup __start_pci_fixups_suspend
[];
93 extern struct pci_fixup __end_pci_fixups_suspend
[];
94 extern struct pci_fixup __start_pci_fixups_suspend_late
[];
95 extern struct pci_fixup __end_pci_fixups_suspend_late
[];
97 static bool pci_apply_fixup_final_quirks
;
99 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
101 struct pci_fixup
*start
, *end
;
104 case pci_fixup_early
:
105 start
= __start_pci_fixups_early
;
106 end
= __end_pci_fixups_early
;
109 case pci_fixup_header
:
110 start
= __start_pci_fixups_header
;
111 end
= __end_pci_fixups_header
;
114 case pci_fixup_final
:
115 if (!pci_apply_fixup_final_quirks
)
117 start
= __start_pci_fixups_final
;
118 end
= __end_pci_fixups_final
;
121 case pci_fixup_enable
:
122 start
= __start_pci_fixups_enable
;
123 end
= __end_pci_fixups_enable
;
126 case pci_fixup_resume
:
127 start
= __start_pci_fixups_resume
;
128 end
= __end_pci_fixups_resume
;
131 case pci_fixup_resume_early
:
132 start
= __start_pci_fixups_resume_early
;
133 end
= __end_pci_fixups_resume_early
;
136 case pci_fixup_suspend
:
137 start
= __start_pci_fixups_suspend
;
138 end
= __end_pci_fixups_suspend
;
141 case pci_fixup_suspend_late
:
142 start
= __start_pci_fixups_suspend_late
;
143 end
= __end_pci_fixups_suspend_late
;
147 /* stupid compiler warning, you would think with an enum... */
150 pci_do_fixups(dev
, start
, end
);
152 EXPORT_SYMBOL(pci_fixup_device
);
154 static int __init
pci_apply_final_quirks(void)
156 struct pci_dev
*dev
= NULL
;
160 if (pci_cache_line_size
)
161 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size
<< 2);
163 pci_apply_fixup_final_quirks
= true;
164 for_each_pci_dev(dev
) {
165 pci_fixup_device(pci_fixup_final
, dev
);
167 * If arch hasn't set it explicitly yet, use the CLS
168 * value shared by all PCI devices. If there's a
169 * mismatch, fall back to the default value.
171 if (!pci_cache_line_size
) {
172 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
175 if (!tmp
|| cls
== tmp
)
178 pci_info(dev
, "CLS mismatch (%u != %u), using %u bytes\n",
180 pci_dfl_cache_line_size
<< 2);
181 pci_cache_line_size
= pci_dfl_cache_line_size
;
185 if (!pci_cache_line_size
) {
186 pr_info("PCI: CLS %u bytes, default %u\n", cls
<< 2,
187 pci_dfl_cache_line_size
<< 2);
188 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
193 fs_initcall_sync(pci_apply_final_quirks
);
196 * Decoding should be disabled for a PCI device during BAR sizing to avoid
197 * conflict. But doing so may cause problems on host bridge and perhaps other
198 * key system devices. For devices that need to have mmio decoding always-on,
199 * we need to set the dev->mmio_always_on bit.
201 static void quirk_mmio_always_on(struct pci_dev
*dev
)
203 dev
->mmio_always_on
= 1;
205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
206 PCI_CLASS_BRIDGE_HOST
, 8, quirk_mmio_always_on
);
208 /* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed
209 * by IO resource file, and need to skip the files
211 static void quirk_marvell_mask_bar(struct pci_dev
*dev
)
215 for (i
= 0; i
< 5; i
++)
216 if (dev
->resource
[i
].start
)
217 dev
->resource
[i
].start
=
218 dev
->resource
[i
].end
= 0;
220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9125,
221 quirk_marvell_mask_bar
);
224 * The Mellanox Tavor device gives false positive parity errors. Mark this
225 * device with a broken_parity_status to allow PCI scanning code to "skip"
226 * this now blacklisted device.
228 static void quirk_mellanox_tavor(struct pci_dev
*dev
)
230 dev
->broken_parity_status
= 1; /* This device gives false positives */
232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR
, quirk_mellanox_tavor
);
233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
, quirk_mellanox_tavor
);
236 * Deal with broken BIOSes that neglect to enable passive release,
237 * which can cause problems in combination with the 82441FX/PPro MTRRs
239 static void quirk_passive_release(struct pci_dev
*dev
)
241 struct pci_dev
*d
= NULL
;
245 * We have to make sure a particular bit is set in the PIIX3
246 * ISA bridge, so we have to go out and find it.
248 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
249 pci_read_config_byte(d
, 0x82, &dlc
);
251 pci_info(d
, "PIIX3: Enabling Passive Release\n");
253 pci_write_config_byte(d
, 0x82, dlc
);
257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
258 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
261 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
262 * workaround but VIA don't answer queries. If you happen to have good
263 * contacts at VIA ask them for me please -- Alan
265 * This appears to be BIOS not version dependent. So presumably there is a
268 static void quirk_isa_dma_hangs(struct pci_dev
*dev
)
270 if (!isa_dma_bridge_buggy
) {
271 isa_dma_bridge_buggy
= 1;
272 pci_info(dev
, "Activating ISA DMA hang workarounds\n");
276 * It's not totally clear which chipsets are the problematic ones. We know
277 * 82C586 and 82C596 variants are affected.
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
288 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
289 * for some HT machines to use C4 w/o hanging.
291 static void quirk_tigerpoint_bm_sts(struct pci_dev
*dev
)
296 pci_read_config_dword(dev
, 0x40, &pmbase
);
297 pmbase
= pmbase
& 0xff80;
301 pci_info(dev
, FW_BUG
"TigerPoint LPC.BM_STS cleared\n");
305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_TGP_LPC
, quirk_tigerpoint_bm_sts
);
307 /* Chipsets where PCI->PCI transfers vanish or hang */
308 static void quirk_nopcipci(struct pci_dev
*dev
)
310 if ((pci_pci_problems
& PCIPCI_FAIL
) == 0) {
311 pci_info(dev
, "Disabling direct PCI/PCI transfers\n");
312 pci_pci_problems
|= PCIPCI_FAIL
;
315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
318 static void quirk_nopciamd(struct pci_dev
*dev
)
321 pci_read_config_byte(dev
, 0x08, &rev
);
324 pci_info(dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
325 pci_pci_problems
|= PCIAGP_FAIL
;
328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
330 /* Triton requires workarounds to be used by the drivers */
331 static void quirk_triton(struct pci_dev
*dev
)
333 if ((pci_pci_problems
&PCIPCI_TRITON
) == 0) {
334 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
335 pci_pci_problems
|= PCIPCI_TRITON
;
338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
344 * VIA Apollo KT133 needs PCI latency patch
345 * Made according to a Windows driver-based patch by George E. Breese;
346 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
347 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
348 * which Mr Breese based his work.
350 * Updated based on further information from the site and also on
351 * information provided by VIA
353 static void quirk_vialatency(struct pci_dev
*dev
)
359 * Ok, we have a potential problem chipset here. Now see if we have
360 * a buggy southbridge.
362 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
366 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
368 * Check for buggy part revisions
370 if (p
->revision
< 0x40 || p
->revision
> 0x42)
373 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
374 if (p
== NULL
) /* No problem parts */
377 /* Check for buggy part revisions */
378 if (p
->revision
< 0x10 || p
->revision
> 0x12)
383 * Ok we have the problem. Now set the PCI master grant to occur
384 * every master grant. The apparent bug is that under high PCI load
385 * (quite common in Linux of course) you can get data loss when the
386 * CPU is held off the bus for 3 bus master requests. This happens
387 * to include the IDE controllers....
389 * VIA only apply this fix when an SB Live! is present but under
390 * both Linux and Windows this isn't enough, and we have seen
391 * corruption without SB Live! but with things like 3 UDMA IDE
392 * controllers. So we ignore that bit of the VIA recommendation..
394 pci_read_config_byte(dev
, 0x76, &busarb
);
397 * Set bit 4 and bit 5 of byte 76 to 0x01
398 * "Master priority rotation on every PCI master grant"
402 pci_write_config_byte(dev
, 0x76, busarb
);
403 pci_info(dev
, "Applying VIA southbridge workaround\n");
407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
410 /* Must restore this on a resume from RAM */
411 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
412 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
413 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
415 /* VIA Apollo VP3 needs ETBF on BT848/878 */
416 static void quirk_viaetbf(struct pci_dev
*dev
)
418 if ((pci_pci_problems
&PCIPCI_VIAETBF
) == 0) {
419 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
420 pci_pci_problems
|= PCIPCI_VIAETBF
;
423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
425 static void quirk_vsfx(struct pci_dev
*dev
)
427 if ((pci_pci_problems
&PCIPCI_VSFX
) == 0) {
428 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
429 pci_pci_problems
|= PCIPCI_VSFX
;
432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
435 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
436 * space. Latency must be set to 0xA and Triton workaround applied too.
437 * [Info kindly provided by ALi]
439 static void quirk_alimagik(struct pci_dev
*dev
)
441 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
) == 0) {
442 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
443 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
449 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
450 static void quirk_natoma(struct pci_dev
*dev
)
452 if ((pci_pci_problems
&PCIPCI_NATOMA
) == 0) {
453 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
454 pci_pci_problems
|= PCIPCI_NATOMA
;
457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
465 * This chip can cause PCI parity errors if config register 0xA0 is read
466 * while DMAs are occurring.
468 static void quirk_citrine(struct pci_dev
*dev
)
470 dev
->cfg_size
= 0xA0;
472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
475 * This chip can cause bus lockups if config addresses above 0x600
476 * are read or written.
478 static void quirk_nfp6000(struct pci_dev
*dev
)
480 dev
->cfg_size
= 0x600;
482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP4000
, quirk_nfp6000
);
483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000
, quirk_nfp6000
);
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP5000
, quirk_nfp6000
);
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000_VF
, quirk_nfp6000
);
487 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
488 static void quirk_extend_bar_to_page(struct pci_dev
*dev
)
492 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++) {
493 struct resource
*r
= &dev
->resource
[i
];
495 if (r
->flags
& IORESOURCE_MEM
&& resource_size(r
) < PAGE_SIZE
) {
496 r
->end
= PAGE_SIZE
- 1;
498 r
->flags
|= IORESOURCE_UNSET
;
499 pci_info(dev
, "expanded BAR %d to page size: %pR\n",
504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, 0x034a, quirk_extend_bar_to_page
);
507 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
508 * If it's needed, re-allocate the region.
510 static void quirk_s3_64M(struct pci_dev
*dev
)
512 struct resource
*r
= &dev
->resource
[0];
514 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
515 r
->flags
|= IORESOURCE_UNSET
;
520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
523 static void quirk_io(struct pci_dev
*dev
, int pos
, unsigned size
,
527 struct pci_bus_region bus_region
;
528 struct resource
*res
= dev
->resource
+ pos
;
530 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), ®ion
);
535 res
->name
= pci_name(dev
);
536 res
->flags
= region
& ~PCI_BASE_ADDRESS_IO_MASK
;
538 (IORESOURCE_IO
| IORESOURCE_PCI_FIXED
| IORESOURCE_SIZEALIGN
);
539 region
&= ~(size
- 1);
541 /* Convert from PCI bus to resource space */
542 bus_region
.start
= region
;
543 bus_region
.end
= region
+ size
- 1;
544 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
546 pci_info(dev
, FW_BUG
"%s quirk: reg 0x%x: %pR\n",
547 name
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), res
);
551 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
552 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
553 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
554 * (which conflicts w/ BAR1's memory range).
556 * CS553x's ISA PCI BARs may also be read-only (ref:
557 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
559 static void quirk_cs5536_vsa(struct pci_dev
*dev
)
561 static char *name
= "CS5536 ISA bridge";
563 if (pci_resource_len(dev
, 0) != 8) {
564 quirk_io(dev
, 0, 8, name
); /* SMB */
565 quirk_io(dev
, 1, 256, name
); /* GPIO */
566 quirk_io(dev
, 2, 64, name
); /* MFGPT */
567 pci_info(dev
, "%s bug detected (incorrect header); workaround applied\n",
571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
573 static void quirk_io_region(struct pci_dev
*dev
, int port
,
574 unsigned size
, int nr
, const char *name
)
577 struct pci_bus_region bus_region
;
578 struct resource
*res
= dev
->resource
+ nr
;
580 pci_read_config_word(dev
, port
, ®ion
);
581 region
&= ~(size
- 1);
586 res
->name
= pci_name(dev
);
587 res
->flags
= IORESOURCE_IO
;
589 /* Convert from PCI bus to resource space */
590 bus_region
.start
= region
;
591 bus_region
.end
= region
+ size
- 1;
592 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
594 if (!pci_claim_resource(dev
, nr
))
595 pci_info(dev
, "quirk: %pR claimed by %s\n", res
, name
);
599 * ATI Northbridge setups MCE the processor if you even read somewhere
600 * between 0x3b0->0x3bb or read 0x3d3
602 static void quirk_ati_exploding_mce(struct pci_dev
*dev
)
604 pci_info(dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
605 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
606 request_region(0x3b0, 0x0C, "RadeonIGP");
607 request_region(0x3d3, 0x01, "RadeonIGP");
609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
612 * In the AMD NL platform, this device ([1022:7912]) has a class code of
613 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
616 * But the dwc3 driver is a more specific driver for this device, and we'd
617 * prefer to use it instead of xhci. To prevent xhci from claiming the
618 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
619 * defines as "USB device (not host controller)". The dwc3 driver can then
620 * claim it based on its Vendor and Device ID.
622 static void quirk_amd_nl_class(struct pci_dev
*pdev
)
624 u32
class = pdev
->class;
626 /* Use "USB Device (not host controller)" class */
627 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
628 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_NL_USB
,
635 * Synopsys USB 3.x host HAPS platform has a class code of
636 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
637 * devices should use dwc3-haps driver. Change these devices' class code to
638 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
641 static void quirk_synopsys_haps(struct pci_dev
*pdev
)
643 u32
class = pdev
->class;
645 switch (pdev
->device
) {
646 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3
:
647 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI
:
648 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31
:
649 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
650 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
655 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS
, PCI_ANY_ID
,
656 PCI_CLASS_SERIAL_USB_XHCI
, 0,
657 quirk_synopsys_haps
);
660 * Let's make the southbridge information explicit instead of having to
661 * worry about people probing the ACPI areas, for example.. (Yes, it
662 * happens, and if you read the wrong ACPI register it will put the machine
663 * to sleep with no way of waking it up again. Bummer).
665 * ALI M7101: Two IO regions pointed to by words at
666 * 0xE0 (64 bytes of ACPI registers)
667 * 0xE2 (32 bytes of SMB registers)
669 static void quirk_ali7101_acpi(struct pci_dev
*dev
)
671 quirk_io_region(dev
, 0xE0, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
672 quirk_io_region(dev
, 0xE2, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
676 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
679 u32 mask
, size
, base
;
681 pci_read_config_dword(dev
, port
, &devres
);
682 if ((devres
& enable
) != enable
)
684 mask
= (devres
>> 16) & 15;
685 base
= devres
& 0xffff;
688 unsigned bit
= size
>> 1;
689 if ((bit
& mask
) == bit
)
694 * For now we only print it out. Eventually we'll want to
695 * reserve it (at least if it's in the 0x1000+ range), but
696 * let's get enough confirmation reports first.
699 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
702 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
705 u32 mask
, size
, base
;
707 pci_read_config_dword(dev
, port
, &devres
);
708 if ((devres
& enable
) != enable
)
710 base
= devres
& 0xffff0000;
711 mask
= (devres
& 0x3f) << 16;
714 unsigned bit
= size
>> 1;
715 if ((bit
& mask
) == bit
)
721 * For now we only print it out. Eventually we'll want to
722 * reserve it, but let's get enough confirmation reports first.
725 pci_info(dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
729 * PIIX4 ACPI: Two IO regions pointed to by longwords at
730 * 0x40 (64 bytes of ACPI registers)
731 * 0x90 (16 bytes of SMB registers)
732 * and a few strange programmable PIIX4 device resources.
734 static void quirk_piix4_acpi(struct pci_dev
*dev
)
738 quirk_io_region(dev
, 0x40, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
739 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
741 /* Device resource A has enables for some of the other ones */
742 pci_read_config_dword(dev
, 0x5c, &res_a
);
744 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
745 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
747 /* Device resource D is just bitfields for static resources */
749 /* Device 12 enabled? */
750 if (res_a
& (1 << 29)) {
751 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
752 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
754 /* Device 13 enabled? */
755 if (res_a
& (1 << 30)) {
756 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
757 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
759 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
760 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
765 #define ICH_PMBASE 0x40
766 #define ICH_ACPI_CNTL 0x44
767 #define ICH4_ACPI_EN 0x10
768 #define ICH6_ACPI_EN 0x80
769 #define ICH4_GPIOBASE 0x58
770 #define ICH4_GPIO_CNTL 0x5c
771 #define ICH4_GPIO_EN 0x10
772 #define ICH6_GPIOBASE 0x48
773 #define ICH6_GPIO_CNTL 0x4c
774 #define ICH6_GPIO_EN 0x10
777 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
778 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
779 * 0x58 (64 bytes of GPIO I/O space)
781 static void quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
786 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
787 * with low legacy (and fixed) ports. We don't know the decoding
788 * priority and can't tell whether the legacy device or the one created
789 * here is really at that address. This happens on boards with broken
792 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
793 if (enable
& ICH4_ACPI_EN
)
794 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
795 "ICH4 ACPI/GPIO/TCO");
797 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
798 if (enable
& ICH4_GPIO_EN
)
799 quirk_io_region(dev
, ICH4_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
804 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
805 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
806 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
807 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
808 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
813 static void ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
817 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
818 if (enable
& ICH6_ACPI_EN
)
819 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
820 "ICH6 ACPI/GPIO/TCO");
822 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
823 if (enable
& ICH6_GPIO_EN
)
824 quirk_io_region(dev
, ICH6_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
828 static void ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
829 const char *name
, int dynsize
)
834 pci_read_config_dword(dev
, reg
, &val
);
842 * This is not correct. It is 16, 32 or 64 bytes depending on
843 * register D31:F0:ADh bits 5:4.
845 * But this gets us at least _part_ of it.
854 * Just print it out for now. We should reserve it after more
857 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
860 static void quirk_ich6_lpc(struct pci_dev
*dev
)
862 /* Shared ACPI/GPIO decode with all ICH6+ */
863 ich6_lpc_acpi_gpio(dev
);
865 /* ICH6-specific generic IO decode */
866 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
867 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
872 static void ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
878 pci_read_config_dword(dev
, reg
, &val
);
884 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
886 mask
= (val
>> 16) & 0xfc;
890 * Just print it out for now. We should reserve it after more
893 pci_info(dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
896 /* ICH7-10 has the same common LPC generic IO decode registers */
897 static void quirk_ich7_lpc(struct pci_dev
*dev
)
899 /* We share the common ACPI/GPIO decode with ICH6 */
900 ich6_lpc_acpi_gpio(dev
);
902 /* And have 4 ICH7+ generic decodes */
903 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
904 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
905 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
906 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
923 * VIA ACPI: One IO region pointed to by longword at
924 * 0x48 or 0x20 (256 bytes of ACPI registers)
926 static void quirk_vt82c586_acpi(struct pci_dev
*dev
)
928 if (dev
->revision
& 0x10)
929 quirk_io_region(dev
, 0x48, 256, PCI_BRIDGE_RESOURCES
,
932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
935 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
936 * 0x48 (256 bytes of ACPI registers)
937 * 0x70 (128 bytes of hardware monitoring register)
938 * 0x90 (16 bytes of SMB registers)
940 static void quirk_vt82c686_acpi(struct pci_dev
*dev
)
942 quirk_vt82c586_acpi(dev
);
944 quirk_io_region(dev
, 0x70, 128, PCI_BRIDGE_RESOURCES
+1,
947 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+2, "vt82c686 SMB");
949 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
952 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
953 * 0x88 (128 bytes of power management registers)
954 * 0xd0 (16 bytes of SMB registers)
956 static void quirk_vt8235_acpi(struct pci_dev
*dev
)
958 quirk_io_region(dev
, 0x88, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
959 quirk_io_region(dev
, 0xd0, 16, PCI_BRIDGE_RESOURCES
+1, "vt8235 SMB");
961 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
964 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
965 * back-to-back: Disable fast back-to-back on the secondary bus segment
967 static void quirk_xio2000a(struct pci_dev
*dev
)
969 struct pci_dev
*pdev
;
972 pci_warn(dev
, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
973 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
974 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
975 if (command
& PCI_COMMAND_FAST_BACK
)
976 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
979 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
982 #ifdef CONFIG_X86_IO_APIC
984 #include <asm/io_apic.h>
987 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
988 * devices to the external APIC.
990 * TODO: When we have device-specific interrupt routers, this code will go
993 static void quirk_via_ioapic(struct pci_dev
*dev
)
998 tmp
= 0; /* nothing routed to external APIC */
1000 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
1002 pci_info(dev
, "%sbling VIA external APIC routing\n",
1003 tmp
== 0 ? "Disa" : "Ena");
1005 /* Offset 0x58: External APIC IRQ output control */
1006 pci_write_config_byte(dev
, 0x58, tmp
);
1008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
1009 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
1012 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1013 * This leads to doubled level interrupt rates.
1014 * Set this bit to get rid of cycle wastage.
1015 * Otherwise uncritical.
1017 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
1020 #define BYPASS_APIC_DEASSERT 8
1022 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
1023 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
1024 pci_info(dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
1025 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
1028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
1029 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
1032 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1033 * We check all revs >= B0 (yet not in the pre production!) as the bug
1034 * is currently marked NoFix
1036 * We have multiple reports of hangs with this chipset that went away with
1037 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1038 * of course. However the advice is demonstrably good even if so.
1040 static void quirk_amd_ioapic(struct pci_dev
*dev
)
1042 if (dev
->revision
>= 0x02) {
1043 pci_warn(dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1044 pci_warn(dev
, " : booting with the \"noapic\" option\n");
1047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
1048 #endif /* CONFIG_X86_IO_APIC */
1050 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1052 static void quirk_cavium_sriov_rnm_link(struct pci_dev
*dev
)
1054 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1055 if (dev
->subsystem_device
== 0xa118)
1056 dev
->sriov
->link
= dev
->devfn
;
1058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM
, 0xa018, quirk_cavium_sriov_rnm_link
);
1062 * Some settings of MMRBC can lead to data corruption so block changes.
1063 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1065 static void quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
1067 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
1068 pci_info(dev
, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1070 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
1073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
1076 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1077 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1078 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1079 * of the ACPI SCI interrupt is only done for convenience.
1082 static void quirk_via_acpi(struct pci_dev
*d
)
1086 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1087 pci_read_config_byte(d
, 0x42, &irq
);
1089 if (irq
&& (irq
!= 2))
1092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
1095 /* VIA bridges which have VLink */
1096 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
1098 static void quirk_via_bridge(struct pci_dev
*dev
)
1100 /* See what bridge we have and find the device ranges */
1101 switch (dev
->device
) {
1102 case PCI_DEVICE_ID_VIA_82C686
:
1104 * The VT82C686 is special; it attaches to PCI and can have
1105 * any device number. All its subdevices are functions of
1106 * that single device.
1108 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
1109 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
1111 case PCI_DEVICE_ID_VIA_8237
:
1112 case PCI_DEVICE_ID_VIA_8237A
:
1113 via_vlink_dev_lo
= 15;
1115 case PCI_DEVICE_ID_VIA_8235
:
1116 via_vlink_dev_lo
= 16;
1118 case PCI_DEVICE_ID_VIA_8231
:
1119 case PCI_DEVICE_ID_VIA_8233_0
:
1120 case PCI_DEVICE_ID_VIA_8233A
:
1121 case PCI_DEVICE_ID_VIA_8233C_0
:
1122 via_vlink_dev_lo
= 17;
1126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
1129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
1130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
1131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
1132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
1136 * quirk_via_vlink - VIA VLink IRQ number update
1139 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1140 * the IRQ line register which usually is not relevant for PCI cards, is
1141 * actually written so that interrupts get sent to the right place.
1143 * We only do this on systems where a VIA south bridge was detected, and
1144 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1146 static void quirk_via_vlink(struct pci_dev
*dev
)
1150 /* Check if we have VLink at all */
1151 if (via_vlink_dev_lo
== -1)
1156 /* Don't quirk interrupts outside the legacy IRQ range */
1157 if (!new_irq
|| new_irq
> 15)
1160 /* Internal device ? */
1161 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
1162 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
1166 * This is an internal VLink device on a PIC interrupt. The BIOS
1167 * ought to have set this but may not have, so we redo it.
1169 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1170 if (new_irq
!= irq
) {
1171 pci_info(dev
, "VIA VLink IRQ fixup, from %d to %d\n",
1173 udelay(15); /* unknown if delay really needed */
1174 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
1177 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
1180 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1181 * of VT82C597 for backward compatibility. We need to switch it off to be
1182 * able to recognize the real type of the chip.
1184 static void quirk_vt82c598_id(struct pci_dev
*dev
)
1186 pci_write_config_byte(dev
, 0xfc, 0);
1187 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
1189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
1192 * CardBus controllers have a legacy base address that enables them to
1193 * respond as i82365 pcmcia controllers. We don't want them to do this
1194 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1195 * driver does not (and should not) handle CardBus.
1197 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
1199 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
1201 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1202 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1203 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
1204 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1207 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1208 * what the designers were smoking but let's not inhale...
1210 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1213 static void quirk_amd_ordering(struct pci_dev
*dev
)
1216 pci_read_config_dword(dev
, 0x4C, &pcic
);
1217 if ((pcic
& 6) != 6) {
1219 pci_warn(dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1220 pci_write_config_dword(dev
, 0x4C, pcic
);
1221 pci_read_config_dword(dev
, 0x84, &pcic
);
1222 pcic
|= (1 << 23); /* Required in this mode */
1223 pci_write_config_dword(dev
, 0x84, pcic
);
1226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1227 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1230 * DreamWorks-provided workaround for Dunord I-3000 problem
1232 * This card decodes and responds to addresses not apparently assigned to
1233 * it. We force a larger allocation to ensure that nothing gets put too
1236 static void quirk_dunord(struct pci_dev
*dev
)
1238 struct resource
*r
= &dev
->resource
[1];
1240 r
->flags
|= IORESOURCE_UNSET
;
1244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
1247 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1248 * decoding (transparent), and does indicate this in the ProgIf.
1249 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1251 static void quirk_transparent_bridge(struct pci_dev
*dev
)
1253 dev
->transparent
= 1;
1255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
1256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1259 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1260 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1261 * found at http://www.national.com/analog for info on what these bits do.
1262 * <christer@weinigel.se>
1264 static void quirk_mediagx_master(struct pci_dev
*dev
)
1268 pci_read_config_byte(dev
, 0x41, ®
);
1271 pci_info(dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1273 pci_write_config_byte(dev
, 0x41, reg
);
1276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1277 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1280 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1281 * in the odd case it is not the results are corruption hence the presence
1284 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1288 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1290 pci_read_config_word(pdev
, 0x40, &config
);
1291 if (config
& (1<<6)) {
1293 pci_write_config_word(pdev
, 0x40, config
);
1294 pci_info(pdev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1298 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1300 static void quirk_amd_ide_mode(struct pci_dev
*pdev
)
1302 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1305 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1307 pci_read_config_byte(pdev
, 0x40, &tmp
);
1308 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1309 pci_write_config_byte(pdev
, 0x9, 1);
1310 pci_write_config_byte(pdev
, 0xa, 6);
1311 pci_write_config_byte(pdev
, 0x40, tmp
);
1313 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1314 pci_info(pdev
, "set SATA to AHCI mode\n");
1317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1318 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1320 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1322 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1324 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1326 /* Serverworks CSB5 IDE does not fully support native mode */
1327 static void quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1330 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1334 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1335 /* PCI layer will sort out resources */
1338 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1340 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1341 static void quirk_ide_samemode(struct pci_dev
*pdev
)
1345 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1347 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1348 pci_info(pdev
, "IDE mode mismatch; forcing legacy mode\n");
1351 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1354 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1356 /* Some ATA devices break if put into D3 */
1357 static void quirk_no_ata_d3(struct pci_dev
*pdev
)
1359 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1361 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1362 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
,
1363 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1364 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
1365 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1366 /* ALi loses some register settings that we cannot then restore */
1367 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
,
1368 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1369 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1370 occur when mode detecting */
1371 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
1372 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1375 * This was originally an Alpha-specific thing, but it really fits here.
1376 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1378 static void quirk_eisa_bridge(struct pci_dev
*dev
)
1380 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1385 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1386 * is not activated. The myth is that Asus said that they do not want the
1387 * users to be irritated by just another PCI Device in the Win98 device
1388 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1389 * package 2.7.0 for details)
1391 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1392 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1393 * becomes necessary to do this tweak in two steps -- the chosen trigger
1394 * is either the Host bridge (preferred) or on-board VGA controller.
1396 * Note that we used to unhide the SMBus that way on Toshiba laptops
1397 * (Satellite A40 and Tecra M2) but then found that the thermal management
1398 * was done by SMM code, which could cause unsynchronized concurrent
1399 * accesses to the SMBus registers, with potentially bad effects. Thus you
1400 * should be very careful when adding new entries: if SMM is accessing the
1401 * Intel SMBus, this is a very good reason to leave it hidden.
1403 * Likewise, many recent laptops use ACPI for thermal management. If the
1404 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1405 * natively, and keeping the SMBus hidden is the right thing to do. If you
1406 * are about to add an entry in the table below, please first disassemble
1407 * the DSDT and double-check that there is no code accessing the SMBus.
1409 static int asus_hides_smbus
;
1411 static void asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1413 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1414 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1415 switch (dev
->subsystem_device
) {
1416 case 0x8025: /* P4B-LX */
1417 case 0x8070: /* P4B */
1418 case 0x8088: /* P4B533 */
1419 case 0x1626: /* L3C notebook */
1420 asus_hides_smbus
= 1;
1422 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1423 switch (dev
->subsystem_device
) {
1424 case 0x80b1: /* P4GE-V */
1425 case 0x80b2: /* P4PE */
1426 case 0x8093: /* P4B533-V */
1427 asus_hides_smbus
= 1;
1429 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1430 switch (dev
->subsystem_device
) {
1431 case 0x8030: /* P4T533 */
1432 asus_hides_smbus
= 1;
1434 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1435 switch (dev
->subsystem_device
) {
1436 case 0x8070: /* P4G8X Deluxe */
1437 asus_hides_smbus
= 1;
1439 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1440 switch (dev
->subsystem_device
) {
1441 case 0x80c9: /* PU-DLS */
1442 asus_hides_smbus
= 1;
1444 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1445 switch (dev
->subsystem_device
) {
1446 case 0x1751: /* M2N notebook */
1447 case 0x1821: /* M5N notebook */
1448 case 0x1897: /* A6L notebook */
1449 asus_hides_smbus
= 1;
1451 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1452 switch (dev
->subsystem_device
) {
1453 case 0x184b: /* W1N notebook */
1454 case 0x186a: /* M6Ne notebook */
1455 asus_hides_smbus
= 1;
1457 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1458 switch (dev
->subsystem_device
) {
1459 case 0x80f2: /* P4P800-X */
1460 asus_hides_smbus
= 1;
1462 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1463 switch (dev
->subsystem_device
) {
1464 case 0x1882: /* M6V notebook */
1465 case 0x1977: /* A6VA notebook */
1466 asus_hides_smbus
= 1;
1468 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1469 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1470 switch (dev
->subsystem_device
) {
1471 case 0x088C: /* HP Compaq nc8000 */
1472 case 0x0890: /* HP Compaq nc6000 */
1473 asus_hides_smbus
= 1;
1475 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1476 switch (dev
->subsystem_device
) {
1477 case 0x12bc: /* HP D330L */
1478 case 0x12bd: /* HP D530 */
1479 case 0x006a: /* HP Compaq nx9500 */
1480 asus_hides_smbus
= 1;
1482 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1483 switch (dev
->subsystem_device
) {
1484 case 0x12bf: /* HP xw4100 */
1485 asus_hides_smbus
= 1;
1487 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1488 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1489 switch (dev
->subsystem_device
) {
1490 case 0xC00C: /* Samsung P35 notebook */
1491 asus_hides_smbus
= 1;
1493 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1494 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1495 switch (dev
->subsystem_device
) {
1496 case 0x0058: /* Compaq Evo N620c */
1497 asus_hides_smbus
= 1;
1499 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1500 switch (dev
->subsystem_device
) {
1501 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1502 /* Motherboard doesn't have Host bridge
1503 * subvendor/subdevice IDs, therefore checking
1504 * its on-board VGA controller */
1505 asus_hides_smbus
= 1;
1507 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1508 switch (dev
->subsystem_device
) {
1509 case 0x00b8: /* Compaq Evo D510 CMT */
1510 case 0x00b9: /* Compaq Evo D510 SFF */
1511 case 0x00ba: /* Compaq Evo D510 USDT */
1512 /* Motherboard doesn't have Host bridge
1513 * subvendor/subdevice IDs and on-board VGA
1514 * controller is disabled if an AGP card is
1515 * inserted, therefore checking USB UHCI
1517 asus_hides_smbus
= 1;
1519 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1520 switch (dev
->subsystem_device
) {
1521 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1522 /* Motherboard doesn't have host bridge
1523 * subvendor/subdevice IDs, therefore checking
1524 * its on-board VGA controller */
1525 asus_hides_smbus
= 1;
1529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1531 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1544 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1548 if (likely(!asus_hides_smbus
))
1551 pci_read_config_word(dev
, 0xF2, &val
);
1553 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1554 pci_read_config_word(dev
, 0xF2, &val
);
1556 pci_info(dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1559 pci_info(dev
, "Enabled i801 SMBus device\n");
1562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1567 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1569 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1570 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1571 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1572 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1577 /* It appears we just have one such device. If not, we have a warning */
1578 static void __iomem
*asus_rcba_base
;
1579 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1583 if (likely(!asus_hides_smbus
))
1585 WARN_ON(asus_rcba_base
);
1587 pci_read_config_dword(dev
, 0xF0, &rcba
);
1588 /* use bits 31:14, 16 kB aligned */
1589 asus_rcba_base
= ioremap(rcba
& 0xFFFFC000, 0x4000);
1590 if (asus_rcba_base
== NULL
)
1594 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1598 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1601 /* read the Function Disable register, dword mode only */
1602 val
= readl(asus_rcba_base
+ 0x3418);
1604 /* enable the SMBus device */
1605 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418);
1608 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1610 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1613 iounmap(asus_rcba_base
);
1614 asus_rcba_base
= NULL
;
1615 pci_info(dev
, "Enabled ICH6/i801 SMBus device\n");
1618 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1620 asus_hides_smbus_lpc_ich6_suspend(dev
);
1621 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1622 asus_hides_smbus_lpc_ich6_resume(dev
);
1624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1625 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1626 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1627 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1629 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1630 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1633 pci_read_config_byte(dev
, 0x77, &val
);
1635 pci_info(dev
, "Enabling SiS 96x SMBus\n");
1636 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1643 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1644 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1645 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1646 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1649 * ... This is further complicated by the fact that some SiS96x south
1650 * bridges pretend to be 85C503/5513 instead. In that case see if we
1651 * spotted a compatible north bridge to make sure.
1652 * (pci_find_device() doesn't work yet)
1654 * We can also enable the sis96x bit in the discovery register..
1656 #define SIS_DETECT_REGISTER 0x40
1658 static void quirk_sis_503(struct pci_dev
*dev
)
1663 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1664 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1665 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1666 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1667 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1672 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1673 * it has already been processed. (Depends on link order, which is
1674 * apparently not guaranteed)
1676 dev
->device
= devid
;
1677 quirk_sis_96x_smbus(dev
);
1679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1680 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1683 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1684 * and MC97 modem controller are disabled when a second PCI soundcard is
1685 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1688 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1691 int asus_hides_ac97
= 0;
1693 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1694 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1695 asus_hides_ac97
= 1;
1698 if (!asus_hides_ac97
)
1701 pci_read_config_byte(dev
, 0x50, &val
);
1703 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1704 pci_read_config_byte(dev
, 0x50, &val
);
1706 pci_info(dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1709 pci_info(dev
, "Enabled onboard AC97/MC97 devices\n");
1712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1713 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1715 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1718 * If we are using libata we can drive this chip properly but must do this
1719 * early on to make the additional device appear during the PCI scanning.
1721 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1723 u32 conf1
, conf5
, class;
1726 /* Only poke fn 0 */
1727 if (PCI_FUNC(pdev
->devfn
))
1730 pci_read_config_dword(pdev
, 0x40, &conf1
);
1731 pci_read_config_dword(pdev
, 0x80, &conf5
);
1733 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1734 conf5
&= ~(1 << 24); /* Clear bit 24 */
1736 switch (pdev
->device
) {
1737 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1738 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1739 case PCI_DEVICE_ID_JMICRON_JMB364
: /* SATA dual ports */
1740 /* The controller should be in single function ahci mode */
1741 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1744 case PCI_DEVICE_ID_JMICRON_JMB365
:
1745 case PCI_DEVICE_ID_JMICRON_JMB366
:
1746 /* Redirect IDE second PATA port to the right spot */
1749 case PCI_DEVICE_ID_JMICRON_JMB361
:
1750 case PCI_DEVICE_ID_JMICRON_JMB363
:
1751 case PCI_DEVICE_ID_JMICRON_JMB369
:
1752 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1753 /* Set the class codes correctly and then direct IDE 0 */
1754 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1757 case PCI_DEVICE_ID_JMICRON_JMB368
:
1758 /* The controller should be in single function IDE mode */
1759 conf1
|= 0x00C00000; /* Set 22, 23 */
1763 pci_write_config_dword(pdev
, 0x40, conf1
);
1764 pci_write_config_dword(pdev
, 0x80, conf5
);
1766 /* Update pdev accordingly */
1767 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1768 pdev
->hdr_type
= hdr
& 0x7f;
1769 pdev
->multifunction
= !!(hdr
& 0x80);
1771 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1772 pdev
->class = class >> 8;
1774 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1775 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1776 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1777 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1778 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1779 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1780 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1781 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1782 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1783 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1784 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1785 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1786 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1787 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1788 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1789 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1790 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1791 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1795 static void quirk_jmicron_async_suspend(struct pci_dev
*dev
)
1797 if (dev
->multifunction
) {
1798 device_disable_async_suspend(&dev
->dev
);
1799 pci_info(dev
, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1802 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_IDE
, 8, quirk_jmicron_async_suspend
);
1803 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_SATA_AHCI
, 0, quirk_jmicron_async_suspend
);
1804 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x2362, quirk_jmicron_async_suspend
);
1805 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x236f, quirk_jmicron_async_suspend
);
1807 #ifdef CONFIG_X86_IO_APIC
1808 static void quirk_alder_ioapic(struct pci_dev
*pdev
)
1812 if ((pdev
->class >> 8) != 0xff00)
1816 * The first BAR is the location of the IO-APIC... we must
1817 * not touch this (and it's already covered by the fixmap), so
1818 * forcibly insert it into the resource tree.
1820 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1821 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1824 * The next five BARs all seem to be rubbish, so just clean
1827 for (i
= 1; i
< PCI_STD_NUM_BARS
; i
++)
1828 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1833 static void quirk_pcie_mch(struct pci_dev
*pdev
)
1837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1841 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI
, 0x1610, PCI_CLASS_BRIDGE_PCI
, 8, quirk_pcie_mch
);
1844 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1845 * together on certain PXH-based systems.
1847 static void quirk_pcie_pxh(struct pci_dev
*dev
)
1850 pci_warn(dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1852 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1853 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1854 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1855 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1859 * Some Intel PCI Express chipsets have trouble with downstream device
1862 static void quirk_intel_pcie_pm(struct pci_dev
*dev
)
1864 pci_pm_d3hot_delay
= 120;
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1889 static void quirk_d3hot_delay(struct pci_dev
*dev
, unsigned int delay
)
1891 if (dev
->d3hot_delay
>= delay
)
1894 dev
->d3hot_delay
= delay
;
1895 pci_info(dev
, "extending delay after power-on from D3hot to %d msec\n",
1899 static void quirk_radeon_pm(struct pci_dev
*dev
)
1901 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
&&
1902 dev
->subsystem_device
== 0x00e2)
1903 quirk_d3hot_delay(dev
, 20);
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6741, quirk_radeon_pm
);
1908 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1909 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1911 * The kernel attempts to transition these devices to D3cold, but that seems
1912 * to be ineffective on the platforms in question; the PCI device appears to
1913 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1914 * extended delay in order to succeed.
1916 static void quirk_ryzen_xhci_d3hot(struct pci_dev
*dev
)
1918 quirk_d3hot_delay(dev
, 20);
1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x15e0, quirk_ryzen_xhci_d3hot
);
1921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x15e1, quirk_ryzen_xhci_d3hot
);
1923 #ifdef CONFIG_X86_IO_APIC
1924 static int dmi_disable_ioapicreroute(const struct dmi_system_id
*d
)
1926 noioapicreroute
= 1;
1927 pr_info("%s detected: disable boot interrupt reroute\n", d
->ident
);
1932 static const struct dmi_system_id boot_interrupt_dmi_table
[] = {
1934 * Systems to exclude from boot interrupt reroute quirks
1937 .callback
= dmi_disable_ioapicreroute
,
1938 .ident
= "ASUSTek Computer INC. M2N-LR",
1940 DMI_MATCH(DMI_SYS_VENDOR
, "ASUSTek Computer INC."),
1941 DMI_MATCH(DMI_PRODUCT_NAME
, "M2N-LR"),
1948 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1949 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1950 * that a PCI device's interrupt handler is installed on the boot interrupt
1953 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1955 dmi_check_system(boot_interrupt_dmi_table
);
1956 if (noioapicquirk
|| noioapicreroute
)
1959 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1960 pci_info(dev
, "rerouting interrupts for [%04x:%04x]\n",
1961 dev
->vendor
, dev
->device
);
1963 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1967 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1971 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1972 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1973 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1974 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1975 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1976 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1977 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1978 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1981 * On some chipsets we can disable the generation of legacy INTx boot
1986 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1987 * 300641-004US, section 5.7.3.
1989 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1990 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1991 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1992 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1993 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1994 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1995 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1996 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1997 * Core IO on Xeon Scalable, see Intel order no 610950.
1999 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
2000 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
2002 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
2003 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
2005 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
2007 u16 pci_config_word
;
2008 u32 pci_config_dword
;
2013 switch (dev
->device
) {
2014 case PCI_DEVICE_ID_INTEL_ESB_10
:
2015 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
,
2017 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
2018 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
,
2021 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2022 case 0x0e28: /* Xeon E5/E7 V2 */
2023 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2024 case 0x6f28: /* Xeon D-1500 */
2025 case 0x2034: /* Xeon Scalable Family */
2026 pci_read_config_dword(dev
, INTEL_CIPINTRC_CFG_OFFSET
,
2028 pci_config_dword
|= INTEL_CIPINTRC_DIS_INTX_ICH
;
2029 pci_write_config_dword(dev
, INTEL_CIPINTRC_CFG_OFFSET
,
2035 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2036 dev
->vendor
, dev
->device
);
2039 * Device 29 Func 5 Device IDs of IO-APIC
2040 * containing ABAR—APIC1 Alternate Base Address Register
2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
,
2043 quirk_disable_intel_boot_interrupt
);
2044 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
,
2045 quirk_disable_intel_boot_interrupt
);
2048 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2049 * containing Coherent Interface Protocol Interrupt Control
2051 * Device IDs obtained from volume 2 datasheets of commented
2054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x3c28,
2055 quirk_disable_intel_boot_interrupt
);
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0e28,
2057 quirk_disable_intel_boot_interrupt
);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2f28,
2059 quirk_disable_intel_boot_interrupt
);
2060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x6f28,
2061 quirk_disable_intel_boot_interrupt
);
2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2034,
2063 quirk_disable_intel_boot_interrupt
);
2064 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x3c28,
2065 quirk_disable_intel_boot_interrupt
);
2066 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x0e28,
2067 quirk_disable_intel_boot_interrupt
);
2068 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x2f28,
2069 quirk_disable_intel_boot_interrupt
);
2070 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x6f28,
2071 quirk_disable_intel_boot_interrupt
);
2072 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x2034,
2073 quirk_disable_intel_boot_interrupt
);
2075 /* Disable boot interrupts on HT-1000 */
2076 #define BC_HT1000_FEATURE_REG 0x64
2077 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2078 #define BC_HT1000_MAP_IDX 0xC00
2079 #define BC_HT1000_MAP_DATA 0xC01
2081 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
2083 u32 pci_config_dword
;
2089 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
2090 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
2091 BC_HT1000_PIC_REGS_ENABLE
);
2093 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
2094 outb(irq
, BC_HT1000_MAP_IDX
);
2095 outb(0x00, BC_HT1000_MAP_DATA
);
2098 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
2100 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2101 dev
->vendor
, dev
->device
);
2103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
2104 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
2106 /* Disable boot interrupts on AMD and ATI chipsets */
2109 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2110 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2111 * (due to an erratum).
2113 #define AMD_813X_MISC 0x40
2114 #define AMD_813X_NOIOAMODE (1<<0)
2115 #define AMD_813X_REV_B1 0x12
2116 #define AMD_813X_REV_B2 0x13
2118 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
2120 u32 pci_config_dword
;
2124 if ((dev
->revision
== AMD_813X_REV_B1
) ||
2125 (dev
->revision
== AMD_813X_REV_B2
))
2128 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
2129 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
2130 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
2132 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2133 dev
->vendor
, dev
->device
);
2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2136 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2138 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2140 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2142 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
2144 u16 pci_config_word
;
2149 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
2150 if (!pci_config_word
) {
2151 pci_info(dev
, "boot interrupts on device [%04x:%04x] already disabled\n",
2152 dev
->vendor
, dev
->device
);
2155 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
2156 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2157 dev
->vendor
, dev
->device
);
2159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2160 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2161 #endif /* CONFIG_X86_IO_APIC */
2164 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2165 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2166 * Re-allocate the region if needed...
2168 static void quirk_tc86c001_ide(struct pci_dev
*dev
)
2170 struct resource
*r
= &dev
->resource
[0];
2172 if (r
->start
& 0x8) {
2173 r
->flags
|= IORESOURCE_UNSET
;
2178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
2179 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
2180 quirk_tc86c001_ide
);
2183 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2184 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2185 * being read correctly if bit 7 of the base address is set.
2186 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2187 * Re-allocate the regions to a 256-byte boundary if necessary.
2189 static void quirk_plx_pci9050(struct pci_dev
*dev
)
2193 /* Fixed in revision 2 (PCI 9052). */
2194 if (dev
->revision
>= 2)
2196 for (bar
= 0; bar
<= 1; bar
++)
2197 if (pci_resource_len(dev
, bar
) == 0x80 &&
2198 (pci_resource_start(dev
, bar
) & 0x80)) {
2199 struct resource
*r
= &dev
->resource
[bar
];
2200 pci_info(dev
, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2202 r
->flags
|= IORESOURCE_UNSET
;
2207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2210 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2211 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2212 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2213 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2215 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2218 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050
);
2219 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050
);
2221 static void quirk_netmos(struct pci_dev
*dev
)
2223 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
2224 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
2227 * These Netmos parts are multiport serial devices with optional
2228 * parallel ports. Even when parallel ports are present, they
2229 * are identified as class SERIAL, which means the serial driver
2230 * will claim them. To prevent this, mark them as class OTHER.
2231 * These combo devices should be claimed by parport_serial.
2233 * The subdevice ID is of the form 0x00PS, where <P> is the number
2234 * of parallel ports and <S> is the number of serial ports.
2236 switch (dev
->device
) {
2237 case PCI_DEVICE_ID_NETMOS_9835
:
2238 /* Well, this rule doesn't hold for the following 9835 device */
2239 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
2240 dev
->subsystem_device
== 0x0299)
2243 case PCI_DEVICE_ID_NETMOS_9735
:
2244 case PCI_DEVICE_ID_NETMOS_9745
:
2245 case PCI_DEVICE_ID_NETMOS_9845
:
2246 case PCI_DEVICE_ID_NETMOS_9855
:
2248 pci_info(dev
, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2249 dev
->device
, num_parallel
, num_serial
);
2250 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
2251 (dev
->class & 0xff);
2255 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
,
2256 PCI_CLASS_COMMUNICATION_SERIAL
, 8, quirk_netmos
);
2258 static void quirk_e100_interrupt(struct pci_dev
*dev
)
2264 switch (dev
->device
) {
2265 /* PCI IDs taken from drivers/net/e100.c */
2267 case 0x1030 ... 0x1034:
2268 case 0x1038 ... 0x103E:
2269 case 0x1050 ... 0x1057:
2271 case 0x1064 ... 0x106B:
2272 case 0x1091 ... 0x1095:
2285 * Some firmware hands off the e100 with interrupts enabled,
2286 * which can cause a flood of interrupts if packets are
2287 * received before the driver attaches to the device. So
2288 * disable all e100 interrupts here. The driver will
2289 * re-enable them when it's ready.
2291 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
2293 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
2297 * Check that the device is in the D0 power state. If it's not,
2298 * there is no point to look any further.
2301 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2302 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
2306 /* Convert from PCI bus to resource space. */
2307 csr
= ioremap(pci_resource_start(dev
, 0), 8);
2309 pci_warn(dev
, "Can't map e100 registers\n");
2313 cmd_hi
= readb(csr
+ 3);
2315 pci_warn(dev
, "Firmware left e100 interrupts enabled; disabling\n");
2321 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
2322 PCI_CLASS_NETWORK_ETHERNET
, 8, quirk_e100_interrupt
);
2325 * The 82575 and 82598 may experience data corruption issues when transitioning
2326 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2328 static void quirk_disable_aspm_l0s(struct pci_dev
*dev
)
2330 pci_info(dev
, "Disabling L0s\n");
2331 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
2333 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
2334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
2335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
2336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
2337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
2338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
2339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
2340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
2341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
2342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
2343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
2344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
2345 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
2346 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
2348 static void quirk_disable_aspm_l0s_l1(struct pci_dev
*dev
)
2350 pci_info(dev
, "Disabling ASPM L0s/L1\n");
2351 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
);
2355 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2356 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2357 * disable both L0s and L1 for now to be safe.
2359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA
, 0x1080, quirk_disable_aspm_l0s_l1
);
2362 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2363 * Link bit cleared after starting the link retrain process to allow this
2364 * process to finish.
2366 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2367 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2369 static void quirk_enable_clear_retrain_link(struct pci_dev
*dev
)
2371 dev
->clear_retrain_link
= 1;
2372 pci_info(dev
, "Enable PCIe Retrain Link quirk\n");
2374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM
, 0xe110, quirk_enable_clear_retrain_link
);
2375 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM
, 0xe111, quirk_enable_clear_retrain_link
);
2376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM
, 0xe130, quirk_enable_clear_retrain_link
);
2378 static void fixup_rev1_53c810(struct pci_dev
*dev
)
2380 u32
class = dev
->class;
2383 * rev 1 ncr53c810 chips don't set the class at all which means
2384 * they don't get their resources remapped. Fix that here.
2389 dev
->class = PCI_CLASS_STORAGE_SCSI
<< 8;
2390 pci_info(dev
, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2393 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
2395 /* Enable 1k I/O space granularity on the Intel P64H2 */
2396 static void quirk_p64h2_1k_io(struct pci_dev
*dev
)
2400 pci_read_config_word(dev
, 0x40, &en1k
);
2403 pci_info(dev
, "Enable I/O Space to 1KB granularity\n");
2404 dev
->io_window_1k
= 1;
2407 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
2410 * Under some circumstances, AER is not linked with extended capabilities.
2411 * Force it to be linked by setting the corresponding control bit in the
2414 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
2418 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
2420 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
2421 pci_info(dev
, "Linking AER extended capability\n");
2425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2426 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2427 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2428 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2430 static void quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2433 * Disable PCI Bus Parking and PCI Master read caching on CX700
2434 * which causes unspecified timing errors with a VT6212L on the PCI
2435 * bus leading to USB2.0 packet loss.
2437 * This quirk is only enabled if a second (on the external PCI bus)
2438 * VT6212L is found -- the CX700 core itself also contains a USB
2439 * host controller with the same PCI ID as the VT6212L.
2442 /* Count VT6212L instances */
2443 struct pci_dev
*p
= pci_get_device(PCI_VENDOR_ID_VIA
,
2444 PCI_DEVICE_ID_VIA_8235_USB_2
, NULL
);
2448 * p should contain the first (internal) VT6212L -- see if we have
2449 * an external one by searching again.
2451 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235_USB_2
, p
);
2456 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2458 /* Turn off PCI Bus Parking */
2459 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2461 pci_info(dev
, "Disabling VIA CX700 PCI parking\n");
2465 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2467 /* Turn off PCI Master read caching */
2468 pci_write_config_byte(dev
, 0x72, 0x0);
2470 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2471 pci_write_config_byte(dev
, 0x75, 0x1);
2473 /* Disable "Read FIFO Timer" */
2474 pci_write_config_byte(dev
, 0x77, 0x0);
2476 pci_info(dev
, "Disabling VIA CX700 PCI caching\n");
2480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2482 static void quirk_brcm_5719_limit_mrrs(struct pci_dev
*dev
)
2486 pci_read_config_dword(dev
, 0xf4, &rev
);
2488 /* Only CAP the MRRS if the device is a 5719 A0 */
2489 if (rev
== 0x05719000) {
2490 int readrq
= pcie_get_readrq(dev
);
2492 pcie_set_readrq(dev
, 2048);
2495 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM
,
2496 PCI_DEVICE_ID_TIGON3_5719
,
2497 quirk_brcm_5719_limit_mrrs
);
2500 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2501 * hide device 6 which configures the overflow device access containing the
2502 * DRBs - this is where we expose device 6.
2503 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2505 static void quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2509 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2510 pci_info(dev
, "Enabling MCH 'Overflow' Device\n");
2511 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2514 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2515 quirk_unhide_mch_dev6
);
2516 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2517 quirk_unhide_mch_dev6
);
2519 #ifdef CONFIG_PCI_MSI
2521 * Some chipsets do not support MSI. We cannot easily rely on setting
2522 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2523 * other buses controlled by the chipset even if Linux is not aware of it.
2524 * Instead of setting the flag on all buses in the machine, simply disable
2527 static void quirk_disable_all_msi(struct pci_dev
*dev
)
2530 pci_warn(dev
, "MSI quirk detected; MSI disabled\n");
2532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2534 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2535 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8380_0
, quirk_disable_all_msi
);
2539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, 0x0761, quirk_disable_all_msi
);
2540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG
, 0xa5e3, quirk_disable_all_msi
);
2542 /* Disable MSI on chipsets that are known to not support it */
2543 static void quirk_disable_msi(struct pci_dev
*dev
)
2545 if (dev
->subordinate
) {
2546 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2547 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2555 * The APC bridge device in AMD 780 family northbridges has some random
2556 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2557 * we use the possible vendor/device IDs of the host bridge for the
2558 * declared quirk, and search for the APC bridge by slot number.
2560 static void quirk_amd_780_apc_msi(struct pci_dev
*host_bridge
)
2562 struct pci_dev
*apc_bridge
;
2564 apc_bridge
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(1, 0));
2566 if (apc_bridge
->device
== 0x9602)
2567 quirk_disable_msi(apc_bridge
);
2568 pci_dev_put(apc_bridge
);
2571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9600, quirk_amd_780_apc_msi
);
2572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9601, quirk_amd_780_apc_msi
);
2575 * Go through the list of HyperTransport capabilities and return 1 if a HT
2576 * MSI capability is found and enabled.
2578 static int msi_ht_cap_enabled(struct pci_dev
*dev
)
2580 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2582 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2583 while (pos
&& ttl
--) {
2586 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2588 pci_info(dev
, "Found %s HT MSI Mapping\n",
2589 flags
& HT_MSI_FLAGS_ENABLE
?
2590 "enabled" : "disabled");
2591 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2594 pos
= pci_find_next_ht_capability(dev
, pos
,
2595 HT_CAPTYPE_MSI_MAPPING
);
2600 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2601 static void quirk_msi_ht_cap(struct pci_dev
*dev
)
2603 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
2604 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2605 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2612 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2613 * if the MSI capability is set in any of these mappings.
2615 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2617 struct pci_dev
*pdev
;
2619 if (!dev
->subordinate
)
2623 * Check HT MSI cap on this chipset and the root one. A single one
2624 * having MSI is enough to be sure that MSI is supported.
2626 pdev
= pci_get_slot(dev
->bus
, 0);
2629 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
2630 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2631 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2636 quirk_nvidia_ck804_msi_ht_cap
);
2638 /* Force enable MSI mapping capability on HT bridges */
2639 static void ht_enable_msi_mapping(struct pci_dev
*dev
)
2641 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2643 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2644 while (pos
&& ttl
--) {
2647 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2649 pci_info(dev
, "Enabling HT MSI Mapping\n");
2651 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2652 flags
| HT_MSI_FLAGS_ENABLE
);
2654 pos
= pci_find_next_ht_capability(dev
, pos
,
2655 HT_CAPTYPE_MSI_MAPPING
);
2658 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2659 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2660 ht_enable_msi_mapping
);
2661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2662 ht_enable_msi_mapping
);
2665 * The P5N32-SLI motherboards from Asus have a problem with MSI
2666 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2667 * also affects other devices. As for now, turn off MSI for this device.
2669 static void nvenet_msi_disable(struct pci_dev
*dev
)
2671 const char *board_name
= dmi_get_system_info(DMI_BOARD_NAME
);
2674 (strstr(board_name
, "P5N32-SLI PREMIUM") ||
2675 strstr(board_name
, "P5N32-E SLI"))) {
2676 pci_info(dev
, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2680 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2681 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2682 nvenet_msi_disable
);
2685 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2686 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2687 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2688 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2689 * for other events, since PCIe specificiation doesn't support using a mix of
2690 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2691 * service drivers registering their respective ISRs for MSIs.
2693 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev
*dev
)
2697 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x1ad0,
2698 PCI_CLASS_BRIDGE_PCI
, 8,
2699 pci_quirk_nvidia_tegra_disable_rp_msi
);
2700 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x1ad1,
2701 PCI_CLASS_BRIDGE_PCI
, 8,
2702 pci_quirk_nvidia_tegra_disable_rp_msi
);
2703 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x1ad2,
2704 PCI_CLASS_BRIDGE_PCI
, 8,
2705 pci_quirk_nvidia_tegra_disable_rp_msi
);
2706 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0bf0,
2707 PCI_CLASS_BRIDGE_PCI
, 8,
2708 pci_quirk_nvidia_tegra_disable_rp_msi
);
2709 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0bf1,
2710 PCI_CLASS_BRIDGE_PCI
, 8,
2711 pci_quirk_nvidia_tegra_disable_rp_msi
);
2712 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e1c,
2713 PCI_CLASS_BRIDGE_PCI
, 8,
2714 pci_quirk_nvidia_tegra_disable_rp_msi
);
2715 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e1d,
2716 PCI_CLASS_BRIDGE_PCI
, 8,
2717 pci_quirk_nvidia_tegra_disable_rp_msi
);
2718 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e12,
2719 PCI_CLASS_BRIDGE_PCI
, 8,
2720 pci_quirk_nvidia_tegra_disable_rp_msi
);
2721 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e13,
2722 PCI_CLASS_BRIDGE_PCI
, 8,
2723 pci_quirk_nvidia_tegra_disable_rp_msi
);
2724 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0fae,
2725 PCI_CLASS_BRIDGE_PCI
, 8,
2726 pci_quirk_nvidia_tegra_disable_rp_msi
);
2727 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0faf,
2728 PCI_CLASS_BRIDGE_PCI
, 8,
2729 pci_quirk_nvidia_tegra_disable_rp_msi
);
2730 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x10e5,
2731 PCI_CLASS_BRIDGE_PCI
, 8,
2732 pci_quirk_nvidia_tegra_disable_rp_msi
);
2733 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x10e6,
2734 PCI_CLASS_BRIDGE_PCI
, 8,
2735 pci_quirk_nvidia_tegra_disable_rp_msi
);
2738 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2739 * config register. This register controls the routing of legacy
2740 * interrupts from devices that route through the MCP55. If this register
2741 * is misprogrammed, interrupts are only sent to the BSP, unlike
2742 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2743 * having this register set properly prevents kdump from booting up
2744 * properly, so let's make sure that we have it set correctly.
2745 * Note that this is an undocumented register.
2747 static void nvbridge_check_legacy_irq_routing(struct pci_dev
*dev
)
2751 if (!pci_find_capability(dev
, PCI_CAP_ID_HT
))
2754 pci_read_config_dword(dev
, 0x74, &cfg
);
2756 if (cfg
& ((1 << 2) | (1 << 15))) {
2757 pr_info("Rewriting IRQ routing register on MCP55\n");
2758 cfg
&= ~((1 << 2) | (1 << 15));
2759 pci_write_config_dword(dev
, 0x74, cfg
);
2762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2763 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
,
2764 nvbridge_check_legacy_irq_routing
);
2765 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2766 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
,
2767 nvbridge_check_legacy_irq_routing
);
2769 static int ht_check_msi_mapping(struct pci_dev
*dev
)
2771 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2774 /* Check if there is HT MSI cap or enabled on this device */
2775 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2776 while (pos
&& ttl
--) {
2781 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2783 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2790 pos
= pci_find_next_ht_capability(dev
, pos
,
2791 HT_CAPTYPE_MSI_MAPPING
);
2797 static int host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2799 struct pci_dev
*dev
;
2804 dev_no
= host_bridge
->devfn
>> 3;
2805 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2806 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2810 /* found next host bridge? */
2811 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2817 if (ht_check_msi_mapping(dev
)) {
2828 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2829 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2831 static int is_end_of_ht_chain(struct pci_dev
*dev
)
2837 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2842 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2844 ctrl_off
= ((flags
>> 10) & 1) ?
2845 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2846 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2848 if (ctrl
& (1 << 6))
2855 static void nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2857 struct pci_dev
*host_bridge
;
2862 dev_no
= dev
->devfn
>> 3;
2863 for (i
= dev_no
; i
>= 0; i
--) {
2864 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2868 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2873 pci_dev_put(host_bridge
);
2879 /* don't enable end_device/host_bridge with leaf directly here */
2880 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2881 host_bridge_with_leaf(host_bridge
))
2884 /* root did that ! */
2885 if (msi_ht_cap_enabled(host_bridge
))
2888 ht_enable_msi_mapping(dev
);
2891 pci_dev_put(host_bridge
);
2894 static void ht_disable_msi_mapping(struct pci_dev
*dev
)
2896 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2898 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2899 while (pos
&& ttl
--) {
2902 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2904 pci_info(dev
, "Disabling HT MSI Mapping\n");
2906 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2907 flags
& ~HT_MSI_FLAGS_ENABLE
);
2909 pos
= pci_find_next_ht_capability(dev
, pos
,
2910 HT_CAPTYPE_MSI_MAPPING
);
2914 static void __nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2916 struct pci_dev
*host_bridge
;
2920 if (!pci_msi_enabled())
2923 /* check if there is HT MSI cap or enabled on this device */
2924 found
= ht_check_msi_mapping(dev
);
2931 * HT MSI mapping should be disabled on devices that are below
2932 * a non-Hypertransport host bridge. Locate the host bridge...
2934 host_bridge
= pci_get_domain_bus_and_slot(pci_domain_nr(dev
->bus
), 0,
2936 if (host_bridge
== NULL
) {
2937 pci_warn(dev
, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2941 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2943 /* Host bridge is to HT */
2945 /* it is not enabled, try to enable it */
2947 ht_enable_msi_mapping(dev
);
2949 nv_ht_enable_msi_mapping(dev
);
2954 /* HT MSI is not enabled */
2958 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2959 ht_disable_msi_mapping(dev
);
2962 pci_dev_put(host_bridge
);
2965 static void nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2967 return __nv_msi_ht_cap_quirk(dev
, 1);
2969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2970 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2972 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2974 return __nv_msi_ht_cap_quirk(dev
, 0);
2976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2977 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2979 static void quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2981 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2984 static void quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2989 * SB700 MSI issue will be fixed at HW level from revision A21;
2990 * we need check PCI REVISION ID of SMBus controller to get SB700
2993 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2998 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2999 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
3003 static void quirk_msi_intx_disable_qca_bug(struct pci_dev
*dev
)
3005 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3006 if (dev
->revision
< 0x18) {
3007 pci_info(dev
, "set MSI_INTX_DISABLE_BUG flag\n");
3008 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
3011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3012 PCI_DEVICE_ID_TIGON3_5780
,
3013 quirk_msi_intx_disable_bug
);
3014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3015 PCI_DEVICE_ID_TIGON3_5780S
,
3016 quirk_msi_intx_disable_bug
);
3017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3018 PCI_DEVICE_ID_TIGON3_5714
,
3019 quirk_msi_intx_disable_bug
);
3020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3021 PCI_DEVICE_ID_TIGON3_5714S
,
3022 quirk_msi_intx_disable_bug
);
3023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3024 PCI_DEVICE_ID_TIGON3_5715
,
3025 quirk_msi_intx_disable_bug
);
3026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3027 PCI_DEVICE_ID_TIGON3_5715S
,
3028 quirk_msi_intx_disable_bug
);
3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
3031 quirk_msi_intx_disable_ati_bug
);
3032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
3033 quirk_msi_intx_disable_ati_bug
);
3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
3035 quirk_msi_intx_disable_ati_bug
);
3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
3037 quirk_msi_intx_disable_ati_bug
);
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
3039 quirk_msi_intx_disable_ati_bug
);
3041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
3042 quirk_msi_intx_disable_bug
);
3043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
3044 quirk_msi_intx_disable_bug
);
3045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
3046 quirk_msi_intx_disable_bug
);
3048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1062,
3049 quirk_msi_intx_disable_bug
);
3050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1063,
3051 quirk_msi_intx_disable_bug
);
3052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2060,
3053 quirk_msi_intx_disable_bug
);
3054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2062,
3055 quirk_msi_intx_disable_bug
);
3056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1073,
3057 quirk_msi_intx_disable_bug
);
3058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1083,
3059 quirk_msi_intx_disable_bug
);
3060 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1090,
3061 quirk_msi_intx_disable_qca_bug
);
3062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1091,
3063 quirk_msi_intx_disable_qca_bug
);
3064 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a0,
3065 quirk_msi_intx_disable_qca_bug
);
3066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a1,
3067 quirk_msi_intx_disable_qca_bug
);
3068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0xe091,
3069 quirk_msi_intx_disable_qca_bug
);
3072 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3073 * should be disabled on platforms where the device (mistakenly) advertises it.
3075 * Notice that this quirk also disables MSI (which may work, but hasn't been
3076 * tested), since currently there is no standard way to disable only MSI-X.
3078 * The 0031 device id is reused for other non Root Port device types,
3079 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3081 static void quirk_al_msi_disable(struct pci_dev
*dev
)
3084 pci_warn(dev
, "Disabling MSI/MSI-X\n");
3086 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS
, 0x0031,
3087 PCI_CLASS_BRIDGE_PCI
, 8, quirk_al_msi_disable
);
3088 #endif /* CONFIG_PCI_MSI */
3091 * Allow manual resource allocation for PCI hotplug bridges via
3092 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3093 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3094 * allocate resources when hotplug device is inserted and PCI bus is
3097 static void quirk_hotplug_bridge(struct pci_dev
*dev
)
3099 dev
->is_hotplug_bridge
= 1;
3101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0020, quirk_hotplug_bridge
);
3104 * This is a quirk for the Ricoh MMC controller found as a part of some
3105 * multifunction chips.
3107 * This is very similar and based on the ricoh_mmc driver written by
3108 * Philip Langdale. Thank you for these magic sequences.
3110 * These chips implement the four main memory card controllers (SD, MMC,
3111 * MS, xD) and one or both of CardBus or FireWire.
3113 * It happens that they implement SD and MMC support as separate
3114 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3115 * cards but the chip detects MMC cards in hardware and directs them to the
3116 * MMC controller - so the SDHCI driver never sees them.
3118 * To get around this, we must disable the useless MMC controller. At that
3119 * point, the SDHCI controller will start seeing them. It seems to be the
3120 * case that the relevant PCI registers to deactivate the MMC controller
3121 * live on PCI function 0, which might be the CardBus controller or the
3122 * FireWire controller, depending on the particular chip in question
3124 * This has to be done early, because as soon as we disable the MMC controller
3125 * other PCI functions shift up one level, e.g. function #2 becomes function
3126 * #1, and this will confuse the PCI core.
3128 #ifdef CONFIG_MMC_RICOH_MMC
3129 static void ricoh_mmc_fixup_rl5c476(struct pci_dev
*dev
)
3136 * Disable via CardBus interface
3138 * This must be done via function #0
3140 if (PCI_FUNC(dev
->devfn
))
3143 pci_read_config_byte(dev
, 0xB7, &disable
);
3147 pci_read_config_byte(dev
, 0x8E, &write_enable
);
3148 pci_write_config_byte(dev
, 0x8E, 0xAA);
3149 pci_read_config_byte(dev
, 0x8D, &write_target
);
3150 pci_write_config_byte(dev
, 0x8D, 0xB7);
3151 pci_write_config_byte(dev
, 0xB7, disable
| 0x02);
3152 pci_write_config_byte(dev
, 0x8E, write_enable
);
3153 pci_write_config_byte(dev
, 0x8D, write_target
);
3155 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3156 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3158 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
3159 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
3161 static void ricoh_mmc_fixup_r5c832(struct pci_dev
*dev
)
3167 * Disable via FireWire interface
3169 * This must be done via function #0
3171 if (PCI_FUNC(dev
->devfn
))
3174 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3175 * certain types of SD/MMC cards. Lowering the SD base clock
3176 * frequency from 200Mhz to 50Mhz fixes this issue.
3178 * 0x150 - SD2.0 mode enable for changing base clock
3179 * frequency to 50Mhz
3180 * 0xe1 - Base clock frequency
3181 * 0x32 - 50Mhz new clock frequency
3182 * 0xf9 - Key register for 0x150
3183 * 0xfc - key register for 0xe1
3185 if (dev
->device
== PCI_DEVICE_ID_RICOH_R5CE822
||
3186 dev
->device
== PCI_DEVICE_ID_RICOH_R5CE823
) {
3187 pci_write_config_byte(dev
, 0xf9, 0xfc);
3188 pci_write_config_byte(dev
, 0x150, 0x10);
3189 pci_write_config_byte(dev
, 0xf9, 0x00);
3190 pci_write_config_byte(dev
, 0xfc, 0x01);
3191 pci_write_config_byte(dev
, 0xe1, 0x32);
3192 pci_write_config_byte(dev
, 0xfc, 0x00);
3194 pci_notice(dev
, "MMC controller base frequency changed to 50Mhz.\n");
3197 pci_read_config_byte(dev
, 0xCB, &disable
);
3202 pci_read_config_byte(dev
, 0xCA, &write_enable
);
3203 pci_write_config_byte(dev
, 0xCA, 0x57);
3204 pci_write_config_byte(dev
, 0xCB, disable
| 0x02);
3205 pci_write_config_byte(dev
, 0xCA, write_enable
);
3207 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3208 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3211 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3212 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3213 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3214 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3215 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3216 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3217 #endif /*CONFIG_MMC_RICOH_MMC*/
3219 #ifdef CONFIG_DMAR_TABLE
3220 #define VTUNCERRMSK_REG 0x1ac
3221 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3223 * This is a quirk for masking VT-d spec-defined errors to platform error
3224 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3225 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3226 * on the RAS config settings of the platform) when a VT-d fault happens.
3227 * The resulting SMI caused the system to hang.
3229 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3230 * need to report the same error through other channels.
3232 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
3236 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
3237 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
3239 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
3240 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
3243 static void fixup_ti816x_class(struct pci_dev
*dev
)
3245 u32
class = dev
->class;
3247 /* TI 816x devices do not have class code set when in PCIe boot mode */
3248 dev
->class = PCI_CLASS_MULTIMEDIA_VIDEO
<< 8;
3249 pci_info(dev
, "PCI class overridden (%#08x -> %#08x)\n",
3252 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI
, 0xb800,
3253 PCI_CLASS_NOT_DEFINED
, 8, fixup_ti816x_class
);
3256 * Some PCIe devices do not work reliably with the claimed maximum
3257 * payload size supported.
3259 static void fixup_mpss_256(struct pci_dev
*dev
)
3261 dev
->pcie_mpss
= 1; /* 256 bytes */
3263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3264 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0
, fixup_mpss_256
);
3265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3266 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
, fixup_mpss_256
);
3267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3268 PCI_DEVICE_ID_SOLARFLARE_SFC4000B
, fixup_mpss_256
);
3271 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3272 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3273 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3274 * until all of the devices are discovered and buses walked, read completion
3275 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3276 * it is possible to hotplug a device with MPS of 256B.
3278 static void quirk_intel_mc_errata(struct pci_dev
*dev
)
3283 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
3284 pcie_bus_config
== PCIE_BUS_DEFAULT
)
3288 * Intel erratum specifies bits to change but does not say what
3289 * they are. Keeping them magical until such time as the registers
3290 * and values can be explained.
3292 err
= pci_read_config_word(dev
, 0x48, &rcc
);
3294 pci_err(dev
, "Error attempting to read the read completion coalescing register\n");
3298 if (!(rcc
& (1 << 10)))
3303 err
= pci_write_config_word(dev
, 0x48, rcc
);
3305 pci_err(dev
, "Error attempting to write the read completion coalescing register\n");
3309 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3311 /* Intel 5000 series memory controllers and ports 2-7 */
3312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25c0, quirk_intel_mc_errata
);
3313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d0, quirk_intel_mc_errata
);
3314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d4, quirk_intel_mc_errata
);
3315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d8, quirk_intel_mc_errata
);
3316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_mc_errata
);
3317 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_mc_errata
);
3318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_mc_errata
);
3319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_mc_errata
);
3320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_mc_errata
);
3321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_mc_errata
);
3322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_mc_errata
);
3323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_mc_errata
);
3324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_mc_errata
);
3325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_mc_errata
);
3326 /* Intel 5100 series memory controllers and ports 2-7 */
3327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65c0, quirk_intel_mc_errata
);
3328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e2, quirk_intel_mc_errata
);
3329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e3, quirk_intel_mc_errata
);
3330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e4, quirk_intel_mc_errata
);
3331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e5, quirk_intel_mc_errata
);
3332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e6, quirk_intel_mc_errata
);
3333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e7, quirk_intel_mc_errata
);
3334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f7, quirk_intel_mc_errata
);
3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f8, quirk_intel_mc_errata
);
3336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f9, quirk_intel_mc_errata
);
3337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65fa, quirk_intel_mc_errata
);
3340 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3341 * To work around this, query the size it should be configured to by the
3342 * device and modify the resource end to correspond to this new size.
3344 static void quirk_intel_ntb(struct pci_dev
*dev
)
3349 rc
= pci_read_config_byte(dev
, 0x00D0, &val
);
3353 dev
->resource
[2].end
= dev
->resource
[2].start
+ ((u64
) 1 << val
) - 1;
3355 rc
= pci_read_config_byte(dev
, 0x00D1, &val
);
3359 dev
->resource
[4].end
= dev
->resource
[4].start
+ ((u64
) 1 << val
) - 1;
3361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e08, quirk_intel_ntb
);
3362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e0d, quirk_intel_ntb
);
3365 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3366 * though no one is handling them (e.g., if the i915 driver is never
3367 * loaded). Additionally the interrupt destination is not set up properly
3368 * and the interrupt ends up -somewhere-.
3370 * These spurious interrupts are "sticky" and the kernel disables the
3371 * (shared) interrupt line after 100,000+ generated interrupts.
3373 * Fix it by disabling the still enabled interrupts. This resolves crashes
3374 * often seen on monitor unplug.
3376 #define I915_DEIER_REG 0x4400c
3377 static void disable_igfx_irq(struct pci_dev
*dev
)
3379 void __iomem
*regs
= pci_iomap(dev
, 0, 0);
3381 pci_warn(dev
, "igfx quirk: Can't iomap PCI device\n");
3385 /* Check if any interrupt line is still enabled */
3386 if (readl(regs
+ I915_DEIER_REG
) != 0) {
3387 pci_warn(dev
, "BIOS left Intel GPU interrupts enabled; disabling\n");
3389 writel(0, regs
+ I915_DEIER_REG
);
3392 pci_iounmap(dev
, regs
);
3394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0042, disable_igfx_irq
);
3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0046, disable_igfx_irq
);
3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x004a, disable_igfx_irq
);
3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0102, disable_igfx_irq
);
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0106, disable_igfx_irq
);
3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x010a, disable_igfx_irq
);
3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0152, disable_igfx_irq
);
3403 * PCI devices which are on Intel chips can skip the 10ms delay
3404 * before entering D3 mode.
3406 static void quirk_remove_d3hot_delay(struct pci_dev
*dev
)
3408 dev
->d3hot_delay
= 0;
3410 /* C600 Series devices do not need 10ms d3hot_delay */
3411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0412, quirk_remove_d3hot_delay
);
3412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c00, quirk_remove_d3hot_delay
);
3413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c0c, quirk_remove_d3hot_delay
);
3414 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c02, quirk_remove_d3hot_delay
);
3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c18, quirk_remove_d3hot_delay
);
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c1c, quirk_remove_d3hot_delay
);
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c20, quirk_remove_d3hot_delay
);
3419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c22, quirk_remove_d3hot_delay
);
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c26, quirk_remove_d3hot_delay
);
3421 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c2d, quirk_remove_d3hot_delay
);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c31, quirk_remove_d3hot_delay
);
3423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3a, quirk_remove_d3hot_delay
);
3424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3d, quirk_remove_d3hot_delay
);
3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c4e, quirk_remove_d3hot_delay
);
3426 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2280, quirk_remove_d3hot_delay
);
3428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2298, quirk_remove_d3hot_delay
);
3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x229c, quirk_remove_d3hot_delay
);
3430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b0, quirk_remove_d3hot_delay
);
3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b5, quirk_remove_d3hot_delay
);
3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b7, quirk_remove_d3hot_delay
);
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b8, quirk_remove_d3hot_delay
);
3434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22d8, quirk_remove_d3hot_delay
);
3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22dc, quirk_remove_d3hot_delay
);
3438 * Some devices may pass our check in pci_intx_mask_supported() if
3439 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3440 * support this feature.
3442 static void quirk_broken_intx_masking(struct pci_dev
*dev
)
3444 dev
->broken_intx_masking
= 1;
3446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO
, 0x0030,
3447 quirk_broken_intx_masking
);
3448 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3449 quirk_broken_intx_masking
);
3450 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3451 quirk_broken_intx_masking
);
3454 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3455 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3457 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK
, 0x8169,
3460 quirk_broken_intx_masking
);
3463 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3464 * DisINTx can be set but the interrupt status bit is non-functional.
3466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1572, quirk_broken_intx_masking
);
3467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1574, quirk_broken_intx_masking
);
3468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1580, quirk_broken_intx_masking
);
3469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1581, quirk_broken_intx_masking
);
3470 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1583, quirk_broken_intx_masking
);
3471 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1584, quirk_broken_intx_masking
);
3472 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1585, quirk_broken_intx_masking
);
3473 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1586, quirk_broken_intx_masking
);
3474 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1587, quirk_broken_intx_masking
);
3475 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1588, quirk_broken_intx_masking
);
3476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1589, quirk_broken_intx_masking
);
3477 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158a, quirk_broken_intx_masking
);
3478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158b, quirk_broken_intx_masking
);
3479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d0, quirk_broken_intx_masking
);
3480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d1, quirk_broken_intx_masking
);
3481 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d2, quirk_broken_intx_masking
);
3483 static u16 mellanox_broken_intx_devs
[] = {
3484 PCI_DEVICE_ID_MELLANOX_HERMON_SDR
,
3485 PCI_DEVICE_ID_MELLANOX_HERMON_DDR
,
3486 PCI_DEVICE_ID_MELLANOX_HERMON_QDR
,
3487 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2
,
3488 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2
,
3489 PCI_DEVICE_ID_MELLANOX_HERMON_EN
,
3490 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2
,
3491 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN
,
3492 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2
,
3493 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2
,
3494 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2
,
3495 PCI_DEVICE_ID_MELLANOX_CONNECTX2
,
3496 PCI_DEVICE_ID_MELLANOX_CONNECTX3
,
3497 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO
,
3500 #define CONNECTX_4_CURR_MAX_MINOR 99
3501 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3504 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3505 * If so, don't mark it as broken.
3506 * FW minor > 99 means older FW version format and no INTx masking support.
3507 * FW minor < 14 means new FW version format and no INTx masking support.
3509 static void mellanox_check_broken_intx_masking(struct pci_dev
*pdev
)
3511 __be32 __iomem
*fw_ver
;
3519 for (i
= 0; i
< ARRAY_SIZE(mellanox_broken_intx_devs
); i
++) {
3520 if (pdev
->device
== mellanox_broken_intx_devs
[i
]) {
3521 pdev
->broken_intx_masking
= 1;
3527 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3528 * support so shouldn't be checked further
3530 if (pdev
->device
== PCI_DEVICE_ID_MELLANOX_CONNECTIB
)
3533 if (pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4
&&
3534 pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
)
3537 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3538 if (pci_enable_device_mem(pdev
)) {
3539 pci_warn(pdev
, "Can't enable device memory\n");
3543 fw_ver
= ioremap(pci_resource_start(pdev
, 0), 4);
3545 pci_warn(pdev
, "Can't map ConnectX-4 initialization segment\n");
3549 /* Reading from resource space should be 32b aligned */
3550 fw_maj_min
= ioread32be(fw_ver
);
3551 fw_sub_min
= ioread32be(fw_ver
+ 1);
3552 fw_major
= fw_maj_min
& 0xffff;
3553 fw_minor
= fw_maj_min
>> 16;
3554 fw_subminor
= fw_sub_min
& 0xffff;
3555 if (fw_minor
> CONNECTX_4_CURR_MAX_MINOR
||
3556 fw_minor
< CONNECTX_4_INTX_SUPPORT_MINOR
) {
3557 pci_warn(pdev
, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3558 fw_major
, fw_minor
, fw_subminor
, pdev
->device
==
3559 PCI_DEVICE_ID_MELLANOX_CONNECTX4
? 12 : 14);
3560 pdev
->broken_intx_masking
= 1;
3566 pci_disable_device(pdev
);
3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_ANY_ID
,
3569 mellanox_check_broken_intx_masking
);
3571 static void quirk_no_bus_reset(struct pci_dev
*dev
)
3573 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_BUS_RESET
;
3577 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3578 * The device will throw a Link Down error on AER-capable systems and
3579 * regardless of AER, config space of the device is never accessible again
3580 * and typically causes the system to hang or reset when access is attempted.
3581 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0030, quirk_no_bus_reset
);
3584 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0032, quirk_no_bus_reset
);
3585 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x003c, quirk_no_bus_reset
);
3586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0033, quirk_no_bus_reset
);
3587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0034, quirk_no_bus_reset
);
3590 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3591 * reset when used with certain child devices. After the reset, config
3592 * accesses to the child may fail.
3594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM
, 0xa100, quirk_no_bus_reset
);
3596 static void quirk_no_pm_reset(struct pci_dev
*dev
)
3599 * We can't do a bus reset on root bus devices, but an ineffective
3600 * PM reset may be better than nothing.
3602 if (!pci_is_root_bus(dev
->bus
))
3603 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_PM_RESET
;
3607 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3608 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3609 * to have no effect on the device: it retains the framebuffer contents and
3610 * monitor sync. Advertising this support makes other layers, like VFIO,
3611 * assume pci_reset_function() is viable for this device. Mark it as
3612 * unavailable to skip it when testing reset methods.
3614 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
3615 PCI_CLASS_DISPLAY_VGA
, 8, quirk_no_pm_reset
);
3618 * Thunderbolt controllers with broken MSI hotplug signaling:
3619 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3620 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3622 static void quirk_thunderbolt_hotplug_msi(struct pci_dev
*pdev
)
3624 if (pdev
->is_hotplug_bridge
&&
3625 (pdev
->device
!= PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
||
3626 pdev
->revision
<= 1))
3629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
,
3630 quirk_thunderbolt_hotplug_msi
);
3631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE
,
3632 quirk_thunderbolt_hotplug_msi
);
3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_PEAK
,
3634 quirk_thunderbolt_hotplug_msi
);
3635 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3636 quirk_thunderbolt_hotplug_msi
);
3637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PORT_RIDGE
,
3638 quirk_thunderbolt_hotplug_msi
);
3642 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3644 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3645 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3646 * be present after resume if a device was plugged in before suspend.
3648 * The Thunderbolt controller consists of a PCIe switch with downstream
3649 * bridges leading to the NHI and to the tunnel PCI bridges.
3651 * This quirk cuts power to the whole chip. Therefore we have to apply it
3652 * during suspend_noirq of the upstream bridge.
3654 * Power is automagically restored before resume. No action is needed.
3656 static void quirk_apple_poweroff_thunderbolt(struct pci_dev
*dev
)
3658 acpi_handle bridge
, SXIO
, SXFP
, SXLV
;
3660 if (!x86_apple_machine
)
3662 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
)
3664 bridge
= ACPI_HANDLE(&dev
->dev
);
3669 * SXIO and SXLV are present only on machines requiring this quirk.
3670 * Thunderbolt bridges in external devices might have the same
3671 * device ID as those on the host, but they will not have the
3672 * associated ACPI methods. This implicitly checks that we are at
3675 if (ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXIO", &SXIO
))
3676 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXFP", &SXFP
))
3677 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXLV", &SXLV
)))
3679 pci_info(dev
, "quirk: cutting power to Thunderbolt controller...\n");
3681 /* magic sequence */
3682 acpi_execute_simple_method(SXIO
, NULL
, 1);
3683 acpi_execute_simple_method(SXFP
, NULL
, 0);
3685 acpi_execute_simple_method(SXLV
, NULL
, 0);
3686 acpi_execute_simple_method(SXIO
, NULL
, 0);
3687 acpi_execute_simple_method(SXLV
, NULL
, 0);
3689 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL
,
3690 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3691 quirk_apple_poweroff_thunderbolt
);
3695 * Following are device-specific reset methods which can be used to
3696 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3699 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
3702 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3704 * The 82599 supports FLR on VFs, but FLR support is reported only
3705 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3706 * Thus we must call pcie_flr() directly without first checking if it is
3714 #define SOUTH_CHICKEN2 0xc2004
3715 #define PCH_PP_STATUS 0xc7200
3716 #define PCH_PP_CONTROL 0xc7204
3717 #define MSG_CTL 0x45010
3718 #define NSDE_PWR_STATE 0xd0100
3719 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3721 static int reset_ivb_igd(struct pci_dev
*dev
, int probe
)
3723 void __iomem
*mmio_base
;
3724 unsigned long timeout
;
3730 mmio_base
= pci_iomap(dev
, 0, 0);
3734 iowrite32(0x00000002, mmio_base
+ MSG_CTL
);
3737 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3738 * driver loaded sets the right bits. However, this's a reset and
3739 * the bits have been set by i915 previously, so we clobber
3740 * SOUTH_CHICKEN2 register directly here.
3742 iowrite32(0x00000005, mmio_base
+ SOUTH_CHICKEN2
);
3744 val
= ioread32(mmio_base
+ PCH_PP_CONTROL
) & 0xfffffffe;
3745 iowrite32(val
, mmio_base
+ PCH_PP_CONTROL
);
3747 timeout
= jiffies
+ msecs_to_jiffies(IGD_OPERATION_TIMEOUT
);
3749 val
= ioread32(mmio_base
+ PCH_PP_STATUS
);
3750 if ((val
& 0xb0000000) == 0)
3751 goto reset_complete
;
3753 } while (time_before(jiffies
, timeout
));
3754 pci_warn(dev
, "timeout during reset\n");
3757 iowrite32(0x00000002, mmio_base
+ NSDE_PWR_STATE
);
3759 pci_iounmap(dev
, mmio_base
);
3763 /* Device-specific reset method for Chelsio T4-based adapters */
3764 static int reset_chelsio_generic_dev(struct pci_dev
*dev
, int probe
)
3770 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3771 * that we have no device-specific reset method.
3773 if ((dev
->device
& 0xf000) != 0x4000)
3777 * If this is the "probe" phase, return 0 indicating that we can
3778 * reset this device.
3784 * T4 can wedge if there are DMAs in flight within the chip and Bus
3785 * Master has been disabled. We need to have it on till the Function
3786 * Level Reset completes. (BUS_MASTER is disabled in
3787 * pci_reset_function()).
3789 pci_read_config_word(dev
, PCI_COMMAND
, &old_command
);
3790 pci_write_config_word(dev
, PCI_COMMAND
,
3791 old_command
| PCI_COMMAND_MASTER
);
3794 * Perform the actual device function reset, saving and restoring
3795 * configuration information around the reset.
3797 pci_save_state(dev
);
3800 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3801 * are disabled when an MSI-X interrupt message needs to be delivered.
3802 * So we briefly re-enable MSI-X interrupts for the duration of the
3803 * FLR. The pci_restore_state() below will restore the original
3806 pci_read_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
, &msix_flags
);
3807 if ((msix_flags
& PCI_MSIX_FLAGS_ENABLE
) == 0)
3808 pci_write_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
,
3810 PCI_MSIX_FLAGS_ENABLE
|
3811 PCI_MSIX_FLAGS_MASKALL
);
3816 * Restore the configuration information (BAR values, etc.) including
3817 * the original PCI Configuration Space Command word, and return
3820 pci_restore_state(dev
);
3821 pci_write_config_word(dev
, PCI_COMMAND
, old_command
);
3825 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3826 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3827 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3830 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3831 * FLR where config space reads from the device return -1. We seem to be
3832 * able to avoid this condition if we disable the NVMe controller prior to
3833 * FLR. This quirk is generic for any NVMe class device requiring similar
3834 * assistance to quiesce the device prior to FLR.
3836 * NVMe specification: https://nvmexpress.org/resources/specifications/
3838 * Chapter 2: Required and optional PCI config registers
3839 * Chapter 3: NVMe control registers
3840 * Chapter 7.3: Reset behavior
3842 static int nvme_disable_and_flr(struct pci_dev
*dev
, int probe
)
3848 if (dev
->class != PCI_CLASS_STORAGE_EXPRESS
||
3849 !pcie_has_flr(dev
) || !pci_resource_start(dev
, 0))
3855 bar
= pci_iomap(dev
, 0, NVME_REG_CC
+ sizeof(cfg
));
3859 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3860 pci_write_config_word(dev
, PCI_COMMAND
, cmd
| PCI_COMMAND_MEMORY
);
3862 cfg
= readl(bar
+ NVME_REG_CC
);
3864 /* Disable controller if enabled */
3865 if (cfg
& NVME_CC_ENABLE
) {
3866 u32 cap
= readl(bar
+ NVME_REG_CAP
);
3867 unsigned long timeout
;
3870 * Per nvme_disable_ctrl() skip shutdown notification as it
3871 * could complete commands to the admin queue. We only intend
3872 * to quiesce the device before reset.
3874 cfg
&= ~(NVME_CC_SHN_MASK
| NVME_CC_ENABLE
);
3876 writel(cfg
, bar
+ NVME_REG_CC
);
3879 * Some controllers require an additional delay here, see
3880 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3881 * supported by this quirk.
3884 /* Cap register provides max timeout in 500ms increments */
3885 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
3888 u32 status
= readl(bar
+ NVME_REG_CSTS
);
3890 /* Ready status becomes zero on disable complete */
3891 if (!(status
& NVME_CSTS_RDY
))
3896 if (time_after(jiffies
, timeout
)) {
3897 pci_warn(dev
, "Timeout waiting for NVMe ready status to clear after disable\n");
3903 pci_iounmap(dev
, bar
);
3911 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3912 * to change after NVMe enable if the driver starts interacting with the
3913 * device too soon after FLR. A 250ms delay after FLR has heuristically
3914 * proven to produce reliably working results for device assignment cases.
3916 static int delay_250ms_after_flr(struct pci_dev
*dev
, int probe
)
3918 if (!pcie_has_flr(dev
))
3931 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
3932 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
3933 reset_intel_82599_sfp_virtfn
},
3934 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M_VGA
,
3936 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M2_VGA
,
3938 { PCI_VENDOR_ID_SAMSUNG
, 0xa804, nvme_disable_and_flr
},
3939 { PCI_VENDOR_ID_INTEL
, 0x0953, delay_250ms_after_flr
},
3940 { PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
3941 reset_chelsio_generic_dev
},
3946 * These device-specific reset methods are here rather than in a driver
3947 * because when a host assigns a device to a guest VM, the host may need
3948 * to reset the device but probably doesn't have a driver for it.
3950 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
3952 const struct pci_dev_reset_methods
*i
;
3954 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
3955 if ((i
->vendor
== dev
->vendor
||
3956 i
->vendor
== (u16
)PCI_ANY_ID
) &&
3957 (i
->device
== dev
->device
||
3958 i
->device
== (u16
)PCI_ANY_ID
))
3959 return i
->reset(dev
, probe
);
3965 static void quirk_dma_func0_alias(struct pci_dev
*dev
)
3967 if (PCI_FUNC(dev
->devfn
) != 0)
3968 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0), 1);
3972 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3974 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe832, quirk_dma_func0_alias
);
3977 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe476, quirk_dma_func0_alias
);
3979 static void quirk_dma_func1_alias(struct pci_dev
*dev
)
3981 if (PCI_FUNC(dev
->devfn
) != 1)
3982 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 1), 1);
3986 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3987 * SKUs function 1 is present and is a legacy IDE controller, in other
3988 * SKUs this function is not present, making this a ghost requester.
3989 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9120,
3992 quirk_dma_func1_alias
);
3993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9123,
3994 quirk_dma_func1_alias
);
3995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9128,
3996 quirk_dma_func1_alias
);
3997 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9130,
3999 quirk_dma_func1_alias
);
4000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9170,
4001 quirk_dma_func1_alias
);
4002 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9172,
4004 quirk_dma_func1_alias
);
4005 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x917a,
4007 quirk_dma_func1_alias
);
4008 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9182,
4010 quirk_dma_func1_alias
);
4011 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9183,
4013 quirk_dma_func1_alias
);
4014 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x91a0,
4016 quirk_dma_func1_alias
);
4017 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9215,
4019 quirk_dma_func1_alias
);
4020 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9220,
4022 quirk_dma_func1_alias
);
4023 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9230,
4025 quirk_dma_func1_alias
);
4026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0642,
4027 quirk_dma_func1_alias
);
4028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0645,
4029 quirk_dma_func1_alias
);
4030 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4031 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON
,
4032 PCI_DEVICE_ID_JMICRON_JMB388_ESD
,
4033 quirk_dma_func1_alias
);
4034 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4035 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4036 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4037 quirk_dma_func1_alias
);
4040 * Some devices DMA with the wrong devfn, not just the wrong function.
4041 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4042 * the alias is "fixed" and independent of the device devfn.
4044 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4045 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4046 * single device on the secondary bus. In reality, the single exposed
4047 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4048 * that provides a bridge to the internal bus of the I/O processor. The
4049 * controller supports private devices, which can be hidden from PCI config
4050 * space. In the case of the Adaptec 3405, a private device at 01.0
4051 * appears to be the DMA engine, which therefore needs to become a DMA
4052 * alias for the device.
4054 static const struct pci_device_id fixed_dma_alias_tbl
[] = {
4055 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
4056 PCI_VENDOR_ID_ADAPTEC2
, 0x02bb), /* Adaptec 3405 */
4057 .driver_data
= PCI_DEVFN(1, 0) },
4058 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
4059 PCI_VENDOR_ID_ADAPTEC2
, 0x02bc), /* Adaptec 3805 */
4060 .driver_data
= PCI_DEVFN(1, 0) },
4064 static void quirk_fixed_dma_alias(struct pci_dev
*dev
)
4066 const struct pci_device_id
*id
;
4068 id
= pci_match_id(fixed_dma_alias_tbl
, dev
);
4070 pci_add_dma_alias(dev
, id
->driver_data
, 1);
4072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2
, 0x0285, quirk_fixed_dma_alias
);
4075 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4076 * using the wrong DMA alias for the device. Some of these devices can be
4077 * used as either forward or reverse bridges, so we need to test whether the
4078 * device is operating in the correct mode. We could probably apply this
4079 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4080 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4081 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4083 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev
*pdev
)
4085 if (!pci_is_root_bus(pdev
->bus
) &&
4086 pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
4087 !pci_is_pcie(pdev
) && pci_is_pcie(pdev
->bus
->self
) &&
4088 pci_pcie_type(pdev
->bus
->self
) != PCI_EXP_TYPE_PCI_BRIDGE
)
4089 pdev
->dev_flags
|= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
;
4091 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA
, 0x1080,
4093 quirk_use_pcie_bridge_dma_alias
);
4094 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4095 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias
);
4096 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4097 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias
);
4098 /* ITE 8893 has the same problem as the 8892 */
4099 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias
);
4100 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4101 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias
);
4104 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4105 * be added as aliases to the DMA device in order to allow buffer access
4106 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4107 * programmed in the EEPROM.
4109 static void quirk_mic_x200_dma_alias(struct pci_dev
*pdev
)
4111 pci_add_dma_alias(pdev
, PCI_DEVFN(0x10, 0x0), 1);
4112 pci_add_dma_alias(pdev
, PCI_DEVFN(0x11, 0x0), 1);
4113 pci_add_dma_alias(pdev
, PCI_DEVFN(0x12, 0x3), 1);
4115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2260, quirk_mic_x200_dma_alias
);
4116 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2264, quirk_mic_x200_dma_alias
);
4119 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4120 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4122 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4123 * when IOMMU is enabled. These aliases allow computational unit access to
4124 * host memory. These aliases mark the whole VCA device as one IOMMU
4127 * All possible slot numbers (0x20) are used, since we are unable to tell
4128 * what slot is used on other side. This quirk is intended for both host
4129 * and computational unit sides. The VCA devices have up to five functions
4130 * (four for DMA channels and one additional).
4132 static void quirk_pex_vca_alias(struct pci_dev
*pdev
)
4134 const unsigned int num_pci_slots
= 0x20;
4137 for (slot
= 0; slot
< num_pci_slots
; slot
++)
4138 pci_add_dma_alias(pdev
, PCI_DEVFN(slot
, 0x0), 5);
4140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2954, quirk_pex_vca_alias
);
4141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2955, quirk_pex_vca_alias
);
4142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2956, quirk_pex_vca_alias
);
4143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2958, quirk_pex_vca_alias
);
4144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2959, quirk_pex_vca_alias
);
4145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x295A, quirk_pex_vca_alias
);
4148 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4149 * associated not at the root bus, but at a bridge below. This quirk avoids
4150 * generating invalid DMA aliases.
4152 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev
*pdev
)
4154 pdev
->dev_flags
|= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
;
4156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9000,
4157 quirk_bridge_cavm_thrx2_pcie_root
);
4158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9084,
4159 quirk_bridge_cavm_thrx2_pcie_root
);
4162 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4163 * class code. Fix it.
4165 static void quirk_tw686x_class(struct pci_dev
*pdev
)
4167 u32
class = pdev
->class;
4169 /* Use "Multimedia controller" class */
4170 pdev
->class = (PCI_CLASS_MULTIMEDIA_OTHER
<< 8) | 0x01;
4171 pci_info(pdev
, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4172 class, pdev
->class);
4174 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED
, 8,
4175 quirk_tw686x_class
);
4176 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED
, 8,
4177 quirk_tw686x_class
);
4178 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED
, 8,
4179 quirk_tw686x_class
);
4180 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED
, 8,
4181 quirk_tw686x_class
);
4184 * Some devices have problems with Transaction Layer Packets with the Relaxed
4185 * Ordering Attribute set. Such devices should mark themselves and other
4186 * device drivers should check before sending TLPs with RO set.
4188 static void quirk_relaxedordering_disable(struct pci_dev
*dev
)
4190 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_RELAXED_ORDERING
;
4191 pci_info(dev
, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4195 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4196 * Complex have a Flow Control Credit issue which can cause performance
4197 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4199 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f01, PCI_CLASS_NOT_DEFINED
, 8,
4200 quirk_relaxedordering_disable
);
4201 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f02, PCI_CLASS_NOT_DEFINED
, 8,
4202 quirk_relaxedordering_disable
);
4203 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f03, PCI_CLASS_NOT_DEFINED
, 8,
4204 quirk_relaxedordering_disable
);
4205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f04, PCI_CLASS_NOT_DEFINED
, 8,
4206 quirk_relaxedordering_disable
);
4207 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f05, PCI_CLASS_NOT_DEFINED
, 8,
4208 quirk_relaxedordering_disable
);
4209 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f06, PCI_CLASS_NOT_DEFINED
, 8,
4210 quirk_relaxedordering_disable
);
4211 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f07, PCI_CLASS_NOT_DEFINED
, 8,
4212 quirk_relaxedordering_disable
);
4213 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f08, PCI_CLASS_NOT_DEFINED
, 8,
4214 quirk_relaxedordering_disable
);
4215 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f09, PCI_CLASS_NOT_DEFINED
, 8,
4216 quirk_relaxedordering_disable
);
4217 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0a, PCI_CLASS_NOT_DEFINED
, 8,
4218 quirk_relaxedordering_disable
);
4219 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0b, PCI_CLASS_NOT_DEFINED
, 8,
4220 quirk_relaxedordering_disable
);
4221 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0c, PCI_CLASS_NOT_DEFINED
, 8,
4222 quirk_relaxedordering_disable
);
4223 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0d, PCI_CLASS_NOT_DEFINED
, 8,
4224 quirk_relaxedordering_disable
);
4225 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0e, PCI_CLASS_NOT_DEFINED
, 8,
4226 quirk_relaxedordering_disable
);
4227 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f01, PCI_CLASS_NOT_DEFINED
, 8,
4228 quirk_relaxedordering_disable
);
4229 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f02, PCI_CLASS_NOT_DEFINED
, 8,
4230 quirk_relaxedordering_disable
);
4231 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f03, PCI_CLASS_NOT_DEFINED
, 8,
4232 quirk_relaxedordering_disable
);
4233 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f04, PCI_CLASS_NOT_DEFINED
, 8,
4234 quirk_relaxedordering_disable
);
4235 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f05, PCI_CLASS_NOT_DEFINED
, 8,
4236 quirk_relaxedordering_disable
);
4237 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f06, PCI_CLASS_NOT_DEFINED
, 8,
4238 quirk_relaxedordering_disable
);
4239 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f07, PCI_CLASS_NOT_DEFINED
, 8,
4240 quirk_relaxedordering_disable
);
4241 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f08, PCI_CLASS_NOT_DEFINED
, 8,
4242 quirk_relaxedordering_disable
);
4243 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f09, PCI_CLASS_NOT_DEFINED
, 8,
4244 quirk_relaxedordering_disable
);
4245 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0a, PCI_CLASS_NOT_DEFINED
, 8,
4246 quirk_relaxedordering_disable
);
4247 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0b, PCI_CLASS_NOT_DEFINED
, 8,
4248 quirk_relaxedordering_disable
);
4249 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0c, PCI_CLASS_NOT_DEFINED
, 8,
4250 quirk_relaxedordering_disable
);
4251 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0d, PCI_CLASS_NOT_DEFINED
, 8,
4252 quirk_relaxedordering_disable
);
4253 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0e, PCI_CLASS_NOT_DEFINED
, 8,
4254 quirk_relaxedordering_disable
);
4257 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4258 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4259 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4260 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4261 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4262 * November 10, 2010). As a result, on this platform we can't use Relaxed
4263 * Ordering for Upstream TLPs.
4265 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a00, PCI_CLASS_NOT_DEFINED
, 8,
4266 quirk_relaxedordering_disable
);
4267 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a01, PCI_CLASS_NOT_DEFINED
, 8,
4268 quirk_relaxedordering_disable
);
4269 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a02, PCI_CLASS_NOT_DEFINED
, 8,
4270 quirk_relaxedordering_disable
);
4273 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4274 * values for the Attribute as were supplied in the header of the
4275 * corresponding Request, except as explicitly allowed when IDO is used."
4277 * If a non-compliant device generates a completion with a different
4278 * attribute than the request, the receiver may accept it (which itself
4279 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4280 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4281 * device access timeout.
4283 * If the non-compliant device generates completions with zero attributes
4284 * (instead of copying the attributes from the request), we can work around
4285 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4286 * upstream devices so they always generate requests with zero attributes.
4288 * This affects other devices under the same Root Port, but since these
4289 * attributes are performance hints, there should be no functional problem.
4291 * Note that Configuration Space accesses are never supposed to have TLP
4292 * Attributes, so we're safe waiting till after any Configuration Space
4293 * accesses to do the Root Port fixup.
4295 static void quirk_disable_root_port_attributes(struct pci_dev
*pdev
)
4297 struct pci_dev
*root_port
= pcie_find_root_port(pdev
);
4300 pci_warn(pdev
, "PCIe Completion erratum may cause device errors\n");
4304 pci_info(root_port
, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4305 dev_name(&pdev
->dev
));
4306 pcie_capability_clear_and_set_word(root_port
, PCI_EXP_DEVCTL
,
4307 PCI_EXP_DEVCTL_RELAX_EN
|
4308 PCI_EXP_DEVCTL_NOSNOOP_EN
, 0);
4312 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4313 * Completion it generates.
4315 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev
*pdev
)
4318 * This mask/compare operation selects for Physical Function 4 on a
4319 * T5. We only need to fix up the Root Port once for any of the
4320 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4321 * 0x54xx so we use that one.
4323 if ((pdev
->device
& 0xff00) == 0x5400)
4324 quirk_disable_root_port_attributes(pdev
);
4326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
4327 quirk_chelsio_T5_disable_root_port_attributes
);
4330 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4332 * @acs_ctrl_req: Bitmask of desired ACS controls
4333 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4334 * the hardware design
4336 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4337 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4338 * caller desires. Return 0 otherwise.
4340 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req
, u16 acs_ctrl_ena
)
4342 if ((acs_ctrl_req
& acs_ctrl_ena
) == acs_ctrl_req
)
4348 * AMD has indicated that the devices below do not support peer-to-peer
4349 * in any system where they are found in the southbridge with an AMD
4350 * IOMMU in the system. Multifunction devices that do not support
4351 * peer-to-peer between functions can claim to support a subset of ACS.
4352 * Such devices effectively enable request redirect (RR) and completion
4353 * redirect (CR) since all transactions are redirected to the upstream
4356 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4357 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4358 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4360 * 1002:4385 SBx00 SMBus Controller
4361 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4362 * 1002:4383 SBx00 Azalia (Intel HDA)
4363 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4364 * 1002:4384 SBx00 PCI to PCI Bridge
4365 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4367 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4369 * 1022:780f [AMD] FCH PCI Bridge
4370 * 1022:7809 [AMD] FCH USB OHCI Controller
4372 static int pci_quirk_amd_sb_acs(struct pci_dev
*dev
, u16 acs_flags
)
4375 struct acpi_table_header
*header
= NULL
;
4378 /* Targeting multifunction devices on the SB (appears on root bus) */
4379 if (!dev
->multifunction
|| !pci_is_root_bus(dev
->bus
))
4382 /* The IVRS table describes the AMD IOMMU */
4383 status
= acpi_get_table("IVRS", 0, &header
);
4384 if (ACPI_FAILURE(status
))
4387 acpi_put_table(header
);
4389 /* Filter out flags not applicable to multifunction */
4390 acs_flags
&= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
| PCI_ACS_DT
);
4392 return pci_acs_ctrl_enabled(acs_flags
, PCI_ACS_RR
| PCI_ACS_CR
);
4398 static bool pci_quirk_cavium_acs_match(struct pci_dev
*dev
)
4400 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4403 switch (dev
->device
) {
4405 * Effectively selects all downstream ports for whole ThunderX1
4406 * (which represents 8 SoCs).
4408 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4409 case 0xaf84: /* ThunderX2 */
4410 case 0xb884: /* ThunderX3 */
4417 static int pci_quirk_cavium_acs(struct pci_dev
*dev
, u16 acs_flags
)
4419 if (!pci_quirk_cavium_acs_match(dev
))
4423 * Cavium Root Ports don't advertise an ACS capability. However,
4424 * the RTL internally implements similar protection as if ACS had
4425 * Source Validation, Request Redirection, Completion Redirection,
4426 * and Upstream Forwarding features enabled. Assert that the
4427 * hardware implements and enables equivalent ACS functionality for
4430 return pci_acs_ctrl_enabled(acs_flags
,
4431 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4434 static int pci_quirk_xgene_acs(struct pci_dev
*dev
, u16 acs_flags
)
4437 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4438 * transactions with others, allowing masking out these bits as if they
4439 * were unimplemented in the ACS capability.
4441 return pci_acs_ctrl_enabled(acs_flags
,
4442 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4446 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4447 * But the implementation could block peer-to-peer transactions between them
4448 * and provide ACS-like functionality.
4450 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev
*dev
, u16 acs_flags
)
4452 if (!pci_is_pcie(dev
) ||
4453 ((pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
) &&
4454 (pci_pcie_type(dev
) != PCI_EXP_TYPE_DOWNSTREAM
)))
4457 switch (dev
->device
) {
4458 case 0x0710 ... 0x071e:
4460 case 0x0723 ... 0x0732:
4461 return pci_acs_ctrl_enabled(acs_flags
,
4462 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4469 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4470 * transactions and validate bus numbers in requests, but do not provide an
4471 * actual PCIe ACS capability. This is the list of device IDs known to fall
4472 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4474 static const u16 pci_quirk_intel_pch_acs_ids
[] = {
4476 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4477 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4478 /* Cougarpoint PCH */
4479 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4480 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4481 /* Pantherpoint PCH */
4482 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4483 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4484 /* Lynxpoint-H PCH */
4485 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4486 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4487 /* Lynxpoint-LP PCH */
4488 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4489 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4491 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4492 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4493 /* Patsburg (X79) PCH */
4494 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4495 /* Wellsburg (X99) PCH */
4496 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4497 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4498 /* Lynx Point (9 series) PCH */
4499 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4502 static bool pci_quirk_intel_pch_acs_match(struct pci_dev
*dev
)
4506 /* Filter out a few obvious non-matches first */
4507 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4510 for (i
= 0; i
< ARRAY_SIZE(pci_quirk_intel_pch_acs_ids
); i
++)
4511 if (pci_quirk_intel_pch_acs_ids
[i
] == dev
->device
)
4517 static int pci_quirk_intel_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4519 if (!pci_quirk_intel_pch_acs_match(dev
))
4522 if (dev
->dev_flags
& PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
)
4523 return pci_acs_ctrl_enabled(acs_flags
,
4524 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4526 return pci_acs_ctrl_enabled(acs_flags
, 0);
4530 * These QCOM Root Ports do provide ACS-like features to disable peer
4531 * transactions and validate bus numbers in requests, but do not provide an
4532 * actual PCIe ACS capability. Hardware supports source validation but it
4533 * will report the issue as Completer Abort instead of ACS Violation.
4534 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4535 * Complex with unique segment numbers. It is not possible for one Root
4536 * Port to pass traffic to another Root Port. All PCIe transactions are
4537 * terminated inside the Root Port.
4539 static int pci_quirk_qcom_rp_acs(struct pci_dev
*dev
, u16 acs_flags
)
4541 return pci_acs_ctrl_enabled(acs_flags
,
4542 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4545 static int pci_quirk_al_acs(struct pci_dev
*dev
, u16 acs_flags
)
4547 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4551 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4552 * but do include ACS-like functionality. The hardware doesn't support
4553 * peer-to-peer transactions via the root port and each has a unique
4556 * Additionally, the root ports cannot send traffic to each other.
4558 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4560 return acs_flags
? 0 : 1;
4564 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4565 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4566 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4567 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4568 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4569 * control register is at offset 8 instead of 6 and we should probably use
4570 * dword accesses to them. This applies to the following PCI Device IDs, as
4571 * found in volume 1 of the datasheet[2]:
4573 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4574 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4576 * N.B. This doesn't fix what lspci shows.
4578 * The 100 series chipset specification update includes this as errata #23[3].
4580 * The 200 series chipset (Union Point) has the same bug according to the
4581 * specification update (Intel 200 Series Chipset Family Platform Controller
4582 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4583 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4586 * 0xa290-0xa29f PCI Express Root port #{0-16}
4587 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4589 * Mobile chipsets are also affected, 7th & 8th Generation
4590 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4591 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4592 * Processor Family I/O for U Quad Core Platforms Specification Update,
4593 * August 2017, Revision 002, Document#: 334660-002)[6]
4594 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4595 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4596 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4598 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4600 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4601 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4602 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4603 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4604 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4605 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4606 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4608 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev
*dev
)
4610 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4613 switch (dev
->device
) {
4614 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4615 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4616 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4623 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4625 static int pci_quirk_intel_spt_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4630 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4637 /* see pci_acs_flags_enabled() */
4638 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4639 acs_flags
&= (cap
| PCI_ACS_EC
);
4641 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4643 return pci_acs_ctrl_enabled(acs_flags
, ctrl
);
4646 static int pci_quirk_mf_endpoint_acs(struct pci_dev
*dev
, u16 acs_flags
)
4649 * SV, TB, and UF are not relevant to multifunction endpoints.
4651 * Multifunction devices are only required to implement RR, CR, and DT
4652 * in their ACS capability if they support peer-to-peer transactions.
4653 * Devices matching this quirk have been verified by the vendor to not
4654 * perform peer-to-peer with other functions, allowing us to mask out
4655 * these bits as if they were unimplemented in the ACS capability.
4657 return pci_acs_ctrl_enabled(acs_flags
,
4658 PCI_ACS_SV
| PCI_ACS_TB
| PCI_ACS_RR
|
4659 PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_DT
);
4662 static int pci_quirk_rciep_acs(struct pci_dev
*dev
, u16 acs_flags
)
4665 * Intel RCiEP's are required to allow p2p only on translated
4666 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4667 * "Root-Complex Peer to Peer Considerations".
4669 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_RC_END
)
4672 return pci_acs_ctrl_enabled(acs_flags
,
4673 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4676 static int pci_quirk_brcm_acs(struct pci_dev
*dev
, u16 acs_flags
)
4679 * iProc PAXB Root Ports don't advertise an ACS capability, but
4680 * they do not allow peer-to-peer transactions between Root Ports.
4681 * Allow each Root Port to be in a separate IOMMU group by masking
4684 return pci_acs_ctrl_enabled(acs_flags
,
4685 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4688 static const struct pci_dev_acs_enabled
{
4691 int (*acs_enabled
)(struct pci_dev
*dev
, u16 acs_flags
);
4692 } pci_dev_acs_enabled
[] = {
4693 { PCI_VENDOR_ID_ATI
, 0x4385, pci_quirk_amd_sb_acs
},
4694 { PCI_VENDOR_ID_ATI
, 0x439c, pci_quirk_amd_sb_acs
},
4695 { PCI_VENDOR_ID_ATI
, 0x4383, pci_quirk_amd_sb_acs
},
4696 { PCI_VENDOR_ID_ATI
, 0x439d, pci_quirk_amd_sb_acs
},
4697 { PCI_VENDOR_ID_ATI
, 0x4384, pci_quirk_amd_sb_acs
},
4698 { PCI_VENDOR_ID_ATI
, 0x4399, pci_quirk_amd_sb_acs
},
4699 { PCI_VENDOR_ID_AMD
, 0x780f, pci_quirk_amd_sb_acs
},
4700 { PCI_VENDOR_ID_AMD
, 0x7809, pci_quirk_amd_sb_acs
},
4701 { PCI_VENDOR_ID_SOLARFLARE
, 0x0903, pci_quirk_mf_endpoint_acs
},
4702 { PCI_VENDOR_ID_SOLARFLARE
, 0x0923, pci_quirk_mf_endpoint_acs
},
4703 { PCI_VENDOR_ID_SOLARFLARE
, 0x0A03, pci_quirk_mf_endpoint_acs
},
4704 { PCI_VENDOR_ID_INTEL
, 0x10C6, pci_quirk_mf_endpoint_acs
},
4705 { PCI_VENDOR_ID_INTEL
, 0x10DB, pci_quirk_mf_endpoint_acs
},
4706 { PCI_VENDOR_ID_INTEL
, 0x10DD, pci_quirk_mf_endpoint_acs
},
4707 { PCI_VENDOR_ID_INTEL
, 0x10E1, pci_quirk_mf_endpoint_acs
},
4708 { PCI_VENDOR_ID_INTEL
, 0x10F1, pci_quirk_mf_endpoint_acs
},
4709 { PCI_VENDOR_ID_INTEL
, 0x10F7, pci_quirk_mf_endpoint_acs
},
4710 { PCI_VENDOR_ID_INTEL
, 0x10F8, pci_quirk_mf_endpoint_acs
},
4711 { PCI_VENDOR_ID_INTEL
, 0x10F9, pci_quirk_mf_endpoint_acs
},
4712 { PCI_VENDOR_ID_INTEL
, 0x10FA, pci_quirk_mf_endpoint_acs
},
4713 { PCI_VENDOR_ID_INTEL
, 0x10FB, pci_quirk_mf_endpoint_acs
},
4714 { PCI_VENDOR_ID_INTEL
, 0x10FC, pci_quirk_mf_endpoint_acs
},
4715 { PCI_VENDOR_ID_INTEL
, 0x1507, pci_quirk_mf_endpoint_acs
},
4716 { PCI_VENDOR_ID_INTEL
, 0x1514, pci_quirk_mf_endpoint_acs
},
4717 { PCI_VENDOR_ID_INTEL
, 0x151C, pci_quirk_mf_endpoint_acs
},
4718 { PCI_VENDOR_ID_INTEL
, 0x1529, pci_quirk_mf_endpoint_acs
},
4719 { PCI_VENDOR_ID_INTEL
, 0x152A, pci_quirk_mf_endpoint_acs
},
4720 { PCI_VENDOR_ID_INTEL
, 0x154D, pci_quirk_mf_endpoint_acs
},
4721 { PCI_VENDOR_ID_INTEL
, 0x154F, pci_quirk_mf_endpoint_acs
},
4722 { PCI_VENDOR_ID_INTEL
, 0x1551, pci_quirk_mf_endpoint_acs
},
4723 { PCI_VENDOR_ID_INTEL
, 0x1558, pci_quirk_mf_endpoint_acs
},
4725 { PCI_VENDOR_ID_INTEL
, 0x1509, pci_quirk_mf_endpoint_acs
},
4726 { PCI_VENDOR_ID_INTEL
, 0x150E, pci_quirk_mf_endpoint_acs
},
4727 { PCI_VENDOR_ID_INTEL
, 0x150F, pci_quirk_mf_endpoint_acs
},
4728 { PCI_VENDOR_ID_INTEL
, 0x1510, pci_quirk_mf_endpoint_acs
},
4729 { PCI_VENDOR_ID_INTEL
, 0x1511, pci_quirk_mf_endpoint_acs
},
4730 { PCI_VENDOR_ID_INTEL
, 0x1516, pci_quirk_mf_endpoint_acs
},
4731 { PCI_VENDOR_ID_INTEL
, 0x1527, pci_quirk_mf_endpoint_acs
},
4733 { PCI_VENDOR_ID_INTEL
, 0x10C9, pci_quirk_mf_endpoint_acs
},
4734 { PCI_VENDOR_ID_INTEL
, 0x10E6, pci_quirk_mf_endpoint_acs
},
4735 { PCI_VENDOR_ID_INTEL
, 0x10E7, pci_quirk_mf_endpoint_acs
},
4736 { PCI_VENDOR_ID_INTEL
, 0x10E8, pci_quirk_mf_endpoint_acs
},
4737 { PCI_VENDOR_ID_INTEL
, 0x150A, pci_quirk_mf_endpoint_acs
},
4738 { PCI_VENDOR_ID_INTEL
, 0x150D, pci_quirk_mf_endpoint_acs
},
4739 { PCI_VENDOR_ID_INTEL
, 0x1518, pci_quirk_mf_endpoint_acs
},
4740 { PCI_VENDOR_ID_INTEL
, 0x1526, pci_quirk_mf_endpoint_acs
},
4742 { PCI_VENDOR_ID_INTEL
, 0x10A7, pci_quirk_mf_endpoint_acs
},
4743 { PCI_VENDOR_ID_INTEL
, 0x10A9, pci_quirk_mf_endpoint_acs
},
4744 { PCI_VENDOR_ID_INTEL
, 0x10D6, pci_quirk_mf_endpoint_acs
},
4746 { PCI_VENDOR_ID_INTEL
, 0x1521, pci_quirk_mf_endpoint_acs
},
4747 { PCI_VENDOR_ID_INTEL
, 0x1522, pci_quirk_mf_endpoint_acs
},
4748 { PCI_VENDOR_ID_INTEL
, 0x1523, pci_quirk_mf_endpoint_acs
},
4749 { PCI_VENDOR_ID_INTEL
, 0x1524, pci_quirk_mf_endpoint_acs
},
4750 /* 82571 (Quads omitted due to non-ACS switch) */
4751 { PCI_VENDOR_ID_INTEL
, 0x105E, pci_quirk_mf_endpoint_acs
},
4752 { PCI_VENDOR_ID_INTEL
, 0x105F, pci_quirk_mf_endpoint_acs
},
4753 { PCI_VENDOR_ID_INTEL
, 0x1060, pci_quirk_mf_endpoint_acs
},
4754 { PCI_VENDOR_ID_INTEL
, 0x10D9, pci_quirk_mf_endpoint_acs
},
4756 { PCI_VENDOR_ID_INTEL
, 0x15b7, pci_quirk_mf_endpoint_acs
},
4757 { PCI_VENDOR_ID_INTEL
, 0x15b8, pci_quirk_mf_endpoint_acs
},
4758 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_rciep_acs
},
4759 /* QCOM QDF2xxx root ports */
4760 { PCI_VENDOR_ID_QCOM
, 0x0400, pci_quirk_qcom_rp_acs
},
4761 { PCI_VENDOR_ID_QCOM
, 0x0401, pci_quirk_qcom_rp_acs
},
4762 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4763 { PCI_VENDOR_ID_HXT
, 0x0401, pci_quirk_qcom_rp_acs
},
4764 /* Intel PCH root ports */
4765 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_pch_acs
},
4766 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_spt_pch_acs
},
4767 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs
}, /* Emulex BE3-R */
4768 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs
}, /* Emulex Skyhawk-R */
4769 /* Cavium ThunderX */
4770 { PCI_VENDOR_ID_CAVIUM
, PCI_ANY_ID
, pci_quirk_cavium_acs
},
4772 { PCI_VENDOR_ID_AMCC
, 0xE004, pci_quirk_xgene_acs
},
4773 /* Ampere Computing */
4774 { PCI_VENDOR_ID_AMPERE
, 0xE005, pci_quirk_xgene_acs
},
4775 { PCI_VENDOR_ID_AMPERE
, 0xE006, pci_quirk_xgene_acs
},
4776 { PCI_VENDOR_ID_AMPERE
, 0xE007, pci_quirk_xgene_acs
},
4777 { PCI_VENDOR_ID_AMPERE
, 0xE008, pci_quirk_xgene_acs
},
4778 { PCI_VENDOR_ID_AMPERE
, 0xE009, pci_quirk_xgene_acs
},
4779 { PCI_VENDOR_ID_AMPERE
, 0xE00A, pci_quirk_xgene_acs
},
4780 { PCI_VENDOR_ID_AMPERE
, 0xE00B, pci_quirk_xgene_acs
},
4781 { PCI_VENDOR_ID_AMPERE
, 0xE00C, pci_quirk_xgene_acs
},
4782 { PCI_VENDOR_ID_BROADCOM
, 0xD714, pci_quirk_brcm_acs
},
4783 /* Amazon Annapurna Labs */
4784 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS
, 0x0031, pci_quirk_al_acs
},
4785 /* Zhaoxin multi-function devices */
4786 { PCI_VENDOR_ID_ZHAOXIN
, 0x3038, pci_quirk_mf_endpoint_acs
},
4787 { PCI_VENDOR_ID_ZHAOXIN
, 0x3104, pci_quirk_mf_endpoint_acs
},
4788 { PCI_VENDOR_ID_ZHAOXIN
, 0x9083, pci_quirk_mf_endpoint_acs
},
4789 /* Zhaoxin Root/Downstream Ports */
4790 { PCI_VENDOR_ID_ZHAOXIN
, PCI_ANY_ID
, pci_quirk_zhaoxin_pcie_ports_acs
},
4795 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4797 * @acs_flags: Bitmask of desired ACS controls
4800 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4801 * device provides the desired controls
4802 * 0: Device does not provide all the desired controls
4803 * >0: Device provides all the controls in @acs_flags
4805 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
)
4807 const struct pci_dev_acs_enabled
*i
;
4811 * Allow devices that do not expose standard PCIe ACS capabilities
4812 * or control to indicate their support here. Multi-function express
4813 * devices which do not allow internal peer-to-peer between functions,
4814 * but do not implement PCIe ACS may wish to return true here.
4816 for (i
= pci_dev_acs_enabled
; i
->acs_enabled
; i
++) {
4817 if ((i
->vendor
== dev
->vendor
||
4818 i
->vendor
== (u16
)PCI_ANY_ID
) &&
4819 (i
->device
== dev
->device
||
4820 i
->device
== (u16
)PCI_ANY_ID
)) {
4821 ret
= i
->acs_enabled(dev
, acs_flags
);
4830 /* Config space offset of Root Complex Base Address register */
4831 #define INTEL_LPC_RCBA_REG 0xf0
4832 /* 31:14 RCBA address */
4833 #define INTEL_LPC_RCBA_MASK 0xffffc000
4835 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4837 /* Backbone Scratch Pad Register */
4838 #define INTEL_BSPR_REG 0x1104
4839 /* Backbone Peer Non-Posted Disable */
4840 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4841 /* Backbone Peer Posted Disable */
4842 #define INTEL_BSPR_REG_BPPD (1 << 9)
4844 /* Upstream Peer Decode Configuration Register */
4845 #define INTEL_UPDCR_REG 0x1014
4846 /* 5:0 Peer Decode Enable bits */
4847 #define INTEL_UPDCR_REG_MASK 0x3f
4849 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev
*dev
)
4851 u32 rcba
, bspr
, updcr
;
4852 void __iomem
*rcba_mem
;
4855 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4856 * are D28:F* and therefore get probed before LPC, thus we can't
4857 * use pci_get_slot()/pci_read_config_dword() here.
4859 pci_bus_read_config_dword(dev
->bus
, PCI_DEVFN(31, 0),
4860 INTEL_LPC_RCBA_REG
, &rcba
);
4861 if (!(rcba
& INTEL_LPC_RCBA_ENABLE
))
4864 rcba_mem
= ioremap(rcba
& INTEL_LPC_RCBA_MASK
,
4865 PAGE_ALIGN(INTEL_UPDCR_REG
));
4870 * The BSPR can disallow peer cycles, but it's set by soft strap and
4871 * therefore read-only. If both posted and non-posted peer cycles are
4872 * disallowed, we're ok. If either are allowed, then we need to use
4873 * the UPDCR to disable peer decodes for each port. This provides the
4874 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4876 bspr
= readl(rcba_mem
+ INTEL_BSPR_REG
);
4877 bspr
&= INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
;
4878 if (bspr
!= (INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
)) {
4879 updcr
= readl(rcba_mem
+ INTEL_UPDCR_REG
);
4880 if (updcr
& INTEL_UPDCR_REG_MASK
) {
4881 pci_info(dev
, "Disabling UPDCR peer decodes\n");
4882 updcr
&= ~INTEL_UPDCR_REG_MASK
;
4883 writel(updcr
, rcba_mem
+ INTEL_UPDCR_REG
);
4891 /* Miscellaneous Port Configuration register */
4892 #define INTEL_MPC_REG 0xd8
4893 /* MPC: Invalid Receive Bus Number Check Enable */
4894 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4896 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev
*dev
)
4901 * When enabled, the IRBNCE bit of the MPC register enables the
4902 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4903 * ensures that requester IDs fall within the bus number range
4904 * of the bridge. Enable if not already.
4906 pci_read_config_dword(dev
, INTEL_MPC_REG
, &mpc
);
4907 if (!(mpc
& INTEL_MPC_REG_IRBNCE
)) {
4908 pci_info(dev
, "Enabling MPC IRBNCE\n");
4909 mpc
|= INTEL_MPC_REG_IRBNCE
;
4910 pci_write_config_word(dev
, INTEL_MPC_REG
, mpc
);
4915 * Currently this quirk does the equivalent of
4916 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4918 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
4919 * if dev->external_facing || dev->untrusted
4921 static int pci_quirk_enable_intel_pch_acs(struct pci_dev
*dev
)
4923 if (!pci_quirk_intel_pch_acs_match(dev
))
4926 if (pci_quirk_enable_intel_lpc_acs(dev
)) {
4927 pci_warn(dev
, "Failed to enable Intel PCH ACS quirk\n");
4931 pci_quirk_enable_intel_rp_mpc_acs(dev
);
4933 dev
->dev_flags
|= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
;
4935 pci_info(dev
, "Intel PCH root port ACS workaround enabled\n");
4940 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev
*dev
)
4945 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4952 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4953 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4955 ctrl
|= (cap
& PCI_ACS_SV
);
4956 ctrl
|= (cap
& PCI_ACS_RR
);
4957 ctrl
|= (cap
& PCI_ACS_CR
);
4958 ctrl
|= (cap
& PCI_ACS_UF
);
4960 if (dev
->external_facing
|| dev
->untrusted
)
4961 ctrl
|= (cap
& PCI_ACS_TB
);
4963 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
4965 pci_info(dev
, "Intel SPT PCH root port ACS workaround enabled\n");
4970 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev
*dev
)
4975 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4982 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4983 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4985 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
4987 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
4989 pci_info(dev
, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4994 static const struct pci_dev_acs_ops
{
4997 int (*enable_acs
)(struct pci_dev
*dev
);
4998 int (*disable_acs_redir
)(struct pci_dev
*dev
);
4999 } pci_dev_acs_ops
[] = {
5000 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
5001 .enable_acs
= pci_quirk_enable_intel_pch_acs
,
5003 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
5004 .enable_acs
= pci_quirk_enable_intel_spt_pch_acs
,
5005 .disable_acs_redir
= pci_quirk_disable_intel_spt_pch_acs_redir
,
5009 int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
5011 const struct pci_dev_acs_ops
*p
;
5014 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
5015 p
= &pci_dev_acs_ops
[i
];
5016 if ((p
->vendor
== dev
->vendor
||
5017 p
->vendor
== (u16
)PCI_ANY_ID
) &&
5018 (p
->device
== dev
->device
||
5019 p
->device
== (u16
)PCI_ANY_ID
) &&
5021 ret
= p
->enable_acs(dev
);
5030 int pci_dev_specific_disable_acs_redir(struct pci_dev
*dev
)
5032 const struct pci_dev_acs_ops
*p
;
5035 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
5036 p
= &pci_dev_acs_ops
[i
];
5037 if ((p
->vendor
== dev
->vendor
||
5038 p
->vendor
== (u16
)PCI_ANY_ID
) &&
5039 (p
->device
== dev
->device
||
5040 p
->device
== (u16
)PCI_ANY_ID
) &&
5041 p
->disable_acs_redir
) {
5042 ret
= p
->disable_acs_redir(dev
);
5052 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5053 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5054 * Next Capability pointer in the MSI Capability Structure should point to
5055 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5058 static void quirk_intel_qat_vf_cap(struct pci_dev
*pdev
)
5063 struct pci_cap_saved_state
*state
;
5065 /* Bail if the hardware bug is fixed */
5066 if (pdev
->pcie_cap
|| pci_find_capability(pdev
, PCI_CAP_ID_EXP
))
5069 /* Bail if MSI Capability Structure is not found for some reason */
5070 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSI
);
5075 * Bail if Next Capability pointer in the MSI Capability Structure
5076 * is not the expected incorrect 0x00.
5078 pci_read_config_byte(pdev
, pos
+ 1, &next_cap
);
5083 * PCIe Capability Structure is expected to be at 0x50 and should
5084 * terminate the list (Next Capability pointer is 0x00). Verify
5085 * Capability Id and Next Capability pointer is as expected.
5086 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5087 * to correctly set kernel data structures which have already been
5088 * set incorrectly due to the hardware bug.
5091 pci_read_config_word(pdev
, pos
, ®16
);
5092 if (reg16
== (0x0000 | PCI_CAP_ID_EXP
)) {
5094 #ifndef PCI_EXP_SAVE_REGS
5095 #define PCI_EXP_SAVE_REGS 7
5097 int size
= PCI_EXP_SAVE_REGS
* sizeof(u16
);
5099 pdev
->pcie_cap
= pos
;
5100 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
5101 pdev
->pcie_flags_reg
= reg16
;
5102 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
5103 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
5105 pdev
->cfg_size
= PCI_CFG_SPACE_EXP_SIZE
;
5106 if (pci_read_config_dword(pdev
, PCI_CFG_SPACE_SIZE
, &status
) !=
5107 PCIBIOS_SUCCESSFUL
|| (status
== 0xffffffff))
5108 pdev
->cfg_size
= PCI_CFG_SPACE_SIZE
;
5110 if (pci_find_saved_cap(pdev
, PCI_CAP_ID_EXP
))
5114 state
= kzalloc(sizeof(*state
) + size
, GFP_KERNEL
);
5118 state
->cap
.cap_nr
= PCI_CAP_ID_EXP
;
5119 state
->cap
.cap_extended
= 0;
5120 state
->cap
.size
= size
;
5121 cap
= (u16
*)&state
->cap
.data
[0];
5122 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
5123 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
5124 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
5125 pcie_capability_read_word(pdev
, PCI_EXP_RTCTL
, &cap
[i
++]);
5126 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
5127 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
5128 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
5129 hlist_add_head(&state
->next
, &pdev
->saved_cap_space
);
5132 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x443, quirk_intel_qat_vf_cap
);
5135 * FLR may cause the following to devices to hang:
5137 * AMD Starship/Matisse HD Audio Controller 0x1487
5138 * AMD Starship USB 3.0 Host Controller 0x148c
5139 * AMD Matisse USB 3.0 Host Controller 0x149c
5140 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5141 * Intel 82579V Gigabit Ethernet Controller 0x1503
5144 static void quirk_no_flr(struct pci_dev
*dev
)
5146 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_FLR_RESET
;
5148 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD
, 0x1487, quirk_no_flr
);
5149 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD
, 0x148c, quirk_no_flr
);
5150 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD
, 0x149c, quirk_no_flr
);
5151 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1502, quirk_no_flr
);
5152 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1503, quirk_no_flr
);
5154 static void quirk_intel_th_rtit_bar(struct pci_dev
*dev
)
5156 struct resource
*r
= &dev
->resource
[4];
5160 * Denverton reports 2k of RTIT_BAR (resource 4), which can't be
5161 * right given the 16 threads. When Intel TH gets enabled, the
5162 * actual resource overlaps the XHCI MMIO space and causes it
5164 * We're not really using RTIT_BAR at all at the moment, so it's
5165 * a safe choice to disable this resource.
5167 if (r
->end
== r
->start
+ 0x7ff) {
5173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x19e1, quirk_intel_th_rtit_bar
);
5175 static void quirk_no_ext_tags(struct pci_dev
*pdev
)
5177 struct pci_host_bridge
*bridge
= pci_find_host_bridge(pdev
->bus
);
5182 bridge
->no_ext_tags
= 1;
5183 pci_info(pdev
, "disabling Extended Tags (this device can't handle them)\n");
5185 pci_walk_bus(bridge
->bus
, pci_configure_extended_tags
, NULL
);
5187 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0132, quirk_no_ext_tags
);
5188 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0140, quirk_no_ext_tags
);
5189 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0141, quirk_no_ext_tags
);
5190 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0142, quirk_no_ext_tags
);
5191 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0144, quirk_no_ext_tags
);
5192 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0420, quirk_no_ext_tags
);
5193 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0422, quirk_no_ext_tags
);
5195 #ifdef CONFIG_PCI_ATS
5197 * Some devices require additional driver setup to enable ATS. Don't use
5198 * ATS for those devices as ATS will be enabled before the driver has had a
5199 * chance to load and configure the device.
5201 static void quirk_amd_harvest_no_ats(struct pci_dev
*pdev
)
5203 if ((pdev
->device
== 0x7312 && pdev
->revision
!= 0x00) ||
5204 (pdev
->device
== 0x7340 && pdev
->revision
!= 0xc5))
5207 if (pdev
->device
== 0x15d8) {
5208 if (pdev
->revision
== 0xcf &&
5209 pdev
->subsystem_vendor
== 0xea50 &&
5210 (pdev
->subsystem_device
== 0xce19 ||
5211 pdev
->subsystem_device
== 0xcc10 ||
5212 pdev
->subsystem_device
== 0xcc08))
5219 pci_info(pdev
, "disabling ATS\n");
5223 /* AMD Stoney platform GPU */
5224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x98e4, quirk_amd_harvest_no_ats
);
5225 /* AMD Iceland dGPU */
5226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6900, quirk_amd_harvest_no_ats
);
5227 /* AMD Navi10 dGPU */
5228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x7312, quirk_amd_harvest_no_ats
);
5229 /* AMD Navi14 dGPU */
5230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x7340, quirk_amd_harvest_no_ats
);
5231 /* AMD Raven platform iGPU */
5232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x15d8, quirk_amd_harvest_no_ats
);
5233 #endif /* CONFIG_PCI_ATS */
5235 /* Freescale PCIe doesn't support MSI in RC mode */
5236 static void quirk_fsl_no_msi(struct pci_dev
*pdev
)
5238 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
)
5241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, quirk_fsl_no_msi
);
5244 * Although not allowed by the spec, some multi-function devices have
5245 * dependencies of one function (consumer) on another (supplier). For the
5246 * consumer to work in D0, the supplier must also be in D0. Create a
5247 * device link from the consumer to the supplier to enforce this
5248 * dependency. Runtime PM is allowed by default on the consumer to prevent
5249 * it from permanently keeping the supplier awake.
5251 static void pci_create_device_link(struct pci_dev
*pdev
, unsigned int consumer
,
5252 unsigned int supplier
, unsigned int class,
5253 unsigned int class_shift
)
5255 struct pci_dev
*supplier_pdev
;
5257 if (PCI_FUNC(pdev
->devfn
) != consumer
)
5260 supplier_pdev
= pci_get_domain_bus_and_slot(pci_domain_nr(pdev
->bus
),
5262 PCI_DEVFN(PCI_SLOT(pdev
->devfn
), supplier
));
5263 if (!supplier_pdev
|| (supplier_pdev
->class >> class_shift
) != class) {
5264 pci_dev_put(supplier_pdev
);
5268 if (device_link_add(&pdev
->dev
, &supplier_pdev
->dev
,
5269 DL_FLAG_STATELESS
| DL_FLAG_PM_RUNTIME
))
5270 pci_info(pdev
, "D0 power state depends on %s\n",
5271 pci_name(supplier_pdev
));
5273 pci_err(pdev
, "Cannot enforce power dependency on %s\n",
5274 pci_name(supplier_pdev
));
5276 pm_runtime_allow(&pdev
->dev
);
5277 pci_dev_put(supplier_pdev
);
5281 * Create device link for GPUs with integrated HDA controller for streaming
5282 * audio to attached displays.
5284 static void quirk_gpu_hda(struct pci_dev
*hda
)
5286 pci_create_device_link(hda
, 1, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5288 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
5289 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5290 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
,
5291 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5292 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5293 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5296 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5297 * controller to VGA.
5299 static void quirk_gpu_usb(struct pci_dev
*usb
)
5301 pci_create_device_link(usb
, 2, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5303 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5304 PCI_CLASS_SERIAL_USB
, 8, quirk_gpu_usb
);
5307 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5308 * to VGA. Currently there is no class code defined for UCSI device over PCI
5309 * so using UNKNOWN class for now and it will be updated when UCSI
5310 * over PCI gets a class code.
5312 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5313 static void quirk_gpu_usb_typec_ucsi(struct pci_dev
*ucsi
)
5315 pci_create_device_link(ucsi
, 3, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5317 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5318 PCI_CLASS_SERIAL_UNKNOWN
, 8,
5319 quirk_gpu_usb_typec_ucsi
);
5322 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5323 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5325 static void quirk_nvidia_hda(struct pci_dev
*gpu
)
5330 /* There was no integrated HDA controller before MCP89 */
5331 if (gpu
->device
< PCI_DEVICE_ID_NVIDIA_GEFORCE_320M
)
5334 /* Bit 25 at offset 0x488 enables the HDA controller */
5335 pci_read_config_dword(gpu
, 0x488, &val
);
5339 pci_info(gpu
, "Enabling HDA controller\n");
5340 pci_write_config_dword(gpu
, 0x488, val
| BIT(25));
5342 /* The GPU becomes a multi-function device when the HDA is enabled */
5343 pci_read_config_byte(gpu
, PCI_HEADER_TYPE
, &hdr_type
);
5344 gpu
->multifunction
= !!(hdr_type
& 0x80);
5346 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5347 PCI_BASE_CLASS_DISPLAY
, 16, quirk_nvidia_hda
);
5348 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5349 PCI_BASE_CLASS_DISPLAY
, 16, quirk_nvidia_hda
);
5352 * Some IDT switches incorrectly flag an ACS Source Validation error on
5353 * completions for config read requests even though PCIe r4.0, sec
5354 * 6.12.1.1, says that completions are never affected by ACS Source
5355 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5357 * Item #36 - Downstream port applies ACS Source Validation to Completions
5358 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5359 * completions are never affected by ACS Source Validation. However,
5360 * completions received by a downstream port of the PCIe switch from a
5361 * device that has not yet captured a PCIe bus number are incorrectly
5362 * dropped by ACS Source Validation by the switch downstream port.
5364 * The workaround suggested by IDT is to issue a config write to the
5365 * downstream device before issuing the first config read. This allows the
5366 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5367 * sec 2.2.9), thus avoiding the ACS error on the completion.
5369 * However, we don't know when the device is ready to accept the config
5370 * write, so we do config reads until we receive a non-Config Request Retry
5371 * Status, then do the config write.
5373 * To avoid hitting the erratum when doing the config reads, we disable ACS
5374 * SV around this process.
5376 int pci_idt_bus_quirk(struct pci_bus
*bus
, int devfn
, u32
*l
, int timeout
)
5381 struct pci_dev
*bridge
= bus
->self
;
5383 pos
= bridge
->acs_cap
;
5385 /* Disable ACS SV before initial config reads */
5387 pci_read_config_word(bridge
, pos
+ PCI_ACS_CTRL
, &ctrl
);
5388 if (ctrl
& PCI_ACS_SV
)
5389 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
,
5390 ctrl
& ~PCI_ACS_SV
);
5393 found
= pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
5395 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5397 pci_bus_write_config_word(bus
, devfn
, PCI_VENDOR_ID
, 0);
5399 /* Re-enable ACS_SV if it was previously enabled */
5400 if (ctrl
& PCI_ACS_SV
)
5401 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
, ctrl
);
5407 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5408 * NT endpoints via the internal switch fabric. These IDs replace the
5409 * originating requestor ID TLPs which access host memory on peer NTB
5410 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5411 * to permit access when the IOMMU is turned on.
5413 static void quirk_switchtec_ntb_dma_alias(struct pci_dev
*pdev
)
5416 struct ntb_info_regs __iomem
*mmio_ntb
;
5417 struct ntb_ctrl_regs __iomem
*mmio_ctrl
;
5422 if (pci_enable_device(pdev
)) {
5423 pci_err(pdev
, "Cannot enable Switchtec device\n");
5427 mmio
= pci_iomap(pdev
, 0, 0);
5429 pci_disable_device(pdev
);
5430 pci_err(pdev
, "Cannot iomap Switchtec device\n");
5434 pci_info(pdev
, "Setting Switchtec proxy ID aliases\n");
5436 mmio_ntb
= mmio
+ SWITCHTEC_GAS_NTB_OFFSET
;
5437 mmio_ctrl
= (void __iomem
*) mmio_ntb
+ SWITCHTEC_NTB_REG_CTRL_OFFSET
;
5439 partition
= ioread8(&mmio_ntb
->partition_id
);
5441 partition_map
= ioread32(&mmio_ntb
->ep_map
);
5442 partition_map
|= ((u64
) ioread32(&mmio_ntb
->ep_map
+ 4)) << 32;
5443 partition_map
&= ~(1ULL << partition
);
5445 for (pp
= 0; pp
< (sizeof(partition_map
) * 8); pp
++) {
5446 struct ntb_ctrl_regs __iomem
*mmio_peer_ctrl
;
5450 if (!(partition_map
& (1ULL << pp
)))
5453 pci_dbg(pdev
, "Processing partition %d\n", pp
);
5455 mmio_peer_ctrl
= &mmio_ctrl
[pp
];
5457 table_sz
= ioread16(&mmio_peer_ctrl
->req_id_table_size
);
5459 pci_warn(pdev
, "Partition %d table_sz 0\n", pp
);
5463 if (table_sz
> 512) {
5465 "Invalid Switchtec partition %d table_sz %d\n",
5470 for (te
= 0; te
< table_sz
; te
++) {
5474 rid_entry
= ioread32(&mmio_peer_ctrl
->req_id_table
[te
]);
5475 devfn
= (rid_entry
>> 1) & 0xFF;
5477 "Aliasing Partition %d Proxy ID %02x.%d\n",
5478 pp
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5479 pci_add_dma_alias(pdev
, devfn
, 1);
5483 pci_iounmap(pdev
, mmio
);
5484 pci_disable_device(pdev
);
5486 #define SWITCHTEC_QUIRK(vid) \
5487 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5488 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5490 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5491 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5492 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5493 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5494 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5495 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5496 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5497 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5498 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5499 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5500 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5501 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5502 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5503 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5504 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5505 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5506 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5507 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5508 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5509 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5510 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5511 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5512 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5513 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5514 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5515 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5516 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5517 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5518 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5519 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5520 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5521 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5522 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5523 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5524 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5525 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5526 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5527 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5528 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5529 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5530 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5531 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5532 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5533 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5534 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5535 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5536 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5537 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5540 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5541 * These IDs are used to forward responses to the originator on the other
5542 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5543 * the IOMMU is turned on.
5545 static void quirk_plx_ntb_dma_alias(struct pci_dev
*pdev
)
5547 pci_info(pdev
, "Setting PLX NTB proxy ID aliases\n");
5548 /* PLX NTB may use all 256 devfns */
5549 pci_add_dma_alias(pdev
, 0, 256);
5551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, 0x87b0, quirk_plx_ntb_dma_alias
);
5552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, 0x87b1, quirk_plx_ntb_dma_alias
);
5555 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5556 * not always reset the secondary Nvidia GPU between reboots if the system
5557 * is configured to use Hybrid Graphics mode. This results in the GPU
5558 * being left in whatever state it was in during the *previous* boot, which
5559 * causes spurious interrupts from the GPU, which in turn causes us to
5560 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5561 * this also completely breaks nouveau.
5563 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5564 * clean state and fixes all these issues.
5566 * When the machine is configured in Dedicated display mode, the issue
5567 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5568 * mode, so we can detect that and avoid resetting it.
5570 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev
*pdev
)
5575 if (pdev
->subsystem_vendor
!= PCI_VENDOR_ID_LENOVO
||
5576 pdev
->subsystem_device
!= 0x222e ||
5580 if (pci_enable_device_mem(pdev
))
5584 * Based on nvkm_device_ctor() in
5585 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5587 map
= pci_iomap(pdev
, 0, 0x23000);
5589 pci_err(pdev
, "Can't map MMIO space\n");
5594 * Make sure the GPU looks like it's been POSTed before resetting
5597 if (ioread32(map
+ 0x2240c) & 0x2) {
5598 pci_info(pdev
, FW_BUG
"GPU left initialized by EFI, resetting\n");
5599 ret
= pci_reset_bus(pdev
);
5601 pci_err(pdev
, "Failed to reset GPU: %d\n", ret
);
5606 pci_disable_device(pdev
);
5608 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, 0x13b1,
5609 PCI_CLASS_DISPLAY_VGA
, 8,
5610 quirk_reset_lenovo_thinkpad_p50_nvgpu
);
5613 * Device [1b21:2142]
5614 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5616 static void pci_fixup_no_d0_pme(struct pci_dev
*dev
)
5618 pci_info(dev
, "PME# does not work under D0, disabling it\n");
5619 dev
->pme_support
&= ~(PCI_PM_CAP_PME_D0
>> PCI_PM_CAP_PME_SHIFT
);
5621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA
, 0x2142, pci_fixup_no_d0_pme
);
5624 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5626 * These devices advertise PME# support in all power states but don't
5627 * reliably assert it.
5629 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5630 * says "The MSI Function is not implemented on this device" in chapters
5631 * 7.3.27, 7.3.29-7.3.31.
5633 static void pci_fixup_no_msi_no_pme(struct pci_dev
*dev
)
5635 #ifdef CONFIG_PCI_MSI
5636 pci_info(dev
, "MSI is not implemented on this device, disabling it\n");
5639 pci_info(dev
, "PME# is unreliable, disabling it\n");
5640 dev
->pme_support
= 0;
5642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM
, 0x400e, pci_fixup_no_msi_no_pme
);
5643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM
, 0x400f, pci_fixup_no_msi_no_pme
);
5645 static void apex_pci_fixup_class(struct pci_dev
*pdev
)
5647 pdev
->class = (PCI_CLASS_SYSTEM_OTHER
<< 8) | pdev
->class;
5649 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5650 PCI_CLASS_NOT_DEFINED
, 8, apex_pci_fixup_class
);
5653 * Device [8086:9a09], [8086:a0b0] and [8086:a0bc]
5654 * BIOS may not be able to access config space of devices under VMD domain, so
5655 * it relies on software to enable ASPM for links under VMD.
5657 static const struct pci_device_id vmd_bridge_tbl
[] = {
5658 { PCI_VDEVICE(INTEL
, 0x9a09) },
5659 { PCI_VDEVICE(INTEL
, 0xa0b0) },
5660 { PCI_VDEVICE(INTEL
, 0xa0bc) },
5664 static void pci_fixup_enable_aspm(struct pci_dev
*pdev
)
5666 if (!pci_match_id(vmd_bridge_tbl
, pdev
))
5669 pdev
->dev_flags
|= PCI_DEV_FLAGS_ENABLE_ASPM
;
5671 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
5672 PCI_CLASS_BRIDGE_PCI
, 8, pci_fixup_enable_aspm
);
5674 static void pci_fixup_enable_vmd_nvme_ltr(struct pci_dev
*pdev
)
5676 struct pci_dev
*parent
;
5680 parent
= pci_upstream_bridge(pdev
);
5684 if (!pci_match_id(vmd_bridge_tbl
, parent
))
5687 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_LTR
);
5691 pci_read_config_word(pdev
, pos
+ PCI_LTR_MAX_SNOOP_LAT
, &val
);
5695 pci_read_config_word(pdev
, pos
+ PCI_LTR_MAX_NOSNOOP_LAT
, &val
);
5699 /* 3145728ns, i.e. 0x300000ns */
5700 pci_write_config_word(pdev
, pos
+ PCI_LTR_MAX_SNOOP_LAT
, 0x1003);
5701 pci_write_config_word(pdev
, pos
+ PCI_LTR_MAX_NOSNOOP_LAT
, 0x1003);
5703 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
5704 PCI_CLASS_STORAGE_EXPRESS
, 0, pci_fixup_enable_vmd_nvme_ltr
);