1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/ktime.h>
27 #include <linux/nvme.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/suspend.h>
31 #include <linux/switchtec.h>
32 #include <asm/dma.h> /* isa_dma_bridge_buggy */
35 static ktime_t
fixup_debug_start(struct pci_dev
*dev
,
36 void (*fn
)(struct pci_dev
*dev
))
39 pci_info(dev
, "calling %pS @ %i\n", fn
, task_pid_nr(current
));
44 static void fixup_debug_report(struct pci_dev
*dev
, ktime_t calltime
,
45 void (*fn
)(struct pci_dev
*dev
))
47 ktime_t delta
, rettime
;
48 unsigned long long duration
;
50 rettime
= ktime_get();
51 delta
= ktime_sub(rettime
, calltime
);
52 duration
= (unsigned long long) ktime_to_ns(delta
) >> 10;
53 if (initcall_debug
|| duration
> 10000)
54 pci_info(dev
, "%pS took %lld usecs\n", fn
, duration
);
57 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
58 struct pci_fixup
*end
)
63 if ((f
->class == (u32
) (dev
->class >> f
->class_shift
) ||
64 f
->class == (u32
) PCI_ANY_ID
) &&
65 (f
->vendor
== dev
->vendor
||
66 f
->vendor
== (u16
) PCI_ANY_ID
) &&
67 (f
->device
== dev
->device
||
68 f
->device
== (u16
) PCI_ANY_ID
)) {
69 void (*hook
)(struct pci_dev
*dev
);
70 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
71 hook
= offset_to_ptr(&f
->hook_offset
);
75 calltime
= fixup_debug_start(dev
, hook
);
77 fixup_debug_report(dev
, calltime
, hook
);
81 extern struct pci_fixup __start_pci_fixups_early
[];
82 extern struct pci_fixup __end_pci_fixups_early
[];
83 extern struct pci_fixup __start_pci_fixups_header
[];
84 extern struct pci_fixup __end_pci_fixups_header
[];
85 extern struct pci_fixup __start_pci_fixups_final
[];
86 extern struct pci_fixup __end_pci_fixups_final
[];
87 extern struct pci_fixup __start_pci_fixups_enable
[];
88 extern struct pci_fixup __end_pci_fixups_enable
[];
89 extern struct pci_fixup __start_pci_fixups_resume
[];
90 extern struct pci_fixup __end_pci_fixups_resume
[];
91 extern struct pci_fixup __start_pci_fixups_resume_early
[];
92 extern struct pci_fixup __end_pci_fixups_resume_early
[];
93 extern struct pci_fixup __start_pci_fixups_suspend
[];
94 extern struct pci_fixup __end_pci_fixups_suspend
[];
95 extern struct pci_fixup __start_pci_fixups_suspend_late
[];
96 extern struct pci_fixup __end_pci_fixups_suspend_late
[];
98 static bool pci_apply_fixup_final_quirks
;
100 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
102 struct pci_fixup
*start
, *end
;
105 case pci_fixup_early
:
106 start
= __start_pci_fixups_early
;
107 end
= __end_pci_fixups_early
;
110 case pci_fixup_header
:
111 start
= __start_pci_fixups_header
;
112 end
= __end_pci_fixups_header
;
115 case pci_fixup_final
:
116 if (!pci_apply_fixup_final_quirks
)
118 start
= __start_pci_fixups_final
;
119 end
= __end_pci_fixups_final
;
122 case pci_fixup_enable
:
123 start
= __start_pci_fixups_enable
;
124 end
= __end_pci_fixups_enable
;
127 case pci_fixup_resume
:
128 start
= __start_pci_fixups_resume
;
129 end
= __end_pci_fixups_resume
;
132 case pci_fixup_resume_early
:
133 start
= __start_pci_fixups_resume_early
;
134 end
= __end_pci_fixups_resume_early
;
137 case pci_fixup_suspend
:
138 start
= __start_pci_fixups_suspend
;
139 end
= __end_pci_fixups_suspend
;
142 case pci_fixup_suspend_late
:
143 start
= __start_pci_fixups_suspend_late
;
144 end
= __end_pci_fixups_suspend_late
;
148 /* stupid compiler warning, you would think with an enum... */
151 pci_do_fixups(dev
, start
, end
);
153 EXPORT_SYMBOL(pci_fixup_device
);
155 static int __init
pci_apply_final_quirks(void)
157 struct pci_dev
*dev
= NULL
;
161 if (pci_cache_line_size
)
162 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size
<< 2);
164 pci_apply_fixup_final_quirks
= true;
165 for_each_pci_dev(dev
) {
166 pci_fixup_device(pci_fixup_final
, dev
);
168 * If arch hasn't set it explicitly yet, use the CLS
169 * value shared by all PCI devices. If there's a
170 * mismatch, fall back to the default value.
172 if (!pci_cache_line_size
) {
173 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
176 if (!tmp
|| cls
== tmp
)
179 pci_info(dev
, "CLS mismatch (%u != %u), using %u bytes\n",
181 pci_dfl_cache_line_size
<< 2);
182 pci_cache_line_size
= pci_dfl_cache_line_size
;
186 if (!pci_cache_line_size
) {
187 pr_info("PCI: CLS %u bytes, default %u\n", cls
<< 2,
188 pci_dfl_cache_line_size
<< 2);
189 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
194 fs_initcall_sync(pci_apply_final_quirks
);
197 * Decoding should be disabled for a PCI device during BAR sizing to avoid
198 * conflict. But doing so may cause problems on host bridge and perhaps other
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
202 static void quirk_mmio_always_on(struct pci_dev
*dev
)
204 dev
->mmio_always_on
= 1;
206 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
207 PCI_CLASS_BRIDGE_HOST
, 8, quirk_mmio_always_on
);
210 * The Mellanox Tavor device gives false positive parity errors. Disable
211 * parity error reporting.
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR
, pci_disable_parity
);
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
, pci_disable_parity
);
217 * Deal with broken BIOSes that neglect to enable passive release,
218 * which can cause problems in combination with the 82441FX/PPro MTRRs
220 static void quirk_passive_release(struct pci_dev
*dev
)
222 struct pci_dev
*d
= NULL
;
226 * We have to make sure a particular bit is set in the PIIX3
227 * ISA bridge, so we have to go out and find it.
229 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
230 pci_read_config_byte(d
, 0x82, &dlc
);
232 pci_info(d
, "PIIX3: Enabling Passive Release\n");
234 pci_write_config_byte(d
, 0x82, dlc
);
238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
242 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
243 * workaround but VIA don't answer queries. If you happen to have good
244 * contacts at VIA ask them for me please -- Alan
246 * This appears to be BIOS not version dependent. So presumably there is a
249 static void quirk_isa_dma_hangs(struct pci_dev
*dev
)
251 if (!isa_dma_bridge_buggy
) {
252 isa_dma_bridge_buggy
= 1;
253 pci_info(dev
, "Activating ISA DMA hang workarounds\n");
257 * It's not totally clear which chipsets are the problematic ones. We know
258 * 82C586 and 82C596 variants are affected.
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
269 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
270 * for some HT machines to use C4 w/o hanging.
272 static void quirk_tigerpoint_bm_sts(struct pci_dev
*dev
)
277 pci_read_config_dword(dev
, 0x40, &pmbase
);
278 pmbase
= pmbase
& 0xff80;
282 pci_info(dev
, FW_BUG
"TigerPoint LPC.BM_STS cleared\n");
286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_TGP_LPC
, quirk_tigerpoint_bm_sts
);
288 /* Chipsets where PCI->PCI transfers vanish or hang */
289 static void quirk_nopcipci(struct pci_dev
*dev
)
291 if ((pci_pci_problems
& PCIPCI_FAIL
) == 0) {
292 pci_info(dev
, "Disabling direct PCI/PCI transfers\n");
293 pci_pci_problems
|= PCIPCI_FAIL
;
296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
299 static void quirk_nopciamd(struct pci_dev
*dev
)
302 pci_read_config_byte(dev
, 0x08, &rev
);
305 pci_info(dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
306 pci_pci_problems
|= PCIAGP_FAIL
;
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
311 /* Triton requires workarounds to be used by the drivers */
312 static void quirk_triton(struct pci_dev
*dev
)
314 if ((pci_pci_problems
&PCIPCI_TRITON
) == 0) {
315 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
316 pci_pci_problems
|= PCIPCI_TRITON
;
319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
325 * VIA Apollo KT133 needs PCI latency patch
326 * Made according to a Windows driver-based patch by George E. Breese;
327 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
328 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
329 * which Mr Breese based his work.
331 * Updated based on further information from the site and also on
332 * information provided by VIA
334 static void quirk_vialatency(struct pci_dev
*dev
)
340 * Ok, we have a potential problem chipset here. Now see if we have
341 * a buggy southbridge.
343 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
347 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
349 * Check for buggy part revisions
351 if (p
->revision
< 0x40 || p
->revision
> 0x42)
354 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
355 if (p
== NULL
) /* No problem parts */
358 /* Check for buggy part revisions */
359 if (p
->revision
< 0x10 || p
->revision
> 0x12)
364 * Ok we have the problem. Now set the PCI master grant to occur
365 * every master grant. The apparent bug is that under high PCI load
366 * (quite common in Linux of course) you can get data loss when the
367 * CPU is held off the bus for 3 bus master requests. This happens
368 * to include the IDE controllers....
370 * VIA only apply this fix when an SB Live! is present but under
371 * both Linux and Windows this isn't enough, and we have seen
372 * corruption without SB Live! but with things like 3 UDMA IDE
373 * controllers. So we ignore that bit of the VIA recommendation..
375 pci_read_config_byte(dev
, 0x76, &busarb
);
378 * Set bit 4 and bit 5 of byte 76 to 0x01
379 * "Master priority rotation on every PCI master grant"
383 pci_write_config_byte(dev
, 0x76, busarb
);
384 pci_info(dev
, "Applying VIA southbridge workaround\n");
388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
391 /* Must restore this on a resume from RAM */
392 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
393 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
394 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
396 /* VIA Apollo VP3 needs ETBF on BT848/878 */
397 static void quirk_viaetbf(struct pci_dev
*dev
)
399 if ((pci_pci_problems
&PCIPCI_VIAETBF
) == 0) {
400 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
401 pci_pci_problems
|= PCIPCI_VIAETBF
;
404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
406 static void quirk_vsfx(struct pci_dev
*dev
)
408 if ((pci_pci_problems
&PCIPCI_VSFX
) == 0) {
409 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
410 pci_pci_problems
|= PCIPCI_VSFX
;
413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
416 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
417 * space. Latency must be set to 0xA and Triton workaround applied too.
418 * [Info kindly provided by ALi]
420 static void quirk_alimagik(struct pci_dev
*dev
)
422 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
) == 0) {
423 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
424 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
430 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
431 static void quirk_natoma(struct pci_dev
*dev
)
433 if ((pci_pci_problems
&PCIPCI_NATOMA
) == 0) {
434 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
435 pci_pci_problems
|= PCIPCI_NATOMA
;
438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
446 * This chip can cause PCI parity errors if config register 0xA0 is read
447 * while DMAs are occurring.
449 static void quirk_citrine(struct pci_dev
*dev
)
451 dev
->cfg_size
= 0xA0;
453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
456 * This chip can cause bus lockups if config addresses above 0x600
457 * are read or written.
459 static void quirk_nfp6000(struct pci_dev
*dev
)
461 dev
->cfg_size
= 0x600;
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP4000
, quirk_nfp6000
);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000
, quirk_nfp6000
);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP5000
, quirk_nfp6000
);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000_VF
, quirk_nfp6000
);
468 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
469 static void quirk_extend_bar_to_page(struct pci_dev
*dev
)
473 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++) {
474 struct resource
*r
= &dev
->resource
[i
];
476 if (r
->flags
& IORESOURCE_MEM
&& resource_size(r
) < PAGE_SIZE
) {
477 r
->end
= PAGE_SIZE
- 1;
479 r
->flags
|= IORESOURCE_UNSET
;
480 pci_info(dev
, "expanded BAR %d to page size: %pR\n",
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, 0x034a, quirk_extend_bar_to_page
);
488 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
489 * If it's needed, re-allocate the region.
491 static void quirk_s3_64M(struct pci_dev
*dev
)
493 struct resource
*r
= &dev
->resource
[0];
495 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
496 r
->flags
|= IORESOURCE_UNSET
;
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
504 static void quirk_io(struct pci_dev
*dev
, int pos
, unsigned size
,
508 struct pci_bus_region bus_region
;
509 struct resource
*res
= dev
->resource
+ pos
;
511 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), ®ion
);
516 res
->name
= pci_name(dev
);
517 res
->flags
= region
& ~PCI_BASE_ADDRESS_IO_MASK
;
519 (IORESOURCE_IO
| IORESOURCE_PCI_FIXED
| IORESOURCE_SIZEALIGN
);
520 region
&= ~(size
- 1);
522 /* Convert from PCI bus to resource space */
523 bus_region
.start
= region
;
524 bus_region
.end
= region
+ size
- 1;
525 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
527 pci_info(dev
, FW_BUG
"%s quirk: reg 0x%x: %pR\n",
528 name
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), res
);
532 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
533 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
534 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
535 * (which conflicts w/ BAR1's memory range).
537 * CS553x's ISA PCI BARs may also be read-only (ref:
538 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
540 static void quirk_cs5536_vsa(struct pci_dev
*dev
)
542 static char *name
= "CS5536 ISA bridge";
544 if (pci_resource_len(dev
, 0) != 8) {
545 quirk_io(dev
, 0, 8, name
); /* SMB */
546 quirk_io(dev
, 1, 256, name
); /* GPIO */
547 quirk_io(dev
, 2, 64, name
); /* MFGPT */
548 pci_info(dev
, "%s bug detected (incorrect header); workaround applied\n",
552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
554 static void quirk_io_region(struct pci_dev
*dev
, int port
,
555 unsigned size
, int nr
, const char *name
)
558 struct pci_bus_region bus_region
;
559 struct resource
*res
= dev
->resource
+ nr
;
561 pci_read_config_word(dev
, port
, ®ion
);
562 region
&= ~(size
- 1);
567 res
->name
= pci_name(dev
);
568 res
->flags
= IORESOURCE_IO
;
570 /* Convert from PCI bus to resource space */
571 bus_region
.start
= region
;
572 bus_region
.end
= region
+ size
- 1;
573 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
575 if (!pci_claim_resource(dev
, nr
))
576 pci_info(dev
, "quirk: %pR claimed by %s\n", res
, name
);
580 * ATI Northbridge setups MCE the processor if you even read somewhere
581 * between 0x3b0->0x3bb or read 0x3d3
583 static void quirk_ati_exploding_mce(struct pci_dev
*dev
)
585 pci_info(dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
586 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
587 request_region(0x3b0, 0x0C, "RadeonIGP");
588 request_region(0x3d3, 0x01, "RadeonIGP");
590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
593 * In the AMD NL platform, this device ([1022:7912]) has a class code of
594 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
597 * But the dwc3 driver is a more specific driver for this device, and we'd
598 * prefer to use it instead of xhci. To prevent xhci from claiming the
599 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
600 * defines as "USB device (not host controller)". The dwc3 driver can then
601 * claim it based on its Vendor and Device ID.
603 static void quirk_amd_nl_class(struct pci_dev
*pdev
)
605 u32
class = pdev
->class;
607 /* Use "USB Device (not host controller)" class */
608 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
609 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_NL_USB
,
616 * Synopsys USB 3.x host HAPS platform has a class code of
617 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
618 * devices should use dwc3-haps driver. Change these devices' class code to
619 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
622 static void quirk_synopsys_haps(struct pci_dev
*pdev
)
624 u32
class = pdev
->class;
626 switch (pdev
->device
) {
627 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3
:
628 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI
:
629 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31
:
630 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
631 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
636 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS
, PCI_ANY_ID
,
637 PCI_CLASS_SERIAL_USB_XHCI
, 0,
638 quirk_synopsys_haps
);
641 * Let's make the southbridge information explicit instead of having to
642 * worry about people probing the ACPI areas, for example.. (Yes, it
643 * happens, and if you read the wrong ACPI register it will put the machine
644 * to sleep with no way of waking it up again. Bummer).
646 * ALI M7101: Two IO regions pointed to by words at
647 * 0xE0 (64 bytes of ACPI registers)
648 * 0xE2 (32 bytes of SMB registers)
650 static void quirk_ali7101_acpi(struct pci_dev
*dev
)
652 quirk_io_region(dev
, 0xE0, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
653 quirk_io_region(dev
, 0xE2, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
657 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
660 u32 mask
, size
, base
;
662 pci_read_config_dword(dev
, port
, &devres
);
663 if ((devres
& enable
) != enable
)
665 mask
= (devres
>> 16) & 15;
666 base
= devres
& 0xffff;
669 unsigned bit
= size
>> 1;
670 if ((bit
& mask
) == bit
)
675 * For now we only print it out. Eventually we'll want to
676 * reserve it (at least if it's in the 0x1000+ range), but
677 * let's get enough confirmation reports first.
680 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
683 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
686 u32 mask
, size
, base
;
688 pci_read_config_dword(dev
, port
, &devres
);
689 if ((devres
& enable
) != enable
)
691 base
= devres
& 0xffff0000;
692 mask
= (devres
& 0x3f) << 16;
695 unsigned bit
= size
>> 1;
696 if ((bit
& mask
) == bit
)
702 * For now we only print it out. Eventually we'll want to
703 * reserve it, but let's get enough confirmation reports first.
706 pci_info(dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
710 * PIIX4 ACPI: Two IO regions pointed to by longwords at
711 * 0x40 (64 bytes of ACPI registers)
712 * 0x90 (16 bytes of SMB registers)
713 * and a few strange programmable PIIX4 device resources.
715 static void quirk_piix4_acpi(struct pci_dev
*dev
)
719 quirk_io_region(dev
, 0x40, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
720 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
722 /* Device resource A has enables for some of the other ones */
723 pci_read_config_dword(dev
, 0x5c, &res_a
);
725 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
726 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
728 /* Device resource D is just bitfields for static resources */
730 /* Device 12 enabled? */
731 if (res_a
& (1 << 29)) {
732 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
733 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
735 /* Device 13 enabled? */
736 if (res_a
& (1 << 30)) {
737 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
738 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
740 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
741 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
743 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
746 #define ICH_PMBASE 0x40
747 #define ICH_ACPI_CNTL 0x44
748 #define ICH4_ACPI_EN 0x10
749 #define ICH6_ACPI_EN 0x80
750 #define ICH4_GPIOBASE 0x58
751 #define ICH4_GPIO_CNTL 0x5c
752 #define ICH4_GPIO_EN 0x10
753 #define ICH6_GPIOBASE 0x48
754 #define ICH6_GPIO_CNTL 0x4c
755 #define ICH6_GPIO_EN 0x10
758 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
759 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
760 * 0x58 (64 bytes of GPIO I/O space)
762 static void quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
767 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
768 * with low legacy (and fixed) ports. We don't know the decoding
769 * priority and can't tell whether the legacy device or the one created
770 * here is really at that address. This happens on boards with broken
773 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
774 if (enable
& ICH4_ACPI_EN
)
775 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
776 "ICH4 ACPI/GPIO/TCO");
778 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
779 if (enable
& ICH4_GPIO_EN
)
780 quirk_io_region(dev
, ICH4_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
784 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
786 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
794 static void ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
798 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
799 if (enable
& ICH6_ACPI_EN
)
800 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
801 "ICH6 ACPI/GPIO/TCO");
803 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
804 if (enable
& ICH6_GPIO_EN
)
805 quirk_io_region(dev
, ICH6_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
809 static void ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
810 const char *name
, int dynsize
)
815 pci_read_config_dword(dev
, reg
, &val
);
823 * This is not correct. It is 16, 32 or 64 bytes depending on
824 * register D31:F0:ADh bits 5:4.
826 * But this gets us at least _part_ of it.
835 * Just print it out for now. We should reserve it after more
838 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
841 static void quirk_ich6_lpc(struct pci_dev
*dev
)
843 /* Shared ACPI/GPIO decode with all ICH6+ */
844 ich6_lpc_acpi_gpio(dev
);
846 /* ICH6-specific generic IO decode */
847 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
848 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
853 static void ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
859 pci_read_config_dword(dev
, reg
, &val
);
865 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
867 mask
= (val
>> 16) & 0xfc;
871 * Just print it out for now. We should reserve it after more
874 pci_info(dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
877 /* ICH7-10 has the same common LPC generic IO decode registers */
878 static void quirk_ich7_lpc(struct pci_dev
*dev
)
880 /* We share the common ACPI/GPIO decode with ICH6 */
881 ich6_lpc_acpi_gpio(dev
);
883 /* And have 4 ICH7+ generic decodes */
884 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
885 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
886 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
887 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
901 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
904 * VIA ACPI: One IO region pointed to by longword at
905 * 0x48 or 0x20 (256 bytes of ACPI registers)
907 static void quirk_vt82c586_acpi(struct pci_dev
*dev
)
909 if (dev
->revision
& 0x10)
910 quirk_io_region(dev
, 0x48, 256, PCI_BRIDGE_RESOURCES
,
913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
916 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
917 * 0x48 (256 bytes of ACPI registers)
918 * 0x70 (128 bytes of hardware monitoring register)
919 * 0x90 (16 bytes of SMB registers)
921 static void quirk_vt82c686_acpi(struct pci_dev
*dev
)
923 quirk_vt82c586_acpi(dev
);
925 quirk_io_region(dev
, 0x70, 128, PCI_BRIDGE_RESOURCES
+1,
928 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+2, "vt82c686 SMB");
930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
933 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
934 * 0x88 (128 bytes of power management registers)
935 * 0xd0 (16 bytes of SMB registers)
937 static void quirk_vt8235_acpi(struct pci_dev
*dev
)
939 quirk_io_region(dev
, 0x88, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
940 quirk_io_region(dev
, 0xd0, 16, PCI_BRIDGE_RESOURCES
+1, "vt8235 SMB");
942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
945 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
946 * back-to-back: Disable fast back-to-back on the secondary bus segment
948 static void quirk_xio2000a(struct pci_dev
*dev
)
950 struct pci_dev
*pdev
;
953 pci_warn(dev
, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
954 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
955 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
956 if (command
& PCI_COMMAND_FAST_BACK
)
957 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
960 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
963 #ifdef CONFIG_X86_IO_APIC
965 #include <asm/io_apic.h>
968 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
969 * devices to the external APIC.
971 * TODO: When we have device-specific interrupt routers, this code will go
974 static void quirk_via_ioapic(struct pci_dev
*dev
)
979 tmp
= 0; /* nothing routed to external APIC */
981 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
983 pci_info(dev
, "%sbling VIA external APIC routing\n",
984 tmp
== 0 ? "Disa" : "Ena");
986 /* Offset 0x58: External APIC IRQ output control */
987 pci_write_config_byte(dev
, 0x58, tmp
);
989 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
990 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
993 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
994 * This leads to doubled level interrupt rates.
995 * Set this bit to get rid of cycle wastage.
996 * Otherwise uncritical.
998 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
1001 #define BYPASS_APIC_DEASSERT 8
1003 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
1004 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
1005 pci_info(dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
1006 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
1009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
1010 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
1013 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1014 * We check all revs >= B0 (yet not in the pre production!) as the bug
1015 * is currently marked NoFix
1017 * We have multiple reports of hangs with this chipset that went away with
1018 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1019 * of course. However the advice is demonstrably good even if so.
1021 static void quirk_amd_ioapic(struct pci_dev
*dev
)
1023 if (dev
->revision
>= 0x02) {
1024 pci_warn(dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1025 pci_warn(dev
, " : booting with the \"noapic\" option\n");
1028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
1029 #endif /* CONFIG_X86_IO_APIC */
1031 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1033 static void quirk_cavium_sriov_rnm_link(struct pci_dev
*dev
)
1035 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1036 if (dev
->subsystem_device
== 0xa118)
1037 dev
->sriov
->link
= dev
->devfn
;
1039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM
, 0xa018, quirk_cavium_sriov_rnm_link
);
1043 * Some settings of MMRBC can lead to data corruption so block changes.
1044 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1046 static void quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
1048 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
1049 pci_info(dev
, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1051 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
1054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
1057 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1058 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1059 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1060 * of the ACPI SCI interrupt is only done for convenience.
1063 static void quirk_via_acpi(struct pci_dev
*d
)
1067 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1068 pci_read_config_byte(d
, 0x42, &irq
);
1070 if (irq
&& (irq
!= 2))
1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
1074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
1076 /* VIA bridges which have VLink */
1077 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
1079 static void quirk_via_bridge(struct pci_dev
*dev
)
1081 /* See what bridge we have and find the device ranges */
1082 switch (dev
->device
) {
1083 case PCI_DEVICE_ID_VIA_82C686
:
1085 * The VT82C686 is special; it attaches to PCI and can have
1086 * any device number. All its subdevices are functions of
1087 * that single device.
1089 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
1090 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
1092 case PCI_DEVICE_ID_VIA_8237
:
1093 case PCI_DEVICE_ID_VIA_8237A
:
1094 via_vlink_dev_lo
= 15;
1096 case PCI_DEVICE_ID_VIA_8235
:
1097 via_vlink_dev_lo
= 16;
1099 case PCI_DEVICE_ID_VIA_8231
:
1100 case PCI_DEVICE_ID_VIA_8233_0
:
1101 case PCI_DEVICE_ID_VIA_8233A
:
1102 case PCI_DEVICE_ID_VIA_8233C_0
:
1103 via_vlink_dev_lo
= 17;
1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
1109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
1117 * quirk_via_vlink - VIA VLink IRQ number update
1120 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1121 * the IRQ line register which usually is not relevant for PCI cards, is
1122 * actually written so that interrupts get sent to the right place.
1124 * We only do this on systems where a VIA south bridge was detected, and
1125 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1127 static void quirk_via_vlink(struct pci_dev
*dev
)
1131 /* Check if we have VLink at all */
1132 if (via_vlink_dev_lo
== -1)
1137 /* Don't quirk interrupts outside the legacy IRQ range */
1138 if (!new_irq
|| new_irq
> 15)
1141 /* Internal device ? */
1142 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
1143 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
1147 * This is an internal VLink device on a PIC interrupt. The BIOS
1148 * ought to have set this but may not have, so we redo it.
1150 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1151 if (new_irq
!= irq
) {
1152 pci_info(dev
, "VIA VLink IRQ fixup, from %d to %d\n",
1154 udelay(15); /* unknown if delay really needed */
1155 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
1158 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
1161 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1162 * of VT82C597 for backward compatibility. We need to switch it off to be
1163 * able to recognize the real type of the chip.
1165 static void quirk_vt82c598_id(struct pci_dev
*dev
)
1167 pci_write_config_byte(dev
, 0xfc, 0);
1168 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
1173 * CardBus controllers have a legacy base address that enables them to
1174 * respond as i82365 pcmcia controllers. We don't want them to do this
1175 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1176 * driver does not (and should not) handle CardBus.
1178 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
1180 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
1182 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1183 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1184 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
1185 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1188 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1189 * what the designers were smoking but let's not inhale...
1191 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1194 static void quirk_amd_ordering(struct pci_dev
*dev
)
1197 pci_read_config_dword(dev
, 0x4C, &pcic
);
1198 if ((pcic
& 6) != 6) {
1200 pci_warn(dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1201 pci_write_config_dword(dev
, 0x4C, pcic
);
1202 pci_read_config_dword(dev
, 0x84, &pcic
);
1203 pcic
|= (1 << 23); /* Required in this mode */
1204 pci_write_config_dword(dev
, 0x84, pcic
);
1207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1208 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1211 * DreamWorks-provided workaround for Dunord I-3000 problem
1213 * This card decodes and responds to addresses not apparently assigned to
1214 * it. We force a larger allocation to ensure that nothing gets put too
1217 static void quirk_dunord(struct pci_dev
*dev
)
1219 struct resource
*r
= &dev
->resource
[1];
1221 r
->flags
|= IORESOURCE_UNSET
;
1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
1228 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1229 * decoding (transparent), and does indicate this in the ProgIf.
1230 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1232 static void quirk_transparent_bridge(struct pci_dev
*dev
)
1234 dev
->transparent
= 1;
1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1240 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1241 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1242 * found at http://www.national.com/analog for info on what these bits do.
1243 * <christer@weinigel.se>
1245 static void quirk_mediagx_master(struct pci_dev
*dev
)
1249 pci_read_config_byte(dev
, 0x41, ®
);
1252 pci_info(dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1254 pci_write_config_byte(dev
, 0x41, reg
);
1257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1258 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1261 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1262 * in the odd case it is not the results are corruption hence the presence
1265 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1269 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1271 pci_read_config_word(pdev
, 0x40, &config
);
1272 if (config
& (1<<6)) {
1274 pci_write_config_word(pdev
, 0x40, config
);
1275 pci_info(pdev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1279 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1281 static void quirk_amd_ide_mode(struct pci_dev
*pdev
)
1283 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1286 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1288 pci_read_config_byte(pdev
, 0x40, &tmp
);
1289 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1290 pci_write_config_byte(pdev
, 0x9, 1);
1291 pci_write_config_byte(pdev
, 0xa, 6);
1292 pci_write_config_byte(pdev
, 0x40, tmp
);
1294 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1295 pci_info(pdev
, "set SATA to AHCI mode\n");
1298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1301 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1303 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1305 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1307 /* Serverworks CSB5 IDE does not fully support native mode */
1308 static void quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1311 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1315 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1316 /* PCI layer will sort out resources */
1319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1321 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1322 static void quirk_ide_samemode(struct pci_dev
*pdev
)
1326 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1328 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1329 pci_info(pdev
, "IDE mode mismatch; forcing legacy mode\n");
1332 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1335 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1337 /* Some ATA devices break if put into D3 */
1338 static void quirk_no_ata_d3(struct pci_dev
*pdev
)
1340 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1342 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1343 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
,
1344 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1345 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
1346 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1347 /* ALi loses some register settings that we cannot then restore */
1348 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
,
1349 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1350 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1351 occur when mode detecting */
1352 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
1353 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1356 * This was originally an Alpha-specific thing, but it really fits here.
1357 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1359 static void quirk_eisa_bridge(struct pci_dev
*dev
)
1361 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1363 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1366 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1367 * is not activated. The myth is that Asus said that they do not want the
1368 * users to be irritated by just another PCI Device in the Win98 device
1369 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1370 * package 2.7.0 for details)
1372 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1373 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1374 * becomes necessary to do this tweak in two steps -- the chosen trigger
1375 * is either the Host bridge (preferred) or on-board VGA controller.
1377 * Note that we used to unhide the SMBus that way on Toshiba laptops
1378 * (Satellite A40 and Tecra M2) but then found that the thermal management
1379 * was done by SMM code, which could cause unsynchronized concurrent
1380 * accesses to the SMBus registers, with potentially bad effects. Thus you
1381 * should be very careful when adding new entries: if SMM is accessing the
1382 * Intel SMBus, this is a very good reason to leave it hidden.
1384 * Likewise, many recent laptops use ACPI for thermal management. If the
1385 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1386 * natively, and keeping the SMBus hidden is the right thing to do. If you
1387 * are about to add an entry in the table below, please first disassemble
1388 * the DSDT and double-check that there is no code accessing the SMBus.
1390 static int asus_hides_smbus
;
1392 static void asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1394 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1395 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1396 switch (dev
->subsystem_device
) {
1397 case 0x8025: /* P4B-LX */
1398 case 0x8070: /* P4B */
1399 case 0x8088: /* P4B533 */
1400 case 0x1626: /* L3C notebook */
1401 asus_hides_smbus
= 1;
1403 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1404 switch (dev
->subsystem_device
) {
1405 case 0x80b1: /* P4GE-V */
1406 case 0x80b2: /* P4PE */
1407 case 0x8093: /* P4B533-V */
1408 asus_hides_smbus
= 1;
1410 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1411 switch (dev
->subsystem_device
) {
1412 case 0x8030: /* P4T533 */
1413 asus_hides_smbus
= 1;
1415 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1416 switch (dev
->subsystem_device
) {
1417 case 0x8070: /* P4G8X Deluxe */
1418 asus_hides_smbus
= 1;
1420 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1421 switch (dev
->subsystem_device
) {
1422 case 0x80c9: /* PU-DLS */
1423 asus_hides_smbus
= 1;
1425 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1426 switch (dev
->subsystem_device
) {
1427 case 0x1751: /* M2N notebook */
1428 case 0x1821: /* M5N notebook */
1429 case 0x1897: /* A6L notebook */
1430 asus_hides_smbus
= 1;
1432 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1433 switch (dev
->subsystem_device
) {
1434 case 0x184b: /* W1N notebook */
1435 case 0x186a: /* M6Ne notebook */
1436 asus_hides_smbus
= 1;
1438 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1439 switch (dev
->subsystem_device
) {
1440 case 0x80f2: /* P4P800-X */
1441 asus_hides_smbus
= 1;
1443 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1444 switch (dev
->subsystem_device
) {
1445 case 0x1882: /* M6V notebook */
1446 case 0x1977: /* A6VA notebook */
1447 asus_hides_smbus
= 1;
1449 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1450 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1451 switch (dev
->subsystem_device
) {
1452 case 0x088C: /* HP Compaq nc8000 */
1453 case 0x0890: /* HP Compaq nc6000 */
1454 asus_hides_smbus
= 1;
1456 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1457 switch (dev
->subsystem_device
) {
1458 case 0x12bc: /* HP D330L */
1459 case 0x12bd: /* HP D530 */
1460 case 0x006a: /* HP Compaq nx9500 */
1461 asus_hides_smbus
= 1;
1463 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1464 switch (dev
->subsystem_device
) {
1465 case 0x12bf: /* HP xw4100 */
1466 asus_hides_smbus
= 1;
1468 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1469 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1470 switch (dev
->subsystem_device
) {
1471 case 0xC00C: /* Samsung P35 notebook */
1472 asus_hides_smbus
= 1;
1474 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1475 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1476 switch (dev
->subsystem_device
) {
1477 case 0x0058: /* Compaq Evo N620c */
1478 asus_hides_smbus
= 1;
1480 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1481 switch (dev
->subsystem_device
) {
1482 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1483 /* Motherboard doesn't have Host bridge
1484 * subvendor/subdevice IDs, therefore checking
1485 * its on-board VGA controller */
1486 asus_hides_smbus
= 1;
1488 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1489 switch (dev
->subsystem_device
) {
1490 case 0x00b8: /* Compaq Evo D510 CMT */
1491 case 0x00b9: /* Compaq Evo D510 SFF */
1492 case 0x00ba: /* Compaq Evo D510 USDT */
1493 /* Motherboard doesn't have Host bridge
1494 * subvendor/subdevice IDs and on-board VGA
1495 * controller is disabled if an AGP card is
1496 * inserted, therefore checking USB UHCI
1498 asus_hides_smbus
= 1;
1500 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1501 switch (dev
->subsystem_device
) {
1502 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1503 /* Motherboard doesn't have host bridge
1504 * subvendor/subdevice IDs, therefore checking
1505 * its on-board VGA controller */
1506 asus_hides_smbus
= 1;
1510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1525 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1529 if (likely(!asus_hides_smbus
))
1532 pci_read_config_word(dev
, 0xF2, &val
);
1534 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1535 pci_read_config_word(dev
, 0xF2, &val
);
1537 pci_info(dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1540 pci_info(dev
, "Enabled i801 SMBus device\n");
1543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1549 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1550 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1551 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1552 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1553 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1556 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1558 /* It appears we just have one such device. If not, we have a warning */
1559 static void __iomem
*asus_rcba_base
;
1560 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1564 if (likely(!asus_hides_smbus
))
1566 WARN_ON(asus_rcba_base
);
1568 pci_read_config_dword(dev
, 0xF0, &rcba
);
1569 /* use bits 31:14, 16 kB aligned */
1570 asus_rcba_base
= ioremap(rcba
& 0xFFFFC000, 0x4000);
1571 if (asus_rcba_base
== NULL
)
1575 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1579 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1582 /* read the Function Disable register, dword mode only */
1583 val
= readl(asus_rcba_base
+ 0x3418);
1585 /* enable the SMBus device */
1586 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418);
1589 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1591 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1594 iounmap(asus_rcba_base
);
1595 asus_rcba_base
= NULL
;
1596 pci_info(dev
, "Enabled ICH6/i801 SMBus device\n");
1599 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1601 asus_hides_smbus_lpc_ich6_suspend(dev
);
1602 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1603 asus_hides_smbus_lpc_ich6_resume(dev
);
1605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1606 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1607 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1610 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1611 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1614 pci_read_config_byte(dev
, 0x77, &val
);
1616 pci_info(dev
, "Enabling SiS 96x SMBus\n");
1617 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1623 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1624 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1625 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1626 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1627 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1630 * ... This is further complicated by the fact that some SiS96x south
1631 * bridges pretend to be 85C503/5513 instead. In that case see if we
1632 * spotted a compatible north bridge to make sure.
1633 * (pci_find_device() doesn't work yet)
1635 * We can also enable the sis96x bit in the discovery register..
1637 #define SIS_DETECT_REGISTER 0x40
1639 static void quirk_sis_503(struct pci_dev
*dev
)
1644 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1645 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1646 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1647 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1648 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1653 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1654 * it has already been processed. (Depends on link order, which is
1655 * apparently not guaranteed)
1657 dev
->device
= devid
;
1658 quirk_sis_96x_smbus(dev
);
1660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1661 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1664 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1665 * and MC97 modem controller are disabled when a second PCI soundcard is
1666 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1669 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1672 int asus_hides_ac97
= 0;
1674 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1675 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1676 asus_hides_ac97
= 1;
1679 if (!asus_hides_ac97
)
1682 pci_read_config_byte(dev
, 0x50, &val
);
1684 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1685 pci_read_config_byte(dev
, 0x50, &val
);
1687 pci_info(dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1690 pci_info(dev
, "Enabled onboard AC97/MC97 devices\n");
1693 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1694 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1696 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1699 * If we are using libata we can drive this chip properly but must do this
1700 * early on to make the additional device appear during the PCI scanning.
1702 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1704 u32 conf1
, conf5
, class;
1707 /* Only poke fn 0 */
1708 if (PCI_FUNC(pdev
->devfn
))
1711 pci_read_config_dword(pdev
, 0x40, &conf1
);
1712 pci_read_config_dword(pdev
, 0x80, &conf5
);
1714 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1715 conf5
&= ~(1 << 24); /* Clear bit 24 */
1717 switch (pdev
->device
) {
1718 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1719 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1720 case PCI_DEVICE_ID_JMICRON_JMB364
: /* SATA dual ports */
1721 /* The controller should be in single function ahci mode */
1722 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1725 case PCI_DEVICE_ID_JMICRON_JMB365
:
1726 case PCI_DEVICE_ID_JMICRON_JMB366
:
1727 /* Redirect IDE second PATA port to the right spot */
1730 case PCI_DEVICE_ID_JMICRON_JMB361
:
1731 case PCI_DEVICE_ID_JMICRON_JMB363
:
1732 case PCI_DEVICE_ID_JMICRON_JMB369
:
1733 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1734 /* Set the class codes correctly and then direct IDE 0 */
1735 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1738 case PCI_DEVICE_ID_JMICRON_JMB368
:
1739 /* The controller should be in single function IDE mode */
1740 conf1
|= 0x00C00000; /* Set 22, 23 */
1744 pci_write_config_dword(pdev
, 0x40, conf1
);
1745 pci_write_config_dword(pdev
, 0x80, conf5
);
1747 /* Update pdev accordingly */
1748 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1749 pdev
->hdr_type
= hdr
& 0x7f;
1750 pdev
->multifunction
= !!(hdr
& 0x80);
1752 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1753 pdev
->class = class >> 8;
1755 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1756 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1757 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1758 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1763 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1764 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1765 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1766 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1767 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1772 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1776 static void quirk_jmicron_async_suspend(struct pci_dev
*dev
)
1778 if (dev
->multifunction
) {
1779 device_disable_async_suspend(&dev
->dev
);
1780 pci_info(dev
, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1783 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_IDE
, 8, quirk_jmicron_async_suspend
);
1784 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_SATA_AHCI
, 0, quirk_jmicron_async_suspend
);
1785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x2362, quirk_jmicron_async_suspend
);
1786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x236f, quirk_jmicron_async_suspend
);
1788 #ifdef CONFIG_X86_IO_APIC
1789 static void quirk_alder_ioapic(struct pci_dev
*pdev
)
1793 if ((pdev
->class >> 8) != 0xff00)
1797 * The first BAR is the location of the IO-APIC... we must
1798 * not touch this (and it's already covered by the fixmap), so
1799 * forcibly insert it into the resource tree.
1801 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1802 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1805 * The next five BARs all seem to be rubbish, so just clean
1808 for (i
= 1; i
< PCI_STD_NUM_BARS
; i
++)
1809 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1814 static void quirk_pcie_mch(struct pci_dev
*pdev
)
1818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1822 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI
, 0x1610, PCI_CLASS_BRIDGE_PCI
, 8, quirk_pcie_mch
);
1825 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1826 * together on certain PXH-based systems.
1828 static void quirk_pcie_pxh(struct pci_dev
*dev
)
1831 pci_warn(dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1833 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1834 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1835 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1836 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1837 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1840 * Some Intel PCI Express chipsets have trouble with downstream device
1843 static void quirk_intel_pcie_pm(struct pci_dev
*dev
)
1845 pci_pm_d3hot_delay
= 120;
1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1870 static void quirk_d3hot_delay(struct pci_dev
*dev
, unsigned int delay
)
1872 if (dev
->d3hot_delay
>= delay
)
1875 dev
->d3hot_delay
= delay
;
1876 pci_info(dev
, "extending delay after power-on from D3hot to %d msec\n",
1880 static void quirk_radeon_pm(struct pci_dev
*dev
)
1882 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
&&
1883 dev
->subsystem_device
== 0x00e2)
1884 quirk_d3hot_delay(dev
, 20);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6741, quirk_radeon_pm
);
1889 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1890 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1892 * The kernel attempts to transition these devices to D3cold, but that seems
1893 * to be ineffective on the platforms in question; the PCI device appears to
1894 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1895 * extended delay in order to succeed.
1897 static void quirk_ryzen_xhci_d3hot(struct pci_dev
*dev
)
1899 quirk_d3hot_delay(dev
, 20);
1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x15e0, quirk_ryzen_xhci_d3hot
);
1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x15e1, quirk_ryzen_xhci_d3hot
);
1904 #ifdef CONFIG_X86_IO_APIC
1905 static int dmi_disable_ioapicreroute(const struct dmi_system_id
*d
)
1907 noioapicreroute
= 1;
1908 pr_info("%s detected: disable boot interrupt reroute\n", d
->ident
);
1913 static const struct dmi_system_id boot_interrupt_dmi_table
[] = {
1915 * Systems to exclude from boot interrupt reroute quirks
1918 .callback
= dmi_disable_ioapicreroute
,
1919 .ident
= "ASUSTek Computer INC. M2N-LR",
1921 DMI_MATCH(DMI_SYS_VENDOR
, "ASUSTek Computer INC."),
1922 DMI_MATCH(DMI_PRODUCT_NAME
, "M2N-LR"),
1929 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1930 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1931 * that a PCI device's interrupt handler is installed on the boot interrupt
1934 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1936 dmi_check_system(boot_interrupt_dmi_table
);
1937 if (noioapicquirk
|| noioapicreroute
)
1940 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1941 pci_info(dev
, "rerouting interrupts for [%04x:%04x]\n",
1942 dev
->vendor
, dev
->device
);
1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1952 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1953 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1954 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1955 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1956 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1957 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1958 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1959 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1962 * On some chipsets we can disable the generation of legacy INTx boot
1967 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1968 * 300641-004US, section 5.7.3.
1970 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1971 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1972 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1973 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1974 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1975 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1976 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1977 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1978 * Core IO on Xeon Scalable, see Intel order no 610950.
1980 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
1981 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1983 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1984 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1986 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
1988 u16 pci_config_word
;
1989 u32 pci_config_dword
;
1994 switch (dev
->device
) {
1995 case PCI_DEVICE_ID_INTEL_ESB_10
:
1996 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
,
1998 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
1999 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
,
2002 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2003 case 0x0e28: /* Xeon E5/E7 V2 */
2004 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2005 case 0x6f28: /* Xeon D-1500 */
2006 case 0x2034: /* Xeon Scalable Family */
2007 pci_read_config_dword(dev
, INTEL_CIPINTRC_CFG_OFFSET
,
2009 pci_config_dword
|= INTEL_CIPINTRC_DIS_INTX_ICH
;
2010 pci_write_config_dword(dev
, INTEL_CIPINTRC_CFG_OFFSET
,
2016 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2017 dev
->vendor
, dev
->device
);
2020 * Device 29 Func 5 Device IDs of IO-APIC
2021 * containing ABAR—APIC1 Alternate Base Address Register
2023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
,
2024 quirk_disable_intel_boot_interrupt
);
2025 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
,
2026 quirk_disable_intel_boot_interrupt
);
2029 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2030 * containing Coherent Interface Protocol Interrupt Control
2032 * Device IDs obtained from volume 2 datasheets of commented
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x3c28,
2036 quirk_disable_intel_boot_interrupt
);
2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0e28,
2038 quirk_disable_intel_boot_interrupt
);
2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2f28,
2040 quirk_disable_intel_boot_interrupt
);
2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x6f28,
2042 quirk_disable_intel_boot_interrupt
);
2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2034,
2044 quirk_disable_intel_boot_interrupt
);
2045 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x3c28,
2046 quirk_disable_intel_boot_interrupt
);
2047 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x0e28,
2048 quirk_disable_intel_boot_interrupt
);
2049 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x2f28,
2050 quirk_disable_intel_boot_interrupt
);
2051 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x6f28,
2052 quirk_disable_intel_boot_interrupt
);
2053 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, 0x2034,
2054 quirk_disable_intel_boot_interrupt
);
2056 /* Disable boot interrupts on HT-1000 */
2057 #define BC_HT1000_FEATURE_REG 0x64
2058 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2059 #define BC_HT1000_MAP_IDX 0xC00
2060 #define BC_HT1000_MAP_DATA 0xC01
2062 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
2064 u32 pci_config_dword
;
2070 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
2071 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
2072 BC_HT1000_PIC_REGS_ENABLE
);
2074 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
2075 outb(irq
, BC_HT1000_MAP_IDX
);
2076 outb(0x00, BC_HT1000_MAP_DATA
);
2079 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
2081 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2082 dev
->vendor
, dev
->device
);
2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
2085 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
2087 /* Disable boot interrupts on AMD and ATI chipsets */
2090 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2091 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2092 * (due to an erratum).
2094 #define AMD_813X_MISC 0x40
2095 #define AMD_813X_NOIOAMODE (1<<0)
2096 #define AMD_813X_REV_B1 0x12
2097 #define AMD_813X_REV_B2 0x13
2099 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
2101 u32 pci_config_dword
;
2105 if ((dev
->revision
== AMD_813X_REV_B1
) ||
2106 (dev
->revision
== AMD_813X_REV_B2
))
2109 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
2110 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
2111 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
2113 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2114 dev
->vendor
, dev
->device
);
2116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2117 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2119 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2121 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2123 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
2125 u16 pci_config_word
;
2130 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
2131 if (!pci_config_word
) {
2132 pci_info(dev
, "boot interrupts on device [%04x:%04x] already disabled\n",
2133 dev
->vendor
, dev
->device
);
2136 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
2137 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2138 dev
->vendor
, dev
->device
);
2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2141 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2142 #endif /* CONFIG_X86_IO_APIC */
2145 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2146 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2147 * Re-allocate the region if needed...
2149 static void quirk_tc86c001_ide(struct pci_dev
*dev
)
2151 struct resource
*r
= &dev
->resource
[0];
2153 if (r
->start
& 0x8) {
2154 r
->flags
|= IORESOURCE_UNSET
;
2159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
2160 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
2161 quirk_tc86c001_ide
);
2164 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2165 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2166 * being read correctly if bit 7 of the base address is set.
2167 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2168 * Re-allocate the regions to a 256-byte boundary if necessary.
2170 static void quirk_plx_pci9050(struct pci_dev
*dev
)
2174 /* Fixed in revision 2 (PCI 9052). */
2175 if (dev
->revision
>= 2)
2177 for (bar
= 0; bar
<= 1; bar
++)
2178 if (pci_resource_len(dev
, bar
) == 0x80 &&
2179 (pci_resource_start(dev
, bar
) & 0x80)) {
2180 struct resource
*r
= &dev
->resource
[bar
];
2181 pci_info(dev
, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2183 r
->flags
|= IORESOURCE_UNSET
;
2188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2191 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2192 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2193 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2194 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2196 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2199 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050
);
2200 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050
);
2202 static void quirk_netmos(struct pci_dev
*dev
)
2204 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
2205 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
2208 * These Netmos parts are multiport serial devices with optional
2209 * parallel ports. Even when parallel ports are present, they
2210 * are identified as class SERIAL, which means the serial driver
2211 * will claim them. To prevent this, mark them as class OTHER.
2212 * These combo devices should be claimed by parport_serial.
2214 * The subdevice ID is of the form 0x00PS, where <P> is the number
2215 * of parallel ports and <S> is the number of serial ports.
2217 switch (dev
->device
) {
2218 case PCI_DEVICE_ID_NETMOS_9835
:
2219 /* Well, this rule doesn't hold for the following 9835 device */
2220 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
2221 dev
->subsystem_device
== 0x0299)
2224 case PCI_DEVICE_ID_NETMOS_9735
:
2225 case PCI_DEVICE_ID_NETMOS_9745
:
2226 case PCI_DEVICE_ID_NETMOS_9845
:
2227 case PCI_DEVICE_ID_NETMOS_9855
:
2229 pci_info(dev
, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2230 dev
->device
, num_parallel
, num_serial
);
2231 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
2232 (dev
->class & 0xff);
2236 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
,
2237 PCI_CLASS_COMMUNICATION_SERIAL
, 8, quirk_netmos
);
2239 static void quirk_e100_interrupt(struct pci_dev
*dev
)
2245 switch (dev
->device
) {
2246 /* PCI IDs taken from drivers/net/e100.c */
2248 case 0x1030 ... 0x1034:
2249 case 0x1038 ... 0x103E:
2250 case 0x1050 ... 0x1057:
2252 case 0x1064 ... 0x106B:
2253 case 0x1091 ... 0x1095:
2266 * Some firmware hands off the e100 with interrupts enabled,
2267 * which can cause a flood of interrupts if packets are
2268 * received before the driver attaches to the device. So
2269 * disable all e100 interrupts here. The driver will
2270 * re-enable them when it's ready.
2272 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
2274 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
2278 * Check that the device is in the D0 power state. If it's not,
2279 * there is no point to look any further.
2282 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2283 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
2287 /* Convert from PCI bus to resource space. */
2288 csr
= ioremap(pci_resource_start(dev
, 0), 8);
2290 pci_warn(dev
, "Can't map e100 registers\n");
2294 cmd_hi
= readb(csr
+ 3);
2296 pci_warn(dev
, "Firmware left e100 interrupts enabled; disabling\n");
2302 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
2303 PCI_CLASS_NETWORK_ETHERNET
, 8, quirk_e100_interrupt
);
2306 * The 82575 and 82598 may experience data corruption issues when transitioning
2307 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2309 static void quirk_disable_aspm_l0s(struct pci_dev
*dev
)
2311 pci_info(dev
, "Disabling L0s\n");
2312 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
2314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
2316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
2317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
2318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
2319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
2320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
2325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
2326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
2327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
2329 static void quirk_disable_aspm_l0s_l1(struct pci_dev
*dev
)
2331 pci_info(dev
, "Disabling ASPM L0s/L1\n");
2332 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
);
2336 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2337 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2338 * disable both L0s and L1 for now to be safe.
2340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA
, 0x1080, quirk_disable_aspm_l0s_l1
);
2343 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2344 * Link bit cleared after starting the link retrain process to allow this
2345 * process to finish.
2347 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2348 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2350 static void quirk_enable_clear_retrain_link(struct pci_dev
*dev
)
2352 dev
->clear_retrain_link
= 1;
2353 pci_info(dev
, "Enable PCIe Retrain Link quirk\n");
2355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM
, 0xe110, quirk_enable_clear_retrain_link
);
2356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM
, 0xe111, quirk_enable_clear_retrain_link
);
2357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM
, 0xe130, quirk_enable_clear_retrain_link
);
2359 static void fixup_rev1_53c810(struct pci_dev
*dev
)
2361 u32
class = dev
->class;
2364 * rev 1 ncr53c810 chips don't set the class at all which means
2365 * they don't get their resources remapped. Fix that here.
2370 dev
->class = PCI_CLASS_STORAGE_SCSI
<< 8;
2371 pci_info(dev
, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
2376 /* Enable 1k I/O space granularity on the Intel P64H2 */
2377 static void quirk_p64h2_1k_io(struct pci_dev
*dev
)
2381 pci_read_config_word(dev
, 0x40, &en1k
);
2384 pci_info(dev
, "Enable I/O Space to 1KB granularity\n");
2385 dev
->io_window_1k
= 1;
2388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
2391 * Under some circumstances, AER is not linked with extended capabilities.
2392 * Force it to be linked by setting the corresponding control bit in the
2395 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
2399 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
2401 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
2402 pci_info(dev
, "Linking AER extended capability\n");
2406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2407 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2408 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2409 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2411 static void quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2414 * Disable PCI Bus Parking and PCI Master read caching on CX700
2415 * which causes unspecified timing errors with a VT6212L on the PCI
2416 * bus leading to USB2.0 packet loss.
2418 * This quirk is only enabled if a second (on the external PCI bus)
2419 * VT6212L is found -- the CX700 core itself also contains a USB
2420 * host controller with the same PCI ID as the VT6212L.
2423 /* Count VT6212L instances */
2424 struct pci_dev
*p
= pci_get_device(PCI_VENDOR_ID_VIA
,
2425 PCI_DEVICE_ID_VIA_8235_USB_2
, NULL
);
2429 * p should contain the first (internal) VT6212L -- see if we have
2430 * an external one by searching again.
2432 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235_USB_2
, p
);
2437 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2439 /* Turn off PCI Bus Parking */
2440 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2442 pci_info(dev
, "Disabling VIA CX700 PCI parking\n");
2446 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2448 /* Turn off PCI Master read caching */
2449 pci_write_config_byte(dev
, 0x72, 0x0);
2451 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2452 pci_write_config_byte(dev
, 0x75, 0x1);
2454 /* Disable "Read FIFO Timer" */
2455 pci_write_config_byte(dev
, 0x77, 0x0);
2457 pci_info(dev
, "Disabling VIA CX700 PCI caching\n");
2461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2463 static void quirk_brcm_5719_limit_mrrs(struct pci_dev
*dev
)
2467 pci_read_config_dword(dev
, 0xf4, &rev
);
2469 /* Only CAP the MRRS if the device is a 5719 A0 */
2470 if (rev
== 0x05719000) {
2471 int readrq
= pcie_get_readrq(dev
);
2473 pcie_set_readrq(dev
, 2048);
2476 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM
,
2477 PCI_DEVICE_ID_TIGON3_5719
,
2478 quirk_brcm_5719_limit_mrrs
);
2481 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2482 * hide device 6 which configures the overflow device access containing the
2483 * DRBs - this is where we expose device 6.
2484 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2486 static void quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2490 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2491 pci_info(dev
, "Enabling MCH 'Overflow' Device\n");
2492 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2495 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2496 quirk_unhide_mch_dev6
);
2497 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2498 quirk_unhide_mch_dev6
);
2500 #ifdef CONFIG_PCI_MSI
2502 * Some chipsets do not support MSI. We cannot easily rely on setting
2503 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2504 * other buses controlled by the chipset even if Linux is not aware of it.
2505 * Instead of setting the flag on all buses in the machine, simply disable
2508 static void quirk_disable_all_msi(struct pci_dev
*dev
)
2511 pci_warn(dev
, "MSI quirk detected; MSI disabled\n");
2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2516 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2517 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8380_0
, quirk_disable_all_msi
);
2520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, 0x0761, quirk_disable_all_msi
);
2521 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG
, 0xa5e3, quirk_disable_all_msi
);
2523 /* Disable MSI on chipsets that are known to not support it */
2524 static void quirk_disable_msi(struct pci_dev
*dev
)
2526 if (dev
->subordinate
) {
2527 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2528 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2533 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2536 * The APC bridge device in AMD 780 family northbridges has some random
2537 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2538 * we use the possible vendor/device IDs of the host bridge for the
2539 * declared quirk, and search for the APC bridge by slot number.
2541 static void quirk_amd_780_apc_msi(struct pci_dev
*host_bridge
)
2543 struct pci_dev
*apc_bridge
;
2545 apc_bridge
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(1, 0));
2547 if (apc_bridge
->device
== 0x9602)
2548 quirk_disable_msi(apc_bridge
);
2549 pci_dev_put(apc_bridge
);
2552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9600, quirk_amd_780_apc_msi
);
2553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9601, quirk_amd_780_apc_msi
);
2556 * Go through the list of HyperTransport capabilities and return 1 if a HT
2557 * MSI capability is found and enabled.
2559 static int msi_ht_cap_enabled(struct pci_dev
*dev
)
2561 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2563 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2564 while (pos
&& ttl
--) {
2567 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2569 pci_info(dev
, "Found %s HT MSI Mapping\n",
2570 flags
& HT_MSI_FLAGS_ENABLE
?
2571 "enabled" : "disabled");
2572 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2575 pos
= pci_find_next_ht_capability(dev
, pos
,
2576 HT_CAPTYPE_MSI_MAPPING
);
2581 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2582 static void quirk_msi_ht_cap(struct pci_dev
*dev
)
2584 if (!msi_ht_cap_enabled(dev
))
2585 quirk_disable_msi(dev
);
2587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2591 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2592 * if the MSI capability is set in any of these mappings.
2594 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2596 struct pci_dev
*pdev
;
2599 * Check HT MSI cap on this chipset and the root one. A single one
2600 * having MSI is enough to be sure that MSI is supported.
2602 pdev
= pci_get_slot(dev
->bus
, 0);
2605 if (!msi_ht_cap_enabled(pdev
))
2606 quirk_msi_ht_cap(dev
);
2609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2610 quirk_nvidia_ck804_msi_ht_cap
);
2612 /* Force enable MSI mapping capability on HT bridges */
2613 static void ht_enable_msi_mapping(struct pci_dev
*dev
)
2615 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2617 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2618 while (pos
&& ttl
--) {
2621 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2623 pci_info(dev
, "Enabling HT MSI Mapping\n");
2625 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2626 flags
| HT_MSI_FLAGS_ENABLE
);
2628 pos
= pci_find_next_ht_capability(dev
, pos
,
2629 HT_CAPTYPE_MSI_MAPPING
);
2632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2633 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2634 ht_enable_msi_mapping
);
2635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2636 ht_enable_msi_mapping
);
2639 * The P5N32-SLI motherboards from Asus have a problem with MSI
2640 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2641 * also affects other devices. As for now, turn off MSI for this device.
2643 static void nvenet_msi_disable(struct pci_dev
*dev
)
2645 const char *board_name
= dmi_get_system_info(DMI_BOARD_NAME
);
2648 (strstr(board_name
, "P5N32-SLI PREMIUM") ||
2649 strstr(board_name
, "P5N32-E SLI"))) {
2650 pci_info(dev
, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2654 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2655 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2656 nvenet_msi_disable
);
2659 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2660 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2661 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2662 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2663 * for other events, since PCIe specificiation doesn't support using a mix of
2664 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2665 * service drivers registering their respective ISRs for MSIs.
2667 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev
*dev
)
2671 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x1ad0,
2672 PCI_CLASS_BRIDGE_PCI
, 8,
2673 pci_quirk_nvidia_tegra_disable_rp_msi
);
2674 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x1ad1,
2675 PCI_CLASS_BRIDGE_PCI
, 8,
2676 pci_quirk_nvidia_tegra_disable_rp_msi
);
2677 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x1ad2,
2678 PCI_CLASS_BRIDGE_PCI
, 8,
2679 pci_quirk_nvidia_tegra_disable_rp_msi
);
2680 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0bf0,
2681 PCI_CLASS_BRIDGE_PCI
, 8,
2682 pci_quirk_nvidia_tegra_disable_rp_msi
);
2683 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0bf1,
2684 PCI_CLASS_BRIDGE_PCI
, 8,
2685 pci_quirk_nvidia_tegra_disable_rp_msi
);
2686 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e1c,
2687 PCI_CLASS_BRIDGE_PCI
, 8,
2688 pci_quirk_nvidia_tegra_disable_rp_msi
);
2689 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e1d,
2690 PCI_CLASS_BRIDGE_PCI
, 8,
2691 pci_quirk_nvidia_tegra_disable_rp_msi
);
2692 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e12,
2693 PCI_CLASS_BRIDGE_PCI
, 8,
2694 pci_quirk_nvidia_tegra_disable_rp_msi
);
2695 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0e13,
2696 PCI_CLASS_BRIDGE_PCI
, 8,
2697 pci_quirk_nvidia_tegra_disable_rp_msi
);
2698 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0fae,
2699 PCI_CLASS_BRIDGE_PCI
, 8,
2700 pci_quirk_nvidia_tegra_disable_rp_msi
);
2701 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x0faf,
2702 PCI_CLASS_BRIDGE_PCI
, 8,
2703 pci_quirk_nvidia_tegra_disable_rp_msi
);
2704 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x10e5,
2705 PCI_CLASS_BRIDGE_PCI
, 8,
2706 pci_quirk_nvidia_tegra_disable_rp_msi
);
2707 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA
, 0x10e6,
2708 PCI_CLASS_BRIDGE_PCI
, 8,
2709 pci_quirk_nvidia_tegra_disable_rp_msi
);
2712 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2713 * config register. This register controls the routing of legacy
2714 * interrupts from devices that route through the MCP55. If this register
2715 * is misprogrammed, interrupts are only sent to the BSP, unlike
2716 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2717 * having this register set properly prevents kdump from booting up
2718 * properly, so let's make sure that we have it set correctly.
2719 * Note that this is an undocumented register.
2721 static void nvbridge_check_legacy_irq_routing(struct pci_dev
*dev
)
2725 if (!pci_find_capability(dev
, PCI_CAP_ID_HT
))
2728 pci_read_config_dword(dev
, 0x74, &cfg
);
2730 if (cfg
& ((1 << 2) | (1 << 15))) {
2731 pr_info("Rewriting IRQ routing register on MCP55\n");
2732 cfg
&= ~((1 << 2) | (1 << 15));
2733 pci_write_config_dword(dev
, 0x74, cfg
);
2736 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2737 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
,
2738 nvbridge_check_legacy_irq_routing
);
2739 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2740 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
,
2741 nvbridge_check_legacy_irq_routing
);
2743 static int ht_check_msi_mapping(struct pci_dev
*dev
)
2745 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2748 /* Check if there is HT MSI cap or enabled on this device */
2749 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2750 while (pos
&& ttl
--) {
2755 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2757 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2764 pos
= pci_find_next_ht_capability(dev
, pos
,
2765 HT_CAPTYPE_MSI_MAPPING
);
2771 static int host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2773 struct pci_dev
*dev
;
2778 dev_no
= host_bridge
->devfn
>> 3;
2779 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2780 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2784 /* found next host bridge? */
2785 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2791 if (ht_check_msi_mapping(dev
)) {
2802 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2803 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2805 static int is_end_of_ht_chain(struct pci_dev
*dev
)
2811 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2816 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2818 ctrl_off
= ((flags
>> 10) & 1) ?
2819 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2820 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2822 if (ctrl
& (1 << 6))
2829 static void nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2831 struct pci_dev
*host_bridge
;
2836 dev_no
= dev
->devfn
>> 3;
2837 for (i
= dev_no
; i
>= 0; i
--) {
2838 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2842 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2847 pci_dev_put(host_bridge
);
2853 /* don't enable end_device/host_bridge with leaf directly here */
2854 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2855 host_bridge_with_leaf(host_bridge
))
2858 /* root did that ! */
2859 if (msi_ht_cap_enabled(host_bridge
))
2862 ht_enable_msi_mapping(dev
);
2865 pci_dev_put(host_bridge
);
2868 static void ht_disable_msi_mapping(struct pci_dev
*dev
)
2870 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2872 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2873 while (pos
&& ttl
--) {
2876 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2878 pci_info(dev
, "Disabling HT MSI Mapping\n");
2880 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2881 flags
& ~HT_MSI_FLAGS_ENABLE
);
2883 pos
= pci_find_next_ht_capability(dev
, pos
,
2884 HT_CAPTYPE_MSI_MAPPING
);
2888 static void __nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2890 struct pci_dev
*host_bridge
;
2894 if (!pci_msi_enabled())
2897 /* check if there is HT MSI cap or enabled on this device */
2898 found
= ht_check_msi_mapping(dev
);
2905 * HT MSI mapping should be disabled on devices that are below
2906 * a non-Hypertransport host bridge. Locate the host bridge...
2908 host_bridge
= pci_get_domain_bus_and_slot(pci_domain_nr(dev
->bus
), 0,
2910 if (host_bridge
== NULL
) {
2911 pci_warn(dev
, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2915 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2917 /* Host bridge is to HT */
2919 /* it is not enabled, try to enable it */
2921 ht_enable_msi_mapping(dev
);
2923 nv_ht_enable_msi_mapping(dev
);
2928 /* HT MSI is not enabled */
2932 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2933 ht_disable_msi_mapping(dev
);
2936 pci_dev_put(host_bridge
);
2939 static void nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2941 return __nv_msi_ht_cap_quirk(dev
, 1);
2943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2944 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2946 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2948 return __nv_msi_ht_cap_quirk(dev
, 0);
2950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2951 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2953 static void quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2955 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2958 static void quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2963 * SB700 MSI issue will be fixed at HW level from revision A21;
2964 * we need check PCI REVISION ID of SMBus controller to get SB700
2967 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2972 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2973 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2977 static void quirk_msi_intx_disable_qca_bug(struct pci_dev
*dev
)
2979 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2980 if (dev
->revision
< 0x18) {
2981 pci_info(dev
, "set MSI_INTX_DISABLE_BUG flag\n");
2982 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2985 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2986 PCI_DEVICE_ID_TIGON3_5780
,
2987 quirk_msi_intx_disable_bug
);
2988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2989 PCI_DEVICE_ID_TIGON3_5780S
,
2990 quirk_msi_intx_disable_bug
);
2991 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2992 PCI_DEVICE_ID_TIGON3_5714
,
2993 quirk_msi_intx_disable_bug
);
2994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2995 PCI_DEVICE_ID_TIGON3_5714S
,
2996 quirk_msi_intx_disable_bug
);
2997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2998 PCI_DEVICE_ID_TIGON3_5715
,
2999 quirk_msi_intx_disable_bug
);
3000 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
3001 PCI_DEVICE_ID_TIGON3_5715S
,
3002 quirk_msi_intx_disable_bug
);
3004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
3005 quirk_msi_intx_disable_ati_bug
);
3006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
3007 quirk_msi_intx_disable_ati_bug
);
3008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
3009 quirk_msi_intx_disable_ati_bug
);
3010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
3011 quirk_msi_intx_disable_ati_bug
);
3012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
3013 quirk_msi_intx_disable_ati_bug
);
3015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
3016 quirk_msi_intx_disable_bug
);
3017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
3018 quirk_msi_intx_disable_bug
);
3019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
3020 quirk_msi_intx_disable_bug
);
3022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1062,
3023 quirk_msi_intx_disable_bug
);
3024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1063,
3025 quirk_msi_intx_disable_bug
);
3026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2060,
3027 quirk_msi_intx_disable_bug
);
3028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2062,
3029 quirk_msi_intx_disable_bug
);
3030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1073,
3031 quirk_msi_intx_disable_bug
);
3032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1083,
3033 quirk_msi_intx_disable_bug
);
3034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1090,
3035 quirk_msi_intx_disable_qca_bug
);
3036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1091,
3037 quirk_msi_intx_disable_qca_bug
);
3038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a0,
3039 quirk_msi_intx_disable_qca_bug
);
3040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a1,
3041 quirk_msi_intx_disable_qca_bug
);
3042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0xe091,
3043 quirk_msi_intx_disable_qca_bug
);
3046 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3047 * should be disabled on platforms where the device (mistakenly) advertises it.
3049 * Notice that this quirk also disables MSI (which may work, but hasn't been
3050 * tested), since currently there is no standard way to disable only MSI-X.
3052 * The 0031 device id is reused for other non Root Port device types,
3053 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3055 static void quirk_al_msi_disable(struct pci_dev
*dev
)
3058 pci_warn(dev
, "Disabling MSI/MSI-X\n");
3060 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS
, 0x0031,
3061 PCI_CLASS_BRIDGE_PCI
, 8, quirk_al_msi_disable
);
3062 #endif /* CONFIG_PCI_MSI */
3065 * Allow manual resource allocation for PCI hotplug bridges via
3066 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3067 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3068 * allocate resources when hotplug device is inserted and PCI bus is
3071 static void quirk_hotplug_bridge(struct pci_dev
*dev
)
3073 dev
->is_hotplug_bridge
= 1;
3075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0020, quirk_hotplug_bridge
);
3078 * This is a quirk for the Ricoh MMC controller found as a part of some
3079 * multifunction chips.
3081 * This is very similar and based on the ricoh_mmc driver written by
3082 * Philip Langdale. Thank you for these magic sequences.
3084 * These chips implement the four main memory card controllers (SD, MMC,
3085 * MS, xD) and one or both of CardBus or FireWire.
3087 * It happens that they implement SD and MMC support as separate
3088 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3089 * cards but the chip detects MMC cards in hardware and directs them to the
3090 * MMC controller - so the SDHCI driver never sees them.
3092 * To get around this, we must disable the useless MMC controller. At that
3093 * point, the SDHCI controller will start seeing them. It seems to be the
3094 * case that the relevant PCI registers to deactivate the MMC controller
3095 * live on PCI function 0, which might be the CardBus controller or the
3096 * FireWire controller, depending on the particular chip in question
3098 * This has to be done early, because as soon as we disable the MMC controller
3099 * other PCI functions shift up one level, e.g. function #2 becomes function
3100 * #1, and this will confuse the PCI core.
3102 #ifdef CONFIG_MMC_RICOH_MMC
3103 static void ricoh_mmc_fixup_rl5c476(struct pci_dev
*dev
)
3110 * Disable via CardBus interface
3112 * This must be done via function #0
3114 if (PCI_FUNC(dev
->devfn
))
3117 pci_read_config_byte(dev
, 0xB7, &disable
);
3121 pci_read_config_byte(dev
, 0x8E, &write_enable
);
3122 pci_write_config_byte(dev
, 0x8E, 0xAA);
3123 pci_read_config_byte(dev
, 0x8D, &write_target
);
3124 pci_write_config_byte(dev
, 0x8D, 0xB7);
3125 pci_write_config_byte(dev
, 0xB7, disable
| 0x02);
3126 pci_write_config_byte(dev
, 0x8E, write_enable
);
3127 pci_write_config_byte(dev
, 0x8D, write_target
);
3129 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3130 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3132 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
3133 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
3135 static void ricoh_mmc_fixup_r5c832(struct pci_dev
*dev
)
3141 * Disable via FireWire interface
3143 * This must be done via function #0
3145 if (PCI_FUNC(dev
->devfn
))
3148 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3149 * certain types of SD/MMC cards. Lowering the SD base clock
3150 * frequency from 200Mhz to 50Mhz fixes this issue.
3152 * 0x150 - SD2.0 mode enable for changing base clock
3153 * frequency to 50Mhz
3154 * 0xe1 - Base clock frequency
3155 * 0x32 - 50Mhz new clock frequency
3156 * 0xf9 - Key register for 0x150
3157 * 0xfc - key register for 0xe1
3159 if (dev
->device
== PCI_DEVICE_ID_RICOH_R5CE822
||
3160 dev
->device
== PCI_DEVICE_ID_RICOH_R5CE823
) {
3161 pci_write_config_byte(dev
, 0xf9, 0xfc);
3162 pci_write_config_byte(dev
, 0x150, 0x10);
3163 pci_write_config_byte(dev
, 0xf9, 0x00);
3164 pci_write_config_byte(dev
, 0xfc, 0x01);
3165 pci_write_config_byte(dev
, 0xe1, 0x32);
3166 pci_write_config_byte(dev
, 0xfc, 0x00);
3168 pci_notice(dev
, "MMC controller base frequency changed to 50Mhz.\n");
3171 pci_read_config_byte(dev
, 0xCB, &disable
);
3176 pci_read_config_byte(dev
, 0xCA, &write_enable
);
3177 pci_write_config_byte(dev
, 0xCA, 0x57);
3178 pci_write_config_byte(dev
, 0xCB, disable
| 0x02);
3179 pci_write_config_byte(dev
, 0xCA, write_enable
);
3181 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3182 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3185 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3186 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3187 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3188 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3189 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3190 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3191 #endif /*CONFIG_MMC_RICOH_MMC*/
3193 #ifdef CONFIG_DMAR_TABLE
3194 #define VTUNCERRMSK_REG 0x1ac
3195 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3197 * This is a quirk for masking VT-d spec-defined errors to platform error
3198 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3199 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3200 * on the RAS config settings of the platform) when a VT-d fault happens.
3201 * The resulting SMI caused the system to hang.
3203 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3204 * need to report the same error through other channels.
3206 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
3210 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
3211 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
3213 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
3214 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
3217 static void fixup_ti816x_class(struct pci_dev
*dev
)
3219 u32
class = dev
->class;
3221 /* TI 816x devices do not have class code set when in PCIe boot mode */
3222 dev
->class = PCI_CLASS_MULTIMEDIA_VIDEO
<< 8;
3223 pci_info(dev
, "PCI class overridden (%#08x -> %#08x)\n",
3226 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI
, 0xb800,
3227 PCI_CLASS_NOT_DEFINED
, 8, fixup_ti816x_class
);
3230 * Some PCIe devices do not work reliably with the claimed maximum
3231 * payload size supported.
3233 static void fixup_mpss_256(struct pci_dev
*dev
)
3235 dev
->pcie_mpss
= 1; /* 256 bytes */
3237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3238 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0
, fixup_mpss_256
);
3239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3240 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
, fixup_mpss_256
);
3241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3242 PCI_DEVICE_ID_SOLARFLARE_SFC4000B
, fixup_mpss_256
);
3245 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3246 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3247 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3248 * until all of the devices are discovered and buses walked, read completion
3249 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3250 * it is possible to hotplug a device with MPS of 256B.
3252 static void quirk_intel_mc_errata(struct pci_dev
*dev
)
3257 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
3258 pcie_bus_config
== PCIE_BUS_DEFAULT
)
3262 * Intel erratum specifies bits to change but does not say what
3263 * they are. Keeping them magical until such time as the registers
3264 * and values can be explained.
3266 err
= pci_read_config_word(dev
, 0x48, &rcc
);
3268 pci_err(dev
, "Error attempting to read the read completion coalescing register\n");
3272 if (!(rcc
& (1 << 10)))
3277 err
= pci_write_config_word(dev
, 0x48, rcc
);
3279 pci_err(dev
, "Error attempting to write the read completion coalescing register\n");
3283 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3285 /* Intel 5000 series memory controllers and ports 2-7 */
3286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25c0, quirk_intel_mc_errata
);
3287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d0, quirk_intel_mc_errata
);
3288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d4, quirk_intel_mc_errata
);
3289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d8, quirk_intel_mc_errata
);
3290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_mc_errata
);
3291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_mc_errata
);
3292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_mc_errata
);
3293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_mc_errata
);
3294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_mc_errata
);
3295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_mc_errata
);
3296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_mc_errata
);
3297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_mc_errata
);
3298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_mc_errata
);
3299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_mc_errata
);
3300 /* Intel 5100 series memory controllers and ports 2-7 */
3301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65c0, quirk_intel_mc_errata
);
3302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e2, quirk_intel_mc_errata
);
3303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e3, quirk_intel_mc_errata
);
3304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e4, quirk_intel_mc_errata
);
3305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e5, quirk_intel_mc_errata
);
3306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e6, quirk_intel_mc_errata
);
3307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e7, quirk_intel_mc_errata
);
3308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f7, quirk_intel_mc_errata
);
3309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f8, quirk_intel_mc_errata
);
3310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f9, quirk_intel_mc_errata
);
3311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65fa, quirk_intel_mc_errata
);
3314 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3315 * To work around this, query the size it should be configured to by the
3316 * device and modify the resource end to correspond to this new size.
3318 static void quirk_intel_ntb(struct pci_dev
*dev
)
3323 rc
= pci_read_config_byte(dev
, 0x00D0, &val
);
3327 dev
->resource
[2].end
= dev
->resource
[2].start
+ ((u64
) 1 << val
) - 1;
3329 rc
= pci_read_config_byte(dev
, 0x00D1, &val
);
3333 dev
->resource
[4].end
= dev
->resource
[4].start
+ ((u64
) 1 << val
) - 1;
3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e08, quirk_intel_ntb
);
3336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e0d, quirk_intel_ntb
);
3339 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3340 * though no one is handling them (e.g., if the i915 driver is never
3341 * loaded). Additionally the interrupt destination is not set up properly
3342 * and the interrupt ends up -somewhere-.
3344 * These spurious interrupts are "sticky" and the kernel disables the
3345 * (shared) interrupt line after 100,000+ generated interrupts.
3347 * Fix it by disabling the still enabled interrupts. This resolves crashes
3348 * often seen on monitor unplug.
3350 #define I915_DEIER_REG 0x4400c
3351 static void disable_igfx_irq(struct pci_dev
*dev
)
3353 void __iomem
*regs
= pci_iomap(dev
, 0, 0);
3355 pci_warn(dev
, "igfx quirk: Can't iomap PCI device\n");
3359 /* Check if any interrupt line is still enabled */
3360 if (readl(regs
+ I915_DEIER_REG
) != 0) {
3361 pci_warn(dev
, "BIOS left Intel GPU interrupts enabled; disabling\n");
3363 writel(0, regs
+ I915_DEIER_REG
);
3366 pci_iounmap(dev
, regs
);
3368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0042, disable_igfx_irq
);
3369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0046, disable_igfx_irq
);
3370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x004a, disable_igfx_irq
);
3371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0102, disable_igfx_irq
);
3372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0106, disable_igfx_irq
);
3373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x010a, disable_igfx_irq
);
3374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0152, disable_igfx_irq
);
3377 * PCI devices which are on Intel chips can skip the 10ms delay
3378 * before entering D3 mode.
3380 static void quirk_remove_d3hot_delay(struct pci_dev
*dev
)
3382 dev
->d3hot_delay
= 0;
3384 /* C600 Series devices do not need 10ms d3hot_delay */
3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0412, quirk_remove_d3hot_delay
);
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c00, quirk_remove_d3hot_delay
);
3387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c0c, quirk_remove_d3hot_delay
);
3388 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c02, quirk_remove_d3hot_delay
);
3390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c18, quirk_remove_d3hot_delay
);
3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c1c, quirk_remove_d3hot_delay
);
3392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c20, quirk_remove_d3hot_delay
);
3393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c22, quirk_remove_d3hot_delay
);
3394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c26, quirk_remove_d3hot_delay
);
3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c2d, quirk_remove_d3hot_delay
);
3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c31, quirk_remove_d3hot_delay
);
3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3a, quirk_remove_d3hot_delay
);
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3d, quirk_remove_d3hot_delay
);
3399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c4e, quirk_remove_d3hot_delay
);
3400 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2280, quirk_remove_d3hot_delay
);
3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2298, quirk_remove_d3hot_delay
);
3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x229c, quirk_remove_d3hot_delay
);
3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b0, quirk_remove_d3hot_delay
);
3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b5, quirk_remove_d3hot_delay
);
3406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b7, quirk_remove_d3hot_delay
);
3407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b8, quirk_remove_d3hot_delay
);
3408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22d8, quirk_remove_d3hot_delay
);
3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22dc, quirk_remove_d3hot_delay
);
3412 * Some devices may pass our check in pci_intx_mask_supported() if
3413 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3414 * support this feature.
3416 static void quirk_broken_intx_masking(struct pci_dev
*dev
)
3418 dev
->broken_intx_masking
= 1;
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO
, 0x0030,
3421 quirk_broken_intx_masking
);
3422 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3423 quirk_broken_intx_masking
);
3424 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3425 quirk_broken_intx_masking
);
3428 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3429 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3431 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK
, 0x8169,
3434 quirk_broken_intx_masking
);
3437 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3438 * DisINTx can be set but the interrupt status bit is non-functional.
3440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1572, quirk_broken_intx_masking
);
3441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1574, quirk_broken_intx_masking
);
3442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1580, quirk_broken_intx_masking
);
3443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1581, quirk_broken_intx_masking
);
3444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1583, quirk_broken_intx_masking
);
3445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1584, quirk_broken_intx_masking
);
3446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1585, quirk_broken_intx_masking
);
3447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1586, quirk_broken_intx_masking
);
3448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1587, quirk_broken_intx_masking
);
3449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1588, quirk_broken_intx_masking
);
3450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1589, quirk_broken_intx_masking
);
3451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158a, quirk_broken_intx_masking
);
3452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158b, quirk_broken_intx_masking
);
3453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d0, quirk_broken_intx_masking
);
3454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d1, quirk_broken_intx_masking
);
3455 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d2, quirk_broken_intx_masking
);
3457 static u16 mellanox_broken_intx_devs
[] = {
3458 PCI_DEVICE_ID_MELLANOX_HERMON_SDR
,
3459 PCI_DEVICE_ID_MELLANOX_HERMON_DDR
,
3460 PCI_DEVICE_ID_MELLANOX_HERMON_QDR
,
3461 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2
,
3462 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2
,
3463 PCI_DEVICE_ID_MELLANOX_HERMON_EN
,
3464 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2
,
3465 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN
,
3466 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2
,
3467 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2
,
3468 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2
,
3469 PCI_DEVICE_ID_MELLANOX_CONNECTX2
,
3470 PCI_DEVICE_ID_MELLANOX_CONNECTX3
,
3471 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO
,
3474 #define CONNECTX_4_CURR_MAX_MINOR 99
3475 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3478 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3479 * If so, don't mark it as broken.
3480 * FW minor > 99 means older FW version format and no INTx masking support.
3481 * FW minor < 14 means new FW version format and no INTx masking support.
3483 static void mellanox_check_broken_intx_masking(struct pci_dev
*pdev
)
3485 __be32 __iomem
*fw_ver
;
3493 for (i
= 0; i
< ARRAY_SIZE(mellanox_broken_intx_devs
); i
++) {
3494 if (pdev
->device
== mellanox_broken_intx_devs
[i
]) {
3495 pdev
->broken_intx_masking
= 1;
3501 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3502 * support so shouldn't be checked further
3504 if (pdev
->device
== PCI_DEVICE_ID_MELLANOX_CONNECTIB
)
3507 if (pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4
&&
3508 pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
)
3511 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3512 if (pci_enable_device_mem(pdev
)) {
3513 pci_warn(pdev
, "Can't enable device memory\n");
3517 fw_ver
= ioremap(pci_resource_start(pdev
, 0), 4);
3519 pci_warn(pdev
, "Can't map ConnectX-4 initialization segment\n");
3523 /* Reading from resource space should be 32b aligned */
3524 fw_maj_min
= ioread32be(fw_ver
);
3525 fw_sub_min
= ioread32be(fw_ver
+ 1);
3526 fw_major
= fw_maj_min
& 0xffff;
3527 fw_minor
= fw_maj_min
>> 16;
3528 fw_subminor
= fw_sub_min
& 0xffff;
3529 if (fw_minor
> CONNECTX_4_CURR_MAX_MINOR
||
3530 fw_minor
< CONNECTX_4_INTX_SUPPORT_MINOR
) {
3531 pci_warn(pdev
, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3532 fw_major
, fw_minor
, fw_subminor
, pdev
->device
==
3533 PCI_DEVICE_ID_MELLANOX_CONNECTX4
? 12 : 14);
3534 pdev
->broken_intx_masking
= 1;
3540 pci_disable_device(pdev
);
3542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_ANY_ID
,
3543 mellanox_check_broken_intx_masking
);
3545 static void quirk_no_bus_reset(struct pci_dev
*dev
)
3547 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_BUS_RESET
;
3551 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3552 * prevented for those affected devices.
3554 static void quirk_nvidia_no_bus_reset(struct pci_dev
*dev
)
3556 if ((dev
->device
& 0xffc0) == 0x2340)
3557 quirk_no_bus_reset(dev
);
3559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
3560 quirk_nvidia_no_bus_reset
);
3563 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3564 * The device will throw a Link Down error on AER-capable systems and
3565 * regardless of AER, config space of the device is never accessible again
3566 * and typically causes the system to hang or reset when access is attempted.
3567 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0030, quirk_no_bus_reset
);
3570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0032, quirk_no_bus_reset
);
3571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x003c, quirk_no_bus_reset
);
3572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0033, quirk_no_bus_reset
);
3573 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0034, quirk_no_bus_reset
);
3576 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3577 * reset when used with certain child devices. After the reset, config
3578 * accesses to the child may fail.
3580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM
, 0xa100, quirk_no_bus_reset
);
3583 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3584 * automatically disables LTSSM when Secondary Bus Reset is received and
3585 * the device stops working. Prevent bus reset for these devices. With
3586 * this change, the device can be assigned to VMs with VFIO, but it will
3587 * leak state between VMs. Reference
3588 * https://e2e.ti.com/support/processors/f/791/t/954382
3590 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI
, 0xb005, quirk_no_bus_reset
);
3592 static void quirk_no_pm_reset(struct pci_dev
*dev
)
3595 * We can't do a bus reset on root bus devices, but an ineffective
3596 * PM reset may be better than nothing.
3598 if (!pci_is_root_bus(dev
->bus
))
3599 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_PM_RESET
;
3603 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3604 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3605 * to have no effect on the device: it retains the framebuffer contents and
3606 * monitor sync. Advertising this support makes other layers, like VFIO,
3607 * assume pci_reset_function() is viable for this device. Mark it as
3608 * unavailable to skip it when testing reset methods.
3610 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
3611 PCI_CLASS_DISPLAY_VGA
, 8, quirk_no_pm_reset
);
3614 * Thunderbolt controllers with broken MSI hotplug signaling:
3615 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3616 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3618 static void quirk_thunderbolt_hotplug_msi(struct pci_dev
*pdev
)
3620 if (pdev
->is_hotplug_bridge
&&
3621 (pdev
->device
!= PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
||
3622 pdev
->revision
<= 1))
3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
,
3626 quirk_thunderbolt_hotplug_msi
);
3627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE
,
3628 quirk_thunderbolt_hotplug_msi
);
3629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_PEAK
,
3630 quirk_thunderbolt_hotplug_msi
);
3631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3632 quirk_thunderbolt_hotplug_msi
);
3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PORT_RIDGE
,
3634 quirk_thunderbolt_hotplug_msi
);
3638 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3640 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3641 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3642 * be present after resume if a device was plugged in before suspend.
3644 * The Thunderbolt controller consists of a PCIe switch with downstream
3645 * bridges leading to the NHI and to the tunnel PCI bridges.
3647 * This quirk cuts power to the whole chip. Therefore we have to apply it
3648 * during suspend_noirq of the upstream bridge.
3650 * Power is automagically restored before resume. No action is needed.
3652 static void quirk_apple_poweroff_thunderbolt(struct pci_dev
*dev
)
3654 acpi_handle bridge
, SXIO
, SXFP
, SXLV
;
3656 if (!x86_apple_machine
)
3658 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
)
3662 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3663 * We don't know how to turn it back on again, but firmware does,
3664 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3667 if (!pm_suspend_via_firmware())
3670 bridge
= ACPI_HANDLE(&dev
->dev
);
3675 * SXIO and SXLV are present only on machines requiring this quirk.
3676 * Thunderbolt bridges in external devices might have the same
3677 * device ID as those on the host, but they will not have the
3678 * associated ACPI methods. This implicitly checks that we are at
3681 if (ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXIO", &SXIO
))
3682 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXFP", &SXFP
))
3683 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXLV", &SXLV
)))
3685 pci_info(dev
, "quirk: cutting power to Thunderbolt controller...\n");
3687 /* magic sequence */
3688 acpi_execute_simple_method(SXIO
, NULL
, 1);
3689 acpi_execute_simple_method(SXFP
, NULL
, 0);
3691 acpi_execute_simple_method(SXLV
, NULL
, 0);
3692 acpi_execute_simple_method(SXIO
, NULL
, 0);
3693 acpi_execute_simple_method(SXLV
, NULL
, 0);
3695 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL
,
3696 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3697 quirk_apple_poweroff_thunderbolt
);
3701 * Following are device-specific reset methods which can be used to
3702 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3705 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
3708 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3710 * The 82599 supports FLR on VFs, but FLR support is reported only
3711 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3712 * Thus we must call pcie_flr() directly without first checking if it is
3720 #define SOUTH_CHICKEN2 0xc2004
3721 #define PCH_PP_STATUS 0xc7200
3722 #define PCH_PP_CONTROL 0xc7204
3723 #define MSG_CTL 0x45010
3724 #define NSDE_PWR_STATE 0xd0100
3725 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3727 static int reset_ivb_igd(struct pci_dev
*dev
, int probe
)
3729 void __iomem
*mmio_base
;
3730 unsigned long timeout
;
3736 mmio_base
= pci_iomap(dev
, 0, 0);
3740 iowrite32(0x00000002, mmio_base
+ MSG_CTL
);
3743 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3744 * driver loaded sets the right bits. However, this's a reset and
3745 * the bits have been set by i915 previously, so we clobber
3746 * SOUTH_CHICKEN2 register directly here.
3748 iowrite32(0x00000005, mmio_base
+ SOUTH_CHICKEN2
);
3750 val
= ioread32(mmio_base
+ PCH_PP_CONTROL
) & 0xfffffffe;
3751 iowrite32(val
, mmio_base
+ PCH_PP_CONTROL
);
3753 timeout
= jiffies
+ msecs_to_jiffies(IGD_OPERATION_TIMEOUT
);
3755 val
= ioread32(mmio_base
+ PCH_PP_STATUS
);
3756 if ((val
& 0xb0000000) == 0)
3757 goto reset_complete
;
3759 } while (time_before(jiffies
, timeout
));
3760 pci_warn(dev
, "timeout during reset\n");
3763 iowrite32(0x00000002, mmio_base
+ NSDE_PWR_STATE
);
3765 pci_iounmap(dev
, mmio_base
);
3769 /* Device-specific reset method for Chelsio T4-based adapters */
3770 static int reset_chelsio_generic_dev(struct pci_dev
*dev
, int probe
)
3776 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3777 * that we have no device-specific reset method.
3779 if ((dev
->device
& 0xf000) != 0x4000)
3783 * If this is the "probe" phase, return 0 indicating that we can
3784 * reset this device.
3790 * T4 can wedge if there are DMAs in flight within the chip and Bus
3791 * Master has been disabled. We need to have it on till the Function
3792 * Level Reset completes. (BUS_MASTER is disabled in
3793 * pci_reset_function()).
3795 pci_read_config_word(dev
, PCI_COMMAND
, &old_command
);
3796 pci_write_config_word(dev
, PCI_COMMAND
,
3797 old_command
| PCI_COMMAND_MASTER
);
3800 * Perform the actual device function reset, saving and restoring
3801 * configuration information around the reset.
3803 pci_save_state(dev
);
3806 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3807 * are disabled when an MSI-X interrupt message needs to be delivered.
3808 * So we briefly re-enable MSI-X interrupts for the duration of the
3809 * FLR. The pci_restore_state() below will restore the original
3812 pci_read_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
, &msix_flags
);
3813 if ((msix_flags
& PCI_MSIX_FLAGS_ENABLE
) == 0)
3814 pci_write_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
,
3816 PCI_MSIX_FLAGS_ENABLE
|
3817 PCI_MSIX_FLAGS_MASKALL
);
3822 * Restore the configuration information (BAR values, etc.) including
3823 * the original PCI Configuration Space Command word, and return
3826 pci_restore_state(dev
);
3827 pci_write_config_word(dev
, PCI_COMMAND
, old_command
);
3831 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3832 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3833 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3836 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3837 * FLR where config space reads from the device return -1. We seem to be
3838 * able to avoid this condition if we disable the NVMe controller prior to
3839 * FLR. This quirk is generic for any NVMe class device requiring similar
3840 * assistance to quiesce the device prior to FLR.
3842 * NVMe specification: https://nvmexpress.org/resources/specifications/
3844 * Chapter 2: Required and optional PCI config registers
3845 * Chapter 3: NVMe control registers
3846 * Chapter 7.3: Reset behavior
3848 static int nvme_disable_and_flr(struct pci_dev
*dev
, int probe
)
3854 if (dev
->class != PCI_CLASS_STORAGE_EXPRESS
||
3855 !pcie_has_flr(dev
) || !pci_resource_start(dev
, 0))
3861 bar
= pci_iomap(dev
, 0, NVME_REG_CC
+ sizeof(cfg
));
3865 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3866 pci_write_config_word(dev
, PCI_COMMAND
, cmd
| PCI_COMMAND_MEMORY
);
3868 cfg
= readl(bar
+ NVME_REG_CC
);
3870 /* Disable controller if enabled */
3871 if (cfg
& NVME_CC_ENABLE
) {
3872 u32 cap
= readl(bar
+ NVME_REG_CAP
);
3873 unsigned long timeout
;
3876 * Per nvme_disable_ctrl() skip shutdown notification as it
3877 * could complete commands to the admin queue. We only intend
3878 * to quiesce the device before reset.
3880 cfg
&= ~(NVME_CC_SHN_MASK
| NVME_CC_ENABLE
);
3882 writel(cfg
, bar
+ NVME_REG_CC
);
3885 * Some controllers require an additional delay here, see
3886 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3887 * supported by this quirk.
3890 /* Cap register provides max timeout in 500ms increments */
3891 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
3894 u32 status
= readl(bar
+ NVME_REG_CSTS
);
3896 /* Ready status becomes zero on disable complete */
3897 if (!(status
& NVME_CSTS_RDY
))
3902 if (time_after(jiffies
, timeout
)) {
3903 pci_warn(dev
, "Timeout waiting for NVMe ready status to clear after disable\n");
3909 pci_iounmap(dev
, bar
);
3917 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3918 * to change after NVMe enable if the driver starts interacting with the
3919 * device too soon after FLR. A 250ms delay after FLR has heuristically
3920 * proven to produce reliably working results for device assignment cases.
3922 static int delay_250ms_after_flr(struct pci_dev
*dev
, int probe
)
3924 if (!pcie_has_flr(dev
))
3937 #define PCI_DEVICE_ID_HINIC_VF 0x375E
3938 #define HINIC_VF_FLR_TYPE 0x1000
3939 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3940 #define HINIC_VF_OP 0xE80
3941 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3942 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3944 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3945 static int reset_hinic_vf_dev(struct pci_dev
*pdev
, int probe
)
3947 unsigned long timeout
;
3954 bar
= pci_iomap(pdev
, 0, 0);
3958 /* Get and check firmware capabilities */
3959 val
= ioread32be(bar
+ HINIC_VF_FLR_TYPE
);
3960 if (!(val
& HINIC_VF_FLR_CAP_BIT
)) {
3961 pci_iounmap(pdev
, bar
);
3965 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
3966 val
= ioread32be(bar
+ HINIC_VF_OP
);
3967 val
= val
| HINIC_VF_FLR_PROC_BIT
;
3968 iowrite32be(val
, bar
+ HINIC_VF_OP
);
3973 * The device must recapture its Bus and Device Numbers after FLR
3974 * in order generate Completions. Issue a config write to let the
3975 * device capture this information.
3977 pci_write_config_word(pdev
, PCI_VENDOR_ID
, 0);
3979 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
3980 timeout
= jiffies
+ msecs_to_jiffies(HINIC_OPERATION_TIMEOUT
);
3982 val
= ioread32be(bar
+ HINIC_VF_OP
);
3983 if (!(val
& HINIC_VF_FLR_PROC_BIT
))
3984 goto reset_complete
;
3986 } while (time_before(jiffies
, timeout
));
3988 val
= ioread32be(bar
+ HINIC_VF_OP
);
3989 if (!(val
& HINIC_VF_FLR_PROC_BIT
))
3990 goto reset_complete
;
3992 pci_warn(pdev
, "Reset dev timeout, FLR ack reg: %#010x\n", val
);
3995 pci_iounmap(pdev
, bar
);
4000 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
4001 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
4002 reset_intel_82599_sfp_virtfn
},
4003 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M_VGA
,
4005 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M2_VGA
,
4007 { PCI_VENDOR_ID_SAMSUNG
, 0xa804, nvme_disable_and_flr
},
4008 { PCI_VENDOR_ID_INTEL
, 0x0953, delay_250ms_after_flr
},
4009 { PCI_VENDOR_ID_INTEL
, 0x0a54, delay_250ms_after_flr
},
4010 { PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
4011 reset_chelsio_generic_dev
},
4012 { PCI_VENDOR_ID_HUAWEI
, PCI_DEVICE_ID_HINIC_VF
,
4013 reset_hinic_vf_dev
},
4018 * These device-specific reset methods are here rather than in a driver
4019 * because when a host assigns a device to a guest VM, the host may need
4020 * to reset the device but probably doesn't have a driver for it.
4022 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
4024 const struct pci_dev_reset_methods
*i
;
4026 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
4027 if ((i
->vendor
== dev
->vendor
||
4028 i
->vendor
== (u16
)PCI_ANY_ID
) &&
4029 (i
->device
== dev
->device
||
4030 i
->device
== (u16
)PCI_ANY_ID
))
4031 return i
->reset(dev
, probe
);
4037 static void quirk_dma_func0_alias(struct pci_dev
*dev
)
4039 if (PCI_FUNC(dev
->devfn
) != 0)
4040 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0), 1);
4044 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4046 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe832, quirk_dma_func0_alias
);
4049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe476, quirk_dma_func0_alias
);
4051 static void quirk_dma_func1_alias(struct pci_dev
*dev
)
4053 if (PCI_FUNC(dev
->devfn
) != 1)
4054 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 1), 1);
4058 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4059 * SKUs function 1 is present and is a legacy IDE controller, in other
4060 * SKUs this function is not present, making this a ghost requester.
4061 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9120,
4064 quirk_dma_func1_alias
);
4065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9123,
4066 quirk_dma_func1_alias
);
4067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9128,
4068 quirk_dma_func1_alias
);
4069 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9130,
4071 quirk_dma_func1_alias
);
4072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9170,
4073 quirk_dma_func1_alias
);
4074 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9172,
4076 quirk_dma_func1_alias
);
4077 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x917a,
4079 quirk_dma_func1_alias
);
4080 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4081 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9182,
4082 quirk_dma_func1_alias
);
4083 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9183,
4085 quirk_dma_func1_alias
);
4086 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x91a0,
4088 quirk_dma_func1_alias
);
4089 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9215,
4091 quirk_dma_func1_alias
);
4092 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9220,
4094 quirk_dma_func1_alias
);
4095 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4096 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9230,
4097 quirk_dma_func1_alias
);
4098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0642,
4099 quirk_dma_func1_alias
);
4100 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0645,
4101 quirk_dma_func1_alias
);
4102 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON
,
4104 PCI_DEVICE_ID_JMICRON_JMB388_ESD
,
4105 quirk_dma_func1_alias
);
4106 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4107 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4108 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4109 quirk_dma_func1_alias
);
4112 * Some devices DMA with the wrong devfn, not just the wrong function.
4113 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4114 * the alias is "fixed" and independent of the device devfn.
4116 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4117 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4118 * single device on the secondary bus. In reality, the single exposed
4119 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4120 * that provides a bridge to the internal bus of the I/O processor. The
4121 * controller supports private devices, which can be hidden from PCI config
4122 * space. In the case of the Adaptec 3405, a private device at 01.0
4123 * appears to be the DMA engine, which therefore needs to become a DMA
4124 * alias for the device.
4126 static const struct pci_device_id fixed_dma_alias_tbl
[] = {
4127 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
4128 PCI_VENDOR_ID_ADAPTEC2
, 0x02bb), /* Adaptec 3405 */
4129 .driver_data
= PCI_DEVFN(1, 0) },
4130 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
4131 PCI_VENDOR_ID_ADAPTEC2
, 0x02bc), /* Adaptec 3805 */
4132 .driver_data
= PCI_DEVFN(1, 0) },
4136 static void quirk_fixed_dma_alias(struct pci_dev
*dev
)
4138 const struct pci_device_id
*id
;
4140 id
= pci_match_id(fixed_dma_alias_tbl
, dev
);
4142 pci_add_dma_alias(dev
, id
->driver_data
, 1);
4144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2
, 0x0285, quirk_fixed_dma_alias
);
4147 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4148 * using the wrong DMA alias for the device. Some of these devices can be
4149 * used as either forward or reverse bridges, so we need to test whether the
4150 * device is operating in the correct mode. We could probably apply this
4151 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4152 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4153 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4155 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev
*pdev
)
4157 if (!pci_is_root_bus(pdev
->bus
) &&
4158 pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
4159 !pci_is_pcie(pdev
) && pci_is_pcie(pdev
->bus
->self
) &&
4160 pci_pcie_type(pdev
->bus
->self
) != PCI_EXP_TYPE_PCI_BRIDGE
)
4161 pdev
->dev_flags
|= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
;
4163 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA
, 0x1080,
4165 quirk_use_pcie_bridge_dma_alias
);
4166 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4167 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias
);
4168 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4169 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias
);
4170 /* ITE 8893 has the same problem as the 8892 */
4171 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias
);
4172 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4173 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias
);
4176 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4177 * be added as aliases to the DMA device in order to allow buffer access
4178 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4179 * programmed in the EEPROM.
4181 static void quirk_mic_x200_dma_alias(struct pci_dev
*pdev
)
4183 pci_add_dma_alias(pdev
, PCI_DEVFN(0x10, 0x0), 1);
4184 pci_add_dma_alias(pdev
, PCI_DEVFN(0x11, 0x0), 1);
4185 pci_add_dma_alias(pdev
, PCI_DEVFN(0x12, 0x3), 1);
4187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2260, quirk_mic_x200_dma_alias
);
4188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2264, quirk_mic_x200_dma_alias
);
4191 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4192 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4194 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4195 * when IOMMU is enabled. These aliases allow computational unit access to
4196 * host memory. These aliases mark the whole VCA device as one IOMMU
4199 * All possible slot numbers (0x20) are used, since we are unable to tell
4200 * what slot is used on other side. This quirk is intended for both host
4201 * and computational unit sides. The VCA devices have up to five functions
4202 * (four for DMA channels and one additional).
4204 static void quirk_pex_vca_alias(struct pci_dev
*pdev
)
4206 const unsigned int num_pci_slots
= 0x20;
4209 for (slot
= 0; slot
< num_pci_slots
; slot
++)
4210 pci_add_dma_alias(pdev
, PCI_DEVFN(slot
, 0x0), 5);
4212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2954, quirk_pex_vca_alias
);
4213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2955, quirk_pex_vca_alias
);
4214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2956, quirk_pex_vca_alias
);
4215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2958, quirk_pex_vca_alias
);
4216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2959, quirk_pex_vca_alias
);
4217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x295A, quirk_pex_vca_alias
);
4220 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4221 * associated not at the root bus, but at a bridge below. This quirk avoids
4222 * generating invalid DMA aliases.
4224 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev
*pdev
)
4226 pdev
->dev_flags
|= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
;
4228 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9000,
4229 quirk_bridge_cavm_thrx2_pcie_root
);
4230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9084,
4231 quirk_bridge_cavm_thrx2_pcie_root
);
4234 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4235 * class code. Fix it.
4237 static void quirk_tw686x_class(struct pci_dev
*pdev
)
4239 u32
class = pdev
->class;
4241 /* Use "Multimedia controller" class */
4242 pdev
->class = (PCI_CLASS_MULTIMEDIA_OTHER
<< 8) | 0x01;
4243 pci_info(pdev
, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4244 class, pdev
->class);
4246 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED
, 8,
4247 quirk_tw686x_class
);
4248 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED
, 8,
4249 quirk_tw686x_class
);
4250 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED
, 8,
4251 quirk_tw686x_class
);
4252 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED
, 8,
4253 quirk_tw686x_class
);
4256 * Some devices have problems with Transaction Layer Packets with the Relaxed
4257 * Ordering Attribute set. Such devices should mark themselves and other
4258 * device drivers should check before sending TLPs with RO set.
4260 static void quirk_relaxedordering_disable(struct pci_dev
*dev
)
4262 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_RELAXED_ORDERING
;
4263 pci_info(dev
, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4267 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4268 * Complex have a Flow Control Credit issue which can cause performance
4269 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4271 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f01, PCI_CLASS_NOT_DEFINED
, 8,
4272 quirk_relaxedordering_disable
);
4273 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f02, PCI_CLASS_NOT_DEFINED
, 8,
4274 quirk_relaxedordering_disable
);
4275 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f03, PCI_CLASS_NOT_DEFINED
, 8,
4276 quirk_relaxedordering_disable
);
4277 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f04, PCI_CLASS_NOT_DEFINED
, 8,
4278 quirk_relaxedordering_disable
);
4279 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f05, PCI_CLASS_NOT_DEFINED
, 8,
4280 quirk_relaxedordering_disable
);
4281 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f06, PCI_CLASS_NOT_DEFINED
, 8,
4282 quirk_relaxedordering_disable
);
4283 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f07, PCI_CLASS_NOT_DEFINED
, 8,
4284 quirk_relaxedordering_disable
);
4285 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f08, PCI_CLASS_NOT_DEFINED
, 8,
4286 quirk_relaxedordering_disable
);
4287 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f09, PCI_CLASS_NOT_DEFINED
, 8,
4288 quirk_relaxedordering_disable
);
4289 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0a, PCI_CLASS_NOT_DEFINED
, 8,
4290 quirk_relaxedordering_disable
);
4291 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0b, PCI_CLASS_NOT_DEFINED
, 8,
4292 quirk_relaxedordering_disable
);
4293 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0c, PCI_CLASS_NOT_DEFINED
, 8,
4294 quirk_relaxedordering_disable
);
4295 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0d, PCI_CLASS_NOT_DEFINED
, 8,
4296 quirk_relaxedordering_disable
);
4297 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0e, PCI_CLASS_NOT_DEFINED
, 8,
4298 quirk_relaxedordering_disable
);
4299 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f01, PCI_CLASS_NOT_DEFINED
, 8,
4300 quirk_relaxedordering_disable
);
4301 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f02, PCI_CLASS_NOT_DEFINED
, 8,
4302 quirk_relaxedordering_disable
);
4303 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f03, PCI_CLASS_NOT_DEFINED
, 8,
4304 quirk_relaxedordering_disable
);
4305 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f04, PCI_CLASS_NOT_DEFINED
, 8,
4306 quirk_relaxedordering_disable
);
4307 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f05, PCI_CLASS_NOT_DEFINED
, 8,
4308 quirk_relaxedordering_disable
);
4309 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f06, PCI_CLASS_NOT_DEFINED
, 8,
4310 quirk_relaxedordering_disable
);
4311 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f07, PCI_CLASS_NOT_DEFINED
, 8,
4312 quirk_relaxedordering_disable
);
4313 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f08, PCI_CLASS_NOT_DEFINED
, 8,
4314 quirk_relaxedordering_disable
);
4315 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f09, PCI_CLASS_NOT_DEFINED
, 8,
4316 quirk_relaxedordering_disable
);
4317 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0a, PCI_CLASS_NOT_DEFINED
, 8,
4318 quirk_relaxedordering_disable
);
4319 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0b, PCI_CLASS_NOT_DEFINED
, 8,
4320 quirk_relaxedordering_disable
);
4321 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0c, PCI_CLASS_NOT_DEFINED
, 8,
4322 quirk_relaxedordering_disable
);
4323 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0d, PCI_CLASS_NOT_DEFINED
, 8,
4324 quirk_relaxedordering_disable
);
4325 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0e, PCI_CLASS_NOT_DEFINED
, 8,
4326 quirk_relaxedordering_disable
);
4329 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4330 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4331 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4332 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4333 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4334 * November 10, 2010). As a result, on this platform we can't use Relaxed
4335 * Ordering for Upstream TLPs.
4337 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a00, PCI_CLASS_NOT_DEFINED
, 8,
4338 quirk_relaxedordering_disable
);
4339 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a01, PCI_CLASS_NOT_DEFINED
, 8,
4340 quirk_relaxedordering_disable
);
4341 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a02, PCI_CLASS_NOT_DEFINED
, 8,
4342 quirk_relaxedordering_disable
);
4345 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4346 * values for the Attribute as were supplied in the header of the
4347 * corresponding Request, except as explicitly allowed when IDO is used."
4349 * If a non-compliant device generates a completion with a different
4350 * attribute than the request, the receiver may accept it (which itself
4351 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4352 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4353 * device access timeout.
4355 * If the non-compliant device generates completions with zero attributes
4356 * (instead of copying the attributes from the request), we can work around
4357 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4358 * upstream devices so they always generate requests with zero attributes.
4360 * This affects other devices under the same Root Port, but since these
4361 * attributes are performance hints, there should be no functional problem.
4363 * Note that Configuration Space accesses are never supposed to have TLP
4364 * Attributes, so we're safe waiting till after any Configuration Space
4365 * accesses to do the Root Port fixup.
4367 static void quirk_disable_root_port_attributes(struct pci_dev
*pdev
)
4369 struct pci_dev
*root_port
= pcie_find_root_port(pdev
);
4372 pci_warn(pdev
, "PCIe Completion erratum may cause device errors\n");
4376 pci_info(root_port
, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4377 dev_name(&pdev
->dev
));
4378 pcie_capability_clear_and_set_word(root_port
, PCI_EXP_DEVCTL
,
4379 PCI_EXP_DEVCTL_RELAX_EN
|
4380 PCI_EXP_DEVCTL_NOSNOOP_EN
, 0);
4384 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4385 * Completion it generates.
4387 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev
*pdev
)
4390 * This mask/compare operation selects for Physical Function 4 on a
4391 * T5. We only need to fix up the Root Port once for any of the
4392 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4393 * 0x54xx so we use that one.
4395 if ((pdev
->device
& 0xff00) == 0x5400)
4396 quirk_disable_root_port_attributes(pdev
);
4398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
4399 quirk_chelsio_T5_disable_root_port_attributes
);
4402 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4404 * @acs_ctrl_req: Bitmask of desired ACS controls
4405 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4406 * the hardware design
4408 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4409 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4410 * caller desires. Return 0 otherwise.
4412 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req
, u16 acs_ctrl_ena
)
4414 if ((acs_ctrl_req
& acs_ctrl_ena
) == acs_ctrl_req
)
4420 * AMD has indicated that the devices below do not support peer-to-peer
4421 * in any system where they are found in the southbridge with an AMD
4422 * IOMMU in the system. Multifunction devices that do not support
4423 * peer-to-peer between functions can claim to support a subset of ACS.
4424 * Such devices effectively enable request redirect (RR) and completion
4425 * redirect (CR) since all transactions are redirected to the upstream
4428 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4429 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4430 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4432 * 1002:4385 SBx00 SMBus Controller
4433 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4434 * 1002:4383 SBx00 Azalia (Intel HDA)
4435 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4436 * 1002:4384 SBx00 PCI to PCI Bridge
4437 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4439 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4441 * 1022:780f [AMD] FCH PCI Bridge
4442 * 1022:7809 [AMD] FCH USB OHCI Controller
4444 static int pci_quirk_amd_sb_acs(struct pci_dev
*dev
, u16 acs_flags
)
4447 struct acpi_table_header
*header
= NULL
;
4450 /* Targeting multifunction devices on the SB (appears on root bus) */
4451 if (!dev
->multifunction
|| !pci_is_root_bus(dev
->bus
))
4454 /* The IVRS table describes the AMD IOMMU */
4455 status
= acpi_get_table("IVRS", 0, &header
);
4456 if (ACPI_FAILURE(status
))
4459 acpi_put_table(header
);
4461 /* Filter out flags not applicable to multifunction */
4462 acs_flags
&= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
| PCI_ACS_DT
);
4464 return pci_acs_ctrl_enabled(acs_flags
, PCI_ACS_RR
| PCI_ACS_CR
);
4470 static bool pci_quirk_cavium_acs_match(struct pci_dev
*dev
)
4472 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4475 switch (dev
->device
) {
4477 * Effectively selects all downstream ports for whole ThunderX1
4478 * (which represents 8 SoCs).
4480 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4481 case 0xaf84: /* ThunderX2 */
4482 case 0xb884: /* ThunderX3 */
4489 static int pci_quirk_cavium_acs(struct pci_dev
*dev
, u16 acs_flags
)
4491 if (!pci_quirk_cavium_acs_match(dev
))
4495 * Cavium Root Ports don't advertise an ACS capability. However,
4496 * the RTL internally implements similar protection as if ACS had
4497 * Source Validation, Request Redirection, Completion Redirection,
4498 * and Upstream Forwarding features enabled. Assert that the
4499 * hardware implements and enables equivalent ACS functionality for
4502 return pci_acs_ctrl_enabled(acs_flags
,
4503 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4506 static int pci_quirk_xgene_acs(struct pci_dev
*dev
, u16 acs_flags
)
4509 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4510 * transactions with others, allowing masking out these bits as if they
4511 * were unimplemented in the ACS capability.
4513 return pci_acs_ctrl_enabled(acs_flags
,
4514 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4518 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4519 * But the implementation could block peer-to-peer transactions between them
4520 * and provide ACS-like functionality.
4522 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev
*dev
, u16 acs_flags
)
4524 if (!pci_is_pcie(dev
) ||
4525 ((pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
) &&
4526 (pci_pcie_type(dev
) != PCI_EXP_TYPE_DOWNSTREAM
)))
4529 switch (dev
->device
) {
4530 case 0x0710 ... 0x071e:
4532 case 0x0723 ... 0x0732:
4533 return pci_acs_ctrl_enabled(acs_flags
,
4534 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4541 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4542 * transactions and validate bus numbers in requests, but do not provide an
4543 * actual PCIe ACS capability. This is the list of device IDs known to fall
4544 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4546 static const u16 pci_quirk_intel_pch_acs_ids
[] = {
4548 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4549 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4550 /* Cougarpoint PCH */
4551 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4552 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4553 /* Pantherpoint PCH */
4554 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4555 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4556 /* Lynxpoint-H PCH */
4557 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4558 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4559 /* Lynxpoint-LP PCH */
4560 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4561 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4563 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4564 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4565 /* Patsburg (X79) PCH */
4566 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4567 /* Wellsburg (X99) PCH */
4568 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4569 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4570 /* Lynx Point (9 series) PCH */
4571 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4574 static bool pci_quirk_intel_pch_acs_match(struct pci_dev
*dev
)
4578 /* Filter out a few obvious non-matches first */
4579 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4582 for (i
= 0; i
< ARRAY_SIZE(pci_quirk_intel_pch_acs_ids
); i
++)
4583 if (pci_quirk_intel_pch_acs_ids
[i
] == dev
->device
)
4589 static int pci_quirk_intel_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4591 if (!pci_quirk_intel_pch_acs_match(dev
))
4594 if (dev
->dev_flags
& PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
)
4595 return pci_acs_ctrl_enabled(acs_flags
,
4596 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4598 return pci_acs_ctrl_enabled(acs_flags
, 0);
4602 * These QCOM Root Ports do provide ACS-like features to disable peer
4603 * transactions and validate bus numbers in requests, but do not provide an
4604 * actual PCIe ACS capability. Hardware supports source validation but it
4605 * will report the issue as Completer Abort instead of ACS Violation.
4606 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4607 * Complex with unique segment numbers. It is not possible for one Root
4608 * Port to pass traffic to another Root Port. All PCIe transactions are
4609 * terminated inside the Root Port.
4611 static int pci_quirk_qcom_rp_acs(struct pci_dev
*dev
, u16 acs_flags
)
4613 return pci_acs_ctrl_enabled(acs_flags
,
4614 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4617 static int pci_quirk_al_acs(struct pci_dev
*dev
, u16 acs_flags
)
4619 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4623 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4624 * but do include ACS-like functionality. The hardware doesn't support
4625 * peer-to-peer transactions via the root port and each has a unique
4628 * Additionally, the root ports cannot send traffic to each other.
4630 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4632 return acs_flags
? 0 : 1;
4636 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4637 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4638 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4639 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4640 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4641 * control register is at offset 8 instead of 6 and we should probably use
4642 * dword accesses to them. This applies to the following PCI Device IDs, as
4643 * found in volume 1 of the datasheet[2]:
4645 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4646 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4648 * N.B. This doesn't fix what lspci shows.
4650 * The 100 series chipset specification update includes this as errata #23[3].
4652 * The 200 series chipset (Union Point) has the same bug according to the
4653 * specification update (Intel 200 Series Chipset Family Platform Controller
4654 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4655 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4658 * 0xa290-0xa29f PCI Express Root port #{0-16}
4659 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4661 * Mobile chipsets are also affected, 7th & 8th Generation
4662 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4663 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4664 * Processor Family I/O for U Quad Core Platforms Specification Update,
4665 * August 2017, Revision 002, Document#: 334660-002)[6]
4666 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4667 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4668 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4670 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4672 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4673 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4674 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4675 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4676 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4677 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4678 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4680 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev
*dev
)
4682 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4685 switch (dev
->device
) {
4686 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4687 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4688 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4695 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4697 static int pci_quirk_intel_spt_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4702 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4709 /* see pci_acs_flags_enabled() */
4710 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4711 acs_flags
&= (cap
| PCI_ACS_EC
);
4713 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4715 return pci_acs_ctrl_enabled(acs_flags
, ctrl
);
4718 static int pci_quirk_mf_endpoint_acs(struct pci_dev
*dev
, u16 acs_flags
)
4721 * SV, TB, and UF are not relevant to multifunction endpoints.
4723 * Multifunction devices are only required to implement RR, CR, and DT
4724 * in their ACS capability if they support peer-to-peer transactions.
4725 * Devices matching this quirk have been verified by the vendor to not
4726 * perform peer-to-peer with other functions, allowing us to mask out
4727 * these bits as if they were unimplemented in the ACS capability.
4729 return pci_acs_ctrl_enabled(acs_flags
,
4730 PCI_ACS_SV
| PCI_ACS_TB
| PCI_ACS_RR
|
4731 PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_DT
);
4734 static int pci_quirk_rciep_acs(struct pci_dev
*dev
, u16 acs_flags
)
4737 * Intel RCiEP's are required to allow p2p only on translated
4738 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4739 * "Root-Complex Peer to Peer Considerations".
4741 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_RC_END
)
4744 return pci_acs_ctrl_enabled(acs_flags
,
4745 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4748 static int pci_quirk_brcm_acs(struct pci_dev
*dev
, u16 acs_flags
)
4751 * iProc PAXB Root Ports don't advertise an ACS capability, but
4752 * they do not allow peer-to-peer transactions between Root Ports.
4753 * Allow each Root Port to be in a separate IOMMU group by masking
4756 return pci_acs_ctrl_enabled(acs_flags
,
4757 PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4760 static const struct pci_dev_acs_enabled
{
4763 int (*acs_enabled
)(struct pci_dev
*dev
, u16 acs_flags
);
4764 } pci_dev_acs_enabled
[] = {
4765 { PCI_VENDOR_ID_ATI
, 0x4385, pci_quirk_amd_sb_acs
},
4766 { PCI_VENDOR_ID_ATI
, 0x439c, pci_quirk_amd_sb_acs
},
4767 { PCI_VENDOR_ID_ATI
, 0x4383, pci_quirk_amd_sb_acs
},
4768 { PCI_VENDOR_ID_ATI
, 0x439d, pci_quirk_amd_sb_acs
},
4769 { PCI_VENDOR_ID_ATI
, 0x4384, pci_quirk_amd_sb_acs
},
4770 { PCI_VENDOR_ID_ATI
, 0x4399, pci_quirk_amd_sb_acs
},
4771 { PCI_VENDOR_ID_AMD
, 0x780f, pci_quirk_amd_sb_acs
},
4772 { PCI_VENDOR_ID_AMD
, 0x7809, pci_quirk_amd_sb_acs
},
4773 { PCI_VENDOR_ID_SOLARFLARE
, 0x0903, pci_quirk_mf_endpoint_acs
},
4774 { PCI_VENDOR_ID_SOLARFLARE
, 0x0923, pci_quirk_mf_endpoint_acs
},
4775 { PCI_VENDOR_ID_SOLARFLARE
, 0x0A03, pci_quirk_mf_endpoint_acs
},
4776 { PCI_VENDOR_ID_INTEL
, 0x10C6, pci_quirk_mf_endpoint_acs
},
4777 { PCI_VENDOR_ID_INTEL
, 0x10DB, pci_quirk_mf_endpoint_acs
},
4778 { PCI_VENDOR_ID_INTEL
, 0x10DD, pci_quirk_mf_endpoint_acs
},
4779 { PCI_VENDOR_ID_INTEL
, 0x10E1, pci_quirk_mf_endpoint_acs
},
4780 { PCI_VENDOR_ID_INTEL
, 0x10F1, pci_quirk_mf_endpoint_acs
},
4781 { PCI_VENDOR_ID_INTEL
, 0x10F7, pci_quirk_mf_endpoint_acs
},
4782 { PCI_VENDOR_ID_INTEL
, 0x10F8, pci_quirk_mf_endpoint_acs
},
4783 { PCI_VENDOR_ID_INTEL
, 0x10F9, pci_quirk_mf_endpoint_acs
},
4784 { PCI_VENDOR_ID_INTEL
, 0x10FA, pci_quirk_mf_endpoint_acs
},
4785 { PCI_VENDOR_ID_INTEL
, 0x10FB, pci_quirk_mf_endpoint_acs
},
4786 { PCI_VENDOR_ID_INTEL
, 0x10FC, pci_quirk_mf_endpoint_acs
},
4787 { PCI_VENDOR_ID_INTEL
, 0x1507, pci_quirk_mf_endpoint_acs
},
4788 { PCI_VENDOR_ID_INTEL
, 0x1514, pci_quirk_mf_endpoint_acs
},
4789 { PCI_VENDOR_ID_INTEL
, 0x151C, pci_quirk_mf_endpoint_acs
},
4790 { PCI_VENDOR_ID_INTEL
, 0x1529, pci_quirk_mf_endpoint_acs
},
4791 { PCI_VENDOR_ID_INTEL
, 0x152A, pci_quirk_mf_endpoint_acs
},
4792 { PCI_VENDOR_ID_INTEL
, 0x154D, pci_quirk_mf_endpoint_acs
},
4793 { PCI_VENDOR_ID_INTEL
, 0x154F, pci_quirk_mf_endpoint_acs
},
4794 { PCI_VENDOR_ID_INTEL
, 0x1551, pci_quirk_mf_endpoint_acs
},
4795 { PCI_VENDOR_ID_INTEL
, 0x1558, pci_quirk_mf_endpoint_acs
},
4797 { PCI_VENDOR_ID_INTEL
, 0x1509, pci_quirk_mf_endpoint_acs
},
4798 { PCI_VENDOR_ID_INTEL
, 0x150E, pci_quirk_mf_endpoint_acs
},
4799 { PCI_VENDOR_ID_INTEL
, 0x150F, pci_quirk_mf_endpoint_acs
},
4800 { PCI_VENDOR_ID_INTEL
, 0x1510, pci_quirk_mf_endpoint_acs
},
4801 { PCI_VENDOR_ID_INTEL
, 0x1511, pci_quirk_mf_endpoint_acs
},
4802 { PCI_VENDOR_ID_INTEL
, 0x1516, pci_quirk_mf_endpoint_acs
},
4803 { PCI_VENDOR_ID_INTEL
, 0x1527, pci_quirk_mf_endpoint_acs
},
4805 { PCI_VENDOR_ID_INTEL
, 0x10C9, pci_quirk_mf_endpoint_acs
},
4806 { PCI_VENDOR_ID_INTEL
, 0x10E6, pci_quirk_mf_endpoint_acs
},
4807 { PCI_VENDOR_ID_INTEL
, 0x10E7, pci_quirk_mf_endpoint_acs
},
4808 { PCI_VENDOR_ID_INTEL
, 0x10E8, pci_quirk_mf_endpoint_acs
},
4809 { PCI_VENDOR_ID_INTEL
, 0x150A, pci_quirk_mf_endpoint_acs
},
4810 { PCI_VENDOR_ID_INTEL
, 0x150D, pci_quirk_mf_endpoint_acs
},
4811 { PCI_VENDOR_ID_INTEL
, 0x1518, pci_quirk_mf_endpoint_acs
},
4812 { PCI_VENDOR_ID_INTEL
, 0x1526, pci_quirk_mf_endpoint_acs
},
4814 { PCI_VENDOR_ID_INTEL
, 0x10A7, pci_quirk_mf_endpoint_acs
},
4815 { PCI_VENDOR_ID_INTEL
, 0x10A9, pci_quirk_mf_endpoint_acs
},
4816 { PCI_VENDOR_ID_INTEL
, 0x10D6, pci_quirk_mf_endpoint_acs
},
4818 { PCI_VENDOR_ID_INTEL
, 0x1521, pci_quirk_mf_endpoint_acs
},
4819 { PCI_VENDOR_ID_INTEL
, 0x1522, pci_quirk_mf_endpoint_acs
},
4820 { PCI_VENDOR_ID_INTEL
, 0x1523, pci_quirk_mf_endpoint_acs
},
4821 { PCI_VENDOR_ID_INTEL
, 0x1524, pci_quirk_mf_endpoint_acs
},
4822 /* 82571 (Quads omitted due to non-ACS switch) */
4823 { PCI_VENDOR_ID_INTEL
, 0x105E, pci_quirk_mf_endpoint_acs
},
4824 { PCI_VENDOR_ID_INTEL
, 0x105F, pci_quirk_mf_endpoint_acs
},
4825 { PCI_VENDOR_ID_INTEL
, 0x1060, pci_quirk_mf_endpoint_acs
},
4826 { PCI_VENDOR_ID_INTEL
, 0x10D9, pci_quirk_mf_endpoint_acs
},
4828 { PCI_VENDOR_ID_INTEL
, 0x15b7, pci_quirk_mf_endpoint_acs
},
4829 { PCI_VENDOR_ID_INTEL
, 0x15b8, pci_quirk_mf_endpoint_acs
},
4830 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_rciep_acs
},
4831 /* QCOM QDF2xxx root ports */
4832 { PCI_VENDOR_ID_QCOM
, 0x0400, pci_quirk_qcom_rp_acs
},
4833 { PCI_VENDOR_ID_QCOM
, 0x0401, pci_quirk_qcom_rp_acs
},
4834 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4835 { PCI_VENDOR_ID_HXT
, 0x0401, pci_quirk_qcom_rp_acs
},
4836 /* Intel PCH root ports */
4837 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_pch_acs
},
4838 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_spt_pch_acs
},
4839 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs
}, /* Emulex BE3-R */
4840 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs
}, /* Emulex Skyhawk-R */
4841 /* Cavium ThunderX */
4842 { PCI_VENDOR_ID_CAVIUM
, PCI_ANY_ID
, pci_quirk_cavium_acs
},
4844 { PCI_VENDOR_ID_AMCC
, 0xE004, pci_quirk_xgene_acs
},
4845 /* Ampere Computing */
4846 { PCI_VENDOR_ID_AMPERE
, 0xE005, pci_quirk_xgene_acs
},
4847 { PCI_VENDOR_ID_AMPERE
, 0xE006, pci_quirk_xgene_acs
},
4848 { PCI_VENDOR_ID_AMPERE
, 0xE007, pci_quirk_xgene_acs
},
4849 { PCI_VENDOR_ID_AMPERE
, 0xE008, pci_quirk_xgene_acs
},
4850 { PCI_VENDOR_ID_AMPERE
, 0xE009, pci_quirk_xgene_acs
},
4851 { PCI_VENDOR_ID_AMPERE
, 0xE00A, pci_quirk_xgene_acs
},
4852 { PCI_VENDOR_ID_AMPERE
, 0xE00B, pci_quirk_xgene_acs
},
4853 { PCI_VENDOR_ID_AMPERE
, 0xE00C, pci_quirk_xgene_acs
},
4854 /* Broadcom multi-function device */
4855 { PCI_VENDOR_ID_BROADCOM
, 0x16D7, pci_quirk_mf_endpoint_acs
},
4856 { PCI_VENDOR_ID_BROADCOM
, 0xD714, pci_quirk_brcm_acs
},
4857 /* Amazon Annapurna Labs */
4858 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS
, 0x0031, pci_quirk_al_acs
},
4859 /* Zhaoxin multi-function devices */
4860 { PCI_VENDOR_ID_ZHAOXIN
, 0x3038, pci_quirk_mf_endpoint_acs
},
4861 { PCI_VENDOR_ID_ZHAOXIN
, 0x3104, pci_quirk_mf_endpoint_acs
},
4862 { PCI_VENDOR_ID_ZHAOXIN
, 0x9083, pci_quirk_mf_endpoint_acs
},
4863 /* Zhaoxin Root/Downstream Ports */
4864 { PCI_VENDOR_ID_ZHAOXIN
, PCI_ANY_ID
, pci_quirk_zhaoxin_pcie_ports_acs
},
4869 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4871 * @acs_flags: Bitmask of desired ACS controls
4874 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4875 * device provides the desired controls
4876 * 0: Device does not provide all the desired controls
4877 * >0: Device provides all the controls in @acs_flags
4879 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
)
4881 const struct pci_dev_acs_enabled
*i
;
4885 * Allow devices that do not expose standard PCIe ACS capabilities
4886 * or control to indicate their support here. Multi-function express
4887 * devices which do not allow internal peer-to-peer between functions,
4888 * but do not implement PCIe ACS may wish to return true here.
4890 for (i
= pci_dev_acs_enabled
; i
->acs_enabled
; i
++) {
4891 if ((i
->vendor
== dev
->vendor
||
4892 i
->vendor
== (u16
)PCI_ANY_ID
) &&
4893 (i
->device
== dev
->device
||
4894 i
->device
== (u16
)PCI_ANY_ID
)) {
4895 ret
= i
->acs_enabled(dev
, acs_flags
);
4904 /* Config space offset of Root Complex Base Address register */
4905 #define INTEL_LPC_RCBA_REG 0xf0
4906 /* 31:14 RCBA address */
4907 #define INTEL_LPC_RCBA_MASK 0xffffc000
4909 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4911 /* Backbone Scratch Pad Register */
4912 #define INTEL_BSPR_REG 0x1104
4913 /* Backbone Peer Non-Posted Disable */
4914 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4915 /* Backbone Peer Posted Disable */
4916 #define INTEL_BSPR_REG_BPPD (1 << 9)
4918 /* Upstream Peer Decode Configuration Register */
4919 #define INTEL_UPDCR_REG 0x1014
4920 /* 5:0 Peer Decode Enable bits */
4921 #define INTEL_UPDCR_REG_MASK 0x3f
4923 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev
*dev
)
4925 u32 rcba
, bspr
, updcr
;
4926 void __iomem
*rcba_mem
;
4929 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4930 * are D28:F* and therefore get probed before LPC, thus we can't
4931 * use pci_get_slot()/pci_read_config_dword() here.
4933 pci_bus_read_config_dword(dev
->bus
, PCI_DEVFN(31, 0),
4934 INTEL_LPC_RCBA_REG
, &rcba
);
4935 if (!(rcba
& INTEL_LPC_RCBA_ENABLE
))
4938 rcba_mem
= ioremap(rcba
& INTEL_LPC_RCBA_MASK
,
4939 PAGE_ALIGN(INTEL_UPDCR_REG
));
4944 * The BSPR can disallow peer cycles, but it's set by soft strap and
4945 * therefore read-only. If both posted and non-posted peer cycles are
4946 * disallowed, we're ok. If either are allowed, then we need to use
4947 * the UPDCR to disable peer decodes for each port. This provides the
4948 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4950 bspr
= readl(rcba_mem
+ INTEL_BSPR_REG
);
4951 bspr
&= INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
;
4952 if (bspr
!= (INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
)) {
4953 updcr
= readl(rcba_mem
+ INTEL_UPDCR_REG
);
4954 if (updcr
& INTEL_UPDCR_REG_MASK
) {
4955 pci_info(dev
, "Disabling UPDCR peer decodes\n");
4956 updcr
&= ~INTEL_UPDCR_REG_MASK
;
4957 writel(updcr
, rcba_mem
+ INTEL_UPDCR_REG
);
4965 /* Miscellaneous Port Configuration register */
4966 #define INTEL_MPC_REG 0xd8
4967 /* MPC: Invalid Receive Bus Number Check Enable */
4968 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4970 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev
*dev
)
4975 * When enabled, the IRBNCE bit of the MPC register enables the
4976 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4977 * ensures that requester IDs fall within the bus number range
4978 * of the bridge. Enable if not already.
4980 pci_read_config_dword(dev
, INTEL_MPC_REG
, &mpc
);
4981 if (!(mpc
& INTEL_MPC_REG_IRBNCE
)) {
4982 pci_info(dev
, "Enabling MPC IRBNCE\n");
4983 mpc
|= INTEL_MPC_REG_IRBNCE
;
4984 pci_write_config_word(dev
, INTEL_MPC_REG
, mpc
);
4989 * Currently this quirk does the equivalent of
4990 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4992 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
4993 * if dev->external_facing || dev->untrusted
4995 static int pci_quirk_enable_intel_pch_acs(struct pci_dev
*dev
)
4997 if (!pci_quirk_intel_pch_acs_match(dev
))
5000 if (pci_quirk_enable_intel_lpc_acs(dev
)) {
5001 pci_warn(dev
, "Failed to enable Intel PCH ACS quirk\n");
5005 pci_quirk_enable_intel_rp_mpc_acs(dev
);
5007 dev
->dev_flags
|= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
;
5009 pci_info(dev
, "Intel PCH root port ACS workaround enabled\n");
5014 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev
*dev
)
5019 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
5026 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
5027 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
5029 ctrl
|= (cap
& PCI_ACS_SV
);
5030 ctrl
|= (cap
& PCI_ACS_RR
);
5031 ctrl
|= (cap
& PCI_ACS_CR
);
5032 ctrl
|= (cap
& PCI_ACS_UF
);
5034 if (dev
->external_facing
|| dev
->untrusted
)
5035 ctrl
|= (cap
& PCI_ACS_TB
);
5037 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
5039 pci_info(dev
, "Intel SPT PCH root port ACS workaround enabled\n");
5044 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev
*dev
)
5049 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
5056 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
5057 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
5059 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
5061 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
5063 pci_info(dev
, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5068 static const struct pci_dev_acs_ops
{
5071 int (*enable_acs
)(struct pci_dev
*dev
);
5072 int (*disable_acs_redir
)(struct pci_dev
*dev
);
5073 } pci_dev_acs_ops
[] = {
5074 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
5075 .enable_acs
= pci_quirk_enable_intel_pch_acs
,
5077 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
5078 .enable_acs
= pci_quirk_enable_intel_spt_pch_acs
,
5079 .disable_acs_redir
= pci_quirk_disable_intel_spt_pch_acs_redir
,
5083 int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
5085 const struct pci_dev_acs_ops
*p
;
5088 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
5089 p
= &pci_dev_acs_ops
[i
];
5090 if ((p
->vendor
== dev
->vendor
||
5091 p
->vendor
== (u16
)PCI_ANY_ID
) &&
5092 (p
->device
== dev
->device
||
5093 p
->device
== (u16
)PCI_ANY_ID
) &&
5095 ret
= p
->enable_acs(dev
);
5104 int pci_dev_specific_disable_acs_redir(struct pci_dev
*dev
)
5106 const struct pci_dev_acs_ops
*p
;
5109 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
5110 p
= &pci_dev_acs_ops
[i
];
5111 if ((p
->vendor
== dev
->vendor
||
5112 p
->vendor
== (u16
)PCI_ANY_ID
) &&
5113 (p
->device
== dev
->device
||
5114 p
->device
== (u16
)PCI_ANY_ID
) &&
5115 p
->disable_acs_redir
) {
5116 ret
= p
->disable_acs_redir(dev
);
5126 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5127 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5128 * Next Capability pointer in the MSI Capability Structure should point to
5129 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5132 static void quirk_intel_qat_vf_cap(struct pci_dev
*pdev
)
5137 struct pci_cap_saved_state
*state
;
5139 /* Bail if the hardware bug is fixed */
5140 if (pdev
->pcie_cap
|| pci_find_capability(pdev
, PCI_CAP_ID_EXP
))
5143 /* Bail if MSI Capability Structure is not found for some reason */
5144 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSI
);
5149 * Bail if Next Capability pointer in the MSI Capability Structure
5150 * is not the expected incorrect 0x00.
5152 pci_read_config_byte(pdev
, pos
+ 1, &next_cap
);
5157 * PCIe Capability Structure is expected to be at 0x50 and should
5158 * terminate the list (Next Capability pointer is 0x00). Verify
5159 * Capability Id and Next Capability pointer is as expected.
5160 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5161 * to correctly set kernel data structures which have already been
5162 * set incorrectly due to the hardware bug.
5165 pci_read_config_word(pdev
, pos
, ®16
);
5166 if (reg16
== (0x0000 | PCI_CAP_ID_EXP
)) {
5168 #ifndef PCI_EXP_SAVE_REGS
5169 #define PCI_EXP_SAVE_REGS 7
5171 int size
= PCI_EXP_SAVE_REGS
* sizeof(u16
);
5173 pdev
->pcie_cap
= pos
;
5174 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
5175 pdev
->pcie_flags_reg
= reg16
;
5176 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
5177 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
5179 pdev
->cfg_size
= PCI_CFG_SPACE_EXP_SIZE
;
5180 if (pci_read_config_dword(pdev
, PCI_CFG_SPACE_SIZE
, &status
) !=
5181 PCIBIOS_SUCCESSFUL
|| (status
== 0xffffffff))
5182 pdev
->cfg_size
= PCI_CFG_SPACE_SIZE
;
5184 if (pci_find_saved_cap(pdev
, PCI_CAP_ID_EXP
))
5188 state
= kzalloc(sizeof(*state
) + size
, GFP_KERNEL
);
5192 state
->cap
.cap_nr
= PCI_CAP_ID_EXP
;
5193 state
->cap
.cap_extended
= 0;
5194 state
->cap
.size
= size
;
5195 cap
= (u16
*)&state
->cap
.data
[0];
5196 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
5197 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
5198 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
5199 pcie_capability_read_word(pdev
, PCI_EXP_RTCTL
, &cap
[i
++]);
5200 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
5201 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
5202 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
5203 hlist_add_head(&state
->next
, &pdev
->saved_cap_space
);
5206 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x443, quirk_intel_qat_vf_cap
);
5209 * FLR may cause the following to devices to hang:
5211 * AMD Starship/Matisse HD Audio Controller 0x1487
5212 * AMD Starship USB 3.0 Host Controller 0x148c
5213 * AMD Matisse USB 3.0 Host Controller 0x149c
5214 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5215 * Intel 82579V Gigabit Ethernet Controller 0x1503
5218 static void quirk_no_flr(struct pci_dev
*dev
)
5220 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_FLR_RESET
;
5222 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD
, 0x1487, quirk_no_flr
);
5223 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD
, 0x148c, quirk_no_flr
);
5224 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD
, 0x149c, quirk_no_flr
);
5225 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1502, quirk_no_flr
);
5226 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1503, quirk_no_flr
);
5228 static void quirk_no_ext_tags(struct pci_dev
*pdev
)
5230 struct pci_host_bridge
*bridge
= pci_find_host_bridge(pdev
->bus
);
5235 bridge
->no_ext_tags
= 1;
5236 pci_info(pdev
, "disabling Extended Tags (this device can't handle them)\n");
5238 pci_walk_bus(bridge
->bus
, pci_configure_extended_tags
, NULL
);
5240 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0132, quirk_no_ext_tags
);
5241 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0140, quirk_no_ext_tags
);
5242 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0141, quirk_no_ext_tags
);
5243 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0142, quirk_no_ext_tags
);
5244 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0144, quirk_no_ext_tags
);
5245 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0420, quirk_no_ext_tags
);
5246 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0422, quirk_no_ext_tags
);
5248 #ifdef CONFIG_PCI_ATS
5250 * Some devices require additional driver setup to enable ATS. Don't use
5251 * ATS for those devices as ATS will be enabled before the driver has had a
5252 * chance to load and configure the device.
5254 static void quirk_amd_harvest_no_ats(struct pci_dev
*pdev
)
5256 if ((pdev
->device
== 0x7312 && pdev
->revision
!= 0x00) ||
5257 (pdev
->device
== 0x7340 && pdev
->revision
!= 0xc5) ||
5258 (pdev
->device
== 0x7341 && pdev
->revision
!= 0x00))
5261 if (pdev
->device
== 0x15d8) {
5262 if (pdev
->revision
== 0xcf &&
5263 pdev
->subsystem_vendor
== 0xea50 &&
5264 (pdev
->subsystem_device
== 0xce19 ||
5265 pdev
->subsystem_device
== 0xcc10 ||
5266 pdev
->subsystem_device
== 0xcc08))
5273 pci_info(pdev
, "disabling ATS\n");
5277 /* AMD Stoney platform GPU */
5278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x98e4, quirk_amd_harvest_no_ats
);
5279 /* AMD Iceland dGPU */
5280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6900, quirk_amd_harvest_no_ats
);
5281 /* AMD Navi10 dGPU */
5282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x7312, quirk_amd_harvest_no_ats
);
5283 /* AMD Navi14 dGPU */
5284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x7340, quirk_amd_harvest_no_ats
);
5285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x7341, quirk_amd_harvest_no_ats
);
5286 /* AMD Raven platform iGPU */
5287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x15d8, quirk_amd_harvest_no_ats
);
5288 #endif /* CONFIG_PCI_ATS */
5290 /* Freescale PCIe doesn't support MSI in RC mode */
5291 static void quirk_fsl_no_msi(struct pci_dev
*pdev
)
5293 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
)
5296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, quirk_fsl_no_msi
);
5299 * Although not allowed by the spec, some multi-function devices have
5300 * dependencies of one function (consumer) on another (supplier). For the
5301 * consumer to work in D0, the supplier must also be in D0. Create a
5302 * device link from the consumer to the supplier to enforce this
5303 * dependency. Runtime PM is allowed by default on the consumer to prevent
5304 * it from permanently keeping the supplier awake.
5306 static void pci_create_device_link(struct pci_dev
*pdev
, unsigned int consumer
,
5307 unsigned int supplier
, unsigned int class,
5308 unsigned int class_shift
)
5310 struct pci_dev
*supplier_pdev
;
5312 if (PCI_FUNC(pdev
->devfn
) != consumer
)
5315 supplier_pdev
= pci_get_domain_bus_and_slot(pci_domain_nr(pdev
->bus
),
5317 PCI_DEVFN(PCI_SLOT(pdev
->devfn
), supplier
));
5318 if (!supplier_pdev
|| (supplier_pdev
->class >> class_shift
) != class) {
5319 pci_dev_put(supplier_pdev
);
5323 if (device_link_add(&pdev
->dev
, &supplier_pdev
->dev
,
5324 DL_FLAG_STATELESS
| DL_FLAG_PM_RUNTIME
))
5325 pci_info(pdev
, "D0 power state depends on %s\n",
5326 pci_name(supplier_pdev
));
5328 pci_err(pdev
, "Cannot enforce power dependency on %s\n",
5329 pci_name(supplier_pdev
));
5331 pm_runtime_allow(&pdev
->dev
);
5332 pci_dev_put(supplier_pdev
);
5336 * Create device link for GPUs with integrated HDA controller for streaming
5337 * audio to attached displays.
5339 static void quirk_gpu_hda(struct pci_dev
*hda
)
5341 pci_create_device_link(hda
, 1, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5343 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
5344 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5345 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
,
5346 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5347 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5348 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5351 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5352 * controller to VGA.
5354 static void quirk_gpu_usb(struct pci_dev
*usb
)
5356 pci_create_device_link(usb
, 2, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5358 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5359 PCI_CLASS_SERIAL_USB
, 8, quirk_gpu_usb
);
5362 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5363 * to VGA. Currently there is no class code defined for UCSI device over PCI
5364 * so using UNKNOWN class for now and it will be updated when UCSI
5365 * over PCI gets a class code.
5367 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5368 static void quirk_gpu_usb_typec_ucsi(struct pci_dev
*ucsi
)
5370 pci_create_device_link(ucsi
, 3, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5372 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5373 PCI_CLASS_SERIAL_UNKNOWN
, 8,
5374 quirk_gpu_usb_typec_ucsi
);
5377 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5378 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5380 static void quirk_nvidia_hda(struct pci_dev
*gpu
)
5385 /* There was no integrated HDA controller before MCP89 */
5386 if (gpu
->device
< PCI_DEVICE_ID_NVIDIA_GEFORCE_320M
)
5389 /* Bit 25 at offset 0x488 enables the HDA controller */
5390 pci_read_config_dword(gpu
, 0x488, &val
);
5394 pci_info(gpu
, "Enabling HDA controller\n");
5395 pci_write_config_dword(gpu
, 0x488, val
| BIT(25));
5397 /* The GPU becomes a multi-function device when the HDA is enabled */
5398 pci_read_config_byte(gpu
, PCI_HEADER_TYPE
, &hdr_type
);
5399 gpu
->multifunction
= !!(hdr_type
& 0x80);
5401 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5402 PCI_BASE_CLASS_DISPLAY
, 16, quirk_nvidia_hda
);
5403 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5404 PCI_BASE_CLASS_DISPLAY
, 16, quirk_nvidia_hda
);
5407 * Some IDT switches incorrectly flag an ACS Source Validation error on
5408 * completions for config read requests even though PCIe r4.0, sec
5409 * 6.12.1.1, says that completions are never affected by ACS Source
5410 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5412 * Item #36 - Downstream port applies ACS Source Validation to Completions
5413 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5414 * completions are never affected by ACS Source Validation. However,
5415 * completions received by a downstream port of the PCIe switch from a
5416 * device that has not yet captured a PCIe bus number are incorrectly
5417 * dropped by ACS Source Validation by the switch downstream port.
5419 * The workaround suggested by IDT is to issue a config write to the
5420 * downstream device before issuing the first config read. This allows the
5421 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5422 * sec 2.2.9), thus avoiding the ACS error on the completion.
5424 * However, we don't know when the device is ready to accept the config
5425 * write, so we do config reads until we receive a non-Config Request Retry
5426 * Status, then do the config write.
5428 * To avoid hitting the erratum when doing the config reads, we disable ACS
5429 * SV around this process.
5431 int pci_idt_bus_quirk(struct pci_bus
*bus
, int devfn
, u32
*l
, int timeout
)
5436 struct pci_dev
*bridge
= bus
->self
;
5438 pos
= bridge
->acs_cap
;
5440 /* Disable ACS SV before initial config reads */
5442 pci_read_config_word(bridge
, pos
+ PCI_ACS_CTRL
, &ctrl
);
5443 if (ctrl
& PCI_ACS_SV
)
5444 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
,
5445 ctrl
& ~PCI_ACS_SV
);
5448 found
= pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
5450 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5452 pci_bus_write_config_word(bus
, devfn
, PCI_VENDOR_ID
, 0);
5454 /* Re-enable ACS_SV if it was previously enabled */
5455 if (ctrl
& PCI_ACS_SV
)
5456 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
, ctrl
);
5462 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5463 * NT endpoints via the internal switch fabric. These IDs replace the
5464 * originating requestor ID TLPs which access host memory on peer NTB
5465 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5466 * to permit access when the IOMMU is turned on.
5468 static void quirk_switchtec_ntb_dma_alias(struct pci_dev
*pdev
)
5471 struct ntb_info_regs __iomem
*mmio_ntb
;
5472 struct ntb_ctrl_regs __iomem
*mmio_ctrl
;
5477 if (pci_enable_device(pdev
)) {
5478 pci_err(pdev
, "Cannot enable Switchtec device\n");
5482 mmio
= pci_iomap(pdev
, 0, 0);
5484 pci_disable_device(pdev
);
5485 pci_err(pdev
, "Cannot iomap Switchtec device\n");
5489 pci_info(pdev
, "Setting Switchtec proxy ID aliases\n");
5491 mmio_ntb
= mmio
+ SWITCHTEC_GAS_NTB_OFFSET
;
5492 mmio_ctrl
= (void __iomem
*) mmio_ntb
+ SWITCHTEC_NTB_REG_CTRL_OFFSET
;
5494 partition
= ioread8(&mmio_ntb
->partition_id
);
5496 partition_map
= ioread32(&mmio_ntb
->ep_map
);
5497 partition_map
|= ((u64
) ioread32(&mmio_ntb
->ep_map
+ 4)) << 32;
5498 partition_map
&= ~(1ULL << partition
);
5500 for (pp
= 0; pp
< (sizeof(partition_map
) * 8); pp
++) {
5501 struct ntb_ctrl_regs __iomem
*mmio_peer_ctrl
;
5505 if (!(partition_map
& (1ULL << pp
)))
5508 pci_dbg(pdev
, "Processing partition %d\n", pp
);
5510 mmio_peer_ctrl
= &mmio_ctrl
[pp
];
5512 table_sz
= ioread16(&mmio_peer_ctrl
->req_id_table_size
);
5514 pci_warn(pdev
, "Partition %d table_sz 0\n", pp
);
5518 if (table_sz
> 512) {
5520 "Invalid Switchtec partition %d table_sz %d\n",
5525 for (te
= 0; te
< table_sz
; te
++) {
5529 rid_entry
= ioread32(&mmio_peer_ctrl
->req_id_table
[te
]);
5530 devfn
= (rid_entry
>> 1) & 0xFF;
5532 "Aliasing Partition %d Proxy ID %02x.%d\n",
5533 pp
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5534 pci_add_dma_alias(pdev
, devfn
, 1);
5538 pci_iounmap(pdev
, mmio
);
5539 pci_disable_device(pdev
);
5541 #define SWITCHTEC_QUIRK(vid) \
5542 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5543 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5545 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5546 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5547 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5548 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5549 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5550 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5551 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5552 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5553 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5554 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5555 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5556 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5557 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5558 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5559 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5560 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5561 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5562 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5563 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5564 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5565 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5566 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5567 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5568 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5569 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5570 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5571 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5572 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5573 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5574 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5575 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5576 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5577 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5578 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5579 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5580 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5581 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5582 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5583 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5584 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5585 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5586 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5587 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5588 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5589 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5590 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5591 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5592 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5595 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5596 * These IDs are used to forward responses to the originator on the other
5597 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5598 * the IOMMU is turned on.
5600 static void quirk_plx_ntb_dma_alias(struct pci_dev
*pdev
)
5602 pci_info(pdev
, "Setting PLX NTB proxy ID aliases\n");
5603 /* PLX NTB may use all 256 devfns */
5604 pci_add_dma_alias(pdev
, 0, 256);
5606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, 0x87b0, quirk_plx_ntb_dma_alias
);
5607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, 0x87b1, quirk_plx_ntb_dma_alias
);
5610 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5611 * not always reset the secondary Nvidia GPU between reboots if the system
5612 * is configured to use Hybrid Graphics mode. This results in the GPU
5613 * being left in whatever state it was in during the *previous* boot, which
5614 * causes spurious interrupts from the GPU, which in turn causes us to
5615 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5616 * this also completely breaks nouveau.
5618 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5619 * clean state and fixes all these issues.
5621 * When the machine is configured in Dedicated display mode, the issue
5622 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5623 * mode, so we can detect that and avoid resetting it.
5625 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev
*pdev
)
5630 if (pdev
->subsystem_vendor
!= PCI_VENDOR_ID_LENOVO
||
5631 pdev
->subsystem_device
!= 0x222e ||
5635 if (pci_enable_device_mem(pdev
))
5639 * Based on nvkm_device_ctor() in
5640 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5642 map
= pci_iomap(pdev
, 0, 0x23000);
5644 pci_err(pdev
, "Can't map MMIO space\n");
5649 * Make sure the GPU looks like it's been POSTed before resetting
5652 if (ioread32(map
+ 0x2240c) & 0x2) {
5653 pci_info(pdev
, FW_BUG
"GPU left initialized by EFI, resetting\n");
5654 ret
= pci_reset_bus(pdev
);
5656 pci_err(pdev
, "Failed to reset GPU: %d\n", ret
);
5661 pci_disable_device(pdev
);
5663 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, 0x13b1,
5664 PCI_CLASS_DISPLAY_VGA
, 8,
5665 quirk_reset_lenovo_thinkpad_p50_nvgpu
);
5668 * Device [1b21:2142]
5669 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5671 static void pci_fixup_no_d0_pme(struct pci_dev
*dev
)
5673 pci_info(dev
, "PME# does not work under D0, disabling it\n");
5674 dev
->pme_support
&= ~(PCI_PM_CAP_PME_D0
>> PCI_PM_CAP_PME_SHIFT
);
5676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA
, 0x2142, pci_fixup_no_d0_pme
);
5679 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5681 * These devices advertise PME# support in all power states but don't
5682 * reliably assert it.
5684 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5685 * says "The MSI Function is not implemented on this device" in chapters
5686 * 7.3.27, 7.3.29-7.3.31.
5688 static void pci_fixup_no_msi_no_pme(struct pci_dev
*dev
)
5690 #ifdef CONFIG_PCI_MSI
5691 pci_info(dev
, "MSI is not implemented on this device, disabling it\n");
5694 pci_info(dev
, "PME# is unreliable, disabling it\n");
5695 dev
->pme_support
= 0;
5697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM
, 0x400e, pci_fixup_no_msi_no_pme
);
5698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM
, 0x400f, pci_fixup_no_msi_no_pme
);
5700 static void apex_pci_fixup_class(struct pci_dev
*pdev
)
5702 pdev
->class = (PCI_CLASS_SYSTEM_OTHER
<< 8) | pdev
->class;
5704 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5705 PCI_CLASS_NOT_DEFINED
, 8, apex_pci_fixup_class
);