1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <linux/nvme.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/switchtec.h>
32 #include <asm/dma.h> /* isa_dma_bridge_buggy */
35 static ktime_t
fixup_debug_start(struct pci_dev
*dev
,
36 void (*fn
)(struct pci_dev
*dev
))
39 pci_info(dev
, "calling %pS @ %i\n", fn
, task_pid_nr(current
));
44 static void fixup_debug_report(struct pci_dev
*dev
, ktime_t calltime
,
45 void (*fn
)(struct pci_dev
*dev
))
47 ktime_t delta
, rettime
;
48 unsigned long long duration
;
50 rettime
= ktime_get();
51 delta
= ktime_sub(rettime
, calltime
);
52 duration
= (unsigned long long) ktime_to_ns(delta
) >> 10;
53 if (initcall_debug
|| duration
> 10000)
54 pci_info(dev
, "%pS took %lld usecs\n", fn
, duration
);
57 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
58 struct pci_fixup
*end
)
63 if ((f
->class == (u32
) (dev
->class >> f
->class_shift
) ||
64 f
->class == (u32
) PCI_ANY_ID
) &&
65 (f
->vendor
== dev
->vendor
||
66 f
->vendor
== (u16
) PCI_ANY_ID
) &&
67 (f
->device
== dev
->device
||
68 f
->device
== (u16
) PCI_ANY_ID
)) {
69 void (*hook
)(struct pci_dev
*dev
);
70 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
71 hook
= offset_to_ptr(&f
->hook_offset
);
75 calltime
= fixup_debug_start(dev
, hook
);
77 fixup_debug_report(dev
, calltime
, hook
);
81 extern struct pci_fixup __start_pci_fixups_early
[];
82 extern struct pci_fixup __end_pci_fixups_early
[];
83 extern struct pci_fixup __start_pci_fixups_header
[];
84 extern struct pci_fixup __end_pci_fixups_header
[];
85 extern struct pci_fixup __start_pci_fixups_final
[];
86 extern struct pci_fixup __end_pci_fixups_final
[];
87 extern struct pci_fixup __start_pci_fixups_enable
[];
88 extern struct pci_fixup __end_pci_fixups_enable
[];
89 extern struct pci_fixup __start_pci_fixups_resume
[];
90 extern struct pci_fixup __end_pci_fixups_resume
[];
91 extern struct pci_fixup __start_pci_fixups_resume_early
[];
92 extern struct pci_fixup __end_pci_fixups_resume_early
[];
93 extern struct pci_fixup __start_pci_fixups_suspend
[];
94 extern struct pci_fixup __end_pci_fixups_suspend
[];
95 extern struct pci_fixup __start_pci_fixups_suspend_late
[];
96 extern struct pci_fixup __end_pci_fixups_suspend_late
[];
98 static bool pci_apply_fixup_final_quirks
;
100 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
102 struct pci_fixup
*start
, *end
;
105 case pci_fixup_early
:
106 start
= __start_pci_fixups_early
;
107 end
= __end_pci_fixups_early
;
110 case pci_fixup_header
:
111 start
= __start_pci_fixups_header
;
112 end
= __end_pci_fixups_header
;
115 case pci_fixup_final
:
116 if (!pci_apply_fixup_final_quirks
)
118 start
= __start_pci_fixups_final
;
119 end
= __end_pci_fixups_final
;
122 case pci_fixup_enable
:
123 start
= __start_pci_fixups_enable
;
124 end
= __end_pci_fixups_enable
;
127 case pci_fixup_resume
:
128 start
= __start_pci_fixups_resume
;
129 end
= __end_pci_fixups_resume
;
132 case pci_fixup_resume_early
:
133 start
= __start_pci_fixups_resume_early
;
134 end
= __end_pci_fixups_resume_early
;
137 case pci_fixup_suspend
:
138 start
= __start_pci_fixups_suspend
;
139 end
= __end_pci_fixups_suspend
;
142 case pci_fixup_suspend_late
:
143 start
= __start_pci_fixups_suspend_late
;
144 end
= __end_pci_fixups_suspend_late
;
148 /* stupid compiler warning, you would think with an enum... */
151 pci_do_fixups(dev
, start
, end
);
153 EXPORT_SYMBOL(pci_fixup_device
);
155 static int __init
pci_apply_final_quirks(void)
157 struct pci_dev
*dev
= NULL
;
161 if (pci_cache_line_size
)
162 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size
<< 2);
164 pci_apply_fixup_final_quirks
= true;
165 for_each_pci_dev(dev
) {
166 pci_fixup_device(pci_fixup_final
, dev
);
168 * If arch hasn't set it explicitly yet, use the CLS
169 * value shared by all PCI devices. If there's a
170 * mismatch, fall back to the default value.
172 if (!pci_cache_line_size
) {
173 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
176 if (!tmp
|| cls
== tmp
)
179 pci_info(dev
, "CLS mismatch (%u != %u), using %u bytes\n",
181 pci_dfl_cache_line_size
<< 2);
182 pci_cache_line_size
= pci_dfl_cache_line_size
;
186 if (!pci_cache_line_size
) {
187 pr_info("PCI: CLS %u bytes, default %u\n", cls
<< 2,
188 pci_dfl_cache_line_size
<< 2);
189 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
194 fs_initcall_sync(pci_apply_final_quirks
);
197 * Decoding should be disabled for a PCI device during BAR sizing to avoid
198 * conflict. But doing so may cause problems on host bridge and perhaps other
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
202 static void quirk_mmio_always_on(struct pci_dev
*dev
)
204 dev
->mmio_always_on
= 1;
206 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
207 PCI_CLASS_BRIDGE_HOST
, 8, quirk_mmio_always_on
);
209 /* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed
210 * by IO resource file, and need to skip the files
212 static void quirk_marvell_mask_bar(struct pci_dev
*dev
)
216 for (i
= 0; i
< 5; i
++)
217 if (dev
->resource
[i
].start
)
218 dev
->resource
[i
].start
=
219 dev
->resource
[i
].end
= 0;
221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9125,
222 quirk_marvell_mask_bar
);
225 * The Mellanox Tavor device gives false positive parity errors. Mark this
226 * device with a broken_parity_status to allow PCI scanning code to "skip"
227 * this now blacklisted device.
229 static void quirk_mellanox_tavor(struct pci_dev
*dev
)
231 dev
->broken_parity_status
= 1; /* This device gives false positives */
233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR
, quirk_mellanox_tavor
);
234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
, quirk_mellanox_tavor
);
237 * Deal with broken BIOSes that neglect to enable passive release,
238 * which can cause problems in combination with the 82441FX/PPro MTRRs
240 static void quirk_passive_release(struct pci_dev
*dev
)
242 struct pci_dev
*d
= NULL
;
246 * We have to make sure a particular bit is set in the PIIX3
247 * ISA bridge, so we have to go out and find it.
249 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
250 pci_read_config_byte(d
, 0x82, &dlc
);
252 pci_info(d
, "PIIX3: Enabling Passive Release\n");
254 pci_write_config_byte(d
, 0x82, dlc
);
258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
259 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
262 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
263 * workaround but VIA don't answer queries. If you happen to have good
264 * contacts at VIA ask them for me please -- Alan
266 * This appears to be BIOS not version dependent. So presumably there is a
269 static void quirk_isa_dma_hangs(struct pci_dev
*dev
)
271 if (!isa_dma_bridge_buggy
) {
272 isa_dma_bridge_buggy
= 1;
273 pci_info(dev
, "Activating ISA DMA hang workarounds\n");
277 * It's not totally clear which chipsets are the problematic ones. We know
278 * 82C586 and 82C596 variants are affected.
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
289 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
290 * for some HT machines to use C4 w/o hanging.
292 static void quirk_tigerpoint_bm_sts(struct pci_dev
*dev
)
297 pci_read_config_dword(dev
, 0x40, &pmbase
);
298 pmbase
= pmbase
& 0xff80;
302 pci_info(dev
, FW_BUG
"TigerPoint LPC.BM_STS cleared\n");
306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_TGP_LPC
, quirk_tigerpoint_bm_sts
);
308 /* Chipsets where PCI->PCI transfers vanish or hang */
309 static void quirk_nopcipci(struct pci_dev
*dev
)
311 if ((pci_pci_problems
& PCIPCI_FAIL
) == 0) {
312 pci_info(dev
, "Disabling direct PCI/PCI transfers\n");
313 pci_pci_problems
|= PCIPCI_FAIL
;
316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
319 static void quirk_nopciamd(struct pci_dev
*dev
)
322 pci_read_config_byte(dev
, 0x08, &rev
);
325 pci_info(dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
326 pci_pci_problems
|= PCIAGP_FAIL
;
329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
331 /* Triton requires workarounds to be used by the drivers */
332 static void quirk_triton(struct pci_dev
*dev
)
334 if ((pci_pci_problems
&PCIPCI_TRITON
) == 0) {
335 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
336 pci_pci_problems
|= PCIPCI_TRITON
;
339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
345 * VIA Apollo KT133 needs PCI latency patch
346 * Made according to a Windows driver-based patch by George E. Breese;
347 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
348 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
349 * which Mr Breese based his work.
351 * Updated based on further information from the site and also on
352 * information provided by VIA
354 static void quirk_vialatency(struct pci_dev
*dev
)
360 * Ok, we have a potential problem chipset here. Now see if we have
361 * a buggy southbridge.
363 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
367 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
369 * Check for buggy part revisions
371 if (p
->revision
< 0x40 || p
->revision
> 0x42)
374 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
375 if (p
== NULL
) /* No problem parts */
378 /* Check for buggy part revisions */
379 if (p
->revision
< 0x10 || p
->revision
> 0x12)
384 * Ok we have the problem. Now set the PCI master grant to occur
385 * every master grant. The apparent bug is that under high PCI load
386 * (quite common in Linux of course) you can get data loss when the
387 * CPU is held off the bus for 3 bus master requests. This happens
388 * to include the IDE controllers....
390 * VIA only apply this fix when an SB Live! is present but under
391 * both Linux and Windows this isn't enough, and we have seen
392 * corruption without SB Live! but with things like 3 UDMA IDE
393 * controllers. So we ignore that bit of the VIA recommendation..
395 pci_read_config_byte(dev
, 0x76, &busarb
);
398 * Set bit 4 and bit 5 of byte 76 to 0x01
399 * "Master priority rotation on every PCI master grant"
403 pci_write_config_byte(dev
, 0x76, busarb
);
404 pci_info(dev
, "Applying VIA southbridge workaround\n");
408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
410 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
411 /* Must restore this on a resume from RAM */
412 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
413 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
414 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
416 /* VIA Apollo VP3 needs ETBF on BT848/878 */
417 static void quirk_viaetbf(struct pci_dev
*dev
)
419 if ((pci_pci_problems
&PCIPCI_VIAETBF
) == 0) {
420 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
421 pci_pci_problems
|= PCIPCI_VIAETBF
;
424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
426 static void quirk_vsfx(struct pci_dev
*dev
)
428 if ((pci_pci_problems
&PCIPCI_VSFX
) == 0) {
429 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
430 pci_pci_problems
|= PCIPCI_VSFX
;
433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
436 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
437 * space. Latency must be set to 0xA and Triton workaround applied too.
438 * [Info kindly provided by ALi]
440 static void quirk_alimagik(struct pci_dev
*dev
)
442 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
) == 0) {
443 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
444 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
450 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
451 static void quirk_natoma(struct pci_dev
*dev
)
453 if ((pci_pci_problems
&PCIPCI_NATOMA
) == 0) {
454 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
455 pci_pci_problems
|= PCIPCI_NATOMA
;
458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
466 * This chip can cause PCI parity errors if config register 0xA0 is read
467 * while DMAs are occurring.
469 static void quirk_citrine(struct pci_dev
*dev
)
471 dev
->cfg_size
= 0xA0;
473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
476 * This chip can cause bus lockups if config addresses above 0x600
477 * are read or written.
479 static void quirk_nfp6000(struct pci_dev
*dev
)
481 dev
->cfg_size
= 0x600;
483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP4000
, quirk_nfp6000
);
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000
, quirk_nfp6000
);
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP5000
, quirk_nfp6000
);
486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000_VF
, quirk_nfp6000
);
488 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
489 static void quirk_extend_bar_to_page(struct pci_dev
*dev
)
493 for (i
= 0; i
<= PCI_STD_RESOURCE_END
; i
++) {
494 struct resource
*r
= &dev
->resource
[i
];
496 if (r
->flags
& IORESOURCE_MEM
&& resource_size(r
) < PAGE_SIZE
) {
497 r
->end
= PAGE_SIZE
- 1;
499 r
->flags
|= IORESOURCE_UNSET
;
500 pci_info(dev
, "expanded BAR %d to page size: %pR\n",
505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, 0x034a, quirk_extend_bar_to_page
);
508 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
509 * If it's needed, re-allocate the region.
511 static void quirk_s3_64M(struct pci_dev
*dev
)
513 struct resource
*r
= &dev
->resource
[0];
515 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
516 r
->flags
|= IORESOURCE_UNSET
;
521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
524 static void quirk_io(struct pci_dev
*dev
, int pos
, unsigned size
,
528 struct pci_bus_region bus_region
;
529 struct resource
*res
= dev
->resource
+ pos
;
531 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), ®ion
);
536 res
->name
= pci_name(dev
);
537 res
->flags
= region
& ~PCI_BASE_ADDRESS_IO_MASK
;
539 (IORESOURCE_IO
| IORESOURCE_PCI_FIXED
| IORESOURCE_SIZEALIGN
);
540 region
&= ~(size
- 1);
542 /* Convert from PCI bus to resource space */
543 bus_region
.start
= region
;
544 bus_region
.end
= region
+ size
- 1;
545 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
547 pci_info(dev
, FW_BUG
"%s quirk: reg 0x%x: %pR\n",
548 name
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), res
);
552 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
553 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
554 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
555 * (which conflicts w/ BAR1's memory range).
557 * CS553x's ISA PCI BARs may also be read-only (ref:
558 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
560 static void quirk_cs5536_vsa(struct pci_dev
*dev
)
562 static char *name
= "CS5536 ISA bridge";
564 if (pci_resource_len(dev
, 0) != 8) {
565 quirk_io(dev
, 0, 8, name
); /* SMB */
566 quirk_io(dev
, 1, 256, name
); /* GPIO */
567 quirk_io(dev
, 2, 64, name
); /* MFGPT */
568 pci_info(dev
, "%s bug detected (incorrect header); workaround applied\n",
572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
574 static void quirk_io_region(struct pci_dev
*dev
, int port
,
575 unsigned size
, int nr
, const char *name
)
578 struct pci_bus_region bus_region
;
579 struct resource
*res
= dev
->resource
+ nr
;
581 pci_read_config_word(dev
, port
, ®ion
);
582 region
&= ~(size
- 1);
587 res
->name
= pci_name(dev
);
588 res
->flags
= IORESOURCE_IO
;
590 /* Convert from PCI bus to resource space */
591 bus_region
.start
= region
;
592 bus_region
.end
= region
+ size
- 1;
593 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
595 if (!pci_claim_resource(dev
, nr
))
596 pci_info(dev
, "quirk: %pR claimed by %s\n", res
, name
);
600 * ATI Northbridge setups MCE the processor if you even read somewhere
601 * between 0x3b0->0x3bb or read 0x3d3
603 static void quirk_ati_exploding_mce(struct pci_dev
*dev
)
605 pci_info(dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
606 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
607 request_region(0x3b0, 0x0C, "RadeonIGP");
608 request_region(0x3d3, 0x01, "RadeonIGP");
610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
613 * In the AMD NL platform, this device ([1022:7912]) has a class code of
614 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
617 * But the dwc3 driver is a more specific driver for this device, and we'd
618 * prefer to use it instead of xhci. To prevent xhci from claiming the
619 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
620 * defines as "USB device (not host controller)". The dwc3 driver can then
621 * claim it based on its Vendor and Device ID.
623 static void quirk_amd_nl_class(struct pci_dev
*pdev
)
625 u32
class = pdev
->class;
627 /* Use "USB Device (not host controller)" class */
628 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
629 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
632 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_NL_USB
,
636 * Synopsys USB 3.x host HAPS platform has a class code of
637 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
638 * devices should use dwc3-haps driver. Change these devices' class code to
639 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
642 static void quirk_synopsys_haps(struct pci_dev
*pdev
)
644 u32
class = pdev
->class;
646 switch (pdev
->device
) {
647 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3
:
648 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI
:
649 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31
:
650 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
651 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
656 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS
, PCI_ANY_ID
,
657 PCI_CLASS_SERIAL_USB_XHCI
, 0,
658 quirk_synopsys_haps
);
661 * Let's make the southbridge information explicit instead of having to
662 * worry about people probing the ACPI areas, for example.. (Yes, it
663 * happens, and if you read the wrong ACPI register it will put the machine
664 * to sleep with no way of waking it up again. Bummer).
666 * ALI M7101: Two IO regions pointed to by words at
667 * 0xE0 (64 bytes of ACPI registers)
668 * 0xE2 (32 bytes of SMB registers)
670 static void quirk_ali7101_acpi(struct pci_dev
*dev
)
672 quirk_io_region(dev
, 0xE0, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
673 quirk_io_region(dev
, 0xE2, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
675 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
677 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
680 u32 mask
, size
, base
;
682 pci_read_config_dword(dev
, port
, &devres
);
683 if ((devres
& enable
) != enable
)
685 mask
= (devres
>> 16) & 15;
686 base
= devres
& 0xffff;
689 unsigned bit
= size
>> 1;
690 if ((bit
& mask
) == bit
)
695 * For now we only print it out. Eventually we'll want to
696 * reserve it (at least if it's in the 0x1000+ range), but
697 * let's get enough confirmation reports first.
700 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
703 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
706 u32 mask
, size
, base
;
708 pci_read_config_dword(dev
, port
, &devres
);
709 if ((devres
& enable
) != enable
)
711 base
= devres
& 0xffff0000;
712 mask
= (devres
& 0x3f) << 16;
715 unsigned bit
= size
>> 1;
716 if ((bit
& mask
) == bit
)
722 * For now we only print it out. Eventually we'll want to
723 * reserve it, but let's get enough confirmation reports first.
726 pci_info(dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
730 * PIIX4 ACPI: Two IO regions pointed to by longwords at
731 * 0x40 (64 bytes of ACPI registers)
732 * 0x90 (16 bytes of SMB registers)
733 * and a few strange programmable PIIX4 device resources.
735 static void quirk_piix4_acpi(struct pci_dev
*dev
)
739 quirk_io_region(dev
, 0x40, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
740 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
742 /* Device resource A has enables for some of the other ones */
743 pci_read_config_dword(dev
, 0x5c, &res_a
);
745 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
746 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
748 /* Device resource D is just bitfields for static resources */
750 /* Device 12 enabled? */
751 if (res_a
& (1 << 29)) {
752 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
753 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
755 /* Device 13 enabled? */
756 if (res_a
& (1 << 30)) {
757 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
758 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
760 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
761 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
766 #define ICH_PMBASE 0x40
767 #define ICH_ACPI_CNTL 0x44
768 #define ICH4_ACPI_EN 0x10
769 #define ICH6_ACPI_EN 0x80
770 #define ICH4_GPIOBASE 0x58
771 #define ICH4_GPIO_CNTL 0x5c
772 #define ICH4_GPIO_EN 0x10
773 #define ICH6_GPIOBASE 0x48
774 #define ICH6_GPIO_CNTL 0x4c
775 #define ICH6_GPIO_EN 0x10
778 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
779 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
780 * 0x58 (64 bytes of GPIO I/O space)
782 static void quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
787 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
788 * with low legacy (and fixed) ports. We don't know the decoding
789 * priority and can't tell whether the legacy device or the one created
790 * here is really at that address. This happens on boards with broken
793 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
794 if (enable
& ICH4_ACPI_EN
)
795 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
796 "ICH4 ACPI/GPIO/TCO");
798 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
799 if (enable
& ICH4_GPIO_EN
)
800 quirk_io_region(dev
, ICH4_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
804 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
805 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
806 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
807 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
808 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
809 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
812 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
814 static void ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
818 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
819 if (enable
& ICH6_ACPI_EN
)
820 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
821 "ICH6 ACPI/GPIO/TCO");
823 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
824 if (enable
& ICH6_GPIO_EN
)
825 quirk_io_region(dev
, ICH6_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
829 static void ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
830 const char *name
, int dynsize
)
835 pci_read_config_dword(dev
, reg
, &val
);
843 * This is not correct. It is 16, 32 or 64 bytes depending on
844 * register D31:F0:ADh bits 5:4.
846 * But this gets us at least _part_ of it.
855 * Just print it out for now. We should reserve it after more
858 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
861 static void quirk_ich6_lpc(struct pci_dev
*dev
)
863 /* Shared ACPI/GPIO decode with all ICH6+ */
864 ich6_lpc_acpi_gpio(dev
);
866 /* ICH6-specific generic IO decode */
867 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
868 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
873 static void ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
879 pci_read_config_dword(dev
, reg
, &val
);
885 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
887 mask
= (val
>> 16) & 0xfc;
891 * Just print it out for now. We should reserve it after more
894 pci_info(dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
897 /* ICH7-10 has the same common LPC generic IO decode registers */
898 static void quirk_ich7_lpc(struct pci_dev
*dev
)
900 /* We share the common ACPI/GPIO decode with ICH6 */
901 ich6_lpc_acpi_gpio(dev
);
903 /* And have 4 ICH7+ generic decodes */
904 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
905 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
906 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
907 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
924 * VIA ACPI: One IO region pointed to by longword at
925 * 0x48 or 0x20 (256 bytes of ACPI registers)
927 static void quirk_vt82c586_acpi(struct pci_dev
*dev
)
929 if (dev
->revision
& 0x10)
930 quirk_io_region(dev
, 0x48, 256, PCI_BRIDGE_RESOURCES
,
933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
936 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
937 * 0x48 (256 bytes of ACPI registers)
938 * 0x70 (128 bytes of hardware monitoring register)
939 * 0x90 (16 bytes of SMB registers)
941 static void quirk_vt82c686_acpi(struct pci_dev
*dev
)
943 quirk_vt82c586_acpi(dev
);
945 quirk_io_region(dev
, 0x70, 128, PCI_BRIDGE_RESOURCES
+1,
948 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+2, "vt82c686 SMB");
950 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
953 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
954 * 0x88 (128 bytes of power management registers)
955 * 0xd0 (16 bytes of SMB registers)
957 static void quirk_vt8235_acpi(struct pci_dev
*dev
)
959 quirk_io_region(dev
, 0x88, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
960 quirk_io_region(dev
, 0xd0, 16, PCI_BRIDGE_RESOURCES
+1, "vt8235 SMB");
962 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
965 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
966 * back-to-back: Disable fast back-to-back on the secondary bus segment
968 static void quirk_xio2000a(struct pci_dev
*dev
)
970 struct pci_dev
*pdev
;
973 pci_warn(dev
, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
974 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
975 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
976 if (command
& PCI_COMMAND_FAST_BACK
)
977 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
980 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
983 #ifdef CONFIG_X86_IO_APIC
985 #include <asm/io_apic.h>
988 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
989 * devices to the external APIC.
991 * TODO: When we have device-specific interrupt routers, this code will go
994 static void quirk_via_ioapic(struct pci_dev
*dev
)
999 tmp
= 0; /* nothing routed to external APIC */
1001 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
1003 pci_info(dev
, "%sbling VIA external APIC routing\n",
1004 tmp
== 0 ? "Disa" : "Ena");
1006 /* Offset 0x58: External APIC IRQ output control */
1007 pci_write_config_byte(dev
, 0x58, tmp
);
1009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
1010 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
1013 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1014 * This leads to doubled level interrupt rates.
1015 * Set this bit to get rid of cycle wastage.
1016 * Otherwise uncritical.
1018 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
1021 #define BYPASS_APIC_DEASSERT 8
1023 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
1024 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
1025 pci_info(dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
1026 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
1029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
1030 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
1033 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1034 * We check all revs >= B0 (yet not in the pre production!) as the bug
1035 * is currently marked NoFix
1037 * We have multiple reports of hangs with this chipset that went away with
1038 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1039 * of course. However the advice is demonstrably good even if so.
1041 static void quirk_amd_ioapic(struct pci_dev
*dev
)
1043 if (dev
->revision
>= 0x02) {
1044 pci_warn(dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1045 pci_warn(dev
, " : booting with the \"noapic\" option\n");
1048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
1049 #endif /* CONFIG_X86_IO_APIC */
1051 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1053 static void quirk_cavium_sriov_rnm_link(struct pci_dev
*dev
)
1055 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1056 if (dev
->subsystem_device
== 0xa118)
1057 dev
->sriov
->link
= dev
->devfn
;
1059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM
, 0xa018, quirk_cavium_sriov_rnm_link
);
1063 * Some settings of MMRBC can lead to data corruption so block changes.
1064 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1066 static void quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
1068 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
1069 pci_info(dev
, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1071 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
1074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
1077 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1078 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1079 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1080 * of the ACPI SCI interrupt is only done for convenience.
1083 static void quirk_via_acpi(struct pci_dev
*d
)
1087 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1088 pci_read_config_byte(d
, 0x42, &irq
);
1090 if (irq
&& (irq
!= 2))
1093 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
1096 /* VIA bridges which have VLink */
1097 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
1099 static void quirk_via_bridge(struct pci_dev
*dev
)
1101 /* See what bridge we have and find the device ranges */
1102 switch (dev
->device
) {
1103 case PCI_DEVICE_ID_VIA_82C686
:
1105 * The VT82C686 is special; it attaches to PCI and can have
1106 * any device number. All its subdevices are functions of
1107 * that single device.
1109 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
1110 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
1112 case PCI_DEVICE_ID_VIA_8237
:
1113 case PCI_DEVICE_ID_VIA_8237A
:
1114 via_vlink_dev_lo
= 15;
1116 case PCI_DEVICE_ID_VIA_8235
:
1117 via_vlink_dev_lo
= 16;
1119 case PCI_DEVICE_ID_VIA_8231
:
1120 case PCI_DEVICE_ID_VIA_8233_0
:
1121 case PCI_DEVICE_ID_VIA_8233A
:
1122 case PCI_DEVICE_ID_VIA_8233C_0
:
1123 via_vlink_dev_lo
= 17;
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
1128 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
1129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
1130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
1131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
1132 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
1134 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
1137 * quirk_via_vlink - VIA VLink IRQ number update
1140 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1141 * the IRQ line register which usually is not relevant for PCI cards, is
1142 * actually written so that interrupts get sent to the right place.
1144 * We only do this on systems where a VIA south bridge was detected, and
1145 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1147 static void quirk_via_vlink(struct pci_dev
*dev
)
1151 /* Check if we have VLink at all */
1152 if (via_vlink_dev_lo
== -1)
1157 /* Don't quirk interrupts outside the legacy IRQ range */
1158 if (!new_irq
|| new_irq
> 15)
1161 /* Internal device ? */
1162 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
1163 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
1167 * This is an internal VLink device on a PIC interrupt. The BIOS
1168 * ought to have set this but may not have, so we redo it.
1170 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1171 if (new_irq
!= irq
) {
1172 pci_info(dev
, "VIA VLink IRQ fixup, from %d to %d\n",
1174 udelay(15); /* unknown if delay really needed */
1175 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
1178 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
1181 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1182 * of VT82C597 for backward compatibility. We need to switch it off to be
1183 * able to recognize the real type of the chip.
1185 static void quirk_vt82c598_id(struct pci_dev
*dev
)
1187 pci_write_config_byte(dev
, 0xfc, 0);
1188 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
1190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
1193 * CardBus controllers have a legacy base address that enables them to
1194 * respond as i82365 pcmcia controllers. We don't want them to do this
1195 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1196 * driver does not (and should not) handle CardBus.
1198 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
1200 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
1202 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1203 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1204 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
1205 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1208 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1209 * what the designers were smoking but let's not inhale...
1211 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1214 static void quirk_amd_ordering(struct pci_dev
*dev
)
1217 pci_read_config_dword(dev
, 0x4C, &pcic
);
1218 if ((pcic
& 6) != 6) {
1220 pci_warn(dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1221 pci_write_config_dword(dev
, 0x4C, pcic
);
1222 pci_read_config_dword(dev
, 0x84, &pcic
);
1223 pcic
|= (1 << 23); /* Required in this mode */
1224 pci_write_config_dword(dev
, 0x84, pcic
);
1227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1228 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1231 * DreamWorks-provided workaround for Dunord I-3000 problem
1233 * This card decodes and responds to addresses not apparently assigned to
1234 * it. We force a larger allocation to ensure that nothing gets put too
1237 static void quirk_dunord(struct pci_dev
*dev
)
1239 struct resource
*r
= &dev
->resource
[1];
1241 r
->flags
|= IORESOURCE_UNSET
;
1245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
1248 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1249 * decoding (transparent), and does indicate this in the ProgIf.
1250 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1252 static void quirk_transparent_bridge(struct pci_dev
*dev
)
1254 dev
->transparent
= 1;
1256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
1257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1260 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1261 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1262 * found at http://www.national.com/analog for info on what these bits do.
1263 * <christer@weinigel.se>
1265 static void quirk_mediagx_master(struct pci_dev
*dev
)
1269 pci_read_config_byte(dev
, 0x41, ®
);
1272 pci_info(dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1274 pci_write_config_byte(dev
, 0x41, reg
);
1277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1278 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1281 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1282 * in the odd case it is not the results are corruption hence the presence
1285 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1289 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1291 pci_read_config_word(pdev
, 0x40, &config
);
1292 if (config
& (1<<6)) {
1294 pci_write_config_word(pdev
, 0x40, config
);
1295 pci_info(pdev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1299 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1301 static void quirk_amd_ide_mode(struct pci_dev
*pdev
)
1303 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1306 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1308 pci_read_config_byte(pdev
, 0x40, &tmp
);
1309 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1310 pci_write_config_byte(pdev
, 0x9, 1);
1311 pci_write_config_byte(pdev
, 0xa, 6);
1312 pci_write_config_byte(pdev
, 0x40, tmp
);
1314 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1315 pci_info(pdev
, "set SATA to AHCI mode\n");
1318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1319 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1321 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1323 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1325 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1327 /* Serverworks CSB5 IDE does not fully support native mode */
1328 static void quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1331 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1335 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1336 /* PCI layer will sort out resources */
1339 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1341 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1342 static void quirk_ide_samemode(struct pci_dev
*pdev
)
1346 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1348 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1349 pci_info(pdev
, "IDE mode mismatch; forcing legacy mode\n");
1352 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1355 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1357 /* Some ATA devices break if put into D3 */
1358 static void quirk_no_ata_d3(struct pci_dev
*pdev
)
1360 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1362 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1363 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
,
1364 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1365 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
1366 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1367 /* ALi loses some register settings that we cannot then restore */
1368 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
,
1369 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1370 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1371 occur when mode detecting */
1372 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
1373 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1374 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SK_HYNIX
, 0x1527, quirk_no_ata_d3
);
1375 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0xf1a6, quirk_no_ata_d3
);
1378 * This was originally an Alpha-specific thing, but it really fits here.
1379 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1381 static void quirk_eisa_bridge(struct pci_dev
*dev
)
1383 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1388 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1389 * is not activated. The myth is that Asus said that they do not want the
1390 * users to be irritated by just another PCI Device in the Win98 device
1391 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1392 * package 2.7.0 for details)
1394 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1395 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1396 * becomes necessary to do this tweak in two steps -- the chosen trigger
1397 * is either the Host bridge (preferred) or on-board VGA controller.
1399 * Note that we used to unhide the SMBus that way on Toshiba laptops
1400 * (Satellite A40 and Tecra M2) but then found that the thermal management
1401 * was done by SMM code, which could cause unsynchronized concurrent
1402 * accesses to the SMBus registers, with potentially bad effects. Thus you
1403 * should be very careful when adding new entries: if SMM is accessing the
1404 * Intel SMBus, this is a very good reason to leave it hidden.
1406 * Likewise, many recent laptops use ACPI for thermal management. If the
1407 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1408 * natively, and keeping the SMBus hidden is the right thing to do. If you
1409 * are about to add an entry in the table below, please first disassemble
1410 * the DSDT and double-check that there is no code accessing the SMBus.
1412 static int asus_hides_smbus
;
1414 static void asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1416 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1417 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1418 switch (dev
->subsystem_device
) {
1419 case 0x8025: /* P4B-LX */
1420 case 0x8070: /* P4B */
1421 case 0x8088: /* P4B533 */
1422 case 0x1626: /* L3C notebook */
1423 asus_hides_smbus
= 1;
1425 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1426 switch (dev
->subsystem_device
) {
1427 case 0x80b1: /* P4GE-V */
1428 case 0x80b2: /* P4PE */
1429 case 0x8093: /* P4B533-V */
1430 asus_hides_smbus
= 1;
1432 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1433 switch (dev
->subsystem_device
) {
1434 case 0x8030: /* P4T533 */
1435 asus_hides_smbus
= 1;
1437 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1438 switch (dev
->subsystem_device
) {
1439 case 0x8070: /* P4G8X Deluxe */
1440 asus_hides_smbus
= 1;
1442 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1443 switch (dev
->subsystem_device
) {
1444 case 0x80c9: /* PU-DLS */
1445 asus_hides_smbus
= 1;
1447 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1448 switch (dev
->subsystem_device
) {
1449 case 0x1751: /* M2N notebook */
1450 case 0x1821: /* M5N notebook */
1451 case 0x1897: /* A6L notebook */
1452 asus_hides_smbus
= 1;
1454 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1455 switch (dev
->subsystem_device
) {
1456 case 0x184b: /* W1N notebook */
1457 case 0x186a: /* M6Ne notebook */
1458 asus_hides_smbus
= 1;
1460 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1461 switch (dev
->subsystem_device
) {
1462 case 0x80f2: /* P4P800-X */
1463 asus_hides_smbus
= 1;
1465 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1466 switch (dev
->subsystem_device
) {
1467 case 0x1882: /* M6V notebook */
1468 case 0x1977: /* A6VA notebook */
1469 asus_hides_smbus
= 1;
1471 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1472 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1473 switch (dev
->subsystem_device
) {
1474 case 0x088C: /* HP Compaq nc8000 */
1475 case 0x0890: /* HP Compaq nc6000 */
1476 asus_hides_smbus
= 1;
1478 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1479 switch (dev
->subsystem_device
) {
1480 case 0x12bc: /* HP D330L */
1481 case 0x12bd: /* HP D530 */
1482 case 0x006a: /* HP Compaq nx9500 */
1483 asus_hides_smbus
= 1;
1485 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1486 switch (dev
->subsystem_device
) {
1487 case 0x12bf: /* HP xw4100 */
1488 asus_hides_smbus
= 1;
1490 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1491 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1492 switch (dev
->subsystem_device
) {
1493 case 0xC00C: /* Samsung P35 notebook */
1494 asus_hides_smbus
= 1;
1496 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1497 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1498 switch (dev
->subsystem_device
) {
1499 case 0x0058: /* Compaq Evo N620c */
1500 asus_hides_smbus
= 1;
1502 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1503 switch (dev
->subsystem_device
) {
1504 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1505 /* Motherboard doesn't have Host bridge
1506 * subvendor/subdevice IDs, therefore checking
1507 * its on-board VGA controller */
1508 asus_hides_smbus
= 1;
1510 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1511 switch (dev
->subsystem_device
) {
1512 case 0x00b8: /* Compaq Evo D510 CMT */
1513 case 0x00b9: /* Compaq Evo D510 SFF */
1514 case 0x00ba: /* Compaq Evo D510 USDT */
1515 /* Motherboard doesn't have Host bridge
1516 * subvendor/subdevice IDs and on-board VGA
1517 * controller is disabled if an AGP card is
1518 * inserted, therefore checking USB UHCI
1520 asus_hides_smbus
= 1;
1522 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1523 switch (dev
->subsystem_device
) {
1524 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1525 /* Motherboard doesn't have host bridge
1526 * subvendor/subdevice IDs, therefore checking
1527 * its on-board VGA controller */
1528 asus_hides_smbus
= 1;
1532 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1535 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1540 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1541 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1547 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1551 if (likely(!asus_hides_smbus
))
1554 pci_read_config_word(dev
, 0xF2, &val
);
1556 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1557 pci_read_config_word(dev
, 0xF2, &val
);
1559 pci_info(dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1562 pci_info(dev
, "Enabled i801 SMBus device\n");
1565 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1566 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1567 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1572 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1573 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1574 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1575 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1576 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1577 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1578 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1580 /* It appears we just have one such device. If not, we have a warning */
1581 static void __iomem
*asus_rcba_base
;
1582 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1586 if (likely(!asus_hides_smbus
))
1588 WARN_ON(asus_rcba_base
);
1590 pci_read_config_dword(dev
, 0xF0, &rcba
);
1591 /* use bits 31:14, 16 kB aligned */
1592 asus_rcba_base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000);
1593 if (asus_rcba_base
== NULL
)
1597 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1601 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1604 /* read the Function Disable register, dword mode only */
1605 val
= readl(asus_rcba_base
+ 0x3418);
1607 /* enable the SMBus device */
1608 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418);
1611 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1613 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1616 iounmap(asus_rcba_base
);
1617 asus_rcba_base
= NULL
;
1618 pci_info(dev
, "Enabled ICH6/i801 SMBus device\n");
1621 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1623 asus_hides_smbus_lpc_ich6_suspend(dev
);
1624 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1625 asus_hides_smbus_lpc_ich6_resume(dev
);
1627 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1628 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1629 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1630 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1632 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1633 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1636 pci_read_config_byte(dev
, 0x77, &val
);
1638 pci_info(dev
, "Enabling SiS 96x SMBus\n");
1639 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1646 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1647 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1648 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1649 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1652 * ... This is further complicated by the fact that some SiS96x south
1653 * bridges pretend to be 85C503/5513 instead. In that case see if we
1654 * spotted a compatible north bridge to make sure.
1655 * (pci_find_device() doesn't work yet)
1657 * We can also enable the sis96x bit in the discovery register..
1659 #define SIS_DETECT_REGISTER 0x40
1661 static void quirk_sis_503(struct pci_dev
*dev
)
1666 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1667 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1668 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1669 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1670 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1675 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1676 * it has already been processed. (Depends on link order, which is
1677 * apparently not guaranteed)
1679 dev
->device
= devid
;
1680 quirk_sis_96x_smbus(dev
);
1682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1683 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1686 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1687 * and MC97 modem controller are disabled when a second PCI soundcard is
1688 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1691 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1694 int asus_hides_ac97
= 0;
1696 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1697 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1698 asus_hides_ac97
= 1;
1701 if (!asus_hides_ac97
)
1704 pci_read_config_byte(dev
, 0x50, &val
);
1706 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1707 pci_read_config_byte(dev
, 0x50, &val
);
1709 pci_info(dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1712 pci_info(dev
, "Enabled onboard AC97/MC97 devices\n");
1715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1716 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1718 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1721 * If we are using libata we can drive this chip properly but must do this
1722 * early on to make the additional device appear during the PCI scanning.
1724 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1726 u32 conf1
, conf5
, class;
1729 /* Only poke fn 0 */
1730 if (PCI_FUNC(pdev
->devfn
))
1733 pci_read_config_dword(pdev
, 0x40, &conf1
);
1734 pci_read_config_dword(pdev
, 0x80, &conf5
);
1736 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1737 conf5
&= ~(1 << 24); /* Clear bit 24 */
1739 switch (pdev
->device
) {
1740 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1741 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1742 case PCI_DEVICE_ID_JMICRON_JMB364
: /* SATA dual ports */
1743 /* The controller should be in single function ahci mode */
1744 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1747 case PCI_DEVICE_ID_JMICRON_JMB365
:
1748 case PCI_DEVICE_ID_JMICRON_JMB366
:
1749 /* Redirect IDE second PATA port to the right spot */
1752 case PCI_DEVICE_ID_JMICRON_JMB361
:
1753 case PCI_DEVICE_ID_JMICRON_JMB363
:
1754 case PCI_DEVICE_ID_JMICRON_JMB369
:
1755 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1756 /* Set the class codes correctly and then direct IDE 0 */
1757 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1760 case PCI_DEVICE_ID_JMICRON_JMB368
:
1761 /* The controller should be in single function IDE mode */
1762 conf1
|= 0x00C00000; /* Set 22, 23 */
1766 pci_write_config_dword(pdev
, 0x40, conf1
);
1767 pci_write_config_dword(pdev
, 0x80, conf5
);
1769 /* Update pdev accordingly */
1770 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1771 pdev
->hdr_type
= hdr
& 0x7f;
1772 pdev
->multifunction
= !!(hdr
& 0x80);
1774 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1775 pdev
->class = class >> 8;
1777 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1778 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1779 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1780 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1781 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1782 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1783 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1784 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1785 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1786 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1787 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1788 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1789 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1790 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1791 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1792 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1793 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1794 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1798 static void quirk_jmicron_async_suspend(struct pci_dev
*dev
)
1800 if (dev
->multifunction
) {
1801 device_disable_async_suspend(&dev
->dev
);
1802 pci_info(dev
, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1805 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_IDE
, 8, quirk_jmicron_async_suspend
);
1806 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_SATA_AHCI
, 0, quirk_jmicron_async_suspend
);
1807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x2362, quirk_jmicron_async_suspend
);
1808 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x236f, quirk_jmicron_async_suspend
);
1810 #ifdef CONFIG_X86_IO_APIC
1811 static void quirk_alder_ioapic(struct pci_dev
*pdev
)
1815 if ((pdev
->class >> 8) != 0xff00)
1819 * The first BAR is the location of the IO-APIC... we must
1820 * not touch this (and it's already covered by the fixmap), so
1821 * forcibly insert it into the resource tree.
1823 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1824 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1827 * The next five BARs all seem to be rubbish, so just clean
1830 for (i
= 1; i
< 6; i
++)
1831 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1836 static void quirk_pcie_mch(struct pci_dev
*pdev
)
1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1844 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI
, 0x1610, PCI_CLASS_BRIDGE_PCI
, 8, quirk_pcie_mch
);
1847 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1848 * together on certain PXH-based systems.
1850 static void quirk_pcie_pxh(struct pci_dev
*dev
)
1853 pci_warn(dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1855 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1858 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1862 * Some Intel PCI Express chipsets have trouble with downstream device
1865 static void quirk_intel_pcie_pm(struct pci_dev
*dev
)
1867 pci_pm_d3_delay
= 120;
1870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1879 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1881 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1882 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1883 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1887 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1890 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1892 static void quirk_radeon_pm(struct pci_dev
*dev
)
1894 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
&&
1895 dev
->subsystem_device
== 0x00e2) {
1896 if (dev
->d3_delay
< 20) {
1898 pci_info(dev
, "extending delay after power-on from D3 to %d msec\n",
1903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6741, quirk_radeon_pm
);
1905 #ifdef CONFIG_X86_IO_APIC
1906 static int dmi_disable_ioapicreroute(const struct dmi_system_id
*d
)
1908 noioapicreroute
= 1;
1909 pr_info("%s detected: disable boot interrupt reroute\n", d
->ident
);
1914 static const struct dmi_system_id boot_interrupt_dmi_table
[] = {
1916 * Systems to exclude from boot interrupt reroute quirks
1919 .callback
= dmi_disable_ioapicreroute
,
1920 .ident
= "ASUSTek Computer INC. M2N-LR",
1922 DMI_MATCH(DMI_SYS_VENDOR
, "ASUSTek Computer INC."),
1923 DMI_MATCH(DMI_PRODUCT_NAME
, "M2N-LR"),
1930 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1931 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1932 * that a PCI device's interrupt handler is installed on the boot interrupt
1935 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1937 dmi_check_system(boot_interrupt_dmi_table
);
1938 if (noioapicquirk
|| noioapicreroute
)
1941 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1942 pci_info(dev
, "rerouting interrupts for [%04x:%04x]\n",
1943 dev
->vendor
, dev
->device
);
1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1952 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1953 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1954 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1955 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1956 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1957 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1958 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1959 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1960 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1963 * On some chipsets we can disable the generation of legacy INTx boot
1968 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1969 * 300641-004US, section 5.7.3.
1971 #define INTEL_6300_IOAPIC_ABAR 0x40
1972 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1974 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
1976 u16 pci_config_word
;
1981 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, &pci_config_word
);
1982 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
1983 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, pci_config_word
);
1985 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1986 dev
->vendor
, dev
->device
);
1988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1989 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1991 /* Disable boot interrupts on HT-1000 */
1992 #define BC_HT1000_FEATURE_REG 0x64
1993 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1994 #define BC_HT1000_MAP_IDX 0xC00
1995 #define BC_HT1000_MAP_DATA 0xC01
1997 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
1999 u32 pci_config_dword
;
2005 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
2006 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
2007 BC_HT1000_PIC_REGS_ENABLE
);
2009 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
2010 outb(irq
, BC_HT1000_MAP_IDX
);
2011 outb(0x00, BC_HT1000_MAP_DATA
);
2014 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
2016 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2017 dev
->vendor
, dev
->device
);
2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
2020 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
2022 /* Disable boot interrupts on AMD and ATI chipsets */
2025 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2026 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2027 * (due to an erratum).
2029 #define AMD_813X_MISC 0x40
2030 #define AMD_813X_NOIOAMODE (1<<0)
2031 #define AMD_813X_REV_B1 0x12
2032 #define AMD_813X_REV_B2 0x13
2034 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
2036 u32 pci_config_dword
;
2040 if ((dev
->revision
== AMD_813X_REV_B1
) ||
2041 (dev
->revision
== AMD_813X_REV_B2
))
2044 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
2045 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
2046 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
2048 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2049 dev
->vendor
, dev
->device
);
2051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2052 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2054 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2056 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2058 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
2060 u16 pci_config_word
;
2065 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
2066 if (!pci_config_word
) {
2067 pci_info(dev
, "boot interrupts on device [%04x:%04x] already disabled\n",
2068 dev
->vendor
, dev
->device
);
2071 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
2072 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2073 dev
->vendor
, dev
->device
);
2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2076 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2077 #endif /* CONFIG_X86_IO_APIC */
2080 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2081 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2082 * Re-allocate the region if needed...
2084 static void quirk_tc86c001_ide(struct pci_dev
*dev
)
2086 struct resource
*r
= &dev
->resource
[0];
2088 if (r
->start
& 0x8) {
2089 r
->flags
|= IORESOURCE_UNSET
;
2094 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
2095 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
2096 quirk_tc86c001_ide
);
2099 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2100 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2101 * being read correctly if bit 7 of the base address is set.
2102 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2103 * Re-allocate the regions to a 256-byte boundary if necessary.
2105 static void quirk_plx_pci9050(struct pci_dev
*dev
)
2109 /* Fixed in revision 2 (PCI 9052). */
2110 if (dev
->revision
>= 2)
2112 for (bar
= 0; bar
<= 1; bar
++)
2113 if (pci_resource_len(dev
, bar
) == 0x80 &&
2114 (pci_resource_start(dev
, bar
) & 0x80)) {
2115 struct resource
*r
= &dev
->resource
[bar
];
2116 pci_info(dev
, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2118 r
->flags
|= IORESOURCE_UNSET
;
2123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2126 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2127 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2128 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2129 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2131 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2134 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050
);
2135 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050
);
2137 static void quirk_netmos(struct pci_dev
*dev
)
2139 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
2140 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
2143 * These Netmos parts are multiport serial devices with optional
2144 * parallel ports. Even when parallel ports are present, they
2145 * are identified as class SERIAL, which means the serial driver
2146 * will claim them. To prevent this, mark them as class OTHER.
2147 * These combo devices should be claimed by parport_serial.
2149 * The subdevice ID is of the form 0x00PS, where <P> is the number
2150 * of parallel ports and <S> is the number of serial ports.
2152 switch (dev
->device
) {
2153 case PCI_DEVICE_ID_NETMOS_9835
:
2154 /* Well, this rule doesn't hold for the following 9835 device */
2155 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
2156 dev
->subsystem_device
== 0x0299)
2158 /* else, fall through */
2159 case PCI_DEVICE_ID_NETMOS_9735
:
2160 case PCI_DEVICE_ID_NETMOS_9745
:
2161 case PCI_DEVICE_ID_NETMOS_9845
:
2162 case PCI_DEVICE_ID_NETMOS_9855
:
2164 pci_info(dev
, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2165 dev
->device
, num_parallel
, num_serial
);
2166 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
2167 (dev
->class & 0xff);
2171 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
,
2172 PCI_CLASS_COMMUNICATION_SERIAL
, 8, quirk_netmos
);
2174 static void quirk_e100_interrupt(struct pci_dev
*dev
)
2180 switch (dev
->device
) {
2181 /* PCI IDs taken from drivers/net/e100.c */
2183 case 0x1030 ... 0x1034:
2184 case 0x1038 ... 0x103E:
2185 case 0x1050 ... 0x1057:
2187 case 0x1064 ... 0x106B:
2188 case 0x1091 ... 0x1095:
2201 * Some firmware hands off the e100 with interrupts enabled,
2202 * which can cause a flood of interrupts if packets are
2203 * received before the driver attaches to the device. So
2204 * disable all e100 interrupts here. The driver will
2205 * re-enable them when it's ready.
2207 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
2209 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
2213 * Check that the device is in the D0 power state. If it's not,
2214 * there is no point to look any further.
2217 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2218 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
2222 /* Convert from PCI bus to resource space. */
2223 csr
= ioremap(pci_resource_start(dev
, 0), 8);
2225 pci_warn(dev
, "Can't map e100 registers\n");
2229 cmd_hi
= readb(csr
+ 3);
2231 pci_warn(dev
, "Firmware left e100 interrupts enabled; disabling\n");
2237 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
2238 PCI_CLASS_NETWORK_ETHERNET
, 8, quirk_e100_interrupt
);
2241 * The 82575 and 82598 may experience data corruption issues when transitioning
2242 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2244 static void quirk_disable_aspm_l0s(struct pci_dev
*dev
)
2246 pci_info(dev
, "Disabling L0s\n");
2247 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
2249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
2250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
2251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
2253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
2254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
2255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
2256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
2257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
2258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
2259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
2260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
2261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
2262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
2265 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2266 * Link bit cleared after starting the link retrain process to allow this
2267 * process to finish.
2269 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2270 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2272 static void quirk_enable_clear_retrain_link(struct pci_dev
*dev
)
2274 dev
->clear_retrain_link
= 1;
2275 pci_info(dev
, "Enable PCIe Retrain Link quirk\n");
2277 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe110, quirk_enable_clear_retrain_link
);
2278 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe111, quirk_enable_clear_retrain_link
);
2279 DECLARE_PCI_FIXUP_HEADER(0x12d8, 0xe130, quirk_enable_clear_retrain_link
);
2281 static void fixup_rev1_53c810(struct pci_dev
*dev
)
2283 u32
class = dev
->class;
2286 * rev 1 ncr53c810 chips don't set the class at all which means
2287 * they don't get their resources remapped. Fix that here.
2292 dev
->class = PCI_CLASS_STORAGE_SCSI
<< 8;
2293 pci_info(dev
, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
2298 /* Enable 1k I/O space granularity on the Intel P64H2 */
2299 static void quirk_p64h2_1k_io(struct pci_dev
*dev
)
2303 pci_read_config_word(dev
, 0x40, &en1k
);
2306 pci_info(dev
, "Enable I/O Space to 1KB granularity\n");
2307 dev
->io_window_1k
= 1;
2310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
2313 * Under some circumstances, AER is not linked with extended capabilities.
2314 * Force it to be linked by setting the corresponding control bit in the
2317 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
2321 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
2323 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
2324 pci_info(dev
, "Linking AER extended capability\n");
2328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2329 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2330 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2331 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2333 static void quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2336 * Disable PCI Bus Parking and PCI Master read caching on CX700
2337 * which causes unspecified timing errors with a VT6212L on the PCI
2338 * bus leading to USB2.0 packet loss.
2340 * This quirk is only enabled if a second (on the external PCI bus)
2341 * VT6212L is found -- the CX700 core itself also contains a USB
2342 * host controller with the same PCI ID as the VT6212L.
2345 /* Count VT6212L instances */
2346 struct pci_dev
*p
= pci_get_device(PCI_VENDOR_ID_VIA
,
2347 PCI_DEVICE_ID_VIA_8235_USB_2
, NULL
);
2351 * p should contain the first (internal) VT6212L -- see if we have
2352 * an external one by searching again.
2354 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235_USB_2
, p
);
2359 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2361 /* Turn off PCI Bus Parking */
2362 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2364 pci_info(dev
, "Disabling VIA CX700 PCI parking\n");
2368 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2370 /* Turn off PCI Master read caching */
2371 pci_write_config_byte(dev
, 0x72, 0x0);
2373 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2374 pci_write_config_byte(dev
, 0x75, 0x1);
2376 /* Disable "Read FIFO Timer" */
2377 pci_write_config_byte(dev
, 0x77, 0x0);
2379 pci_info(dev
, "Disabling VIA CX700 PCI caching\n");
2383 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2385 static void quirk_brcm_5719_limit_mrrs(struct pci_dev
*dev
)
2389 pci_read_config_dword(dev
, 0xf4, &rev
);
2391 /* Only CAP the MRRS if the device is a 5719 A0 */
2392 if (rev
== 0x05719000) {
2393 int readrq
= pcie_get_readrq(dev
);
2395 pcie_set_readrq(dev
, 2048);
2398 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM
,
2399 PCI_DEVICE_ID_TIGON3_5719
,
2400 quirk_brcm_5719_limit_mrrs
);
2402 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2403 static void quirk_paxc_bridge(struct pci_dev
*pdev
)
2406 * The PCI config space is shared with the PAXC root port and the first
2407 * Ethernet device. So, we need to workaround this by telling the PCI
2408 * code that the bridge is not an Ethernet device.
2410 if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
2411 pdev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
2414 * MPSS is not being set properly (as it is currently 0). This is
2415 * because that area of the PCI config space is hard coded to zero, and
2416 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2417 * so that the MPS can be set to the real max value.
2419 pdev
->pcie_mpss
= 2;
2421 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0x16cd, quirk_paxc_bridge
);
2422 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0x16f0, quirk_paxc_bridge
);
2423 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0xd750, quirk_paxc_bridge
);
2424 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0xd802, quirk_paxc_bridge
);
2425 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0xd804, quirk_paxc_bridge
);
2429 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2430 * hide device 6 which configures the overflow device access containing the
2431 * DRBs - this is where we expose device 6.
2432 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2434 static void quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2438 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2439 pci_info(dev
, "Enabling MCH 'Overflow' Device\n");
2440 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2443 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2444 quirk_unhide_mch_dev6
);
2445 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2446 quirk_unhide_mch_dev6
);
2448 #ifdef CONFIG_PCI_MSI
2450 * Some chipsets do not support MSI. We cannot easily rely on setting
2451 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2452 * other buses controlled by the chipset even if Linux is not aware of it.
2453 * Instead of setting the flag on all buses in the machine, simply disable
2456 static void quirk_disable_all_msi(struct pci_dev
*dev
)
2459 pci_warn(dev
, "MSI quirk detected; MSI disabled\n");
2461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8380_0
, quirk_disable_all_msi
);
2468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, 0x0761, quirk_disable_all_msi
);
2470 /* Disable MSI on chipsets that are known to not support it */
2471 static void quirk_disable_msi(struct pci_dev
*dev
)
2473 if (dev
->subordinate
) {
2474 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2475 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2478 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2479 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2480 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2483 * The APC bridge device in AMD 780 family northbridges has some random
2484 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2485 * we use the possible vendor/device IDs of the host bridge for the
2486 * declared quirk, and search for the APC bridge by slot number.
2488 static void quirk_amd_780_apc_msi(struct pci_dev
*host_bridge
)
2490 struct pci_dev
*apc_bridge
;
2492 apc_bridge
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(1, 0));
2494 if (apc_bridge
->device
== 0x9602)
2495 quirk_disable_msi(apc_bridge
);
2496 pci_dev_put(apc_bridge
);
2499 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9600, quirk_amd_780_apc_msi
);
2500 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9601, quirk_amd_780_apc_msi
);
2503 * Go through the list of HyperTransport capabilities and return 1 if a HT
2504 * MSI capability is found and enabled.
2506 static int msi_ht_cap_enabled(struct pci_dev
*dev
)
2508 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2510 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2511 while (pos
&& ttl
--) {
2514 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2516 pci_info(dev
, "Found %s HT MSI Mapping\n",
2517 flags
& HT_MSI_FLAGS_ENABLE
?
2518 "enabled" : "disabled");
2519 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2522 pos
= pci_find_next_ht_capability(dev
, pos
,
2523 HT_CAPTYPE_MSI_MAPPING
);
2528 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2529 static void quirk_msi_ht_cap(struct pci_dev
*dev
)
2531 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
2532 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2533 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2540 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2541 * if the MSI capability is set in any of these mappings.
2543 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2545 struct pci_dev
*pdev
;
2547 if (!dev
->subordinate
)
2551 * Check HT MSI cap on this chipset and the root one. A single one
2552 * having MSI is enough to be sure that MSI is supported.
2554 pdev
= pci_get_slot(dev
->bus
, 0);
2557 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
2558 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2559 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2564 quirk_nvidia_ck804_msi_ht_cap
);
2566 /* Force enable MSI mapping capability on HT bridges */
2567 static void ht_enable_msi_mapping(struct pci_dev
*dev
)
2569 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2571 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2572 while (pos
&& ttl
--) {
2575 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2577 pci_info(dev
, "Enabling HT MSI Mapping\n");
2579 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2580 flags
| HT_MSI_FLAGS_ENABLE
);
2582 pos
= pci_find_next_ht_capability(dev
, pos
,
2583 HT_CAPTYPE_MSI_MAPPING
);
2586 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2587 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2588 ht_enable_msi_mapping
);
2589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2590 ht_enable_msi_mapping
);
2593 * The P5N32-SLI motherboards from Asus have a problem with MSI
2594 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2595 * also affects other devices. As for now, turn off MSI for this device.
2597 static void nvenet_msi_disable(struct pci_dev
*dev
)
2599 const char *board_name
= dmi_get_system_info(DMI_BOARD_NAME
);
2602 (strstr(board_name
, "P5N32-SLI PREMIUM") ||
2603 strstr(board_name
, "P5N32-E SLI"))) {
2604 pci_info(dev
, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2609 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2610 nvenet_msi_disable
);
2613 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2614 * config register. This register controls the routing of legacy
2615 * interrupts from devices that route through the MCP55. If this register
2616 * is misprogrammed, interrupts are only sent to the BSP, unlike
2617 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2618 * having this register set properly prevents kdump from booting up
2619 * properly, so let's make sure that we have it set correctly.
2620 * Note that this is an undocumented register.
2622 static void nvbridge_check_legacy_irq_routing(struct pci_dev
*dev
)
2626 if (!pci_find_capability(dev
, PCI_CAP_ID_HT
))
2629 pci_read_config_dword(dev
, 0x74, &cfg
);
2631 if (cfg
& ((1 << 2) | (1 << 15))) {
2632 pr_info("Rewriting IRQ routing register on MCP55\n");
2633 cfg
&= ~((1 << 2) | (1 << 15));
2634 pci_write_config_dword(dev
, 0x74, cfg
);
2637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2638 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
,
2639 nvbridge_check_legacy_irq_routing
);
2640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2641 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
,
2642 nvbridge_check_legacy_irq_routing
);
2644 static int ht_check_msi_mapping(struct pci_dev
*dev
)
2646 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2649 /* Check if there is HT MSI cap or enabled on this device */
2650 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2651 while (pos
&& ttl
--) {
2656 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2658 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2665 pos
= pci_find_next_ht_capability(dev
, pos
,
2666 HT_CAPTYPE_MSI_MAPPING
);
2672 static int host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2674 struct pci_dev
*dev
;
2679 dev_no
= host_bridge
->devfn
>> 3;
2680 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2681 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2685 /* found next host bridge? */
2686 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2692 if (ht_check_msi_mapping(dev
)) {
2703 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2704 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2706 static int is_end_of_ht_chain(struct pci_dev
*dev
)
2712 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2717 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2719 ctrl_off
= ((flags
>> 10) & 1) ?
2720 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2721 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2723 if (ctrl
& (1 << 6))
2730 static void nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2732 struct pci_dev
*host_bridge
;
2737 dev_no
= dev
->devfn
>> 3;
2738 for (i
= dev_no
; i
>= 0; i
--) {
2739 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2743 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2748 pci_dev_put(host_bridge
);
2754 /* don't enable end_device/host_bridge with leaf directly here */
2755 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2756 host_bridge_with_leaf(host_bridge
))
2759 /* root did that ! */
2760 if (msi_ht_cap_enabled(host_bridge
))
2763 ht_enable_msi_mapping(dev
);
2766 pci_dev_put(host_bridge
);
2769 static void ht_disable_msi_mapping(struct pci_dev
*dev
)
2771 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2773 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2774 while (pos
&& ttl
--) {
2777 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2779 pci_info(dev
, "Disabling HT MSI Mapping\n");
2781 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2782 flags
& ~HT_MSI_FLAGS_ENABLE
);
2784 pos
= pci_find_next_ht_capability(dev
, pos
,
2785 HT_CAPTYPE_MSI_MAPPING
);
2789 static void __nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2791 struct pci_dev
*host_bridge
;
2795 if (!pci_msi_enabled())
2798 /* check if there is HT MSI cap or enabled on this device */
2799 found
= ht_check_msi_mapping(dev
);
2806 * HT MSI mapping should be disabled on devices that are below
2807 * a non-Hypertransport host bridge. Locate the host bridge...
2809 host_bridge
= pci_get_domain_bus_and_slot(pci_domain_nr(dev
->bus
), 0,
2811 if (host_bridge
== NULL
) {
2812 pci_warn(dev
, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2816 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2818 /* Host bridge is to HT */
2820 /* it is not enabled, try to enable it */
2822 ht_enable_msi_mapping(dev
);
2824 nv_ht_enable_msi_mapping(dev
);
2829 /* HT MSI is not enabled */
2833 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2834 ht_disable_msi_mapping(dev
);
2837 pci_dev_put(host_bridge
);
2840 static void nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2842 return __nv_msi_ht_cap_quirk(dev
, 1);
2844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2845 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2847 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2849 return __nv_msi_ht_cap_quirk(dev
, 0);
2851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2852 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2854 static void quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2856 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2859 static void quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2864 * SB700 MSI issue will be fixed at HW level from revision A21;
2865 * we need check PCI REVISION ID of SMBus controller to get SB700
2868 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2873 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2874 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2878 static void quirk_msi_intx_disable_qca_bug(struct pci_dev
*dev
)
2880 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2881 if (dev
->revision
< 0x18) {
2882 pci_info(dev
, "set MSI_INTX_DISABLE_BUG flag\n");
2883 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2886 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2887 PCI_DEVICE_ID_TIGON3_5780
,
2888 quirk_msi_intx_disable_bug
);
2889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2890 PCI_DEVICE_ID_TIGON3_5780S
,
2891 quirk_msi_intx_disable_bug
);
2892 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2893 PCI_DEVICE_ID_TIGON3_5714
,
2894 quirk_msi_intx_disable_bug
);
2895 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2896 PCI_DEVICE_ID_TIGON3_5714S
,
2897 quirk_msi_intx_disable_bug
);
2898 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2899 PCI_DEVICE_ID_TIGON3_5715
,
2900 quirk_msi_intx_disable_bug
);
2901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2902 PCI_DEVICE_ID_TIGON3_5715S
,
2903 quirk_msi_intx_disable_bug
);
2905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
2906 quirk_msi_intx_disable_ati_bug
);
2907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
2908 quirk_msi_intx_disable_ati_bug
);
2909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
2910 quirk_msi_intx_disable_ati_bug
);
2911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
2912 quirk_msi_intx_disable_ati_bug
);
2913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
2914 quirk_msi_intx_disable_ati_bug
);
2916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
2917 quirk_msi_intx_disable_bug
);
2918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
2919 quirk_msi_intx_disable_bug
);
2920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
2921 quirk_msi_intx_disable_bug
);
2923 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1062,
2924 quirk_msi_intx_disable_bug
);
2925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1063,
2926 quirk_msi_intx_disable_bug
);
2927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2060,
2928 quirk_msi_intx_disable_bug
);
2929 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2062,
2930 quirk_msi_intx_disable_bug
);
2931 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1073,
2932 quirk_msi_intx_disable_bug
);
2933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1083,
2934 quirk_msi_intx_disable_bug
);
2935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1090,
2936 quirk_msi_intx_disable_qca_bug
);
2937 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1091,
2938 quirk_msi_intx_disable_qca_bug
);
2939 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a0,
2940 quirk_msi_intx_disable_qca_bug
);
2941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a1,
2942 quirk_msi_intx_disable_qca_bug
);
2943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0xe091,
2944 quirk_msi_intx_disable_qca_bug
);
2945 #endif /* CONFIG_PCI_MSI */
2948 * Allow manual resource allocation for PCI hotplug bridges via
2949 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2950 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2951 * allocate resources when hotplug device is inserted and PCI bus is
2954 static void quirk_hotplug_bridge(struct pci_dev
*dev
)
2956 dev
->is_hotplug_bridge
= 1;
2958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0020, quirk_hotplug_bridge
);
2961 * This is a quirk for the Ricoh MMC controller found as a part of some
2962 * multifunction chips.
2964 * This is very similar and based on the ricoh_mmc driver written by
2965 * Philip Langdale. Thank you for these magic sequences.
2967 * These chips implement the four main memory card controllers (SD, MMC,
2968 * MS, xD) and one or both of CardBus or FireWire.
2970 * It happens that they implement SD and MMC support as separate
2971 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
2972 * cards but the chip detects MMC cards in hardware and directs them to the
2973 * MMC controller - so the SDHCI driver never sees them.
2975 * To get around this, we must disable the useless MMC controller. At that
2976 * point, the SDHCI controller will start seeing them. It seems to be the
2977 * case that the relevant PCI registers to deactivate the MMC controller
2978 * live on PCI function 0, which might be the CardBus controller or the
2979 * FireWire controller, depending on the particular chip in question
2981 * This has to be done early, because as soon as we disable the MMC controller
2982 * other PCI functions shift up one level, e.g. function #2 becomes function
2983 * #1, and this will confuse the PCI core.
2985 #ifdef CONFIG_MMC_RICOH_MMC
2986 static void ricoh_mmc_fixup_rl5c476(struct pci_dev
*dev
)
2993 * Disable via CardBus interface
2995 * This must be done via function #0
2997 if (PCI_FUNC(dev
->devfn
))
3000 pci_read_config_byte(dev
, 0xB7, &disable
);
3004 pci_read_config_byte(dev
, 0x8E, &write_enable
);
3005 pci_write_config_byte(dev
, 0x8E, 0xAA);
3006 pci_read_config_byte(dev
, 0x8D, &write_target
);
3007 pci_write_config_byte(dev
, 0x8D, 0xB7);
3008 pci_write_config_byte(dev
, 0xB7, disable
| 0x02);
3009 pci_write_config_byte(dev
, 0x8E, write_enable
);
3010 pci_write_config_byte(dev
, 0x8D, write_target
);
3012 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3013 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3015 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
3016 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
3018 static void ricoh_mmc_fixup_r5c832(struct pci_dev
*dev
)
3024 * Disable via FireWire interface
3026 * This must be done via function #0
3028 if (PCI_FUNC(dev
->devfn
))
3031 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3032 * certain types of SD/MMC cards. Lowering the SD base clock
3033 * frequency from 200Mhz to 50Mhz fixes this issue.
3035 * 0x150 - SD2.0 mode enable for changing base clock
3036 * frequency to 50Mhz
3037 * 0xe1 - Base clock frequency
3038 * 0x32 - 50Mhz new clock frequency
3039 * 0xf9 - Key register for 0x150
3040 * 0xfc - key register for 0xe1
3042 if (dev
->device
== PCI_DEVICE_ID_RICOH_R5CE822
||
3043 dev
->device
== PCI_DEVICE_ID_RICOH_R5CE823
) {
3044 pci_write_config_byte(dev
, 0xf9, 0xfc);
3045 pci_write_config_byte(dev
, 0x150, 0x10);
3046 pci_write_config_byte(dev
, 0xf9, 0x00);
3047 pci_write_config_byte(dev
, 0xfc, 0x01);
3048 pci_write_config_byte(dev
, 0xe1, 0x32);
3049 pci_write_config_byte(dev
, 0xfc, 0x00);
3051 pci_notice(dev
, "MMC controller base frequency changed to 50Mhz.\n");
3054 pci_read_config_byte(dev
, 0xCB, &disable
);
3059 pci_read_config_byte(dev
, 0xCA, &write_enable
);
3060 pci_write_config_byte(dev
, 0xCA, 0x57);
3061 pci_write_config_byte(dev
, 0xCB, disable
| 0x02);
3062 pci_write_config_byte(dev
, 0xCA, write_enable
);
3064 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3065 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3068 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3069 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3070 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3071 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3072 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3073 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3074 #endif /*CONFIG_MMC_RICOH_MMC*/
3076 #ifdef CONFIG_DMAR_TABLE
3077 #define VTUNCERRMSK_REG 0x1ac
3078 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3080 * This is a quirk for masking VT-d spec-defined errors to platform error
3081 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3082 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3083 * on the RAS config settings of the platform) when a VT-d fault happens.
3084 * The resulting SMI caused the system to hang.
3086 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3087 * need to report the same error through other channels.
3089 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
3093 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
3094 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
3096 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
3097 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
3100 static void fixup_ti816x_class(struct pci_dev
*dev
)
3102 u32
class = dev
->class;
3104 /* TI 816x devices do not have class code set when in PCIe boot mode */
3105 dev
->class = PCI_CLASS_MULTIMEDIA_VIDEO
<< 8;
3106 pci_info(dev
, "PCI class overridden (%#08x -> %#08x)\n",
3109 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI
, 0xb800,
3110 PCI_CLASS_NOT_DEFINED
, 8, fixup_ti816x_class
);
3113 * Some PCIe devices do not work reliably with the claimed maximum
3114 * payload size supported.
3116 static void fixup_mpss_256(struct pci_dev
*dev
)
3118 dev
->pcie_mpss
= 1; /* 256 bytes */
3120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3121 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0
, fixup_mpss_256
);
3122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3123 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
, fixup_mpss_256
);
3124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3125 PCI_DEVICE_ID_SOLARFLARE_SFC4000B
, fixup_mpss_256
);
3128 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3129 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3130 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3131 * until all of the devices are discovered and buses walked, read completion
3132 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3133 * it is possible to hotplug a device with MPS of 256B.
3135 static void quirk_intel_mc_errata(struct pci_dev
*dev
)
3140 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
3141 pcie_bus_config
== PCIE_BUS_DEFAULT
)
3145 * Intel erratum specifies bits to change but does not say what
3146 * they are. Keeping them magical until such time as the registers
3147 * and values can be explained.
3149 err
= pci_read_config_word(dev
, 0x48, &rcc
);
3151 pci_err(dev
, "Error attempting to read the read completion coalescing register\n");
3155 if (!(rcc
& (1 << 10)))
3160 err
= pci_write_config_word(dev
, 0x48, rcc
);
3162 pci_err(dev
, "Error attempting to write the read completion coalescing register\n");
3166 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3168 /* Intel 5000 series memory controllers and ports 2-7 */
3169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25c0, quirk_intel_mc_errata
);
3170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d0, quirk_intel_mc_errata
);
3171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d4, quirk_intel_mc_errata
);
3172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d8, quirk_intel_mc_errata
);
3173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_mc_errata
);
3174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_mc_errata
);
3175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_mc_errata
);
3176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_mc_errata
);
3177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_mc_errata
);
3178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_mc_errata
);
3179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_mc_errata
);
3180 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_mc_errata
);
3181 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_mc_errata
);
3182 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_mc_errata
);
3183 /* Intel 5100 series memory controllers and ports 2-7 */
3184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65c0, quirk_intel_mc_errata
);
3185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e2, quirk_intel_mc_errata
);
3186 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e3, quirk_intel_mc_errata
);
3187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e4, quirk_intel_mc_errata
);
3188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e5, quirk_intel_mc_errata
);
3189 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e6, quirk_intel_mc_errata
);
3190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e7, quirk_intel_mc_errata
);
3191 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f7, quirk_intel_mc_errata
);
3192 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f8, quirk_intel_mc_errata
);
3193 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f9, quirk_intel_mc_errata
);
3194 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65fa, quirk_intel_mc_errata
);
3197 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3198 * To work around this, query the size it should be configured to by the
3199 * device and modify the resource end to correspond to this new size.
3201 static void quirk_intel_ntb(struct pci_dev
*dev
)
3206 rc
= pci_read_config_byte(dev
, 0x00D0, &val
);
3210 dev
->resource
[2].end
= dev
->resource
[2].start
+ ((u64
) 1 << val
) - 1;
3212 rc
= pci_read_config_byte(dev
, 0x00D1, &val
);
3216 dev
->resource
[4].end
= dev
->resource
[4].start
+ ((u64
) 1 << val
) - 1;
3218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e08, quirk_intel_ntb
);
3219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e0d, quirk_intel_ntb
);
3222 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3223 * though no one is handling them (e.g., if the i915 driver is never
3224 * loaded). Additionally the interrupt destination is not set up properly
3225 * and the interrupt ends up -somewhere-.
3227 * These spurious interrupts are "sticky" and the kernel disables the
3228 * (shared) interrupt line after 100,000+ generated interrupts.
3230 * Fix it by disabling the still enabled interrupts. This resolves crashes
3231 * often seen on monitor unplug.
3233 #define I915_DEIER_REG 0x4400c
3234 static void disable_igfx_irq(struct pci_dev
*dev
)
3236 void __iomem
*regs
= pci_iomap(dev
, 0, 0);
3238 pci_warn(dev
, "igfx quirk: Can't iomap PCI device\n");
3242 /* Check if any interrupt line is still enabled */
3243 if (readl(regs
+ I915_DEIER_REG
) != 0) {
3244 pci_warn(dev
, "BIOS left Intel GPU interrupts enabled; disabling\n");
3246 writel(0, regs
+ I915_DEIER_REG
);
3249 pci_iounmap(dev
, regs
);
3251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0042, disable_igfx_irq
);
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0046, disable_igfx_irq
);
3253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x004a, disable_igfx_irq
);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0102, disable_igfx_irq
);
3255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0106, disable_igfx_irq
);
3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x010a, disable_igfx_irq
);
3257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0152, disable_igfx_irq
);
3260 * PCI devices which are on Intel chips can skip the 10ms delay
3261 * before entering D3 mode.
3263 static void quirk_remove_d3_delay(struct pci_dev
*dev
)
3267 /* C600 Series devices do not need 10ms d3_delay */
3268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0412, quirk_remove_d3_delay
);
3269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c00, quirk_remove_d3_delay
);
3270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c0c, quirk_remove_d3_delay
);
3271 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c02, quirk_remove_d3_delay
);
3273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c18, quirk_remove_d3_delay
);
3274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c1c, quirk_remove_d3_delay
);
3275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c20, quirk_remove_d3_delay
);
3276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c22, quirk_remove_d3_delay
);
3277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c26, quirk_remove_d3_delay
);
3278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c2d, quirk_remove_d3_delay
);
3279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c31, quirk_remove_d3_delay
);
3280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3a, quirk_remove_d3_delay
);
3281 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3d, quirk_remove_d3_delay
);
3282 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c4e, quirk_remove_d3_delay
);
3283 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2280, quirk_remove_d3_delay
);
3285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2298, quirk_remove_d3_delay
);
3286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x229c, quirk_remove_d3_delay
);
3287 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b0, quirk_remove_d3_delay
);
3288 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b5, quirk_remove_d3_delay
);
3289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b7, quirk_remove_d3_delay
);
3290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b8, quirk_remove_d3_delay
);
3291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22d8, quirk_remove_d3_delay
);
3292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22dc, quirk_remove_d3_delay
);
3295 * Some devices may pass our check in pci_intx_mask_supported() if
3296 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3297 * support this feature.
3299 static void quirk_broken_intx_masking(struct pci_dev
*dev
)
3301 dev
->broken_intx_masking
= 1;
3303 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO
, 0x0030,
3304 quirk_broken_intx_masking
);
3305 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3306 quirk_broken_intx_masking
);
3307 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3308 quirk_broken_intx_masking
);
3311 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3312 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3314 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK
, 0x8169,
3317 quirk_broken_intx_masking
);
3320 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3321 * DisINTx can be set but the interrupt status bit is non-functional.
3323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1572, quirk_broken_intx_masking
);
3324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1574, quirk_broken_intx_masking
);
3325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1580, quirk_broken_intx_masking
);
3326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1581, quirk_broken_intx_masking
);
3327 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1583, quirk_broken_intx_masking
);
3328 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1584, quirk_broken_intx_masking
);
3329 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1585, quirk_broken_intx_masking
);
3330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1586, quirk_broken_intx_masking
);
3331 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1587, quirk_broken_intx_masking
);
3332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1588, quirk_broken_intx_masking
);
3333 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1589, quirk_broken_intx_masking
);
3334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158a, quirk_broken_intx_masking
);
3335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158b, quirk_broken_intx_masking
);
3336 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d0, quirk_broken_intx_masking
);
3337 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d1, quirk_broken_intx_masking
);
3338 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d2, quirk_broken_intx_masking
);
3340 static u16 mellanox_broken_intx_devs
[] = {
3341 PCI_DEVICE_ID_MELLANOX_HERMON_SDR
,
3342 PCI_DEVICE_ID_MELLANOX_HERMON_DDR
,
3343 PCI_DEVICE_ID_MELLANOX_HERMON_QDR
,
3344 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2
,
3345 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2
,
3346 PCI_DEVICE_ID_MELLANOX_HERMON_EN
,
3347 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2
,
3348 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN
,
3349 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2
,
3350 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2
,
3351 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2
,
3352 PCI_DEVICE_ID_MELLANOX_CONNECTX2
,
3353 PCI_DEVICE_ID_MELLANOX_CONNECTX3
,
3354 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO
,
3357 #define CONNECTX_4_CURR_MAX_MINOR 99
3358 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3361 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3362 * If so, don't mark it as broken.
3363 * FW minor > 99 means older FW version format and no INTx masking support.
3364 * FW minor < 14 means new FW version format and no INTx masking support.
3366 static void mellanox_check_broken_intx_masking(struct pci_dev
*pdev
)
3368 __be32 __iomem
*fw_ver
;
3376 for (i
= 0; i
< ARRAY_SIZE(mellanox_broken_intx_devs
); i
++) {
3377 if (pdev
->device
== mellanox_broken_intx_devs
[i
]) {
3378 pdev
->broken_intx_masking
= 1;
3384 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3385 * support so shouldn't be checked further
3387 if (pdev
->device
== PCI_DEVICE_ID_MELLANOX_CONNECTIB
)
3390 if (pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4
&&
3391 pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
)
3394 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3395 if (pci_enable_device_mem(pdev
)) {
3396 pci_warn(pdev
, "Can't enable device memory\n");
3400 fw_ver
= ioremap(pci_resource_start(pdev
, 0), 4);
3402 pci_warn(pdev
, "Can't map ConnectX-4 initialization segment\n");
3406 /* Reading from resource space should be 32b aligned */
3407 fw_maj_min
= ioread32be(fw_ver
);
3408 fw_sub_min
= ioread32be(fw_ver
+ 1);
3409 fw_major
= fw_maj_min
& 0xffff;
3410 fw_minor
= fw_maj_min
>> 16;
3411 fw_subminor
= fw_sub_min
& 0xffff;
3412 if (fw_minor
> CONNECTX_4_CURR_MAX_MINOR
||
3413 fw_minor
< CONNECTX_4_INTX_SUPPORT_MINOR
) {
3414 pci_warn(pdev
, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3415 fw_major
, fw_minor
, fw_subminor
, pdev
->device
==
3416 PCI_DEVICE_ID_MELLANOX_CONNECTX4
? 12 : 14);
3417 pdev
->broken_intx_masking
= 1;
3423 pci_disable_device(pdev
);
3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_ANY_ID
,
3426 mellanox_check_broken_intx_masking
);
3428 static void quirk_no_bus_reset(struct pci_dev
*dev
)
3430 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_BUS_RESET
;
3434 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3435 * The device will throw a Link Down error on AER-capable systems and
3436 * regardless of AER, config space of the device is never accessible again
3437 * and typically causes the system to hang or reset when access is attempted.
3438 * http://www.spinics.net/lists/linux-pci/msg34797.html
3440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0030, quirk_no_bus_reset
);
3441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0032, quirk_no_bus_reset
);
3442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x003c, quirk_no_bus_reset
);
3443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0033, quirk_no_bus_reset
);
3444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0034, quirk_no_bus_reset
);
3447 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3448 * reset when used with certain child devices. After the reset, config
3449 * accesses to the child may fail.
3451 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM
, 0xa100, quirk_no_bus_reset
);
3453 static void quirk_no_pm_reset(struct pci_dev
*dev
)
3456 * We can't do a bus reset on root bus devices, but an ineffective
3457 * PM reset may be better than nothing.
3459 if (!pci_is_root_bus(dev
->bus
))
3460 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_PM_RESET
;
3464 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3465 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3466 * to have no effect on the device: it retains the framebuffer contents and
3467 * monitor sync. Advertising this support makes other layers, like VFIO,
3468 * assume pci_reset_function() is viable for this device. Mark it as
3469 * unavailable to skip it when testing reset methods.
3471 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
3472 PCI_CLASS_DISPLAY_VGA
, 8, quirk_no_pm_reset
);
3475 * Thunderbolt controllers with broken MSI hotplug signaling:
3476 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3477 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3479 static void quirk_thunderbolt_hotplug_msi(struct pci_dev
*pdev
)
3481 if (pdev
->is_hotplug_bridge
&&
3482 (pdev
->device
!= PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
||
3483 pdev
->revision
<= 1))
3486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
,
3487 quirk_thunderbolt_hotplug_msi
);
3488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE
,
3489 quirk_thunderbolt_hotplug_msi
);
3490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_PEAK
,
3491 quirk_thunderbolt_hotplug_msi
);
3492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3493 quirk_thunderbolt_hotplug_msi
);
3494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PORT_RIDGE
,
3495 quirk_thunderbolt_hotplug_msi
);
3499 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3501 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3502 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3503 * be present after resume if a device was plugged in before suspend.
3505 * The Thunderbolt controller consists of a PCIe switch with downstream
3506 * bridges leading to the NHI and to the tunnel PCI bridges.
3508 * This quirk cuts power to the whole chip. Therefore we have to apply it
3509 * during suspend_noirq of the upstream bridge.
3511 * Power is automagically restored before resume. No action is needed.
3513 static void quirk_apple_poweroff_thunderbolt(struct pci_dev
*dev
)
3515 acpi_handle bridge
, SXIO
, SXFP
, SXLV
;
3517 if (!x86_apple_machine
)
3519 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
)
3521 bridge
= ACPI_HANDLE(&dev
->dev
);
3526 * SXIO and SXLV are present only on machines requiring this quirk.
3527 * Thunderbolt bridges in external devices might have the same
3528 * device ID as those on the host, but they will not have the
3529 * associated ACPI methods. This implicitly checks that we are at
3532 if (ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXIO", &SXIO
))
3533 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXFP", &SXFP
))
3534 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXLV", &SXLV
)))
3536 pci_info(dev
, "quirk: cutting power to Thunderbolt controller...\n");
3538 /* magic sequence */
3539 acpi_execute_simple_method(SXIO
, NULL
, 1);
3540 acpi_execute_simple_method(SXFP
, NULL
, 0);
3542 acpi_execute_simple_method(SXLV
, NULL
, 0);
3543 acpi_execute_simple_method(SXIO
, NULL
, 0);
3544 acpi_execute_simple_method(SXLV
, NULL
, 0);
3546 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL
,
3547 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3548 quirk_apple_poweroff_thunderbolt
);
3551 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3553 * During suspend the Thunderbolt controller is reset and all PCI
3554 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3555 * during resume. We have to manually wait for the NHI since there is
3556 * no parent child relationship between the NHI and the tunneled
3559 static void quirk_apple_wait_for_thunderbolt(struct pci_dev
*dev
)
3561 struct pci_dev
*sibling
= NULL
;
3562 struct pci_dev
*nhi
= NULL
;
3564 if (!x86_apple_machine
)
3566 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_DOWNSTREAM
)
3570 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3571 * host controller and not on a Thunderbolt endpoint.
3573 sibling
= pci_get_slot(dev
->bus
, 0x0);
3575 goto out
; /* we are the downstream bridge to the NHI */
3576 if (!sibling
|| !sibling
->subordinate
)
3578 nhi
= pci_get_slot(sibling
->subordinate
, 0x0);
3581 if (nhi
->vendor
!= PCI_VENDOR_ID_INTEL
3582 || (nhi
->device
!= PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
&&
3583 nhi
->device
!= PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
&&
3584 nhi
->device
!= PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI
&&
3585 nhi
->device
!= PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI
)
3586 || nhi
->class != PCI_CLASS_SYSTEM_OTHER
<< 8)
3588 pci_info(dev
, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3589 device_pm_wait_for_dev(&dev
->dev
, &nhi
->dev
);
3592 pci_dev_put(sibling
);
3594 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3595 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
,
3596 quirk_apple_wait_for_thunderbolt
);
3597 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3598 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3599 quirk_apple_wait_for_thunderbolt
);
3600 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3601 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE
,
3602 quirk_apple_wait_for_thunderbolt
);
3603 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3604 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE
,
3605 quirk_apple_wait_for_thunderbolt
);
3609 * Following are device-specific reset methods which can be used to
3610 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3613 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
3616 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3618 * The 82599 supports FLR on VFs, but FLR support is reported only
3619 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3620 * Thus we must call pcie_flr() directly without first checking if it is
3628 #define SOUTH_CHICKEN2 0xc2004
3629 #define PCH_PP_STATUS 0xc7200
3630 #define PCH_PP_CONTROL 0xc7204
3631 #define MSG_CTL 0x45010
3632 #define NSDE_PWR_STATE 0xd0100
3633 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3635 static int reset_ivb_igd(struct pci_dev
*dev
, int probe
)
3637 void __iomem
*mmio_base
;
3638 unsigned long timeout
;
3644 mmio_base
= pci_iomap(dev
, 0, 0);
3648 iowrite32(0x00000002, mmio_base
+ MSG_CTL
);
3651 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3652 * driver loaded sets the right bits. However, this's a reset and
3653 * the bits have been set by i915 previously, so we clobber
3654 * SOUTH_CHICKEN2 register directly here.
3656 iowrite32(0x00000005, mmio_base
+ SOUTH_CHICKEN2
);
3658 val
= ioread32(mmio_base
+ PCH_PP_CONTROL
) & 0xfffffffe;
3659 iowrite32(val
, mmio_base
+ PCH_PP_CONTROL
);
3661 timeout
= jiffies
+ msecs_to_jiffies(IGD_OPERATION_TIMEOUT
);
3663 val
= ioread32(mmio_base
+ PCH_PP_STATUS
);
3664 if ((val
& 0xb0000000) == 0)
3665 goto reset_complete
;
3667 } while (time_before(jiffies
, timeout
));
3668 pci_warn(dev
, "timeout during reset\n");
3671 iowrite32(0x00000002, mmio_base
+ NSDE_PWR_STATE
);
3673 pci_iounmap(dev
, mmio_base
);
3677 /* Device-specific reset method for Chelsio T4-based adapters */
3678 static int reset_chelsio_generic_dev(struct pci_dev
*dev
, int probe
)
3684 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3685 * that we have no device-specific reset method.
3687 if ((dev
->device
& 0xf000) != 0x4000)
3691 * If this is the "probe" phase, return 0 indicating that we can
3692 * reset this device.
3698 * T4 can wedge if there are DMAs in flight within the chip and Bus
3699 * Master has been disabled. We need to have it on till the Function
3700 * Level Reset completes. (BUS_MASTER is disabled in
3701 * pci_reset_function()).
3703 pci_read_config_word(dev
, PCI_COMMAND
, &old_command
);
3704 pci_write_config_word(dev
, PCI_COMMAND
,
3705 old_command
| PCI_COMMAND_MASTER
);
3708 * Perform the actual device function reset, saving and restoring
3709 * configuration information around the reset.
3711 pci_save_state(dev
);
3714 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3715 * are disabled when an MSI-X interrupt message needs to be delivered.
3716 * So we briefly re-enable MSI-X interrupts for the duration of the
3717 * FLR. The pci_restore_state() below will restore the original
3720 pci_read_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
, &msix_flags
);
3721 if ((msix_flags
& PCI_MSIX_FLAGS_ENABLE
) == 0)
3722 pci_write_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
,
3724 PCI_MSIX_FLAGS_ENABLE
|
3725 PCI_MSIX_FLAGS_MASKALL
);
3730 * Restore the configuration information (BAR values, etc.) including
3731 * the original PCI Configuration Space Command word, and return
3734 pci_restore_state(dev
);
3735 pci_write_config_word(dev
, PCI_COMMAND
, old_command
);
3739 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3740 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3741 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3744 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3745 * FLR where config space reads from the device return -1. We seem to be
3746 * able to avoid this condition if we disable the NVMe controller prior to
3747 * FLR. This quirk is generic for any NVMe class device requiring similar
3748 * assistance to quiesce the device prior to FLR.
3750 * NVMe specification: https://nvmexpress.org/resources/specifications/
3752 * Chapter 2: Required and optional PCI config registers
3753 * Chapter 3: NVMe control registers
3754 * Chapter 7.3: Reset behavior
3756 static int nvme_disable_and_flr(struct pci_dev
*dev
, int probe
)
3762 if (dev
->class != PCI_CLASS_STORAGE_EXPRESS
||
3763 !pcie_has_flr(dev
) || !pci_resource_start(dev
, 0))
3769 bar
= pci_iomap(dev
, 0, NVME_REG_CC
+ sizeof(cfg
));
3773 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3774 pci_write_config_word(dev
, PCI_COMMAND
, cmd
| PCI_COMMAND_MEMORY
);
3776 cfg
= readl(bar
+ NVME_REG_CC
);
3778 /* Disable controller if enabled */
3779 if (cfg
& NVME_CC_ENABLE
) {
3780 u32 cap
= readl(bar
+ NVME_REG_CAP
);
3781 unsigned long timeout
;
3784 * Per nvme_disable_ctrl() skip shutdown notification as it
3785 * could complete commands to the admin queue. We only intend
3786 * to quiesce the device before reset.
3788 cfg
&= ~(NVME_CC_SHN_MASK
| NVME_CC_ENABLE
);
3790 writel(cfg
, bar
+ NVME_REG_CC
);
3793 * Some controllers require an additional delay here, see
3794 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3795 * supported by this quirk.
3798 /* Cap register provides max timeout in 500ms increments */
3799 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
3802 u32 status
= readl(bar
+ NVME_REG_CSTS
);
3804 /* Ready status becomes zero on disable complete */
3805 if (!(status
& NVME_CSTS_RDY
))
3810 if (time_after(jiffies
, timeout
)) {
3811 pci_warn(dev
, "Timeout waiting for NVMe ready status to clear after disable\n");
3817 pci_iounmap(dev
, bar
);
3825 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3826 * to change after NVMe enable if the driver starts interacting with the
3827 * device too soon after FLR. A 250ms delay after FLR has heuristically
3828 * proven to produce reliably working results for device assignment cases.
3830 static int delay_250ms_after_flr(struct pci_dev
*dev
, int probe
)
3832 if (!pcie_has_flr(dev
))
3845 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
3846 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
3847 reset_intel_82599_sfp_virtfn
},
3848 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M_VGA
,
3850 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M2_VGA
,
3852 { PCI_VENDOR_ID_SAMSUNG
, 0xa804, nvme_disable_and_flr
},
3853 { PCI_VENDOR_ID_INTEL
, 0x0953, delay_250ms_after_flr
},
3854 { PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
3855 reset_chelsio_generic_dev
},
3860 * These device-specific reset methods are here rather than in a driver
3861 * because when a host assigns a device to a guest VM, the host may need
3862 * to reset the device but probably doesn't have a driver for it.
3864 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
3866 const struct pci_dev_reset_methods
*i
;
3868 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
3869 if ((i
->vendor
== dev
->vendor
||
3870 i
->vendor
== (u16
)PCI_ANY_ID
) &&
3871 (i
->device
== dev
->device
||
3872 i
->device
== (u16
)PCI_ANY_ID
))
3873 return i
->reset(dev
, probe
);
3879 static void quirk_dma_func0_alias(struct pci_dev
*dev
)
3881 if (PCI_FUNC(dev
->devfn
) != 0)
3882 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0));
3886 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3888 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe832, quirk_dma_func0_alias
);
3891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe476, quirk_dma_func0_alias
);
3893 static void quirk_dma_func1_alias(struct pci_dev
*dev
)
3895 if (PCI_FUNC(dev
->devfn
) != 1)
3896 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 1));
3900 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3901 * SKUs function 1 is present and is a legacy IDE controller, in other
3902 * SKUs this function is not present, making this a ghost requester.
3903 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9120,
3906 quirk_dma_func1_alias
);
3907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9123,
3908 quirk_dma_func1_alias
);
3909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9128,
3910 quirk_dma_func1_alias
);
3911 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9130,
3913 quirk_dma_func1_alias
);
3914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9170,
3915 quirk_dma_func1_alias
);
3916 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9172,
3918 quirk_dma_func1_alias
);
3919 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x917a,
3921 quirk_dma_func1_alias
);
3922 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9182,
3924 quirk_dma_func1_alias
);
3925 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
3926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9183,
3927 quirk_dma_func1_alias
);
3928 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x91a0,
3930 quirk_dma_func1_alias
);
3931 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3932 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9220,
3933 quirk_dma_func1_alias
);
3934 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9230,
3936 quirk_dma_func1_alias
);
3937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0642,
3938 quirk_dma_func1_alias
);
3939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0645,
3940 quirk_dma_func1_alias
);
3941 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON
,
3943 PCI_DEVICE_ID_JMICRON_JMB388_ESD
,
3944 quirk_dma_func1_alias
);
3945 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3946 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3947 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3948 quirk_dma_func1_alias
);
3951 * Some devices DMA with the wrong devfn, not just the wrong function.
3952 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3953 * the alias is "fixed" and independent of the device devfn.
3955 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3956 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3957 * single device on the secondary bus. In reality, the single exposed
3958 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3959 * that provides a bridge to the internal bus of the I/O processor. The
3960 * controller supports private devices, which can be hidden from PCI config
3961 * space. In the case of the Adaptec 3405, a private device at 01.0
3962 * appears to be the DMA engine, which therefore needs to become a DMA
3963 * alias for the device.
3965 static const struct pci_device_id fixed_dma_alias_tbl
[] = {
3966 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
3967 PCI_VENDOR_ID_ADAPTEC2
, 0x02bb), /* Adaptec 3405 */
3968 .driver_data
= PCI_DEVFN(1, 0) },
3969 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
3970 PCI_VENDOR_ID_ADAPTEC2
, 0x02bc), /* Adaptec 3805 */
3971 .driver_data
= PCI_DEVFN(1, 0) },
3975 static void quirk_fixed_dma_alias(struct pci_dev
*dev
)
3977 const struct pci_device_id
*id
;
3979 id
= pci_match_id(fixed_dma_alias_tbl
, dev
);
3981 pci_add_dma_alias(dev
, id
->driver_data
);
3984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2
, 0x0285, quirk_fixed_dma_alias
);
3987 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3988 * using the wrong DMA alias for the device. Some of these devices can be
3989 * used as either forward or reverse bridges, so we need to test whether the
3990 * device is operating in the correct mode. We could probably apply this
3991 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3992 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3993 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3995 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev
*pdev
)
3997 if (!pci_is_root_bus(pdev
->bus
) &&
3998 pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
3999 !pci_is_pcie(pdev
) && pci_is_pcie(pdev
->bus
->self
) &&
4000 pci_pcie_type(pdev
->bus
->self
) != PCI_EXP_TYPE_PCI_BRIDGE
)
4001 pdev
->dev_flags
|= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
;
4003 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA
, 0x1080,
4005 quirk_use_pcie_bridge_dma_alias
);
4006 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4007 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias
);
4008 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4009 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias
);
4010 /* ITE 8893 has the same problem as the 8892 */
4011 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias
);
4012 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4013 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias
);
4016 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4017 * be added as aliases to the DMA device in order to allow buffer access
4018 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4019 * programmed in the EEPROM.
4021 static void quirk_mic_x200_dma_alias(struct pci_dev
*pdev
)
4023 pci_add_dma_alias(pdev
, PCI_DEVFN(0x10, 0x0));
4024 pci_add_dma_alias(pdev
, PCI_DEVFN(0x11, 0x0));
4025 pci_add_dma_alias(pdev
, PCI_DEVFN(0x12, 0x3));
4027 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2260, quirk_mic_x200_dma_alias
);
4028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2264, quirk_mic_x200_dma_alias
);
4031 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4032 * associated not at the root bus, but at a bridge below. This quirk avoids
4033 * generating invalid DMA aliases.
4035 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev
*pdev
)
4037 pdev
->dev_flags
|= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
;
4039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9000,
4040 quirk_bridge_cavm_thrx2_pcie_root
);
4041 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9084,
4042 quirk_bridge_cavm_thrx2_pcie_root
);
4045 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4046 * class code. Fix it.
4048 static void quirk_tw686x_class(struct pci_dev
*pdev
)
4050 u32
class = pdev
->class;
4052 /* Use "Multimedia controller" class */
4053 pdev
->class = (PCI_CLASS_MULTIMEDIA_OTHER
<< 8) | 0x01;
4054 pci_info(pdev
, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4055 class, pdev
->class);
4057 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED
, 8,
4058 quirk_tw686x_class
);
4059 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED
, 8,
4060 quirk_tw686x_class
);
4061 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED
, 8,
4062 quirk_tw686x_class
);
4063 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED
, 8,
4064 quirk_tw686x_class
);
4067 * Some devices have problems with Transaction Layer Packets with the Relaxed
4068 * Ordering Attribute set. Such devices should mark themselves and other
4069 * device drivers should check before sending TLPs with RO set.
4071 static void quirk_relaxedordering_disable(struct pci_dev
*dev
)
4073 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_RELAXED_ORDERING
;
4074 pci_info(dev
, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4078 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4079 * Complex have a Flow Control Credit issue which can cause performance
4080 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4082 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f01, PCI_CLASS_NOT_DEFINED
, 8,
4083 quirk_relaxedordering_disable
);
4084 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f02, PCI_CLASS_NOT_DEFINED
, 8,
4085 quirk_relaxedordering_disable
);
4086 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f03, PCI_CLASS_NOT_DEFINED
, 8,
4087 quirk_relaxedordering_disable
);
4088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f04, PCI_CLASS_NOT_DEFINED
, 8,
4089 quirk_relaxedordering_disable
);
4090 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f05, PCI_CLASS_NOT_DEFINED
, 8,
4091 quirk_relaxedordering_disable
);
4092 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f06, PCI_CLASS_NOT_DEFINED
, 8,
4093 quirk_relaxedordering_disable
);
4094 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f07, PCI_CLASS_NOT_DEFINED
, 8,
4095 quirk_relaxedordering_disable
);
4096 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f08, PCI_CLASS_NOT_DEFINED
, 8,
4097 quirk_relaxedordering_disable
);
4098 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f09, PCI_CLASS_NOT_DEFINED
, 8,
4099 quirk_relaxedordering_disable
);
4100 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0a, PCI_CLASS_NOT_DEFINED
, 8,
4101 quirk_relaxedordering_disable
);
4102 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0b, PCI_CLASS_NOT_DEFINED
, 8,
4103 quirk_relaxedordering_disable
);
4104 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0c, PCI_CLASS_NOT_DEFINED
, 8,
4105 quirk_relaxedordering_disable
);
4106 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0d, PCI_CLASS_NOT_DEFINED
, 8,
4107 quirk_relaxedordering_disable
);
4108 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0e, PCI_CLASS_NOT_DEFINED
, 8,
4109 quirk_relaxedordering_disable
);
4110 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f01, PCI_CLASS_NOT_DEFINED
, 8,
4111 quirk_relaxedordering_disable
);
4112 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f02, PCI_CLASS_NOT_DEFINED
, 8,
4113 quirk_relaxedordering_disable
);
4114 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f03, PCI_CLASS_NOT_DEFINED
, 8,
4115 quirk_relaxedordering_disable
);
4116 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f04, PCI_CLASS_NOT_DEFINED
, 8,
4117 quirk_relaxedordering_disable
);
4118 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f05, PCI_CLASS_NOT_DEFINED
, 8,
4119 quirk_relaxedordering_disable
);
4120 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f06, PCI_CLASS_NOT_DEFINED
, 8,
4121 quirk_relaxedordering_disable
);
4122 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f07, PCI_CLASS_NOT_DEFINED
, 8,
4123 quirk_relaxedordering_disable
);
4124 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f08, PCI_CLASS_NOT_DEFINED
, 8,
4125 quirk_relaxedordering_disable
);
4126 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f09, PCI_CLASS_NOT_DEFINED
, 8,
4127 quirk_relaxedordering_disable
);
4128 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0a, PCI_CLASS_NOT_DEFINED
, 8,
4129 quirk_relaxedordering_disable
);
4130 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0b, PCI_CLASS_NOT_DEFINED
, 8,
4131 quirk_relaxedordering_disable
);
4132 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0c, PCI_CLASS_NOT_DEFINED
, 8,
4133 quirk_relaxedordering_disable
);
4134 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0d, PCI_CLASS_NOT_DEFINED
, 8,
4135 quirk_relaxedordering_disable
);
4136 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0e, PCI_CLASS_NOT_DEFINED
, 8,
4137 quirk_relaxedordering_disable
);
4140 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4141 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4142 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4143 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4144 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4145 * November 10, 2010). As a result, on this platform we can't use Relaxed
4146 * Ordering for Upstream TLPs.
4148 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a00, PCI_CLASS_NOT_DEFINED
, 8,
4149 quirk_relaxedordering_disable
);
4150 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a01, PCI_CLASS_NOT_DEFINED
, 8,
4151 quirk_relaxedordering_disable
);
4152 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a02, PCI_CLASS_NOT_DEFINED
, 8,
4153 quirk_relaxedordering_disable
);
4156 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4157 * values for the Attribute as were supplied in the header of the
4158 * corresponding Request, except as explicitly allowed when IDO is used."
4160 * If a non-compliant device generates a completion with a different
4161 * attribute than the request, the receiver may accept it (which itself
4162 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4163 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4164 * device access timeout.
4166 * If the non-compliant device generates completions with zero attributes
4167 * (instead of copying the attributes from the request), we can work around
4168 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4169 * upstream devices so they always generate requests with zero attributes.
4171 * This affects other devices under the same Root Port, but since these
4172 * attributes are performance hints, there should be no functional problem.
4174 * Note that Configuration Space accesses are never supposed to have TLP
4175 * Attributes, so we're safe waiting till after any Configuration Space
4176 * accesses to do the Root Port fixup.
4178 static void quirk_disable_root_port_attributes(struct pci_dev
*pdev
)
4180 struct pci_dev
*root_port
= pci_find_pcie_root_port(pdev
);
4183 pci_warn(pdev
, "PCIe Completion erratum may cause device errors\n");
4187 pci_info(root_port
, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4188 dev_name(&pdev
->dev
));
4189 pcie_capability_clear_and_set_word(root_port
, PCI_EXP_DEVCTL
,
4190 PCI_EXP_DEVCTL_RELAX_EN
|
4191 PCI_EXP_DEVCTL_NOSNOOP_EN
, 0);
4195 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4196 * Completion it generates.
4198 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev
*pdev
)
4201 * This mask/compare operation selects for Physical Function 4 on a
4202 * T5. We only need to fix up the Root Port once for any of the
4203 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4204 * 0x54xx so we use that one.
4206 if ((pdev
->device
& 0xff00) == 0x5400)
4207 quirk_disable_root_port_attributes(pdev
);
4209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
4210 quirk_chelsio_T5_disable_root_port_attributes
);
4213 * AMD has indicated that the devices below do not support peer-to-peer
4214 * in any system where they are found in the southbridge with an AMD
4215 * IOMMU in the system. Multifunction devices that do not support
4216 * peer-to-peer between functions can claim to support a subset of ACS.
4217 * Such devices effectively enable request redirect (RR) and completion
4218 * redirect (CR) since all transactions are redirected to the upstream
4221 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4222 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4223 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4225 * 1002:4385 SBx00 SMBus Controller
4226 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4227 * 1002:4383 SBx00 Azalia (Intel HDA)
4228 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4229 * 1002:4384 SBx00 PCI to PCI Bridge
4230 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4232 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4234 * 1022:780f [AMD] FCH PCI Bridge
4235 * 1022:7809 [AMD] FCH USB OHCI Controller
4237 static int pci_quirk_amd_sb_acs(struct pci_dev
*dev
, u16 acs_flags
)
4240 struct acpi_table_header
*header
= NULL
;
4243 /* Targeting multifunction devices on the SB (appears on root bus) */
4244 if (!dev
->multifunction
|| !pci_is_root_bus(dev
->bus
))
4247 /* The IVRS table describes the AMD IOMMU */
4248 status
= acpi_get_table("IVRS", 0, &header
);
4249 if (ACPI_FAILURE(status
))
4252 /* Filter out flags not applicable to multifunction */
4253 acs_flags
&= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
| PCI_ACS_DT
);
4255 return acs_flags
& ~(PCI_ACS_RR
| PCI_ACS_CR
) ? 0 : 1;
4261 static bool pci_quirk_cavium_acs_match(struct pci_dev
*dev
)
4263 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4266 switch (dev
->device
) {
4268 * Effectively selects all downstream ports for whole ThunderX1
4269 * (which represents 8 SoCs).
4271 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4272 case 0xaf84: /* ThunderX2 */
4273 case 0xb884: /* ThunderX3 */
4280 static int pci_quirk_cavium_acs(struct pci_dev
*dev
, u16 acs_flags
)
4283 * Cavium root ports don't advertise an ACS capability. However,
4284 * the RTL internally implements similar protection as if ACS had
4285 * Request Redirection, Completion Redirection, Source Validation,
4286 * and Upstream Forwarding features enabled. Assert that the
4287 * hardware implements and enables equivalent ACS functionality for
4290 acs_flags
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_SV
| PCI_ACS_UF
);
4292 if (!pci_quirk_cavium_acs_match(dev
))
4295 return acs_flags
? 0 : 1;
4298 static int pci_quirk_xgene_acs(struct pci_dev
*dev
, u16 acs_flags
)
4301 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4302 * transactions with others, allowing masking out these bits as if they
4303 * were unimplemented in the ACS capability.
4305 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4307 return acs_flags
? 0 : 1;
4311 * Many Intel PCH root ports do provide ACS-like features to disable peer
4312 * transactions and validate bus numbers in requests, but do not provide an
4313 * actual PCIe ACS capability. This is the list of device IDs known to fall
4314 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4316 static const u16 pci_quirk_intel_pch_acs_ids
[] = {
4318 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4319 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4320 /* Cougarpoint PCH */
4321 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4322 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4323 /* Pantherpoint PCH */
4324 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4325 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4326 /* Lynxpoint-H PCH */
4327 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4328 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4329 /* Lynxpoint-LP PCH */
4330 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4331 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4333 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4334 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4335 /* Patsburg (X79) PCH */
4336 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4337 /* Wellsburg (X99) PCH */
4338 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4339 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4340 /* Lynx Point (9 series) PCH */
4341 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4344 static bool pci_quirk_intel_pch_acs_match(struct pci_dev
*dev
)
4348 /* Filter out a few obvious non-matches first */
4349 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4352 for (i
= 0; i
< ARRAY_SIZE(pci_quirk_intel_pch_acs_ids
); i
++)
4353 if (pci_quirk_intel_pch_acs_ids
[i
] == dev
->device
)
4359 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4361 static int pci_quirk_intel_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4363 u16 flags
= dev
->dev_flags
& PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
?
4364 INTEL_PCH_ACS_FLAGS
: 0;
4366 if (!pci_quirk_intel_pch_acs_match(dev
))
4369 return acs_flags
& ~flags
? 0 : 1;
4373 * These QCOM root ports do provide ACS-like features to disable peer
4374 * transactions and validate bus numbers in requests, but do not provide an
4375 * actual PCIe ACS capability. Hardware supports source validation but it
4376 * will report the issue as Completer Abort instead of ACS Violation.
4377 * Hardware doesn't support peer-to-peer and each root port is a root
4378 * complex with unique segment numbers. It is not possible for one root
4379 * port to pass traffic to another root port. All PCIe transactions are
4380 * terminated inside the root port.
4382 static int pci_quirk_qcom_rp_acs(struct pci_dev
*dev
, u16 acs_flags
)
4384 u16 flags
= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_SV
);
4385 int ret
= acs_flags
& ~flags
? 0 : 1;
4387 pci_info(dev
, "Using QCOM ACS Quirk (%d)\n", ret
);
4393 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4394 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4395 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4396 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4397 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4398 * control register is at offset 8 instead of 6 and we should probably use
4399 * dword accesses to them. This applies to the following PCI Device IDs, as
4400 * found in volume 1 of the datasheet[2]:
4402 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4403 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4405 * N.B. This doesn't fix what lspci shows.
4407 * The 100 series chipset specification update includes this as errata #23[3].
4409 * The 200 series chipset (Union Point) has the same bug according to the
4410 * specification update (Intel 200 Series Chipset Family Platform Controller
4411 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4412 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4415 * 0xa290-0xa29f PCI Express Root port #{0-16}
4416 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4418 * Mobile chipsets are also affected, 7th & 8th Generation
4419 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4420 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4421 * Processor Family I/O for U Quad Core Platforms Specification Update,
4422 * August 2017, Revision 002, Document#: 334660-002)[6]
4423 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4424 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4425 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4427 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4429 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4430 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4431 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4432 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4433 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4434 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4435 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4437 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev
*dev
)
4439 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4442 switch (dev
->device
) {
4443 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4444 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4445 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4452 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4454 static int pci_quirk_intel_spt_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4459 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4462 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
4466 /* see pci_acs_flags_enabled() */
4467 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4468 acs_flags
&= (cap
| PCI_ACS_EC
);
4470 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4472 return acs_flags
& ~ctrl
? 0 : 1;
4475 static int pci_quirk_mf_endpoint_acs(struct pci_dev
*dev
, u16 acs_flags
)
4478 * SV, TB, and UF are not relevant to multifunction endpoints.
4480 * Multifunction devices are only required to implement RR, CR, and DT
4481 * in their ACS capability if they support peer-to-peer transactions.
4482 * Devices matching this quirk have been verified by the vendor to not
4483 * perform peer-to-peer with other functions, allowing us to mask out
4484 * these bits as if they were unimplemented in the ACS capability.
4486 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_TB
| PCI_ACS_RR
|
4487 PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_DT
);
4489 return acs_flags
? 0 : 1;
4492 static const struct pci_dev_acs_enabled
{
4495 int (*acs_enabled
)(struct pci_dev
*dev
, u16 acs_flags
);
4496 } pci_dev_acs_enabled
[] = {
4497 { PCI_VENDOR_ID_ATI
, 0x4385, pci_quirk_amd_sb_acs
},
4498 { PCI_VENDOR_ID_ATI
, 0x439c, pci_quirk_amd_sb_acs
},
4499 { PCI_VENDOR_ID_ATI
, 0x4383, pci_quirk_amd_sb_acs
},
4500 { PCI_VENDOR_ID_ATI
, 0x439d, pci_quirk_amd_sb_acs
},
4501 { PCI_VENDOR_ID_ATI
, 0x4384, pci_quirk_amd_sb_acs
},
4502 { PCI_VENDOR_ID_ATI
, 0x4399, pci_quirk_amd_sb_acs
},
4503 { PCI_VENDOR_ID_AMD
, 0x780f, pci_quirk_amd_sb_acs
},
4504 { PCI_VENDOR_ID_AMD
, 0x7809, pci_quirk_amd_sb_acs
},
4505 { PCI_VENDOR_ID_SOLARFLARE
, 0x0903, pci_quirk_mf_endpoint_acs
},
4506 { PCI_VENDOR_ID_SOLARFLARE
, 0x0923, pci_quirk_mf_endpoint_acs
},
4507 { PCI_VENDOR_ID_SOLARFLARE
, 0x0A03, pci_quirk_mf_endpoint_acs
},
4508 { PCI_VENDOR_ID_INTEL
, 0x10C6, pci_quirk_mf_endpoint_acs
},
4509 { PCI_VENDOR_ID_INTEL
, 0x10DB, pci_quirk_mf_endpoint_acs
},
4510 { PCI_VENDOR_ID_INTEL
, 0x10DD, pci_quirk_mf_endpoint_acs
},
4511 { PCI_VENDOR_ID_INTEL
, 0x10E1, pci_quirk_mf_endpoint_acs
},
4512 { PCI_VENDOR_ID_INTEL
, 0x10F1, pci_quirk_mf_endpoint_acs
},
4513 { PCI_VENDOR_ID_INTEL
, 0x10F7, pci_quirk_mf_endpoint_acs
},
4514 { PCI_VENDOR_ID_INTEL
, 0x10F8, pci_quirk_mf_endpoint_acs
},
4515 { PCI_VENDOR_ID_INTEL
, 0x10F9, pci_quirk_mf_endpoint_acs
},
4516 { PCI_VENDOR_ID_INTEL
, 0x10FA, pci_quirk_mf_endpoint_acs
},
4517 { PCI_VENDOR_ID_INTEL
, 0x10FB, pci_quirk_mf_endpoint_acs
},
4518 { PCI_VENDOR_ID_INTEL
, 0x10FC, pci_quirk_mf_endpoint_acs
},
4519 { PCI_VENDOR_ID_INTEL
, 0x1507, pci_quirk_mf_endpoint_acs
},
4520 { PCI_VENDOR_ID_INTEL
, 0x1514, pci_quirk_mf_endpoint_acs
},
4521 { PCI_VENDOR_ID_INTEL
, 0x151C, pci_quirk_mf_endpoint_acs
},
4522 { PCI_VENDOR_ID_INTEL
, 0x1529, pci_quirk_mf_endpoint_acs
},
4523 { PCI_VENDOR_ID_INTEL
, 0x152A, pci_quirk_mf_endpoint_acs
},
4524 { PCI_VENDOR_ID_INTEL
, 0x154D, pci_quirk_mf_endpoint_acs
},
4525 { PCI_VENDOR_ID_INTEL
, 0x154F, pci_quirk_mf_endpoint_acs
},
4526 { PCI_VENDOR_ID_INTEL
, 0x1551, pci_quirk_mf_endpoint_acs
},
4527 { PCI_VENDOR_ID_INTEL
, 0x1558, pci_quirk_mf_endpoint_acs
},
4529 { PCI_VENDOR_ID_INTEL
, 0x1509, pci_quirk_mf_endpoint_acs
},
4530 { PCI_VENDOR_ID_INTEL
, 0x150E, pci_quirk_mf_endpoint_acs
},
4531 { PCI_VENDOR_ID_INTEL
, 0x150F, pci_quirk_mf_endpoint_acs
},
4532 { PCI_VENDOR_ID_INTEL
, 0x1510, pci_quirk_mf_endpoint_acs
},
4533 { PCI_VENDOR_ID_INTEL
, 0x1511, pci_quirk_mf_endpoint_acs
},
4534 { PCI_VENDOR_ID_INTEL
, 0x1516, pci_quirk_mf_endpoint_acs
},
4535 { PCI_VENDOR_ID_INTEL
, 0x1527, pci_quirk_mf_endpoint_acs
},
4537 { PCI_VENDOR_ID_INTEL
, 0x10C9, pci_quirk_mf_endpoint_acs
},
4538 { PCI_VENDOR_ID_INTEL
, 0x10E6, pci_quirk_mf_endpoint_acs
},
4539 { PCI_VENDOR_ID_INTEL
, 0x10E7, pci_quirk_mf_endpoint_acs
},
4540 { PCI_VENDOR_ID_INTEL
, 0x10E8, pci_quirk_mf_endpoint_acs
},
4541 { PCI_VENDOR_ID_INTEL
, 0x150A, pci_quirk_mf_endpoint_acs
},
4542 { PCI_VENDOR_ID_INTEL
, 0x150D, pci_quirk_mf_endpoint_acs
},
4543 { PCI_VENDOR_ID_INTEL
, 0x1518, pci_quirk_mf_endpoint_acs
},
4544 { PCI_VENDOR_ID_INTEL
, 0x1526, pci_quirk_mf_endpoint_acs
},
4546 { PCI_VENDOR_ID_INTEL
, 0x10A7, pci_quirk_mf_endpoint_acs
},
4547 { PCI_VENDOR_ID_INTEL
, 0x10A9, pci_quirk_mf_endpoint_acs
},
4548 { PCI_VENDOR_ID_INTEL
, 0x10D6, pci_quirk_mf_endpoint_acs
},
4550 { PCI_VENDOR_ID_INTEL
, 0x1521, pci_quirk_mf_endpoint_acs
},
4551 { PCI_VENDOR_ID_INTEL
, 0x1522, pci_quirk_mf_endpoint_acs
},
4552 { PCI_VENDOR_ID_INTEL
, 0x1523, pci_quirk_mf_endpoint_acs
},
4553 { PCI_VENDOR_ID_INTEL
, 0x1524, pci_quirk_mf_endpoint_acs
},
4554 /* 82571 (Quads omitted due to non-ACS switch) */
4555 { PCI_VENDOR_ID_INTEL
, 0x105E, pci_quirk_mf_endpoint_acs
},
4556 { PCI_VENDOR_ID_INTEL
, 0x105F, pci_quirk_mf_endpoint_acs
},
4557 { PCI_VENDOR_ID_INTEL
, 0x1060, pci_quirk_mf_endpoint_acs
},
4558 { PCI_VENDOR_ID_INTEL
, 0x10D9, pci_quirk_mf_endpoint_acs
},
4560 { PCI_VENDOR_ID_INTEL
, 0x15b7, pci_quirk_mf_endpoint_acs
},
4561 { PCI_VENDOR_ID_INTEL
, 0x15b8, pci_quirk_mf_endpoint_acs
},
4562 /* QCOM QDF2xxx root ports */
4563 { PCI_VENDOR_ID_QCOM
, 0x0400, pci_quirk_qcom_rp_acs
},
4564 { PCI_VENDOR_ID_QCOM
, 0x0401, pci_quirk_qcom_rp_acs
},
4565 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4566 { PCI_VENDOR_ID_HXT
, 0x0401, pci_quirk_qcom_rp_acs
},
4567 /* Intel PCH root ports */
4568 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_pch_acs
},
4569 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_spt_pch_acs
},
4570 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs
}, /* Emulex BE3-R */
4571 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs
}, /* Emulex Skyhawk-R */
4572 /* Cavium ThunderX */
4573 { PCI_VENDOR_ID_CAVIUM
, PCI_ANY_ID
, pci_quirk_cavium_acs
},
4575 { PCI_VENDOR_ID_AMCC
, 0xE004, pci_quirk_xgene_acs
},
4576 /* Ampere Computing */
4577 { PCI_VENDOR_ID_AMPERE
, 0xE005, pci_quirk_xgene_acs
},
4578 { PCI_VENDOR_ID_AMPERE
, 0xE006, pci_quirk_xgene_acs
},
4579 { PCI_VENDOR_ID_AMPERE
, 0xE007, pci_quirk_xgene_acs
},
4580 { PCI_VENDOR_ID_AMPERE
, 0xE008, pci_quirk_xgene_acs
},
4581 { PCI_VENDOR_ID_AMPERE
, 0xE009, pci_quirk_xgene_acs
},
4582 { PCI_VENDOR_ID_AMPERE
, 0xE00A, pci_quirk_xgene_acs
},
4583 { PCI_VENDOR_ID_AMPERE
, 0xE00B, pci_quirk_xgene_acs
},
4584 { PCI_VENDOR_ID_AMPERE
, 0xE00C, pci_quirk_xgene_acs
},
4588 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
)
4590 const struct pci_dev_acs_enabled
*i
;
4594 * Allow devices that do not expose standard PCIe ACS capabilities
4595 * or control to indicate their support here. Multi-function express
4596 * devices which do not allow internal peer-to-peer between functions,
4597 * but do not implement PCIe ACS may wish to return true here.
4599 for (i
= pci_dev_acs_enabled
; i
->acs_enabled
; i
++) {
4600 if ((i
->vendor
== dev
->vendor
||
4601 i
->vendor
== (u16
)PCI_ANY_ID
) &&
4602 (i
->device
== dev
->device
||
4603 i
->device
== (u16
)PCI_ANY_ID
)) {
4604 ret
= i
->acs_enabled(dev
, acs_flags
);
4613 /* Config space offset of Root Complex Base Address register */
4614 #define INTEL_LPC_RCBA_REG 0xf0
4615 /* 31:14 RCBA address */
4616 #define INTEL_LPC_RCBA_MASK 0xffffc000
4618 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4620 /* Backbone Scratch Pad Register */
4621 #define INTEL_BSPR_REG 0x1104
4622 /* Backbone Peer Non-Posted Disable */
4623 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4624 /* Backbone Peer Posted Disable */
4625 #define INTEL_BSPR_REG_BPPD (1 << 9)
4627 /* Upstream Peer Decode Configuration Register */
4628 #define INTEL_UPDCR_REG 0x1014
4629 /* 5:0 Peer Decode Enable bits */
4630 #define INTEL_UPDCR_REG_MASK 0x3f
4632 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev
*dev
)
4634 u32 rcba
, bspr
, updcr
;
4635 void __iomem
*rcba_mem
;
4638 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4639 * are D28:F* and therefore get probed before LPC, thus we can't
4640 * use pci_get_slot()/pci_read_config_dword() here.
4642 pci_bus_read_config_dword(dev
->bus
, PCI_DEVFN(31, 0),
4643 INTEL_LPC_RCBA_REG
, &rcba
);
4644 if (!(rcba
& INTEL_LPC_RCBA_ENABLE
))
4647 rcba_mem
= ioremap_nocache(rcba
& INTEL_LPC_RCBA_MASK
,
4648 PAGE_ALIGN(INTEL_UPDCR_REG
));
4653 * The BSPR can disallow peer cycles, but it's set by soft strap and
4654 * therefore read-only. If both posted and non-posted peer cycles are
4655 * disallowed, we're ok. If either are allowed, then we need to use
4656 * the UPDCR to disable peer decodes for each port. This provides the
4657 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4659 bspr
= readl(rcba_mem
+ INTEL_BSPR_REG
);
4660 bspr
&= INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
;
4661 if (bspr
!= (INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
)) {
4662 updcr
= readl(rcba_mem
+ INTEL_UPDCR_REG
);
4663 if (updcr
& INTEL_UPDCR_REG_MASK
) {
4664 pci_info(dev
, "Disabling UPDCR peer decodes\n");
4665 updcr
&= ~INTEL_UPDCR_REG_MASK
;
4666 writel(updcr
, rcba_mem
+ INTEL_UPDCR_REG
);
4674 /* Miscellaneous Port Configuration register */
4675 #define INTEL_MPC_REG 0xd8
4676 /* MPC: Invalid Receive Bus Number Check Enable */
4677 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4679 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev
*dev
)
4684 * When enabled, the IRBNCE bit of the MPC register enables the
4685 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4686 * ensures that requester IDs fall within the bus number range
4687 * of the bridge. Enable if not already.
4689 pci_read_config_dword(dev
, INTEL_MPC_REG
, &mpc
);
4690 if (!(mpc
& INTEL_MPC_REG_IRBNCE
)) {
4691 pci_info(dev
, "Enabling MPC IRBNCE\n");
4692 mpc
|= INTEL_MPC_REG_IRBNCE
;
4693 pci_write_config_word(dev
, INTEL_MPC_REG
, mpc
);
4697 static int pci_quirk_enable_intel_pch_acs(struct pci_dev
*dev
)
4699 if (!pci_quirk_intel_pch_acs_match(dev
))
4702 if (pci_quirk_enable_intel_lpc_acs(dev
)) {
4703 pci_warn(dev
, "Failed to enable Intel PCH ACS quirk\n");
4707 pci_quirk_enable_intel_rp_mpc_acs(dev
);
4709 dev
->dev_flags
|= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
;
4711 pci_info(dev
, "Intel PCH root port ACS workaround enabled\n");
4716 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev
*dev
)
4721 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4724 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
4728 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4729 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4731 ctrl
|= (cap
& PCI_ACS_SV
);
4732 ctrl
|= (cap
& PCI_ACS_RR
);
4733 ctrl
|= (cap
& PCI_ACS_CR
);
4734 ctrl
|= (cap
& PCI_ACS_UF
);
4736 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
4738 pci_info(dev
, "Intel SPT PCH root port ACS workaround enabled\n");
4743 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev
*dev
)
4748 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4751 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
4755 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4756 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4758 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
4760 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
4762 pci_info(dev
, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4767 static const struct pci_dev_acs_ops
{
4770 int (*enable_acs
)(struct pci_dev
*dev
);
4771 int (*disable_acs_redir
)(struct pci_dev
*dev
);
4772 } pci_dev_acs_ops
[] = {
4773 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
4774 .enable_acs
= pci_quirk_enable_intel_pch_acs
,
4776 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
4777 .enable_acs
= pci_quirk_enable_intel_spt_pch_acs
,
4778 .disable_acs_redir
= pci_quirk_disable_intel_spt_pch_acs_redir
,
4782 int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
4784 const struct pci_dev_acs_ops
*p
;
4787 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
4788 p
= &pci_dev_acs_ops
[i
];
4789 if ((p
->vendor
== dev
->vendor
||
4790 p
->vendor
== (u16
)PCI_ANY_ID
) &&
4791 (p
->device
== dev
->device
||
4792 p
->device
== (u16
)PCI_ANY_ID
) &&
4794 ret
= p
->enable_acs(dev
);
4803 int pci_dev_specific_disable_acs_redir(struct pci_dev
*dev
)
4805 const struct pci_dev_acs_ops
*p
;
4808 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
4809 p
= &pci_dev_acs_ops
[i
];
4810 if ((p
->vendor
== dev
->vendor
||
4811 p
->vendor
== (u16
)PCI_ANY_ID
) &&
4812 (p
->device
== dev
->device
||
4813 p
->device
== (u16
)PCI_ANY_ID
) &&
4814 p
->disable_acs_redir
) {
4815 ret
= p
->disable_acs_redir(dev
);
4825 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4826 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4827 * Next Capability pointer in the MSI Capability Structure should point to
4828 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4831 static void quirk_intel_qat_vf_cap(struct pci_dev
*pdev
)
4836 struct pci_cap_saved_state
*state
;
4838 /* Bail if the hardware bug is fixed */
4839 if (pdev
->pcie_cap
|| pci_find_capability(pdev
, PCI_CAP_ID_EXP
))
4842 /* Bail if MSI Capability Structure is not found for some reason */
4843 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSI
);
4848 * Bail if Next Capability pointer in the MSI Capability Structure
4849 * is not the expected incorrect 0x00.
4851 pci_read_config_byte(pdev
, pos
+ 1, &next_cap
);
4856 * PCIe Capability Structure is expected to be at 0x50 and should
4857 * terminate the list (Next Capability pointer is 0x00). Verify
4858 * Capability Id and Next Capability pointer is as expected.
4859 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4860 * to correctly set kernel data structures which have already been
4861 * set incorrectly due to the hardware bug.
4864 pci_read_config_word(pdev
, pos
, ®16
);
4865 if (reg16
== (0x0000 | PCI_CAP_ID_EXP
)) {
4867 #ifndef PCI_EXP_SAVE_REGS
4868 #define PCI_EXP_SAVE_REGS 7
4870 int size
= PCI_EXP_SAVE_REGS
* sizeof(u16
);
4872 pdev
->pcie_cap
= pos
;
4873 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
4874 pdev
->pcie_flags_reg
= reg16
;
4875 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
4876 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
4878 pdev
->cfg_size
= PCI_CFG_SPACE_EXP_SIZE
;
4879 if (pci_read_config_dword(pdev
, PCI_CFG_SPACE_SIZE
, &status
) !=
4880 PCIBIOS_SUCCESSFUL
|| (status
== 0xffffffff))
4881 pdev
->cfg_size
= PCI_CFG_SPACE_SIZE
;
4883 if (pci_find_saved_cap(pdev
, PCI_CAP_ID_EXP
))
4887 state
= kzalloc(sizeof(*state
) + size
, GFP_KERNEL
);
4891 state
->cap
.cap_nr
= PCI_CAP_ID_EXP
;
4892 state
->cap
.cap_extended
= 0;
4893 state
->cap
.size
= size
;
4894 cap
= (u16
*)&state
->cap
.data
[0];
4895 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
4896 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
4897 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
4898 pcie_capability_read_word(pdev
, PCI_EXP_RTCTL
, &cap
[i
++]);
4899 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
4900 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
4901 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
4902 hlist_add_head(&state
->next
, &pdev
->saved_cap_space
);
4905 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x443, quirk_intel_qat_vf_cap
);
4907 /* FLR may cause some 82579 devices to hang */
4908 static void quirk_intel_no_flr(struct pci_dev
*dev
)
4910 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_FLR_RESET
;
4912 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1502, quirk_intel_no_flr
);
4913 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1503, quirk_intel_no_flr
);
4915 static void quirk_intel_th_rtit_bar(struct pci_dev
*dev
)
4917 struct resource
*r
= &dev
->resource
[4];
4921 * Denverton reports 2k of RTIT_BAR (resource 4), which can't be
4922 * right given the 16 threads. When Intel TH gets enabled, the
4923 * actual resource overlaps the XHCI MMIO space and causes it
4925 * We're not really using RTIT_BAR at all at the moment, so it's
4926 * a safe choice to disable this resource.
4928 if (r
->end
== r
->start
+ 0x7ff) {
4934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x19e1, quirk_intel_th_rtit_bar
);
4936 static void quirk_no_ext_tags(struct pci_dev
*pdev
)
4938 struct pci_host_bridge
*bridge
= pci_find_host_bridge(pdev
->bus
);
4943 bridge
->no_ext_tags
= 1;
4944 pci_info(pdev
, "disabling Extended Tags (this device can't handle them)\n");
4946 pci_walk_bus(bridge
->bus
, pci_configure_extended_tags
, NULL
);
4948 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0132, quirk_no_ext_tags
);
4949 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0140, quirk_no_ext_tags
);
4950 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0141, quirk_no_ext_tags
);
4951 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0142, quirk_no_ext_tags
);
4952 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0144, quirk_no_ext_tags
);
4953 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0420, quirk_no_ext_tags
);
4954 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0422, quirk_no_ext_tags
);
4956 #ifdef CONFIG_PCI_ATS
4958 * Some devices have a broken ATS implementation causing IOMMU stalls.
4959 * Don't use ATS for those devices.
4961 static void quirk_no_ats(struct pci_dev
*pdev
)
4963 pci_info(pdev
, "disabling ATS (broken on this device)\n");
4967 /* AMD Stoney platform GPU */
4968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x98e4, quirk_no_ats
);
4969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6900, quirk_no_ats
);
4970 #endif /* CONFIG_PCI_ATS */
4972 /* Freescale PCIe doesn't support MSI in RC mode */
4973 static void quirk_fsl_no_msi(struct pci_dev
*pdev
)
4975 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
)
4978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, quirk_fsl_no_msi
);
4981 * Although not allowed by the spec, some multi-function devices have
4982 * dependencies of one function (consumer) on another (supplier). For the
4983 * consumer to work in D0, the supplier must also be in D0. Create a
4984 * device link from the consumer to the supplier to enforce this
4985 * dependency. Runtime PM is allowed by default on the consumer to prevent
4986 * it from permanently keeping the supplier awake.
4988 static void pci_create_device_link(struct pci_dev
*pdev
, unsigned int consumer
,
4989 unsigned int supplier
, unsigned int class,
4990 unsigned int class_shift
)
4992 struct pci_dev
*supplier_pdev
;
4994 if (PCI_FUNC(pdev
->devfn
) != consumer
)
4997 supplier_pdev
= pci_get_domain_bus_and_slot(pci_domain_nr(pdev
->bus
),
4999 PCI_DEVFN(PCI_SLOT(pdev
->devfn
), supplier
));
5000 if (!supplier_pdev
|| (supplier_pdev
->class >> class_shift
) != class) {
5001 pci_dev_put(supplier_pdev
);
5005 if (device_link_add(&pdev
->dev
, &supplier_pdev
->dev
,
5006 DL_FLAG_STATELESS
| DL_FLAG_PM_RUNTIME
))
5007 pci_info(pdev
, "D0 power state depends on %s\n",
5008 pci_name(supplier_pdev
));
5010 pci_err(pdev
, "Cannot enforce power dependency on %s\n",
5011 pci_name(supplier_pdev
));
5013 pm_runtime_allow(&pdev
->dev
);
5014 pci_dev_put(supplier_pdev
);
5018 * Create device link for GPUs with integrated HDA controller for streaming
5019 * audio to attached displays.
5021 static void quirk_gpu_hda(struct pci_dev
*hda
)
5023 pci_create_device_link(hda
, 1, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5025 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
5026 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5027 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
,
5028 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5029 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5030 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
5033 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5034 * controller to VGA.
5036 static void quirk_gpu_usb(struct pci_dev
*usb
)
5038 pci_create_device_link(usb
, 2, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5040 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5041 PCI_CLASS_SERIAL_USB
, 8, quirk_gpu_usb
);
5044 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5045 * to VGA. Currently there is no class code defined for UCSI device over PCI
5046 * so using UNKNOWN class for now and it will be updated when UCSI
5047 * over PCI gets a class code.
5049 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5050 static void quirk_gpu_usb_typec_ucsi(struct pci_dev
*ucsi
)
5052 pci_create_device_link(ucsi
, 3, 0, PCI_BASE_CLASS_DISPLAY
, 16);
5054 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5055 PCI_CLASS_SERIAL_UNKNOWN
, 8,
5056 quirk_gpu_usb_typec_ucsi
);
5059 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5060 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5062 static void quirk_nvidia_hda(struct pci_dev
*gpu
)
5067 /* There was no integrated HDA controller before MCP89 */
5068 if (gpu
->device
< PCI_DEVICE_ID_NVIDIA_GEFORCE_320M
)
5071 /* Bit 25 at offset 0x488 enables the HDA controller */
5072 pci_read_config_dword(gpu
, 0x488, &val
);
5076 pci_info(gpu
, "Enabling HDA controller\n");
5077 pci_write_config_dword(gpu
, 0x488, val
| BIT(25));
5079 /* The GPU becomes a multi-function device when the HDA is enabled */
5080 pci_read_config_byte(gpu
, PCI_HEADER_TYPE
, &hdr_type
);
5081 gpu
->multifunction
= !!(hdr_type
& 0x80);
5083 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5084 PCI_BASE_CLASS_DISPLAY
, 16, quirk_nvidia_hda
);
5085 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
5086 PCI_BASE_CLASS_DISPLAY
, 16, quirk_nvidia_hda
);
5089 * Some IDT switches incorrectly flag an ACS Source Validation error on
5090 * completions for config read requests even though PCIe r4.0, sec
5091 * 6.12.1.1, says that completions are never affected by ACS Source
5092 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5094 * Item #36 - Downstream port applies ACS Source Validation to Completions
5095 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5096 * completions are never affected by ACS Source Validation. However,
5097 * completions received by a downstream port of the PCIe switch from a
5098 * device that has not yet captured a PCIe bus number are incorrectly
5099 * dropped by ACS Source Validation by the switch downstream port.
5101 * The workaround suggested by IDT is to issue a config write to the
5102 * downstream device before issuing the first config read. This allows the
5103 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5104 * sec 2.2.9), thus avoiding the ACS error on the completion.
5106 * However, we don't know when the device is ready to accept the config
5107 * write, so we do config reads until we receive a non-Config Request Retry
5108 * Status, then do the config write.
5110 * To avoid hitting the erratum when doing the config reads, we disable ACS
5111 * SV around this process.
5113 int pci_idt_bus_quirk(struct pci_bus
*bus
, int devfn
, u32
*l
, int timeout
)
5118 struct pci_dev
*bridge
= bus
->self
;
5120 pos
= pci_find_ext_capability(bridge
, PCI_EXT_CAP_ID_ACS
);
5122 /* Disable ACS SV before initial config reads */
5124 pci_read_config_word(bridge
, pos
+ PCI_ACS_CTRL
, &ctrl
);
5125 if (ctrl
& PCI_ACS_SV
)
5126 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
,
5127 ctrl
& ~PCI_ACS_SV
);
5130 found
= pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
5132 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5134 pci_bus_write_config_word(bus
, devfn
, PCI_VENDOR_ID
, 0);
5136 /* Re-enable ACS_SV if it was previously enabled */
5137 if (ctrl
& PCI_ACS_SV
)
5138 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
, ctrl
);
5144 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5145 * NT endpoints via the internal switch fabric. These IDs replace the
5146 * originating requestor ID TLPs which access host memory on peer NTB
5147 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5148 * to permit access when the IOMMU is turned on.
5150 static void quirk_switchtec_ntb_dma_alias(struct pci_dev
*pdev
)
5153 struct ntb_info_regs __iomem
*mmio_ntb
;
5154 struct ntb_ctrl_regs __iomem
*mmio_ctrl
;
5159 if (pci_enable_device(pdev
)) {
5160 pci_err(pdev
, "Cannot enable Switchtec device\n");
5164 mmio
= pci_iomap(pdev
, 0, 0);
5166 pci_disable_device(pdev
);
5167 pci_err(pdev
, "Cannot iomap Switchtec device\n");
5171 pci_info(pdev
, "Setting Switchtec proxy ID aliases\n");
5173 mmio_ntb
= mmio
+ SWITCHTEC_GAS_NTB_OFFSET
;
5174 mmio_ctrl
= (void __iomem
*) mmio_ntb
+ SWITCHTEC_NTB_REG_CTRL_OFFSET
;
5176 partition
= ioread8(&mmio_ntb
->partition_id
);
5178 partition_map
= ioread32(&mmio_ntb
->ep_map
);
5179 partition_map
|= ((u64
) ioread32(&mmio_ntb
->ep_map
+ 4)) << 32;
5180 partition_map
&= ~(1ULL << partition
);
5182 for (pp
= 0; pp
< (sizeof(partition_map
) * 8); pp
++) {
5183 struct ntb_ctrl_regs __iomem
*mmio_peer_ctrl
;
5187 if (!(partition_map
& (1ULL << pp
)))
5190 pci_dbg(pdev
, "Processing partition %d\n", pp
);
5192 mmio_peer_ctrl
= &mmio_ctrl
[pp
];
5194 table_sz
= ioread16(&mmio_peer_ctrl
->req_id_table_size
);
5196 pci_warn(pdev
, "Partition %d table_sz 0\n", pp
);
5200 if (table_sz
> 512) {
5202 "Invalid Switchtec partition %d table_sz %d\n",
5207 for (te
= 0; te
< table_sz
; te
++) {
5211 rid_entry
= ioread32(&mmio_peer_ctrl
->req_id_table
[te
]);
5212 devfn
= (rid_entry
>> 1) & 0xFF;
5214 "Aliasing Partition %d Proxy ID %02x.%d\n",
5215 pp
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5216 pci_add_dma_alias(pdev
, devfn
);
5220 pci_iounmap(pdev
, mmio
);
5221 pci_disable_device(pdev
);
5223 #define SWITCHTEC_QUIRK(vid) \
5224 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5225 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5227 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5228 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5229 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5230 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5231 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5232 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5233 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5234 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5235 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5236 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5237 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5238 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5239 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5240 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5241 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5242 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5243 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5244 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5245 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5246 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5247 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5248 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5249 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5250 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5251 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5252 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5253 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5254 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5255 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5256 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5259 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5260 * not always reset the secondary Nvidia GPU between reboots if the system
5261 * is configured to use Hybrid Graphics mode. This results in the GPU
5262 * being left in whatever state it was in during the *previous* boot, which
5263 * causes spurious interrupts from the GPU, which in turn causes us to
5264 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5265 * this also completely breaks nouveau.
5267 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5268 * clean state and fixes all these issues.
5270 * When the machine is configured in Dedicated display mode, the issue
5271 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5272 * mode, so we can detect that and avoid resetting it.
5274 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev
*pdev
)
5279 if (pdev
->subsystem_vendor
!= PCI_VENDOR_ID_LENOVO
||
5280 pdev
->subsystem_device
!= 0x222e ||
5284 if (pci_enable_device_mem(pdev
))
5288 * Based on nvkm_device_ctor() in
5289 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5291 map
= pci_iomap(pdev
, 0, 0x23000);
5293 pci_err(pdev
, "Can't map MMIO space\n");
5298 * Make sure the GPU looks like it's been POSTed before resetting
5301 if (ioread32(map
+ 0x2240c) & 0x2) {
5302 pci_info(pdev
, FW_BUG
"GPU left initialized by EFI, resetting\n");
5303 ret
= pci_reset_bus(pdev
);
5305 pci_err(pdev
, "Failed to reset GPU: %d\n", ret
);
5310 pci_disable_device(pdev
);
5312 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, 0x13b1,
5313 PCI_CLASS_DISPLAY_VGA
, 8,
5314 quirk_reset_lenovo_thinkpad_p50_nvgpu
);
5317 * Device [1b21:2142]
5318 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5320 static void pci_fixup_no_d0_pme(struct pci_dev
*dev
)
5322 pci_info(dev
, "PME# does not work under D0, disabling it\n");
5323 dev
->pme_support
&= ~(PCI_PM_CAP_PME_D0
>> PCI_PM_CAP_PME_SHIFT
);
5325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA
, 0x2142, pci_fixup_no_d0_pme
);