1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
28 #include <linux/nvme.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/switchtec.h>
32 #include <asm/dma.h> /* isa_dma_bridge_buggy */
35 static ktime_t
fixup_debug_start(struct pci_dev
*dev
,
36 void (*fn
)(struct pci_dev
*dev
))
39 pci_info(dev
, "calling %pF @ %i\n", fn
, task_pid_nr(current
));
44 static void fixup_debug_report(struct pci_dev
*dev
, ktime_t calltime
,
45 void (*fn
)(struct pci_dev
*dev
))
47 ktime_t delta
, rettime
;
48 unsigned long long duration
;
50 rettime
= ktime_get();
51 delta
= ktime_sub(rettime
, calltime
);
52 duration
= (unsigned long long) ktime_to_ns(delta
) >> 10;
53 if (initcall_debug
|| duration
> 10000)
54 pci_info(dev
, "%pF took %lld usecs\n", fn
, duration
);
57 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
,
58 struct pci_fixup
*end
)
63 if ((f
->class == (u32
) (dev
->class >> f
->class_shift
) ||
64 f
->class == (u32
) PCI_ANY_ID
) &&
65 (f
->vendor
== dev
->vendor
||
66 f
->vendor
== (u16
) PCI_ANY_ID
) &&
67 (f
->device
== dev
->device
||
68 f
->device
== (u16
) PCI_ANY_ID
)) {
69 calltime
= fixup_debug_start(dev
, f
->hook
);
71 fixup_debug_report(dev
, calltime
, f
->hook
);
75 extern struct pci_fixup __start_pci_fixups_early
[];
76 extern struct pci_fixup __end_pci_fixups_early
[];
77 extern struct pci_fixup __start_pci_fixups_header
[];
78 extern struct pci_fixup __end_pci_fixups_header
[];
79 extern struct pci_fixup __start_pci_fixups_final
[];
80 extern struct pci_fixup __end_pci_fixups_final
[];
81 extern struct pci_fixup __start_pci_fixups_enable
[];
82 extern struct pci_fixup __end_pci_fixups_enable
[];
83 extern struct pci_fixup __start_pci_fixups_resume
[];
84 extern struct pci_fixup __end_pci_fixups_resume
[];
85 extern struct pci_fixup __start_pci_fixups_resume_early
[];
86 extern struct pci_fixup __end_pci_fixups_resume_early
[];
87 extern struct pci_fixup __start_pci_fixups_suspend
[];
88 extern struct pci_fixup __end_pci_fixups_suspend
[];
89 extern struct pci_fixup __start_pci_fixups_suspend_late
[];
90 extern struct pci_fixup __end_pci_fixups_suspend_late
[];
92 static bool pci_apply_fixup_final_quirks
;
94 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
96 struct pci_fixup
*start
, *end
;
100 start
= __start_pci_fixups_early
;
101 end
= __end_pci_fixups_early
;
104 case pci_fixup_header
:
105 start
= __start_pci_fixups_header
;
106 end
= __end_pci_fixups_header
;
109 case pci_fixup_final
:
110 if (!pci_apply_fixup_final_quirks
)
112 start
= __start_pci_fixups_final
;
113 end
= __end_pci_fixups_final
;
116 case pci_fixup_enable
:
117 start
= __start_pci_fixups_enable
;
118 end
= __end_pci_fixups_enable
;
121 case pci_fixup_resume
:
122 start
= __start_pci_fixups_resume
;
123 end
= __end_pci_fixups_resume
;
126 case pci_fixup_resume_early
:
127 start
= __start_pci_fixups_resume_early
;
128 end
= __end_pci_fixups_resume_early
;
131 case pci_fixup_suspend
:
132 start
= __start_pci_fixups_suspend
;
133 end
= __end_pci_fixups_suspend
;
136 case pci_fixup_suspend_late
:
137 start
= __start_pci_fixups_suspend_late
;
138 end
= __end_pci_fixups_suspend_late
;
142 /* stupid compiler warning, you would think with an enum... */
145 pci_do_fixups(dev
, start
, end
);
147 EXPORT_SYMBOL(pci_fixup_device
);
149 static int __init
pci_apply_final_quirks(void)
151 struct pci_dev
*dev
= NULL
;
155 if (pci_cache_line_size
)
156 printk(KERN_DEBUG
"PCI: CLS %u bytes\n",
157 pci_cache_line_size
<< 2);
159 pci_apply_fixup_final_quirks
= true;
160 for_each_pci_dev(dev
) {
161 pci_fixup_device(pci_fixup_final
, dev
);
163 * If arch hasn't set it explicitly yet, use the CLS
164 * value shared by all PCI devices. If there's a
165 * mismatch, fall back to the default value.
167 if (!pci_cache_line_size
) {
168 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &tmp
);
171 if (!tmp
|| cls
== tmp
)
174 printk(KERN_DEBUG
"PCI: CLS mismatch (%u != %u), using %u bytes\n",
176 pci_dfl_cache_line_size
<< 2);
177 pci_cache_line_size
= pci_dfl_cache_line_size
;
181 if (!pci_cache_line_size
) {
182 printk(KERN_DEBUG
"PCI: CLS %u bytes, default %u\n",
183 cls
<< 2, pci_dfl_cache_line_size
<< 2);
184 pci_cache_line_size
= cls
? cls
: pci_dfl_cache_line_size
;
189 fs_initcall_sync(pci_apply_final_quirks
);
192 * Decoding should be disabled for a PCI device during BAR sizing to avoid
193 * conflict. But doing so may cause problems on host bridge and perhaps other
194 * key system devices. For devices that need to have mmio decoding always-on,
195 * we need to set the dev->mmio_always_on bit.
197 static void quirk_mmio_always_on(struct pci_dev
*dev
)
199 dev
->mmio_always_on
= 1;
201 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
202 PCI_CLASS_BRIDGE_HOST
, 8, quirk_mmio_always_on
);
205 * The Mellanox Tavor device gives false positive parity errors. Mark this
206 * device with a broken_parity_status to allow PCI scanning code to "skip"
207 * this now blacklisted device.
209 static void quirk_mellanox_tavor(struct pci_dev
*dev
)
211 dev
->broken_parity_status
= 1; /* This device gives false positives */
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR
, quirk_mellanox_tavor
);
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
, quirk_mellanox_tavor
);
217 * Deal with broken BIOSes that neglect to enable passive release,
218 * which can cause problems in combination with the 82441FX/PPro MTRRs
220 static void quirk_passive_release(struct pci_dev
*dev
)
222 struct pci_dev
*d
= NULL
;
226 * We have to make sure a particular bit is set in the PIIX3
227 * ISA bridge, so we have to go out and find it.
229 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
230 pci_read_config_byte(d
, 0x82, &dlc
);
232 pci_info(d
, "PIIX3: Enabling Passive Release\n");
234 pci_write_config_byte(d
, 0x82, dlc
);
238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
242 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
243 * workaround but VIA don't answer queries. If you happen to have good
244 * contacts at VIA ask them for me please -- Alan
246 * This appears to be BIOS not version dependent. So presumably there is a
249 static void quirk_isa_dma_hangs(struct pci_dev
*dev
)
251 if (!isa_dma_bridge_buggy
) {
252 isa_dma_bridge_buggy
= 1;
253 pci_info(dev
, "Activating ISA DMA hang workarounds\n");
257 * It's not totally clear which chipsets are the problematic ones. We know
258 * 82C586 and 82C596 variants are affected.
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
269 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
270 * for some HT machines to use C4 w/o hanging.
272 static void quirk_tigerpoint_bm_sts(struct pci_dev
*dev
)
277 pci_read_config_dword(dev
, 0x40, &pmbase
);
278 pmbase
= pmbase
& 0xff80;
282 pci_info(dev
, FW_BUG
"TigerPoint LPC.BM_STS cleared\n");
286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_TGP_LPC
, quirk_tigerpoint_bm_sts
);
288 /* Chipsets where PCI->PCI transfers vanish or hang */
289 static void quirk_nopcipci(struct pci_dev
*dev
)
291 if ((pci_pci_problems
& PCIPCI_FAIL
) == 0) {
292 pci_info(dev
, "Disabling direct PCI/PCI transfers\n");
293 pci_pci_problems
|= PCIPCI_FAIL
;
296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
299 static void quirk_nopciamd(struct pci_dev
*dev
)
302 pci_read_config_byte(dev
, 0x08, &rev
);
305 pci_info(dev
, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
306 pci_pci_problems
|= PCIAGP_FAIL
;
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
311 /* Triton requires workarounds to be used by the drivers */
312 static void quirk_triton(struct pci_dev
*dev
)
314 if ((pci_pci_problems
&PCIPCI_TRITON
) == 0) {
315 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
316 pci_pci_problems
|= PCIPCI_TRITON
;
319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
325 * VIA Apollo KT133 needs PCI latency patch
326 * Made according to a Windows driver-based patch by George E. Breese;
327 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
328 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
329 * which Mr Breese based his work.
331 * Updated based on further information from the site and also on
332 * information provided by VIA
334 static void quirk_vialatency(struct pci_dev
*dev
)
340 * Ok, we have a potential problem chipset here. Now see if we have
341 * a buggy southbridge.
343 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
347 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
349 * Check for buggy part revisions
351 if (p
->revision
< 0x40 || p
->revision
> 0x42)
354 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
355 if (p
== NULL
) /* No problem parts */
358 /* Check for buggy part revisions */
359 if (p
->revision
< 0x10 || p
->revision
> 0x12)
364 * Ok we have the problem. Now set the PCI master grant to occur
365 * every master grant. The apparent bug is that under high PCI load
366 * (quite common in Linux of course) you can get data loss when the
367 * CPU is held off the bus for 3 bus master requests. This happens
368 * to include the IDE controllers....
370 * VIA only apply this fix when an SB Live! is present but under
371 * both Linux and Windows this isn't enough, and we have seen
372 * corruption without SB Live! but with things like 3 UDMA IDE
373 * controllers. So we ignore that bit of the VIA recommendation..
375 pci_read_config_byte(dev
, 0x76, &busarb
);
378 * Set bit 4 and bit 5 of byte 76 to 0x01
379 * "Master priority rotation on every PCI master grant"
383 pci_write_config_byte(dev
, 0x76, busarb
);
384 pci_info(dev
, "Applying VIA southbridge workaround\n");
388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
391 /* Must restore this on a resume from RAM */
392 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
393 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
394 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
396 /* VIA Apollo VP3 needs ETBF on BT848/878 */
397 static void quirk_viaetbf(struct pci_dev
*dev
)
399 if ((pci_pci_problems
&PCIPCI_VIAETBF
) == 0) {
400 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
401 pci_pci_problems
|= PCIPCI_VIAETBF
;
404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
406 static void quirk_vsfx(struct pci_dev
*dev
)
408 if ((pci_pci_problems
&PCIPCI_VSFX
) == 0) {
409 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
410 pci_pci_problems
|= PCIPCI_VSFX
;
413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
416 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
417 * space. Latency must be set to 0xA and Triton workaround applied too.
418 * [Info kindly provided by ALi]
420 static void quirk_alimagik(struct pci_dev
*dev
)
422 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
) == 0) {
423 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
424 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
430 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
431 static void quirk_natoma(struct pci_dev
*dev
)
433 if ((pci_pci_problems
&PCIPCI_NATOMA
) == 0) {
434 pci_info(dev
, "Limiting direct PCI/PCI transfers\n");
435 pci_pci_problems
|= PCIPCI_NATOMA
;
438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
446 * This chip can cause PCI parity errors if config register 0xA0 is read
447 * while DMAs are occurring.
449 static void quirk_citrine(struct pci_dev
*dev
)
451 dev
->cfg_size
= 0xA0;
453 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
456 * This chip can cause bus lockups if config addresses above 0x600
457 * are read or written.
459 static void quirk_nfp6000(struct pci_dev
*dev
)
461 dev
->cfg_size
= 0x600;
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP4000
, quirk_nfp6000
);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000
, quirk_nfp6000
);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP5000
, quirk_nfp6000
);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME
, PCI_DEVICE_ID_NETRONOME_NFP6000_VF
, quirk_nfp6000
);
468 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
469 static void quirk_extend_bar_to_page(struct pci_dev
*dev
)
473 for (i
= 0; i
<= PCI_STD_RESOURCE_END
; i
++) {
474 struct resource
*r
= &dev
->resource
[i
];
476 if (r
->flags
& IORESOURCE_MEM
&& resource_size(r
) < PAGE_SIZE
) {
477 r
->end
= PAGE_SIZE
- 1;
479 r
->flags
|= IORESOURCE_UNSET
;
480 pci_info(dev
, "expanded BAR %d to page size: %pR\n",
485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, 0x034a, quirk_extend_bar_to_page
);
488 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
489 * If it's needed, re-allocate the region.
491 static void quirk_s3_64M(struct pci_dev
*dev
)
493 struct resource
*r
= &dev
->resource
[0];
495 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
496 r
->flags
|= IORESOURCE_UNSET
;
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
504 static void quirk_io(struct pci_dev
*dev
, int pos
, unsigned size
,
508 struct pci_bus_region bus_region
;
509 struct resource
*res
= dev
->resource
+ pos
;
511 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), ®ion
);
516 res
->name
= pci_name(dev
);
517 res
->flags
= region
& ~PCI_BASE_ADDRESS_IO_MASK
;
519 (IORESOURCE_IO
| IORESOURCE_PCI_FIXED
| IORESOURCE_SIZEALIGN
);
520 region
&= ~(size
- 1);
522 /* Convert from PCI bus to resource space */
523 bus_region
.start
= region
;
524 bus_region
.end
= region
+ size
- 1;
525 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
527 pci_info(dev
, FW_BUG
"%s quirk: reg 0x%x: %pR\n",
528 name
, PCI_BASE_ADDRESS_0
+ (pos
<< 2), res
);
532 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
533 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
534 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
535 * (which conflicts w/ BAR1's memory range).
537 * CS553x's ISA PCI BARs may also be read-only (ref:
538 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
540 static void quirk_cs5536_vsa(struct pci_dev
*dev
)
542 static char *name
= "CS5536 ISA bridge";
544 if (pci_resource_len(dev
, 0) != 8) {
545 quirk_io(dev
, 0, 8, name
); /* SMB */
546 quirk_io(dev
, 1, 256, name
); /* GPIO */
547 quirk_io(dev
, 2, 64, name
); /* MFGPT */
548 pci_info(dev
, "%s bug detected (incorrect header); workaround applied\n",
552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_CS5536_ISA
, quirk_cs5536_vsa
);
554 static void quirk_io_region(struct pci_dev
*dev
, int port
,
555 unsigned size
, int nr
, const char *name
)
558 struct pci_bus_region bus_region
;
559 struct resource
*res
= dev
->resource
+ nr
;
561 pci_read_config_word(dev
, port
, ®ion
);
562 region
&= ~(size
- 1);
567 res
->name
= pci_name(dev
);
568 res
->flags
= IORESOURCE_IO
;
570 /* Convert from PCI bus to resource space */
571 bus_region
.start
= region
;
572 bus_region
.end
= region
+ size
- 1;
573 pcibios_bus_to_resource(dev
->bus
, res
, &bus_region
);
575 if (!pci_claim_resource(dev
, nr
))
576 pci_info(dev
, "quirk: %pR claimed by %s\n", res
, name
);
580 * ATI Northbridge setups MCE the processor if you even read somewhere
581 * between 0x3b0->0x3bb or read 0x3d3
583 static void quirk_ati_exploding_mce(struct pci_dev
*dev
)
585 pci_info(dev
, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
586 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
587 request_region(0x3b0, 0x0C, "RadeonIGP");
588 request_region(0x3d3, 0x01, "RadeonIGP");
590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
593 * In the AMD NL platform, this device ([1022:7912]) has a class code of
594 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
597 * But the dwc3 driver is a more specific driver for this device, and we'd
598 * prefer to use it instead of xhci. To prevent xhci from claiming the
599 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
600 * defines as "USB device (not host controller)". The dwc3 driver can then
601 * claim it based on its Vendor and Device ID.
603 static void quirk_amd_nl_class(struct pci_dev
*pdev
)
605 u32
class = pdev
->class;
607 /* Use "USB Device (not host controller)" class */
608 pdev
->class = PCI_CLASS_SERIAL_USB_DEVICE
;
609 pci_info(pdev
, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_NL_USB
,
616 * Let's make the southbridge information explicit instead of having to
617 * worry about people probing the ACPI areas, for example.. (Yes, it
618 * happens, and if you read the wrong ACPI register it will put the machine
619 * to sleep with no way of waking it up again. Bummer).
621 * ALI M7101: Two IO regions pointed to by words at
622 * 0xE0 (64 bytes of ACPI registers)
623 * 0xE2 (32 bytes of SMB registers)
625 static void quirk_ali7101_acpi(struct pci_dev
*dev
)
627 quirk_io_region(dev
, 0xE0, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
628 quirk_io_region(dev
, 0xE2, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
632 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
635 u32 mask
, size
, base
;
637 pci_read_config_dword(dev
, port
, &devres
);
638 if ((devres
& enable
) != enable
)
640 mask
= (devres
>> 16) & 15;
641 base
= devres
& 0xffff;
644 unsigned bit
= size
>> 1;
645 if ((bit
& mask
) == bit
)
650 * For now we only print it out. Eventually we'll want to
651 * reserve it (at least if it's in the 0x1000+ range), but
652 * let's get enough confirmation reports first.
655 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
658 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
661 u32 mask
, size
, base
;
663 pci_read_config_dword(dev
, port
, &devres
);
664 if ((devres
& enable
) != enable
)
666 base
= devres
& 0xffff0000;
667 mask
= (devres
& 0x3f) << 16;
670 unsigned bit
= size
>> 1;
671 if ((bit
& mask
) == bit
)
677 * For now we only print it out. Eventually we'll want to
678 * reserve it, but let's get enough confirmation reports first.
681 pci_info(dev
, "%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
685 * PIIX4 ACPI: Two IO regions pointed to by longwords at
686 * 0x40 (64 bytes of ACPI registers)
687 * 0x90 (16 bytes of SMB registers)
688 * and a few strange programmable PIIX4 device resources.
690 static void quirk_piix4_acpi(struct pci_dev
*dev
)
694 quirk_io_region(dev
, 0x40, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
695 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
697 /* Device resource A has enables for some of the other ones */
698 pci_read_config_dword(dev
, 0x5c, &res_a
);
700 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
701 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
703 /* Device resource D is just bitfields for static resources */
705 /* Device 12 enabled? */
706 if (res_a
& (1 << 29)) {
707 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
708 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
710 /* Device 13 enabled? */
711 if (res_a
& (1 << 30)) {
712 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
713 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
715 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
716 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
721 #define ICH_PMBASE 0x40
722 #define ICH_ACPI_CNTL 0x44
723 #define ICH4_ACPI_EN 0x10
724 #define ICH6_ACPI_EN 0x80
725 #define ICH4_GPIOBASE 0x58
726 #define ICH4_GPIO_CNTL 0x5c
727 #define ICH4_GPIO_EN 0x10
728 #define ICH6_GPIOBASE 0x48
729 #define ICH6_GPIO_CNTL 0x4c
730 #define ICH6_GPIO_EN 0x10
733 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
734 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
735 * 0x58 (64 bytes of GPIO I/O space)
737 static void quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
742 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
743 * with low legacy (and fixed) ports. We don't know the decoding
744 * priority and can't tell whether the legacy device or the one created
745 * here is really at that address. This happens on boards with broken
748 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
749 if (enable
& ICH4_ACPI_EN
)
750 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
751 "ICH4 ACPI/GPIO/TCO");
753 pci_read_config_byte(dev
, ICH4_GPIO_CNTL
, &enable
);
754 if (enable
& ICH4_GPIO_EN
)
755 quirk_io_region(dev
, ICH4_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
760 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
766 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
769 static void ich6_lpc_acpi_gpio(struct pci_dev
*dev
)
773 pci_read_config_byte(dev
, ICH_ACPI_CNTL
, &enable
);
774 if (enable
& ICH6_ACPI_EN
)
775 quirk_io_region(dev
, ICH_PMBASE
, 128, PCI_BRIDGE_RESOURCES
,
776 "ICH6 ACPI/GPIO/TCO");
778 pci_read_config_byte(dev
, ICH6_GPIO_CNTL
, &enable
);
779 if (enable
& ICH6_GPIO_EN
)
780 quirk_io_region(dev
, ICH6_GPIOBASE
, 64, PCI_BRIDGE_RESOURCES
+1,
784 static void ich6_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
785 const char *name
, int dynsize
)
790 pci_read_config_dword(dev
, reg
, &val
);
798 * This is not correct. It is 16, 32 or 64 bytes depending on
799 * register D31:F0:ADh bits 5:4.
801 * But this gets us at least _part_ of it.
810 * Just print it out for now. We should reserve it after more
813 pci_info(dev
, "%s PIO at %04x-%04x\n", name
, base
, base
+size
-1);
816 static void quirk_ich6_lpc(struct pci_dev
*dev
)
818 /* Shared ACPI/GPIO decode with all ICH6+ */
819 ich6_lpc_acpi_gpio(dev
);
821 /* ICH6-specific generic IO decode */
822 ich6_lpc_generic_decode(dev
, 0x84, "LPC Generic IO decode 1", 0);
823 ich6_lpc_generic_decode(dev
, 0x88, "LPC Generic IO decode 2", 1);
825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc
);
826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc
);
828 static void ich7_lpc_generic_decode(struct pci_dev
*dev
, unsigned reg
,
834 pci_read_config_dword(dev
, reg
, &val
);
840 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
842 mask
= (val
>> 16) & 0xfc;
846 * Just print it out for now. We should reserve it after more
849 pci_info(dev
, "%s PIO at %04x (mask %04x)\n", name
, base
, mask
);
852 /* ICH7-10 has the same common LPC generic IO decode registers */
853 static void quirk_ich7_lpc(struct pci_dev
*dev
)
855 /* We share the common ACPI/GPIO decode with ICH6 */
856 ich6_lpc_acpi_gpio(dev
);
858 /* And have 4 ICH7+ generic decodes */
859 ich7_lpc_generic_decode(dev
, 0x84, "ICH7 LPC Generic IO decode 1");
860 ich7_lpc_generic_decode(dev
, 0x88, "ICH7 LPC Generic IO decode 2");
861 ich7_lpc_generic_decode(dev
, 0x8c, "ICH7 LPC Generic IO decode 3");
862 ich7_lpc_generic_decode(dev
, 0x90, "ICH7 LPC Generic IO decode 4");
864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich7_lpc
);
865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich7_lpc
);
866 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich7_lpc
);
867 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich7_lpc
);
868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich7_lpc
);
869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich7_lpc
);
870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
, quirk_ich7_lpc
);
871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
, quirk_ich7_lpc
);
872 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_2
, quirk_ich7_lpc
);
873 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_4
, quirk_ich7_lpc
);
874 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
, quirk_ich7_lpc
);
875 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_8
, quirk_ich7_lpc
);
876 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH10_1
, quirk_ich7_lpc
);
879 * VIA ACPI: One IO region pointed to by longword at
880 * 0x48 or 0x20 (256 bytes of ACPI registers)
882 static void quirk_vt82c586_acpi(struct pci_dev
*dev
)
884 if (dev
->revision
& 0x10)
885 quirk_io_region(dev
, 0x48, 256, PCI_BRIDGE_RESOURCES
,
888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
891 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
892 * 0x48 (256 bytes of ACPI registers)
893 * 0x70 (128 bytes of hardware monitoring register)
894 * 0x90 (16 bytes of SMB registers)
896 static void quirk_vt82c686_acpi(struct pci_dev
*dev
)
898 quirk_vt82c586_acpi(dev
);
900 quirk_io_region(dev
, 0x70, 128, PCI_BRIDGE_RESOURCES
+1,
903 quirk_io_region(dev
, 0x90, 16, PCI_BRIDGE_RESOURCES
+2, "vt82c686 SMB");
905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
908 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
909 * 0x88 (128 bytes of power management registers)
910 * 0xd0 (16 bytes of SMB registers)
912 static void quirk_vt8235_acpi(struct pci_dev
*dev
)
914 quirk_io_region(dev
, 0x88, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
915 quirk_io_region(dev
, 0xd0, 16, PCI_BRIDGE_RESOURCES
+1, "vt8235 SMB");
917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
920 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
921 * back-to-back: Disable fast back-to-back on the secondary bus segment
923 static void quirk_xio2000a(struct pci_dev
*dev
)
925 struct pci_dev
*pdev
;
928 pci_warn(dev
, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
929 list_for_each_entry(pdev
, &dev
->subordinate
->devices
, bus_list
) {
930 pci_read_config_word(pdev
, PCI_COMMAND
, &command
);
931 if (command
& PCI_COMMAND_FAST_BACK
)
932 pci_write_config_word(pdev
, PCI_COMMAND
, command
& ~PCI_COMMAND_FAST_BACK
);
935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_XIO2000A
,
938 #ifdef CONFIG_X86_IO_APIC
940 #include <asm/io_apic.h>
943 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
944 * devices to the external APIC.
946 * TODO: When we have device-specific interrupt routers, this code will go
949 static void quirk_via_ioapic(struct pci_dev
*dev
)
954 tmp
= 0; /* nothing routed to external APIC */
956 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
958 pci_info(dev
, "%sbling VIA external APIC routing\n",
959 tmp
== 0 ? "Disa" : "Ena");
961 /* Offset 0x58: External APIC IRQ output control */
962 pci_write_config_byte(dev
, 0x58, tmp
);
964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
965 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
968 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
969 * This leads to doubled level interrupt rates.
970 * Set this bit to get rid of cycle wastage.
971 * Otherwise uncritical.
973 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
976 #define BYPASS_APIC_DEASSERT 8
978 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
979 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
980 pci_info(dev
, "Bypassing VIA 8237 APIC De-Assert Message\n");
981 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
985 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
988 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
989 * We check all revs >= B0 (yet not in the pre production!) as the bug
990 * is currently marked NoFix
992 * We have multiple reports of hangs with this chipset that went away with
993 * noapic specified. For the moment we assume it's the erratum. We may be wrong
994 * of course. However the advice is demonstrably good even if so.
996 static void quirk_amd_ioapic(struct pci_dev
*dev
)
998 if (dev
->revision
>= 0x02) {
999 pci_warn(dev
, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1000 pci_warn(dev
, " : booting with the \"noapic\" option\n");
1003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
1004 #endif /* CONFIG_X86_IO_APIC */
1006 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1008 static void quirk_cavium_sriov_rnm_link(struct pci_dev
*dev
)
1010 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1011 if (dev
->subsystem_device
== 0xa118)
1012 dev
->sriov
->link
= dev
->devfn
;
1014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM
, 0xa018, quirk_cavium_sriov_rnm_link
);
1018 * Some settings of MMRBC can lead to data corruption so block changes.
1019 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1021 static void quirk_amd_8131_mmrbc(struct pci_dev
*dev
)
1023 if (dev
->subordinate
&& dev
->revision
<= 0x12) {
1024 pci_info(dev
, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1026 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MMRBC
;
1029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_mmrbc
);
1032 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1033 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1034 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1035 * of the ACPI SCI interrupt is only done for convenience.
1038 static void quirk_via_acpi(struct pci_dev
*d
)
1042 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1043 pci_read_config_byte(d
, 0x42, &irq
);
1045 if (irq
&& (irq
!= 2))
1048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
1049 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
1051 /* VIA bridges which have VLink */
1052 static int via_vlink_dev_lo
= -1, via_vlink_dev_hi
= 18;
1054 static void quirk_via_bridge(struct pci_dev
*dev
)
1056 /* See what bridge we have and find the device ranges */
1057 switch (dev
->device
) {
1058 case PCI_DEVICE_ID_VIA_82C686
:
1060 * The VT82C686 is special; it attaches to PCI and can have
1061 * any device number. All its subdevices are functions of
1062 * that single device.
1064 via_vlink_dev_lo
= PCI_SLOT(dev
->devfn
);
1065 via_vlink_dev_hi
= PCI_SLOT(dev
->devfn
);
1067 case PCI_DEVICE_ID_VIA_8237
:
1068 case PCI_DEVICE_ID_VIA_8237A
:
1069 via_vlink_dev_lo
= 15;
1071 case PCI_DEVICE_ID_VIA_8235
:
1072 via_vlink_dev_lo
= 16;
1074 case PCI_DEVICE_ID_VIA_8231
:
1075 case PCI_DEVICE_ID_VIA_8233_0
:
1076 case PCI_DEVICE_ID_VIA_8233A
:
1077 case PCI_DEVICE_ID_VIA_8233C_0
:
1078 via_vlink_dev_lo
= 17;
1082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_bridge
);
1083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, quirk_via_bridge
);
1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233_0
, quirk_via_bridge
);
1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233A
, quirk_via_bridge
);
1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8233C_0
, quirk_via_bridge
);
1087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_bridge
);
1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_bridge
);
1089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237A
, quirk_via_bridge
);
1092 * quirk_via_vlink - VIA VLink IRQ number update
1095 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1096 * the IRQ line register which usually is not relevant for PCI cards, is
1097 * actually written so that interrupts get sent to the right place.
1099 * We only do this on systems where a VIA south bridge was detected, and
1100 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1102 static void quirk_via_vlink(struct pci_dev
*dev
)
1106 /* Check if we have VLink at all */
1107 if (via_vlink_dev_lo
== -1)
1112 /* Don't quirk interrupts outside the legacy IRQ range */
1113 if (!new_irq
|| new_irq
> 15)
1116 /* Internal device ? */
1117 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > via_vlink_dev_hi
||
1118 PCI_SLOT(dev
->devfn
) < via_vlink_dev_lo
)
1122 * This is an internal VLink device on a PIC interrupt. The BIOS
1123 * ought to have set this but may not have, so we redo it.
1125 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1126 if (new_irq
!= irq
) {
1127 pci_info(dev
, "VIA VLink IRQ fixup, from %d to %d\n",
1129 udelay(15); /* unknown if delay really needed */
1130 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
1133 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
1136 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1137 * of VT82C597 for backward compatibility. We need to switch it off to be
1138 * able to recognize the real type of the chip.
1140 static void quirk_vt82c598_id(struct pci_dev
*dev
)
1142 pci_write_config_byte(dev
, 0xfc, 0);
1143 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
1145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
1148 * CardBus controllers have a legacy base address that enables them to
1149 * respond as i82365 pcmcia controllers. We don't want them to do this
1150 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1151 * driver does not (and should not) handle CardBus.
1153 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
1155 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
1157 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1158 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1159 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID
, PCI_ANY_ID
,
1160 PCI_CLASS_BRIDGE_CARDBUS
, 8, quirk_cardbus_legacy
);
1163 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1164 * what the designers were smoking but let's not inhale...
1166 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1169 static void quirk_amd_ordering(struct pci_dev
*dev
)
1172 pci_read_config_dword(dev
, 0x4C, &pcic
);
1173 if ((pcic
& 6) != 6) {
1175 pci_warn(dev
, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1176 pci_write_config_dword(dev
, 0x4C, pcic
);
1177 pci_read_config_dword(dev
, 0x84, &pcic
);
1178 pcic
|= (1 << 23); /* Required in this mode */
1179 pci_write_config_dword(dev
, 0x84, pcic
);
1182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1183 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
1186 * DreamWorks-provided workaround for Dunord I-3000 problem
1188 * This card decodes and responds to addresses not apparently assigned to
1189 * it. We force a larger allocation to ensure that nothing gets put too
1192 static void quirk_dunord(struct pci_dev
*dev
)
1194 struct resource
*r
= &dev
->resource
[1];
1196 r
->flags
|= IORESOURCE_UNSET
;
1200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
1203 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1204 * decoding (transparent), and does indicate this in the ProgIf.
1205 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1207 static void quirk_transparent_bridge(struct pci_dev
*dev
)
1209 dev
->transparent
= 1;
1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
1215 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1216 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1217 * found at http://www.national.com/analog for info on what these bits do.
1218 * <christer@weinigel.se>
1220 static void quirk_mediagx_master(struct pci_dev
*dev
)
1224 pci_read_config_byte(dev
, 0x41, ®
);
1227 pci_info(dev
, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1229 pci_write_config_byte(dev
, 0x41, reg
);
1232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1233 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
1236 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1237 * in the odd case it is not the results are corruption hence the presence
1240 static void quirk_disable_pxb(struct pci_dev
*pdev
)
1244 if (pdev
->revision
!= 0x04) /* Only C0 requires this */
1246 pci_read_config_word(pdev
, 0x40, &config
);
1247 if (config
& (1<<6)) {
1249 pci_write_config_word(pdev
, 0x40, config
);
1250 pci_info(pdev
, "C0 revision 450NX. Disabling PCI restreaming\n");
1253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1254 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
1256 static void quirk_amd_ide_mode(struct pci_dev
*pdev
)
1258 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1261 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &tmp
);
1263 pci_read_config_byte(pdev
, 0x40, &tmp
);
1264 pci_write_config_byte(pdev
, 0x40, tmp
|1);
1265 pci_write_config_byte(pdev
, 0x9, 1);
1266 pci_write_config_byte(pdev
, 0xa, 6);
1267 pci_write_config_byte(pdev
, 0x40, tmp
);
1269 pdev
->class = PCI_CLASS_STORAGE_SATA_AHCI
;
1270 pci_info(pdev
, "set SATA to AHCI mode\n");
1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1274 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_amd_ide_mode
);
1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1276 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP700_SATA
, quirk_amd_ide_mode
);
1277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1278 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
, quirk_amd_ide_mode
);
1279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1280 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD
, 0x7900, quirk_amd_ide_mode
);
1282 /* Serverworks CSB5 IDE does not fully support native mode */
1283 static void quirk_svwks_csb5ide(struct pci_dev
*pdev
)
1286 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1290 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1291 /* PCI layer will sort out resources */
1294 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
1296 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1297 static void quirk_ide_samemode(struct pci_dev
*pdev
)
1301 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1303 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
1304 pci_info(pdev
, "IDE mode mismatch; forcing legacy mode\n");
1307 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
1310 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
1312 /* Some ATA devices break if put into D3 */
1313 static void quirk_no_ata_d3(struct pci_dev
*pdev
)
1315 pdev
->dev_flags
|= PCI_DEV_FLAGS_NO_D3
;
1317 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1318 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_ANY_ID
,
1319 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1320 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
1321 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1322 /* ALi loses some register settings that we cannot then restore */
1323 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
,
1324 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1325 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1326 occur when mode detecting */
1327 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
,
1328 PCI_CLASS_STORAGE_IDE
, 8, quirk_no_ata_d3
);
1331 * This was originally an Alpha-specific thing, but it really fits here.
1332 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1334 static void quirk_eisa_bridge(struct pci_dev
*dev
)
1336 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
1341 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1342 * is not activated. The myth is that Asus said that they do not want the
1343 * users to be irritated by just another PCI Device in the Win98 device
1344 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1345 * package 2.7.0 for details)
1347 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1348 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1349 * becomes necessary to do this tweak in two steps -- the chosen trigger
1350 * is either the Host bridge (preferred) or on-board VGA controller.
1352 * Note that we used to unhide the SMBus that way on Toshiba laptops
1353 * (Satellite A40 and Tecra M2) but then found that the thermal management
1354 * was done by SMM code, which could cause unsynchronized concurrent
1355 * accesses to the SMBus registers, with potentially bad effects. Thus you
1356 * should be very careful when adding new entries: if SMM is accessing the
1357 * Intel SMBus, this is a very good reason to leave it hidden.
1359 * Likewise, many recent laptops use ACPI for thermal management. If the
1360 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1361 * natively, and keeping the SMBus hidden is the right thing to do. If you
1362 * are about to add an entry in the table below, please first disassemble
1363 * the DSDT and double-check that there is no code accessing the SMBus.
1365 static int asus_hides_smbus
;
1367 static void asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
1369 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1370 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
1371 switch (dev
->subsystem_device
) {
1372 case 0x8025: /* P4B-LX */
1373 case 0x8070: /* P4B */
1374 case 0x8088: /* P4B533 */
1375 case 0x1626: /* L3C notebook */
1376 asus_hides_smbus
= 1;
1378 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
1379 switch (dev
->subsystem_device
) {
1380 case 0x80b1: /* P4GE-V */
1381 case 0x80b2: /* P4PE */
1382 case 0x8093: /* P4B533-V */
1383 asus_hides_smbus
= 1;
1385 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
1386 switch (dev
->subsystem_device
) {
1387 case 0x8030: /* P4T533 */
1388 asus_hides_smbus
= 1;
1390 else if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
1391 switch (dev
->subsystem_device
) {
1392 case 0x8070: /* P4G8X Deluxe */
1393 asus_hides_smbus
= 1;
1395 else if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
1396 switch (dev
->subsystem_device
) {
1397 case 0x80c9: /* PU-DLS */
1398 asus_hides_smbus
= 1;
1400 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1401 switch (dev
->subsystem_device
) {
1402 case 0x1751: /* M2N notebook */
1403 case 0x1821: /* M5N notebook */
1404 case 0x1897: /* A6L notebook */
1405 asus_hides_smbus
= 1;
1407 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1408 switch (dev
->subsystem_device
) {
1409 case 0x184b: /* W1N notebook */
1410 case 0x186a: /* M6Ne notebook */
1411 asus_hides_smbus
= 1;
1413 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1414 switch (dev
->subsystem_device
) {
1415 case 0x80f2: /* P4P800-X */
1416 asus_hides_smbus
= 1;
1418 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
)
1419 switch (dev
->subsystem_device
) {
1420 case 0x1882: /* M6V notebook */
1421 case 0x1977: /* A6VA notebook */
1422 asus_hides_smbus
= 1;
1424 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1425 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1426 switch (dev
->subsystem_device
) {
1427 case 0x088C: /* HP Compaq nc8000 */
1428 case 0x0890: /* HP Compaq nc6000 */
1429 asus_hides_smbus
= 1;
1431 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1432 switch (dev
->subsystem_device
) {
1433 case 0x12bc: /* HP D330L */
1434 case 0x12bd: /* HP D530 */
1435 case 0x006a: /* HP Compaq nx9500 */
1436 asus_hides_smbus
= 1;
1438 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82875_HB
)
1439 switch (dev
->subsystem_device
) {
1440 case 0x12bf: /* HP xw4100 */
1441 asus_hides_smbus
= 1;
1443 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1444 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1445 switch (dev
->subsystem_device
) {
1446 case 0xC00C: /* Samsung P35 notebook */
1447 asus_hides_smbus
= 1;
1449 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1450 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1451 switch (dev
->subsystem_device
) {
1452 case 0x0058: /* Compaq Evo N620c */
1453 asus_hides_smbus
= 1;
1455 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82810_IG3
)
1456 switch (dev
->subsystem_device
) {
1457 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1458 /* Motherboard doesn't have Host bridge
1459 * subvendor/subdevice IDs, therefore checking
1460 * its on-board VGA controller */
1461 asus_hides_smbus
= 1;
1463 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82801DB_2
)
1464 switch (dev
->subsystem_device
) {
1465 case 0x00b8: /* Compaq Evo D510 CMT */
1466 case 0x00b9: /* Compaq Evo D510 SFF */
1467 case 0x00ba: /* Compaq Evo D510 USDT */
1468 /* Motherboard doesn't have Host bridge
1469 * subvendor/subdevice IDs and on-board VGA
1470 * controller is disabled if an AGP card is
1471 * inserted, therefore checking USB UHCI
1473 asus_hides_smbus
= 1;
1475 else if (dev
->device
== PCI_DEVICE_ID_INTEL_82815_CGC
)
1476 switch (dev
->subsystem_device
) {
1477 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1478 /* Motherboard doesn't have host bridge
1479 * subvendor/subdevice IDs, therefore checking
1480 * its on-board VGA controller */
1481 asus_hides_smbus
= 1;
1485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
, asus_hides_smbus_hostbridge
);
1490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82810_IG3
, asus_hides_smbus_hostbridge
);
1497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_2
, asus_hides_smbus_hostbridge
);
1498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82815_CGC
, asus_hides_smbus_hostbridge
);
1500 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1504 if (likely(!asus_hides_smbus
))
1507 pci_read_config_word(dev
, 0xF2, &val
);
1509 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1510 pci_read_config_word(dev
, 0xF2, &val
);
1512 pci_info(dev
, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1515 pci_info(dev
, "Enabled i801 SMBus device\n");
1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, asus_hides_smbus_lpc
);
1526 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1527 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1529 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1530 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1533 /* It appears we just have one such device. If not, we have a warning */
1534 static void __iomem
*asus_rcba_base
;
1535 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev
*dev
)
1539 if (likely(!asus_hides_smbus
))
1541 WARN_ON(asus_rcba_base
);
1543 pci_read_config_dword(dev
, 0xF0, &rcba
);
1544 /* use bits 31:14, 16 kB aligned */
1545 asus_rcba_base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000);
1546 if (asus_rcba_base
== NULL
)
1550 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev
*dev
)
1554 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1557 /* read the Function Disable register, dword mode only */
1558 val
= readl(asus_rcba_base
+ 0x3418);
1560 /* enable the SMBus device */
1561 writel(val
& 0xFFFFFFF7, asus_rcba_base
+ 0x3418);
1564 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev
*dev
)
1566 if (likely(!asus_hides_smbus
|| !asus_rcba_base
))
1569 iounmap(asus_rcba_base
);
1570 asus_rcba_base
= NULL
;
1571 pci_info(dev
, "Enabled ICH6/i801 SMBus device\n");
1574 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1576 asus_hides_smbus_lpc_ich6_suspend(dev
);
1577 asus_hides_smbus_lpc_ich6_resume_early(dev
);
1578 asus_hides_smbus_lpc_ich6_resume(dev
);
1580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1581 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_suspend
);
1582 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume
);
1583 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6_resume_early
);
1585 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1586 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1589 pci_read_config_byte(dev
, 0x77, &val
);
1591 pci_info(dev
, "Enabling SiS 96x SMBus\n");
1592 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1599 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1600 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1601 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1602 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1605 * ... This is further complicated by the fact that some SiS96x south
1606 * bridges pretend to be 85C503/5513 instead. In that case see if we
1607 * spotted a compatible north bridge to make sure.
1608 * (pci_find_device() doesn't work yet)
1610 * We can also enable the sis96x bit in the discovery register..
1612 #define SIS_DETECT_REGISTER 0x40
1614 static void quirk_sis_503(struct pci_dev
*dev
)
1619 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1620 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1621 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1622 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1623 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1628 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1629 * it has already been processed. (Depends on link order, which is
1630 * apparently not guaranteed)
1632 dev
->device
= devid
;
1633 quirk_sis_96x_smbus(dev
);
1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1636 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1639 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1640 * and MC97 modem controller are disabled when a second PCI soundcard is
1641 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1644 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1647 int asus_hides_ac97
= 0;
1649 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1650 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1651 asus_hides_ac97
= 1;
1654 if (!asus_hides_ac97
)
1657 pci_read_config_byte(dev
, 0x50, &val
);
1659 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1660 pci_read_config_byte(dev
, 0x50, &val
);
1662 pci_info(dev
, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1665 pci_info(dev
, "Enabled onboard AC97/MC97 devices\n");
1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1669 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1671 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1674 * If we are using libata we can drive this chip properly but must do this
1675 * early on to make the additional device appear during the PCI scanning.
1677 static void quirk_jmicron_ata(struct pci_dev
*pdev
)
1679 u32 conf1
, conf5
, class;
1682 /* Only poke fn 0 */
1683 if (PCI_FUNC(pdev
->devfn
))
1686 pci_read_config_dword(pdev
, 0x40, &conf1
);
1687 pci_read_config_dword(pdev
, 0x80, &conf5
);
1689 conf1
&= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1690 conf5
&= ~(1 << 24); /* Clear bit 24 */
1692 switch (pdev
->device
) {
1693 case PCI_DEVICE_ID_JMICRON_JMB360
: /* SATA single port */
1694 case PCI_DEVICE_ID_JMICRON_JMB362
: /* SATA dual ports */
1695 case PCI_DEVICE_ID_JMICRON_JMB364
: /* SATA dual ports */
1696 /* The controller should be in single function ahci mode */
1697 conf1
|= 0x0002A100; /* Set 8, 13, 15, 17 */
1700 case PCI_DEVICE_ID_JMICRON_JMB365
:
1701 case PCI_DEVICE_ID_JMICRON_JMB366
:
1702 /* Redirect IDE second PATA port to the right spot */
1705 case PCI_DEVICE_ID_JMICRON_JMB361
:
1706 case PCI_DEVICE_ID_JMICRON_JMB363
:
1707 case PCI_DEVICE_ID_JMICRON_JMB369
:
1708 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1709 /* Set the class codes correctly and then direct IDE 0 */
1710 conf1
|= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1713 case PCI_DEVICE_ID_JMICRON_JMB368
:
1714 /* The controller should be in single function IDE mode */
1715 conf1
|= 0x00C00000; /* Set 22, 23 */
1719 pci_write_config_dword(pdev
, 0x40, conf1
);
1720 pci_write_config_dword(pdev
, 0x80, conf5
);
1722 /* Update pdev accordingly */
1723 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1724 pdev
->hdr_type
= hdr
& 0x7f;
1725 pdev
->multifunction
= !!(hdr
& 0x80);
1727 pci_read_config_dword(pdev
, PCI_CLASS_REVISION
, &class);
1728 pdev
->class = class >> 8;
1730 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1731 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1732 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1733 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1734 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1735 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1736 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1737 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1738 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1739 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB360
, quirk_jmicron_ata
);
1740 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB361
, quirk_jmicron_ata
);
1741 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB362
, quirk_jmicron_ata
);
1742 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB363
, quirk_jmicron_ata
);
1743 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB364
, quirk_jmicron_ata
);
1744 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB365
, quirk_jmicron_ata
);
1745 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB366
, quirk_jmicron_ata
);
1746 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB368
, quirk_jmicron_ata
);
1747 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_DEVICE_ID_JMICRON_JMB369
, quirk_jmicron_ata
);
1751 static void quirk_jmicron_async_suspend(struct pci_dev
*dev
)
1753 if (dev
->multifunction
) {
1754 device_disable_async_suspend(&dev
->dev
);
1755 pci_info(dev
, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1758 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_IDE
, 8, quirk_jmicron_async_suspend
);
1759 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_CLASS_STORAGE_SATA_AHCI
, 0, quirk_jmicron_async_suspend
);
1760 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x2362, quirk_jmicron_async_suspend
);
1761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON
, 0x236f, quirk_jmicron_async_suspend
);
1763 #ifdef CONFIG_X86_IO_APIC
1764 static void quirk_alder_ioapic(struct pci_dev
*pdev
)
1768 if ((pdev
->class >> 8) != 0xff00)
1772 * The first BAR is the location of the IO-APIC... we must
1773 * not touch this (and it's already covered by the fixmap), so
1774 * forcibly insert it into the resource tree.
1776 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1777 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1780 * The next five BARs all seem to be rubbish, so just clean
1783 for (i
= 1; i
< 6; i
++)
1784 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1786 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1789 static void quirk_pcie_mch(struct pci_dev
*pdev
)
1793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1795 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1797 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI
, 0x1610, PCI_CLASS_BRIDGE_PCI
, 8, quirk_pcie_mch
);
1800 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1801 * together on certain PXH-based systems.
1803 static void quirk_pcie_pxh(struct pci_dev
*dev
)
1806 pci_warn(dev
, "PXH quirk detected; SHPC device MSI disabled\n");
1808 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1809 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1810 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1811 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1812 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1815 * Some Intel PCI Express chipsets have trouble with downstream device
1818 static void quirk_intel_pcie_pm(struct pci_dev
*dev
)
1820 pci_pm_d3_delay
= 120;
1823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1829 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1833 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1835 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1837 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1845 static void quirk_radeon_pm(struct pci_dev
*dev
)
1847 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_APPLE
&&
1848 dev
->subsystem_device
== 0x00e2) {
1849 if (dev
->d3_delay
< 20) {
1851 pci_info(dev
, "extending delay after power-on from D3 to %d msec\n",
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x6741, quirk_radeon_pm
);
1858 #ifdef CONFIG_X86_IO_APIC
1859 static int dmi_disable_ioapicreroute(const struct dmi_system_id
*d
)
1861 noioapicreroute
= 1;
1862 pr_info("%s detected: disable boot interrupt reroute\n", d
->ident
);
1867 static const struct dmi_system_id boot_interrupt_dmi_table
[] = {
1869 * Systems to exclude from boot interrupt reroute quirks
1872 .callback
= dmi_disable_ioapicreroute
,
1873 .ident
= "ASUSTek Computer INC. M2N-LR",
1875 DMI_MATCH(DMI_SYS_VENDOR
, "ASUSTek Computer INC."),
1876 DMI_MATCH(DMI_PRODUCT_NAME
, "M2N-LR"),
1883 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1884 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1885 * that a PCI device's interrupt handler is installed on the boot interrupt
1888 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev
*dev
)
1890 dmi_check_system(boot_interrupt_dmi_table
);
1891 if (noioapicquirk
|| noioapicreroute
)
1894 dev
->irq_reroute_variant
= INTEL_IRQ_REROUTE_VARIANT
;
1895 pci_info(dev
, "rerouting interrupts for [%04x:%04x]\n",
1896 dev
->vendor
, dev
->device
);
1898 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1899 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1902 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1903 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1906 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_0
, quirk_reroute_to_boot_interrupts_intel
);
1907 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80333_1
, quirk_reroute_to_boot_interrupts_intel
);
1908 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
, quirk_reroute_to_boot_interrupts_intel
);
1909 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_reroute_to_boot_interrupts_intel
);
1910 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_reroute_to_boot_interrupts_intel
);
1911 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_reroute_to_boot_interrupts_intel
);
1912 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_0
, quirk_reroute_to_boot_interrupts_intel
);
1913 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80332_1
, quirk_reroute_to_boot_interrupts_intel
);
1916 * On some chipsets we can disable the generation of legacy INTx boot
1921 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1922 * 300641-004US, section 5.7.3.
1924 #define INTEL_6300_IOAPIC_ABAR 0x40
1925 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1927 static void quirk_disable_intel_boot_interrupt(struct pci_dev
*dev
)
1929 u16 pci_config_word
;
1934 pci_read_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, &pci_config_word
);
1935 pci_config_word
|= INTEL_6300_DISABLE_BOOT_IRQ
;
1936 pci_write_config_word(dev
, INTEL_6300_IOAPIC_ABAR
, pci_config_word
);
1938 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1939 dev
->vendor
, dev
->device
);
1941 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1942 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_10
, quirk_disable_intel_boot_interrupt
);
1944 /* Disable boot interrupts on HT-1000 */
1945 #define BC_HT1000_FEATURE_REG 0x64
1946 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1947 #define BC_HT1000_MAP_IDX 0xC00
1948 #define BC_HT1000_MAP_DATA 0xC01
1950 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev
*dev
)
1952 u32 pci_config_dword
;
1958 pci_read_config_dword(dev
, BC_HT1000_FEATURE_REG
, &pci_config_dword
);
1959 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
|
1960 BC_HT1000_PIC_REGS_ENABLE
);
1962 for (irq
= 0x10; irq
< 0x10 + 32; irq
++) {
1963 outb(irq
, BC_HT1000_MAP_IDX
);
1964 outb(0x00, BC_HT1000_MAP_DATA
);
1967 pci_write_config_dword(dev
, BC_HT1000_FEATURE_REG
, pci_config_dword
);
1969 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
1970 dev
->vendor
, dev
->device
);
1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1973 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000SB
, quirk_disable_broadcom_boot_interrupt
);
1975 /* Disable boot interrupts on AMD and ATI chipsets */
1978 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1979 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1980 * (due to an erratum).
1982 #define AMD_813X_MISC 0x40
1983 #define AMD_813X_NOIOAMODE (1<<0)
1984 #define AMD_813X_REV_B1 0x12
1985 #define AMD_813X_REV_B2 0x13
1987 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev
*dev
)
1989 u32 pci_config_dword
;
1993 if ((dev
->revision
== AMD_813X_REV_B1
) ||
1994 (dev
->revision
== AMD_813X_REV_B2
))
1997 pci_read_config_dword(dev
, AMD_813X_MISC
, &pci_config_dword
);
1998 pci_config_dword
&= ~AMD_813X_NOIOAMODE
;
1999 pci_write_config_dword(dev
, AMD_813X_MISC
, pci_config_dword
);
2001 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2002 dev
->vendor
, dev
->device
);
2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2005 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2007 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
, quirk_disable_amd_813x_boot_interrupt
);
2009 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2011 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev
*dev
)
2013 u16 pci_config_word
;
2018 pci_read_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, &pci_config_word
);
2019 if (!pci_config_word
) {
2020 pci_info(dev
, "boot interrupts on device [%04x:%04x] already disabled\n",
2021 dev
->vendor
, dev
->device
);
2024 pci_write_config_word(dev
, AMD_8111_PCI_IRQ_ROUTING
, 0);
2025 pci_info(dev
, "disabled boot interrupts on device [%04x:%04x]\n",
2026 dev
->vendor
, dev
->device
);
2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2029 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8111_SMBUS
, quirk_disable_amd_8111_boot_interrupt
);
2030 #endif /* CONFIG_X86_IO_APIC */
2033 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2034 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2035 * Re-allocate the region if needed...
2037 static void quirk_tc86c001_ide(struct pci_dev
*dev
)
2039 struct resource
*r
= &dev
->resource
[0];
2041 if (r
->start
& 0x8) {
2042 r
->flags
|= IORESOURCE_UNSET
;
2047 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2
,
2048 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
,
2049 quirk_tc86c001_ide
);
2052 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2053 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2054 * being read correctly if bit 7 of the base address is set.
2055 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2056 * Re-allocate the regions to a 256-byte boundary if necessary.
2058 static void quirk_plx_pci9050(struct pci_dev
*dev
)
2062 /* Fixed in revision 2 (PCI 9052). */
2063 if (dev
->revision
>= 2)
2065 for (bar
= 0; bar
<= 1; bar
++)
2066 if (pci_resource_len(dev
, bar
) == 0x80 &&
2067 (pci_resource_start(dev
, bar
) & 0x80)) {
2068 struct resource
*r
= &dev
->resource
[bar
];
2069 pci_info(dev
, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2071 r
->flags
|= IORESOURCE_UNSET
;
2076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2079 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2080 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2081 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2082 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2084 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2087 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050
);
2088 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050
);
2090 static void quirk_netmos(struct pci_dev
*dev
)
2092 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
2093 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
2096 * These Netmos parts are multiport serial devices with optional
2097 * parallel ports. Even when parallel ports are present, they
2098 * are identified as class SERIAL, which means the serial driver
2099 * will claim them. To prevent this, mark them as class OTHER.
2100 * These combo devices should be claimed by parport_serial.
2102 * The subdevice ID is of the form 0x00PS, where <P> is the number
2103 * of parallel ports and <S> is the number of serial ports.
2105 switch (dev
->device
) {
2106 case PCI_DEVICE_ID_NETMOS_9835
:
2107 /* Well, this rule doesn't hold for the following 9835 device */
2108 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
&&
2109 dev
->subsystem_device
== 0x0299)
2111 /* else: fall through */
2112 case PCI_DEVICE_ID_NETMOS_9735
:
2113 case PCI_DEVICE_ID_NETMOS_9745
:
2114 case PCI_DEVICE_ID_NETMOS_9845
:
2115 case PCI_DEVICE_ID_NETMOS_9855
:
2117 pci_info(dev
, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2118 dev
->device
, num_parallel
, num_serial
);
2119 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
2120 (dev
->class & 0xff);
2124 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
,
2125 PCI_CLASS_COMMUNICATION_SERIAL
, 8, quirk_netmos
);
2127 static void quirk_e100_interrupt(struct pci_dev
*dev
)
2133 switch (dev
->device
) {
2134 /* PCI IDs taken from drivers/net/e100.c */
2136 case 0x1030 ... 0x1034:
2137 case 0x1038 ... 0x103E:
2138 case 0x1050 ... 0x1057:
2140 case 0x1064 ... 0x106B:
2141 case 0x1091 ... 0x1095:
2154 * Some firmware hands off the e100 with interrupts enabled,
2155 * which can cause a flood of interrupts if packets are
2156 * received before the driver attaches to the device. So
2157 * disable all e100 interrupts here. The driver will
2158 * re-enable them when it's ready.
2160 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
2162 if (!(command
& PCI_COMMAND_MEMORY
) || !pci_resource_start(dev
, 0))
2166 * Check that the device is in the D0 power state. If it's not,
2167 * there is no point to look any further.
2170 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2171 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) != PCI_D0
)
2175 /* Convert from PCI bus to resource space. */
2176 csr
= ioremap(pci_resource_start(dev
, 0), 8);
2178 pci_warn(dev
, "Can't map e100 registers\n");
2182 cmd_hi
= readb(csr
+ 3);
2184 pci_warn(dev
, "Firmware left e100 interrupts enabled; disabling\n");
2190 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
2191 PCI_CLASS_NETWORK_ETHERNET
, 8, quirk_e100_interrupt
);
2194 * The 82575 and 82598 may experience data corruption issues when transitioning
2195 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2197 static void quirk_disable_aspm_l0s(struct pci_dev
*dev
)
2199 pci_info(dev
, "Disabling L0s\n");
2200 pci_disable_link_state(dev
, PCIE_LINK_STATE_L0S
);
2202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a7, quirk_disable_aspm_l0s
);
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10a9, quirk_disable_aspm_l0s
);
2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10b6, quirk_disable_aspm_l0s
);
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c6, quirk_disable_aspm_l0s
);
2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c7, quirk_disable_aspm_l0s
);
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10c8, quirk_disable_aspm_l0s
);
2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10d6, quirk_disable_aspm_l0s
);
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10db, quirk_disable_aspm_l0s
);
2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10dd, quirk_disable_aspm_l0s
);
2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10e1, quirk_disable_aspm_l0s
);
2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10ec, quirk_disable_aspm_l0s
);
2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f1, quirk_disable_aspm_l0s
);
2214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x10f4, quirk_disable_aspm_l0s
);
2215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1508, quirk_disable_aspm_l0s
);
2217 static void fixup_rev1_53c810(struct pci_dev
*dev
)
2219 u32
class = dev
->class;
2222 * rev 1 ncr53c810 chips don't set the class at all which means
2223 * they don't get their resources remapped. Fix that here.
2228 dev
->class = PCI_CLASS_STORAGE_SCSI
<< 8;
2229 pci_info(dev
, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
2234 /* Enable 1k I/O space granularity on the Intel P64H2 */
2235 static void quirk_p64h2_1k_io(struct pci_dev
*dev
)
2239 pci_read_config_word(dev
, 0x40, &en1k
);
2242 pci_info(dev
, "Enable I/O Space to 1KB granularity\n");
2243 dev
->io_window_1k
= 1;
2246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
2249 * Under some circumstances, AER is not linked with extended capabilities.
2250 * Force it to be linked by setting the corresponding control bit in the
2253 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
2257 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
2259 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
2260 pci_info(dev
, "Linking AER extended capability\n");
2264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2265 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2266 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2267 quirk_nvidia_ck804_pcie_aer_ext_cap
);
2269 static void quirk_via_cx700_pci_parking_caching(struct pci_dev
*dev
)
2272 * Disable PCI Bus Parking and PCI Master read caching on CX700
2273 * which causes unspecified timing errors with a VT6212L on the PCI
2274 * bus leading to USB2.0 packet loss.
2276 * This quirk is only enabled if a second (on the external PCI bus)
2277 * VT6212L is found -- the CX700 core itself also contains a USB
2278 * host controller with the same PCI ID as the VT6212L.
2281 /* Count VT6212L instances */
2282 struct pci_dev
*p
= pci_get_device(PCI_VENDOR_ID_VIA
,
2283 PCI_DEVICE_ID_VIA_8235_USB_2
, NULL
);
2287 * p should contain the first (internal) VT6212L -- see if we have
2288 * an external one by searching again.
2290 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235_USB_2
, p
);
2295 if (pci_read_config_byte(dev
, 0x76, &b
) == 0) {
2297 /* Turn off PCI Bus Parking */
2298 pci_write_config_byte(dev
, 0x76, b
^ 0x40);
2300 pci_info(dev
, "Disabling VIA CX700 PCI parking\n");
2304 if (pci_read_config_byte(dev
, 0x72, &b
) == 0) {
2306 /* Turn off PCI Master read caching */
2307 pci_write_config_byte(dev
, 0x72, 0x0);
2309 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2310 pci_write_config_byte(dev
, 0x75, 0x1);
2312 /* Disable "Read FIFO Timer" */
2313 pci_write_config_byte(dev
, 0x77, 0x0);
2315 pci_info(dev
, "Disabling VIA CX700 PCI caching\n");
2319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0x324e, quirk_via_cx700_pci_parking_caching
);
2321 static void quirk_brcm_5719_limit_mrrs(struct pci_dev
*dev
)
2325 pci_read_config_dword(dev
, 0xf4, &rev
);
2327 /* Only CAP the MRRS if the device is a 5719 A0 */
2328 if (rev
== 0x05719000) {
2329 int readrq
= pcie_get_readrq(dev
);
2331 pcie_set_readrq(dev
, 2048);
2334 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM
,
2335 PCI_DEVICE_ID_TIGON3_5719
,
2336 quirk_brcm_5719_limit_mrrs
);
2338 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2339 static void quirk_paxc_bridge(struct pci_dev
*pdev
)
2342 * The PCI config space is shared with the PAXC root port and the first
2343 * Ethernet device. So, we need to workaround this by telling the PCI
2344 * code that the bridge is not an Ethernet device.
2346 if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
2347 pdev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
2350 * MPSS is not being set properly (as it is currently 0). This is
2351 * because that area of the PCI config space is hard coded to zero, and
2352 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2353 * so that the MPS can be set to the real max value.
2355 pdev
->pcie_mpss
= 2;
2357 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0x16cd, quirk_paxc_bridge
);
2358 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM
, 0x16f0, quirk_paxc_bridge
);
2362 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2363 * hide device 6 which configures the overflow device access containing the
2364 * DRBs - this is where we expose device 6.
2365 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2367 static void quirk_unhide_mch_dev6(struct pci_dev
*dev
)
2371 if (pci_read_config_byte(dev
, 0xF4, ®
) == 0 && !(reg
& 0x02)) {
2372 pci_info(dev
, "Enabling MCH 'Overflow' Device\n");
2373 pci_write_config_byte(dev
, 0xF4, reg
| 0x02);
2376 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
,
2377 quirk_unhide_mch_dev6
);
2378 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82875_HB
,
2379 quirk_unhide_mch_dev6
);
2381 #ifdef CONFIG_PCI_MSI
2383 * Some chipsets do not support MSI. We cannot easily rely on setting
2384 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2385 * other buses controlled by the chipset even if Linux is not aware of it.
2386 * Instead of setting the flag on all buses in the machine, simply disable
2389 static void quirk_disable_all_msi(struct pci_dev
*dev
)
2392 pci_warn(dev
, "MSI quirk detected; MSI disabled\n");
2394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_disable_all_msi
);
2395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS400_200
, quirk_disable_all_msi
);
2396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS480
, quirk_disable_all_msi
);
2397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3336
, quirk_disable_all_msi
);
2398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3351
, quirk_disable_all_msi
);
2399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_VT3364
, quirk_disable_all_msi
);
2400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8380_0
, quirk_disable_all_msi
);
2401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, 0x0761, quirk_disable_all_msi
);
2403 /* Disable MSI on chipsets that are known to not support it */
2404 static void quirk_disable_msi(struct pci_dev
*dev
)
2406 if (dev
->subordinate
) {
2407 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2408 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
2412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, 0xa238, quirk_disable_msi
);
2413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x5a3f, quirk_disable_msi
);
2416 * The APC bridge device in AMD 780 family northbridges has some random
2417 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2418 * we use the possible vendor/device IDs of the host bridge for the
2419 * declared quirk, and search for the APC bridge by slot number.
2421 static void quirk_amd_780_apc_msi(struct pci_dev
*host_bridge
)
2423 struct pci_dev
*apc_bridge
;
2425 apc_bridge
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(1, 0));
2427 if (apc_bridge
->device
== 0x9602)
2428 quirk_disable_msi(apc_bridge
);
2429 pci_dev_put(apc_bridge
);
2432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9600, quirk_amd_780_apc_msi
);
2433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, 0x9601, quirk_amd_780_apc_msi
);
2436 * Go through the list of HyperTransport capabilities and return 1 if a HT
2437 * MSI capability is found and enabled.
2439 static int msi_ht_cap_enabled(struct pci_dev
*dev
)
2441 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2443 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2444 while (pos
&& ttl
--) {
2447 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2449 pci_info(dev
, "Found %s HT MSI Mapping\n",
2450 flags
& HT_MSI_FLAGS_ENABLE
?
2451 "enabled" : "disabled");
2452 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
2455 pos
= pci_find_next_ht_capability(dev
, pos
,
2456 HT_CAPTYPE_MSI_MAPPING
);
2461 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2462 static void quirk_msi_ht_cap(struct pci_dev
*dev
)
2464 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
2465 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2466 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
2473 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2474 * if the MSI capability is set in any of these mappings.
2476 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
2478 struct pci_dev
*pdev
;
2480 if (!dev
->subordinate
)
2484 * Check HT MSI cap on this chipset and the root one. A single one
2485 * having MSI is enough to be sure that MSI is supported.
2487 pdev
= pci_get_slot(dev
->bus
, 0);
2490 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
2491 pci_warn(dev
, "MSI quirk detected; subordinate MSI disabled\n");
2492 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
2496 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
2497 quirk_nvidia_ck804_msi_ht_cap
);
2499 /* Force enable MSI mapping capability on HT bridges */
2500 static void ht_enable_msi_mapping(struct pci_dev
*dev
)
2502 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2504 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2505 while (pos
&& ttl
--) {
2508 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2510 pci_info(dev
, "Enabling HT MSI Mapping\n");
2512 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2513 flags
| HT_MSI_FLAGS_ENABLE
);
2515 pos
= pci_find_next_ht_capability(dev
, pos
,
2516 HT_CAPTYPE_MSI_MAPPING
);
2519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
,
2520 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
,
2521 ht_enable_msi_mapping
);
2522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8132_BRIDGE
,
2523 ht_enable_msi_mapping
);
2526 * The P5N32-SLI motherboards from Asus have a problem with MSI
2527 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2528 * also affects other devices. As for now, turn off MSI for this device.
2530 static void nvenet_msi_disable(struct pci_dev
*dev
)
2532 const char *board_name
= dmi_get_system_info(DMI_BOARD_NAME
);
2535 (strstr(board_name
, "P5N32-SLI PREMIUM") ||
2536 strstr(board_name
, "P5N32-E SLI"))) {
2537 pci_info(dev
, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2541 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2542 PCI_DEVICE_ID_NVIDIA_NVENET_15
,
2543 nvenet_msi_disable
);
2546 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2547 * config register. This register controls the routing of legacy
2548 * interrupts from devices that route through the MCP55. If this register
2549 * is misprogrammed, interrupts are only sent to the BSP, unlike
2550 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2551 * having this register set properly prevents kdump from booting up
2552 * properly, so let's make sure that we have it set correctly.
2553 * Note that this is an undocumented register.
2555 static void nvbridge_check_legacy_irq_routing(struct pci_dev
*dev
)
2559 if (!pci_find_capability(dev
, PCI_CAP_ID_HT
))
2562 pci_read_config_dword(dev
, 0x74, &cfg
);
2564 if (cfg
& ((1 << 2) | (1 << 15))) {
2565 printk(KERN_INFO
"Rewriting IRQ routing register on MCP55\n");
2566 cfg
&= ~((1 << 2) | (1 << 15));
2567 pci_write_config_dword(dev
, 0x74, cfg
);
2570 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2571 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
,
2572 nvbridge_check_legacy_irq_routing
);
2573 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA
,
2574 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
,
2575 nvbridge_check_legacy_irq_routing
);
2577 static int ht_check_msi_mapping(struct pci_dev
*dev
)
2579 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2582 /* Check if there is HT MSI cap or enabled on this device */
2583 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2584 while (pos
&& ttl
--) {
2589 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2591 if (flags
& HT_MSI_FLAGS_ENABLE
) {
2598 pos
= pci_find_next_ht_capability(dev
, pos
,
2599 HT_CAPTYPE_MSI_MAPPING
);
2605 static int host_bridge_with_leaf(struct pci_dev
*host_bridge
)
2607 struct pci_dev
*dev
;
2612 dev_no
= host_bridge
->devfn
>> 3;
2613 for (i
= dev_no
+ 1; i
< 0x20; i
++) {
2614 dev
= pci_get_slot(host_bridge
->bus
, PCI_DEVFN(i
, 0));
2618 /* found next host bridge? */
2619 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2625 if (ht_check_msi_mapping(dev
)) {
2636 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2637 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2639 static int is_end_of_ht_chain(struct pci_dev
*dev
)
2645 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_SLAVE
);
2650 pci_read_config_word(dev
, pos
+ PCI_CAP_FLAGS
, &flags
);
2652 ctrl_off
= ((flags
>> 10) & 1) ?
2653 PCI_HT_CAP_SLAVE_CTRL0
: PCI_HT_CAP_SLAVE_CTRL1
;
2654 pci_read_config_word(dev
, pos
+ ctrl_off
, &ctrl
);
2656 if (ctrl
& (1 << 6))
2663 static void nv_ht_enable_msi_mapping(struct pci_dev
*dev
)
2665 struct pci_dev
*host_bridge
;
2670 dev_no
= dev
->devfn
>> 3;
2671 for (i
= dev_no
; i
>= 0; i
--) {
2672 host_bridge
= pci_get_slot(dev
->bus
, PCI_DEVFN(i
, 0));
2676 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2681 pci_dev_put(host_bridge
);
2687 /* don't enable end_device/host_bridge with leaf directly here */
2688 if (host_bridge
== dev
&& is_end_of_ht_chain(host_bridge
) &&
2689 host_bridge_with_leaf(host_bridge
))
2692 /* root did that ! */
2693 if (msi_ht_cap_enabled(host_bridge
))
2696 ht_enable_msi_mapping(dev
);
2699 pci_dev_put(host_bridge
);
2702 static void ht_disable_msi_mapping(struct pci_dev
*dev
)
2704 int pos
, ttl
= PCI_FIND_CAP_TTL
;
2706 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
2707 while (pos
&& ttl
--) {
2710 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2712 pci_info(dev
, "Disabling HT MSI Mapping\n");
2714 pci_write_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
2715 flags
& ~HT_MSI_FLAGS_ENABLE
);
2717 pos
= pci_find_next_ht_capability(dev
, pos
,
2718 HT_CAPTYPE_MSI_MAPPING
);
2722 static void __nv_msi_ht_cap_quirk(struct pci_dev
*dev
, int all
)
2724 struct pci_dev
*host_bridge
;
2728 if (!pci_msi_enabled())
2731 /* check if there is HT MSI cap or enabled on this device */
2732 found
= ht_check_msi_mapping(dev
);
2739 * HT MSI mapping should be disabled on devices that are below
2740 * a non-Hypertransport host bridge. Locate the host bridge...
2742 host_bridge
= pci_get_domain_bus_and_slot(pci_domain_nr(dev
->bus
), 0,
2744 if (host_bridge
== NULL
) {
2745 pci_warn(dev
, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2749 pos
= pci_find_ht_capability(host_bridge
, HT_CAPTYPE_SLAVE
);
2751 /* Host bridge is to HT */
2753 /* it is not enabled, try to enable it */
2755 ht_enable_msi_mapping(dev
);
2757 nv_ht_enable_msi_mapping(dev
);
2762 /* HT MSI is not enabled */
2766 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2767 ht_disable_msi_mapping(dev
);
2770 pci_dev_put(host_bridge
);
2773 static void nv_msi_ht_cap_quirk_all(struct pci_dev
*dev
)
2775 return __nv_msi_ht_cap_quirk(dev
, 1);
2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2778 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_all
);
2780 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev
*dev
)
2782 return __nv_msi_ht_cap_quirk(dev
, 0);
2784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2785 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
, nv_msi_ht_cap_quirk_leaf
);
2787 static void quirk_msi_intx_disable_bug(struct pci_dev
*dev
)
2789 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2792 static void quirk_msi_intx_disable_ati_bug(struct pci_dev
*dev
)
2797 * SB700 MSI issue will be fixed at HW level from revision A21;
2798 * we need check PCI REVISION ID of SMBus controller to get SB700
2801 p
= pci_get_device(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2806 if ((p
->revision
< 0x3B) && (p
->revision
>= 0x30))
2807 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2811 static void quirk_msi_intx_disable_qca_bug(struct pci_dev
*dev
)
2813 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2814 if (dev
->revision
< 0x18) {
2815 pci_info(dev
, "set MSI_INTX_DISABLE_BUG flag\n");
2816 dev
->dev_flags
|= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
;
2819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2820 PCI_DEVICE_ID_TIGON3_5780
,
2821 quirk_msi_intx_disable_bug
);
2822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2823 PCI_DEVICE_ID_TIGON3_5780S
,
2824 quirk_msi_intx_disable_bug
);
2825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2826 PCI_DEVICE_ID_TIGON3_5714
,
2827 quirk_msi_intx_disable_bug
);
2828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2829 PCI_DEVICE_ID_TIGON3_5714S
,
2830 quirk_msi_intx_disable_bug
);
2831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2832 PCI_DEVICE_ID_TIGON3_5715
,
2833 quirk_msi_intx_disable_bug
);
2834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM
,
2835 PCI_DEVICE_ID_TIGON3_5715S
,
2836 quirk_msi_intx_disable_bug
);
2838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4390,
2839 quirk_msi_intx_disable_ati_bug
);
2840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4391,
2841 quirk_msi_intx_disable_ati_bug
);
2842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4392,
2843 quirk_msi_intx_disable_ati_bug
);
2844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4393,
2845 quirk_msi_intx_disable_ati_bug
);
2846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4394,
2847 quirk_msi_intx_disable_ati_bug
);
2849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4373,
2850 quirk_msi_intx_disable_bug
);
2851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4374,
2852 quirk_msi_intx_disable_bug
);
2853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x4375,
2854 quirk_msi_intx_disable_bug
);
2856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1062,
2857 quirk_msi_intx_disable_bug
);
2858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1063,
2859 quirk_msi_intx_disable_bug
);
2860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2060,
2861 quirk_msi_intx_disable_bug
);
2862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x2062,
2863 quirk_msi_intx_disable_bug
);
2864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1073,
2865 quirk_msi_intx_disable_bug
);
2866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1083,
2867 quirk_msi_intx_disable_bug
);
2868 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1090,
2869 quirk_msi_intx_disable_qca_bug
);
2870 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x1091,
2871 quirk_msi_intx_disable_qca_bug
);
2872 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a0,
2873 quirk_msi_intx_disable_qca_bug
);
2874 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0x10a1,
2875 quirk_msi_intx_disable_qca_bug
);
2876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC
, 0xe091,
2877 quirk_msi_intx_disable_qca_bug
);
2878 #endif /* CONFIG_PCI_MSI */
2881 * Allow manual resource allocation for PCI hotplug bridges via
2882 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
2883 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
2884 * allocate resources when hotplug device is inserted and PCI bus is
2887 static void quirk_hotplug_bridge(struct pci_dev
*dev
)
2889 dev
->is_hotplug_bridge
= 1;
2891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT
, 0x0020, quirk_hotplug_bridge
);
2894 * This is a quirk for the Ricoh MMC controller found as a part of some
2895 * multifunction chips.
2897 * This is very similar and based on the ricoh_mmc driver written by
2898 * Philip Langdale. Thank you for these magic sequences.
2900 * These chips implement the four main memory card controllers (SD, MMC,
2901 * MS, xD) and one or both of CardBus or FireWire.
2903 * It happens that they implement SD and MMC support as separate
2904 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
2905 * cards but the chip detects MMC cards in hardware and directs them to the
2906 * MMC controller - so the SDHCI driver never sees them.
2908 * To get around this, we must disable the useless MMC controller. At that
2909 * point, the SDHCI controller will start seeing them. It seems to be the
2910 * case that the relevant PCI registers to deactivate the MMC controller
2911 * live on PCI function 0, which might be the CardBus controller or the
2912 * FireWire controller, depending on the particular chip in question
2914 * This has to be done early, because as soon as we disable the MMC controller
2915 * other PCI functions shift up one level, e.g. function #2 becomes function
2916 * #1, and this will confuse the PCI core.
2918 #ifdef CONFIG_MMC_RICOH_MMC
2919 static void ricoh_mmc_fixup_rl5c476(struct pci_dev
*dev
)
2926 * Disable via CardBus interface
2928 * This must be done via function #0
2930 if (PCI_FUNC(dev
->devfn
))
2933 pci_read_config_byte(dev
, 0xB7, &disable
);
2937 pci_read_config_byte(dev
, 0x8E, &write_enable
);
2938 pci_write_config_byte(dev
, 0x8E, 0xAA);
2939 pci_read_config_byte(dev
, 0x8D, &write_target
);
2940 pci_write_config_byte(dev
, 0x8D, 0xB7);
2941 pci_write_config_byte(dev
, 0xB7, disable
| 0x02);
2942 pci_write_config_byte(dev
, 0x8E, write_enable
);
2943 pci_write_config_byte(dev
, 0x8D, write_target
);
2945 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
2946 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
2948 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
2949 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_RL5C476
, ricoh_mmc_fixup_rl5c476
);
2951 static void ricoh_mmc_fixup_r5c832(struct pci_dev
*dev
)
2957 * Disable via FireWire interface
2959 * This must be done via function #0
2961 if (PCI_FUNC(dev
->devfn
))
2964 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2965 * certain types of SD/MMC cards. Lowering the SD base clock
2966 * frequency from 200Mhz to 50Mhz fixes this issue.
2968 * 0x150 - SD2.0 mode enable for changing base clock
2969 * frequency to 50Mhz
2970 * 0xe1 - Base clock frequency
2971 * 0x32 - 50Mhz new clock frequency
2972 * 0xf9 - Key register for 0x150
2973 * 0xfc - key register for 0xe1
2975 if (dev
->device
== PCI_DEVICE_ID_RICOH_R5CE822
||
2976 dev
->device
== PCI_DEVICE_ID_RICOH_R5CE823
) {
2977 pci_write_config_byte(dev
, 0xf9, 0xfc);
2978 pci_write_config_byte(dev
, 0x150, 0x10);
2979 pci_write_config_byte(dev
, 0xf9, 0x00);
2980 pci_write_config_byte(dev
, 0xfc, 0x01);
2981 pci_write_config_byte(dev
, 0xe1, 0x32);
2982 pci_write_config_byte(dev
, 0xfc, 0x00);
2984 pci_notice(dev
, "MMC controller base frequency changed to 50Mhz.\n");
2987 pci_read_config_byte(dev
, 0xCB, &disable
);
2992 pci_read_config_byte(dev
, 0xCA, &write_enable
);
2993 pci_write_config_byte(dev
, 0xCA, 0x57);
2994 pci_write_config_byte(dev
, 0xCB, disable
| 0x02);
2995 pci_write_config_byte(dev
, 0xCA, write_enable
);
2997 pci_notice(dev
, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
2998 pci_notice(dev
, "MMC cards are now supported by standard SDHCI controller\n");
3001 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3002 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5C832
, ricoh_mmc_fixup_r5c832
);
3003 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3004 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE822
, ricoh_mmc_fixup_r5c832
);
3005 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3006 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH
, PCI_DEVICE_ID_RICOH_R5CE823
, ricoh_mmc_fixup_r5c832
);
3007 #endif /*CONFIG_MMC_RICOH_MMC*/
3009 #ifdef CONFIG_DMAR_TABLE
3010 #define VTUNCERRMSK_REG 0x1ac
3011 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3013 * This is a quirk for masking VT-d spec-defined errors to platform error
3014 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3015 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3016 * on the RAS config settings of the platform) when a VT-d fault happens.
3017 * The resulting SMI caused the system to hang.
3019 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3020 * need to report the same error through other channels.
3022 static void vtd_mask_spec_errors(struct pci_dev
*dev
)
3026 pci_read_config_dword(dev
, VTUNCERRMSK_REG
, &word
);
3027 pci_write_config_dword(dev
, VTUNCERRMSK_REG
, word
| VTD_MSK_SPEC_ERRORS
);
3029 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x342e, vtd_mask_spec_errors
);
3030 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x3c28, vtd_mask_spec_errors
);
3033 static void fixup_ti816x_class(struct pci_dev
*dev
)
3035 u32
class = dev
->class;
3037 /* TI 816x devices do not have class code set when in PCIe boot mode */
3038 dev
->class = PCI_CLASS_MULTIMEDIA_VIDEO
<< 8;
3039 pci_info(dev
, "PCI class overridden (%#08x -> %#08x)\n",
3042 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI
, 0xb800,
3043 PCI_CLASS_NOT_DEFINED
, 8, fixup_ti816x_class
);
3046 * Some PCIe devices do not work reliably with the claimed maximum
3047 * payload size supported.
3049 static void fixup_mpss_256(struct pci_dev
*dev
)
3051 dev
->pcie_mpss
= 1; /* 256 bytes */
3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3054 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0
, fixup_mpss_256
);
3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3056 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
, fixup_mpss_256
);
3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE
,
3058 PCI_DEVICE_ID_SOLARFLARE_SFC4000B
, fixup_mpss_256
);
3061 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3062 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3063 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3064 * until all of the devices are discovered and buses walked, read completion
3065 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3066 * it is possible to hotplug a device with MPS of 256B.
3068 static void quirk_intel_mc_errata(struct pci_dev
*dev
)
3073 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
3074 pcie_bus_config
== PCIE_BUS_DEFAULT
)
3078 * Intel erratum specifies bits to change but does not say what
3079 * they are. Keeping them magical until such time as the registers
3080 * and values can be explained.
3082 err
= pci_read_config_word(dev
, 0x48, &rcc
);
3084 pci_err(dev
, "Error attempting to read the read completion coalescing register\n");
3088 if (!(rcc
& (1 << 10)))
3093 err
= pci_write_config_word(dev
, 0x48, rcc
);
3095 pci_err(dev
, "Error attempting to write the read completion coalescing register\n");
3099 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3101 /* Intel 5000 series memory controllers and ports 2-7 */
3102 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25c0, quirk_intel_mc_errata
);
3103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d0, quirk_intel_mc_errata
);
3104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d4, quirk_intel_mc_errata
);
3105 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25d8, quirk_intel_mc_errata
);
3106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_mc_errata
);
3107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_mc_errata
);
3108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_mc_errata
);
3109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_mc_errata
);
3110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_mc_errata
);
3111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_mc_errata
);
3112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_mc_errata
);
3113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_mc_errata
);
3114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_mc_errata
);
3115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_mc_errata
);
3116 /* Intel 5100 series memory controllers and ports 2-7 */
3117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65c0, quirk_intel_mc_errata
);
3118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e2, quirk_intel_mc_errata
);
3119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e3, quirk_intel_mc_errata
);
3120 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e4, quirk_intel_mc_errata
);
3121 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e5, quirk_intel_mc_errata
);
3122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e6, quirk_intel_mc_errata
);
3123 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65e7, quirk_intel_mc_errata
);
3124 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f7, quirk_intel_mc_errata
);
3125 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f8, quirk_intel_mc_errata
);
3126 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65f9, quirk_intel_mc_errata
);
3127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x65fa, quirk_intel_mc_errata
);
3130 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3131 * To work around this, query the size it should be configured to by the
3132 * device and modify the resource end to correspond to this new size.
3134 static void quirk_intel_ntb(struct pci_dev
*dev
)
3139 rc
= pci_read_config_byte(dev
, 0x00D0, &val
);
3143 dev
->resource
[2].end
= dev
->resource
[2].start
+ ((u64
) 1 << val
) - 1;
3145 rc
= pci_read_config_byte(dev
, 0x00D1, &val
);
3149 dev
->resource
[4].end
= dev
->resource
[4].start
+ ((u64
) 1 << val
) - 1;
3151 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e08, quirk_intel_ntb
);
3152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x0e0d, quirk_intel_ntb
);
3155 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3156 * though no one is handling them (e.g., if the i915 driver is never
3157 * loaded). Additionally the interrupt destination is not set up properly
3158 * and the interrupt ends up -somewhere-.
3160 * These spurious interrupts are "sticky" and the kernel disables the
3161 * (shared) interrupt line after 100,000+ generated interrupts.
3163 * Fix it by disabling the still enabled interrupts. This resolves crashes
3164 * often seen on monitor unplug.
3166 #define I915_DEIER_REG 0x4400c
3167 static void disable_igfx_irq(struct pci_dev
*dev
)
3169 void __iomem
*regs
= pci_iomap(dev
, 0, 0);
3171 pci_warn(dev
, "igfx quirk: Can't iomap PCI device\n");
3175 /* Check if any interrupt line is still enabled */
3176 if (readl(regs
+ I915_DEIER_REG
) != 0) {
3177 pci_warn(dev
, "BIOS left Intel GPU interrupts enabled; disabling\n");
3179 writel(0, regs
+ I915_DEIER_REG
);
3182 pci_iounmap(dev
, regs
);
3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0102, disable_igfx_irq
);
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x010a, disable_igfx_irq
);
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0152, disable_igfx_irq
);
3189 * PCI devices which are on Intel chips can skip the 10ms delay
3190 * before entering D3 mode.
3192 static void quirk_remove_d3_delay(struct pci_dev
*dev
)
3196 /* C600 Series devices do not need 10ms d3_delay */
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0412, quirk_remove_d3_delay
);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c00, quirk_remove_d3_delay
);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x0c0c, quirk_remove_d3_delay
);
3200 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c02, quirk_remove_d3_delay
);
3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c18, quirk_remove_d3_delay
);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c1c, quirk_remove_d3_delay
);
3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c20, quirk_remove_d3_delay
);
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c22, quirk_remove_d3_delay
);
3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c26, quirk_remove_d3_delay
);
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c2d, quirk_remove_d3_delay
);
3208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c31, quirk_remove_d3_delay
);
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3a, quirk_remove_d3_delay
);
3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c3d, quirk_remove_d3_delay
);
3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x8c4e, quirk_remove_d3_delay
);
3212 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2280, quirk_remove_d3_delay
);
3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2298, quirk_remove_d3_delay
);
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x229c, quirk_remove_d3_delay
);
3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b0, quirk_remove_d3_delay
);
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b5, quirk_remove_d3_delay
);
3218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b7, quirk_remove_d3_delay
);
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22b8, quirk_remove_d3_delay
);
3220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22d8, quirk_remove_d3_delay
);
3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x22dc, quirk_remove_d3_delay
);
3224 * Some devices may pass our check in pci_intx_mask_supported() if
3225 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3226 * support this feature.
3228 static void quirk_broken_intx_masking(struct pci_dev
*dev
)
3230 dev
->broken_intx_masking
= 1;
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO
, 0x0030,
3233 quirk_broken_intx_masking
);
3234 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3235 quirk_broken_intx_masking
);
3236 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3237 quirk_broken_intx_masking
);
3240 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3241 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3243 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK
, 0x8169,
3246 quirk_broken_intx_masking
);
3249 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3250 * DisINTx can be set but the interrupt status bit is non-functional.
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1572, quirk_broken_intx_masking
);
3253 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1574, quirk_broken_intx_masking
);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1580, quirk_broken_intx_masking
);
3255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1581, quirk_broken_intx_masking
);
3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1583, quirk_broken_intx_masking
);
3257 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1584, quirk_broken_intx_masking
);
3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1585, quirk_broken_intx_masking
);
3259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1586, quirk_broken_intx_masking
);
3260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1587, quirk_broken_intx_masking
);
3261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1588, quirk_broken_intx_masking
);
3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x1589, quirk_broken_intx_masking
);
3263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158a, quirk_broken_intx_masking
);
3264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x158b, quirk_broken_intx_masking
);
3265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d0, quirk_broken_intx_masking
);
3266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d1, quirk_broken_intx_masking
);
3267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x37d2, quirk_broken_intx_masking
);
3269 static u16 mellanox_broken_intx_devs
[] = {
3270 PCI_DEVICE_ID_MELLANOX_HERMON_SDR
,
3271 PCI_DEVICE_ID_MELLANOX_HERMON_DDR
,
3272 PCI_DEVICE_ID_MELLANOX_HERMON_QDR
,
3273 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2
,
3274 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2
,
3275 PCI_DEVICE_ID_MELLANOX_HERMON_EN
,
3276 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2
,
3277 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN
,
3278 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2
,
3279 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2
,
3280 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2
,
3281 PCI_DEVICE_ID_MELLANOX_CONNECTX2
,
3282 PCI_DEVICE_ID_MELLANOX_CONNECTX3
,
3283 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO
,
3286 #define CONNECTX_4_CURR_MAX_MINOR 99
3287 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3290 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3291 * If so, don't mark it as broken.
3292 * FW minor > 99 means older FW version format and no INTx masking support.
3293 * FW minor < 14 means new FW version format and no INTx masking support.
3295 static void mellanox_check_broken_intx_masking(struct pci_dev
*pdev
)
3297 __be32 __iomem
*fw_ver
;
3305 for (i
= 0; i
< ARRAY_SIZE(mellanox_broken_intx_devs
); i
++) {
3306 if (pdev
->device
== mellanox_broken_intx_devs
[i
]) {
3307 pdev
->broken_intx_masking
= 1;
3313 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3314 * support so shouldn't be checked further
3316 if (pdev
->device
== PCI_DEVICE_ID_MELLANOX_CONNECTIB
)
3319 if (pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4
&&
3320 pdev
->device
!= PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
)
3323 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3324 if (pci_enable_device_mem(pdev
)) {
3325 pci_warn(pdev
, "Can't enable device memory\n");
3329 fw_ver
= ioremap(pci_resource_start(pdev
, 0), 4);
3331 pci_warn(pdev
, "Can't map ConnectX-4 initialization segment\n");
3335 /* Reading from resource space should be 32b aligned */
3336 fw_maj_min
= ioread32be(fw_ver
);
3337 fw_sub_min
= ioread32be(fw_ver
+ 1);
3338 fw_major
= fw_maj_min
& 0xffff;
3339 fw_minor
= fw_maj_min
>> 16;
3340 fw_subminor
= fw_sub_min
& 0xffff;
3341 if (fw_minor
> CONNECTX_4_CURR_MAX_MINOR
||
3342 fw_minor
< CONNECTX_4_INTX_SUPPORT_MINOR
) {
3343 pci_warn(pdev
, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3344 fw_major
, fw_minor
, fw_subminor
, pdev
->device
==
3345 PCI_DEVICE_ID_MELLANOX_CONNECTX4
? 12 : 14);
3346 pdev
->broken_intx_masking
= 1;
3352 pci_disable_device(pdev
);
3354 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
, PCI_ANY_ID
,
3355 mellanox_check_broken_intx_masking
);
3357 static void quirk_no_bus_reset(struct pci_dev
*dev
)
3359 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_BUS_RESET
;
3363 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3364 * The device will throw a Link Down error on AER-capable systems and
3365 * regardless of AER, config space of the device is never accessible again
3366 * and typically causes the system to hang or reset when access is attempted.
3367 * http://www.spinics.net/lists/linux-pci/msg34797.html
3369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0030, quirk_no_bus_reset
);
3370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0032, quirk_no_bus_reset
);
3371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x003c, quirk_no_bus_reset
);
3372 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS
, 0x0033, quirk_no_bus_reset
);
3375 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3376 * reset when used with certain child devices. After the reset, config
3377 * accesses to the child may fail.
3379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM
, 0xa100, quirk_no_bus_reset
);
3381 static void quirk_no_pm_reset(struct pci_dev
*dev
)
3384 * We can't do a bus reset on root bus devices, but an ineffective
3385 * PM reset may be better than nothing.
3387 if (!pci_is_root_bus(dev
->bus
))
3388 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_PM_RESET
;
3392 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3393 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3394 * to have no effect on the device: it retains the framebuffer contents and
3395 * monitor sync. Advertising this support makes other layers, like VFIO,
3396 * assume pci_reset_function() is viable for this device. Mark it as
3397 * unavailable to skip it when testing reset methods.
3399 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
3400 PCI_CLASS_DISPLAY_VGA
, 8, quirk_no_pm_reset
);
3403 * Thunderbolt controllers with broken MSI hotplug signaling:
3404 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3405 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3407 static void quirk_thunderbolt_hotplug_msi(struct pci_dev
*pdev
)
3409 if (pdev
->is_hotplug_bridge
&&
3410 (pdev
->device
!= PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
||
3411 pdev
->revision
<= 1))
3414 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
,
3415 quirk_thunderbolt_hotplug_msi
);
3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE
,
3417 quirk_thunderbolt_hotplug_msi
);
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_LIGHT_PEAK
,
3419 quirk_thunderbolt_hotplug_msi
);
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3421 quirk_thunderbolt_hotplug_msi
);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PORT_RIDGE
,
3423 quirk_thunderbolt_hotplug_msi
);
3427 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3429 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3430 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3431 * be present after resume if a device was plugged in before suspend.
3433 * The Thunderbolt controller consists of a PCIe switch with downstream
3434 * bridges leading to the NHI and to the tunnel PCI bridges.
3436 * This quirk cuts power to the whole chip. Therefore we have to apply it
3437 * during suspend_noirq of the upstream bridge.
3439 * Power is automagically restored before resume. No action is needed.
3441 static void quirk_apple_poweroff_thunderbolt(struct pci_dev
*dev
)
3443 acpi_handle bridge
, SXIO
, SXFP
, SXLV
;
3445 if (!x86_apple_machine
)
3447 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
)
3449 bridge
= ACPI_HANDLE(&dev
->dev
);
3454 * SXIO and SXLV are present only on machines requiring this quirk.
3455 * Thunderbolt bridges in external devices might have the same
3456 * device ID as those on the host, but they will not have the
3457 * associated ACPI methods. This implicitly checks that we are at
3460 if (ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXIO", &SXIO
))
3461 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXFP", &SXFP
))
3462 || ACPI_FAILURE(acpi_get_handle(bridge
, "DSB0.NHI0.SXLV", &SXLV
)))
3464 pci_info(dev
, "quirk: cutting power to Thunderbolt controller...\n");
3466 /* magic sequence */
3467 acpi_execute_simple_method(SXIO
, NULL
, 1);
3468 acpi_execute_simple_method(SXFP
, NULL
, 0);
3470 acpi_execute_simple_method(SXLV
, NULL
, 0);
3471 acpi_execute_simple_method(SXIO
, NULL
, 0);
3472 acpi_execute_simple_method(SXLV
, NULL
, 0);
3474 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL
,
3475 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3476 quirk_apple_poweroff_thunderbolt
);
3479 * Apple: Wait for the Thunderbolt controller to reestablish PCI tunnels
3481 * During suspend the Thunderbolt controller is reset and all PCI
3482 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3483 * during resume. We have to manually wait for the NHI since there is
3484 * no parent child relationship between the NHI and the tunneled
3487 static void quirk_apple_wait_for_thunderbolt(struct pci_dev
*dev
)
3489 struct pci_dev
*sibling
= NULL
;
3490 struct pci_dev
*nhi
= NULL
;
3492 if (!x86_apple_machine
)
3494 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_DOWNSTREAM
)
3498 * Find the NHI and confirm that we are a bridge on the Thunderbolt
3499 * host controller and not on a Thunderbolt endpoint.
3501 sibling
= pci_get_slot(dev
->bus
, 0x0);
3503 goto out
; /* we are the downstream bridge to the NHI */
3504 if (!sibling
|| !sibling
->subordinate
)
3506 nhi
= pci_get_slot(sibling
->subordinate
, 0x0);
3509 if (nhi
->vendor
!= PCI_VENDOR_ID_INTEL
3510 || (nhi
->device
!= PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
&&
3511 nhi
->device
!= PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
&&
3512 nhi
->device
!= PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI
&&
3513 nhi
->device
!= PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI
)
3514 || nhi
->class != PCI_CLASS_SYSTEM_OTHER
<< 8)
3516 pci_info(dev
, "quirk: waiting for Thunderbolt to reestablish PCI tunnels...\n");
3517 device_pm_wait_for_dev(&dev
->dev
, &nhi
->dev
);
3520 pci_dev_put(sibling
);
3522 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3523 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
,
3524 quirk_apple_wait_for_thunderbolt
);
3525 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3526 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
,
3527 quirk_apple_wait_for_thunderbolt
);
3528 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3529 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE
,
3530 quirk_apple_wait_for_thunderbolt
);
3531 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL
,
3532 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE
,
3533 quirk_apple_wait_for_thunderbolt
);
3537 * Following are device-specific reset methods which can be used to
3538 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3541 static int reset_intel_82599_sfp_virtfn(struct pci_dev
*dev
, int probe
)
3544 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3546 * The 82599 supports FLR on VFs, but FLR support is reported only
3547 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3548 * Thus we must call pcie_flr() directly without first checking if it is
3556 #define SOUTH_CHICKEN2 0xc2004
3557 #define PCH_PP_STATUS 0xc7200
3558 #define PCH_PP_CONTROL 0xc7204
3559 #define MSG_CTL 0x45010
3560 #define NSDE_PWR_STATE 0xd0100
3561 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3563 static int reset_ivb_igd(struct pci_dev
*dev
, int probe
)
3565 void __iomem
*mmio_base
;
3566 unsigned long timeout
;
3572 mmio_base
= pci_iomap(dev
, 0, 0);
3576 iowrite32(0x00000002, mmio_base
+ MSG_CTL
);
3579 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3580 * driver loaded sets the right bits. However, this's a reset and
3581 * the bits have been set by i915 previously, so we clobber
3582 * SOUTH_CHICKEN2 register directly here.
3584 iowrite32(0x00000005, mmio_base
+ SOUTH_CHICKEN2
);
3586 val
= ioread32(mmio_base
+ PCH_PP_CONTROL
) & 0xfffffffe;
3587 iowrite32(val
, mmio_base
+ PCH_PP_CONTROL
);
3589 timeout
= jiffies
+ msecs_to_jiffies(IGD_OPERATION_TIMEOUT
);
3591 val
= ioread32(mmio_base
+ PCH_PP_STATUS
);
3592 if ((val
& 0xb0000000) == 0)
3593 goto reset_complete
;
3595 } while (time_before(jiffies
, timeout
));
3596 pci_warn(dev
, "timeout during reset\n");
3599 iowrite32(0x00000002, mmio_base
+ NSDE_PWR_STATE
);
3601 pci_iounmap(dev
, mmio_base
);
3605 /* Device-specific reset method for Chelsio T4-based adapters */
3606 static int reset_chelsio_generic_dev(struct pci_dev
*dev
, int probe
)
3612 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3613 * that we have no device-specific reset method.
3615 if ((dev
->device
& 0xf000) != 0x4000)
3619 * If this is the "probe" phase, return 0 indicating that we can
3620 * reset this device.
3626 * T4 can wedge if there are DMAs in flight within the chip and Bus
3627 * Master has been disabled. We need to have it on till the Function
3628 * Level Reset completes. (BUS_MASTER is disabled in
3629 * pci_reset_function()).
3631 pci_read_config_word(dev
, PCI_COMMAND
, &old_command
);
3632 pci_write_config_word(dev
, PCI_COMMAND
,
3633 old_command
| PCI_COMMAND_MASTER
);
3636 * Perform the actual device function reset, saving and restoring
3637 * configuration information around the reset.
3639 pci_save_state(dev
);
3642 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3643 * are disabled when an MSI-X interrupt message needs to be delivered.
3644 * So we briefly re-enable MSI-X interrupts for the duration of the
3645 * FLR. The pci_restore_state() below will restore the original
3648 pci_read_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
, &msix_flags
);
3649 if ((msix_flags
& PCI_MSIX_FLAGS_ENABLE
) == 0)
3650 pci_write_config_word(dev
, dev
->msix_cap
+PCI_MSIX_FLAGS
,
3652 PCI_MSIX_FLAGS_ENABLE
|
3653 PCI_MSIX_FLAGS_MASKALL
);
3658 * Restore the configuration information (BAR values, etc.) including
3659 * the original PCI Configuration Space Command word, and return
3662 pci_restore_state(dev
);
3663 pci_write_config_word(dev
, PCI_COMMAND
, old_command
);
3667 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3668 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3669 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3672 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3673 * FLR where config space reads from the device return -1. We seem to be
3674 * able to avoid this condition if we disable the NVMe controller prior to
3675 * FLR. This quirk is generic for any NVMe class device requiring similar
3676 * assistance to quiesce the device prior to FLR.
3678 * NVMe specification: https://nvmexpress.org/resources/specifications/
3680 * Chapter 2: Required and optional PCI config registers
3681 * Chapter 3: NVMe control registers
3682 * Chapter 7.3: Reset behavior
3684 static int nvme_disable_and_flr(struct pci_dev
*dev
, int probe
)
3690 if (dev
->class != PCI_CLASS_STORAGE_EXPRESS
||
3691 !pcie_has_flr(dev
) || !pci_resource_start(dev
, 0))
3697 bar
= pci_iomap(dev
, 0, NVME_REG_CC
+ sizeof(cfg
));
3701 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3702 pci_write_config_word(dev
, PCI_COMMAND
, cmd
| PCI_COMMAND_MEMORY
);
3704 cfg
= readl(bar
+ NVME_REG_CC
);
3706 /* Disable controller if enabled */
3707 if (cfg
& NVME_CC_ENABLE
) {
3708 u32 cap
= readl(bar
+ NVME_REG_CAP
);
3709 unsigned long timeout
;
3712 * Per nvme_disable_ctrl() skip shutdown notification as it
3713 * could complete commands to the admin queue. We only intend
3714 * to quiesce the device before reset.
3716 cfg
&= ~(NVME_CC_SHN_MASK
| NVME_CC_ENABLE
);
3718 writel(cfg
, bar
+ NVME_REG_CC
);
3721 * Some controllers require an additional delay here, see
3722 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3723 * supported by this quirk.
3726 /* Cap register provides max timeout in 500ms increments */
3727 timeout
= ((NVME_CAP_TIMEOUT(cap
) + 1) * HZ
/ 2) + jiffies
;
3730 u32 status
= readl(bar
+ NVME_REG_CSTS
);
3732 /* Ready status becomes zero on disable complete */
3733 if (!(status
& NVME_CSTS_RDY
))
3738 if (time_after(jiffies
, timeout
)) {
3739 pci_warn(dev
, "Timeout waiting for NVMe ready status to clear after disable\n");
3745 pci_iounmap(dev
, bar
);
3753 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3754 * to change after NVMe enable if the driver starts interacting with the
3755 * device too soon after FLR. A 250ms delay after FLR has heuristically
3756 * proven to produce reliably working results for device assignment cases.
3758 static int delay_250ms_after_flr(struct pci_dev
*dev
, int probe
)
3760 if (!pcie_has_flr(dev
))
3773 static const struct pci_dev_reset_methods pci_dev_reset_methods
[] = {
3774 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82599_SFP_VF
,
3775 reset_intel_82599_sfp_virtfn
},
3776 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M_VGA
,
3778 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_IVB_M2_VGA
,
3780 { PCI_VENDOR_ID_SAMSUNG
, 0xa804, nvme_disable_and_flr
},
3781 { PCI_VENDOR_ID_INTEL
, 0x0953, delay_250ms_after_flr
},
3782 { PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
3783 reset_chelsio_generic_dev
},
3788 * These device-specific reset methods are here rather than in a driver
3789 * because when a host assigns a device to a guest VM, the host may need
3790 * to reset the device but probably doesn't have a driver for it.
3792 int pci_dev_specific_reset(struct pci_dev
*dev
, int probe
)
3794 const struct pci_dev_reset_methods
*i
;
3796 for (i
= pci_dev_reset_methods
; i
->reset
; i
++) {
3797 if ((i
->vendor
== dev
->vendor
||
3798 i
->vendor
== (u16
)PCI_ANY_ID
) &&
3799 (i
->device
== dev
->device
||
3800 i
->device
== (u16
)PCI_ANY_ID
))
3801 return i
->reset(dev
, probe
);
3807 static void quirk_dma_func0_alias(struct pci_dev
*dev
)
3809 if (PCI_FUNC(dev
->devfn
) != 0)
3810 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0));
3814 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3816 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe832, quirk_dma_func0_alias
);
3819 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH
, 0xe476, quirk_dma_func0_alias
);
3821 static void quirk_dma_func1_alias(struct pci_dev
*dev
)
3823 if (PCI_FUNC(dev
->devfn
) != 1)
3824 pci_add_dma_alias(dev
, PCI_DEVFN(PCI_SLOT(dev
->devfn
), 1));
3828 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3829 * SKUs function 1 is present and is a legacy IDE controller, in other
3830 * SKUs this function is not present, making this a ghost requester.
3831 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9120,
3834 quirk_dma_func1_alias
);
3835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9123,
3836 quirk_dma_func1_alias
);
3837 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9128,
3838 quirk_dma_func1_alias
);
3839 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9130,
3841 quirk_dma_func1_alias
);
3842 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9172,
3844 quirk_dma_func1_alias
);
3845 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x917a,
3847 quirk_dma_func1_alias
);
3848 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9182,
3850 quirk_dma_func1_alias
);
3851 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
3852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9183,
3853 quirk_dma_func1_alias
);
3854 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x91a0,
3856 quirk_dma_func1_alias
);
3857 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9220,
3859 quirk_dma_func1_alias
);
3860 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT
, 0x9230,
3862 quirk_dma_func1_alias
);
3863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0642,
3864 quirk_dma_func1_alias
);
3865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI
, 0x0645,
3866 quirk_dma_func1_alias
);
3867 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON
,
3869 PCI_DEVICE_ID_JMICRON_JMB388_ESD
,
3870 quirk_dma_func1_alias
);
3871 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3872 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3873 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3874 quirk_dma_func1_alias
);
3877 * Some devices DMA with the wrong devfn, not just the wrong function.
3878 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3879 * the alias is "fixed" and independent of the device devfn.
3881 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3882 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3883 * single device on the secondary bus. In reality, the single exposed
3884 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3885 * that provides a bridge to the internal bus of the I/O processor. The
3886 * controller supports private devices, which can be hidden from PCI config
3887 * space. In the case of the Adaptec 3405, a private device at 01.0
3888 * appears to be the DMA engine, which therefore needs to become a DMA
3889 * alias for the device.
3891 static const struct pci_device_id fixed_dma_alias_tbl
[] = {
3892 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
3893 PCI_VENDOR_ID_ADAPTEC2
, 0x02bb), /* Adaptec 3405 */
3894 .driver_data
= PCI_DEVFN(1, 0) },
3895 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2
, 0x0285,
3896 PCI_VENDOR_ID_ADAPTEC2
, 0x02bc), /* Adaptec 3805 */
3897 .driver_data
= PCI_DEVFN(1, 0) },
3901 static void quirk_fixed_dma_alias(struct pci_dev
*dev
)
3903 const struct pci_device_id
*id
;
3905 id
= pci_match_id(fixed_dma_alias_tbl
, dev
);
3907 pci_add_dma_alias(dev
, id
->driver_data
);
3910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2
, 0x0285, quirk_fixed_dma_alias
);
3913 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3914 * using the wrong DMA alias for the device. Some of these devices can be
3915 * used as either forward or reverse bridges, so we need to test whether the
3916 * device is operating in the correct mode. We could probably apply this
3917 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3918 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3919 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3921 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev
*pdev
)
3923 if (!pci_is_root_bus(pdev
->bus
) &&
3924 pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
3925 !pci_is_pcie(pdev
) && pci_is_pcie(pdev
->bus
->self
) &&
3926 pci_pcie_type(pdev
->bus
->self
) != PCI_EXP_TYPE_PCI_BRIDGE
)
3927 pdev
->dev_flags
|= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
;
3929 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA
, 0x1080,
3931 quirk_use_pcie_bridge_dma_alias
);
3932 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3933 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias
);
3934 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3935 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias
);
3936 /* ITE 8893 has the same problem as the 8892 */
3937 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias
);
3938 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3939 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias
);
3942 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3943 * be added as aliases to the DMA device in order to allow buffer access
3944 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3945 * programmed in the EEPROM.
3947 static void quirk_mic_x200_dma_alias(struct pci_dev
*pdev
)
3949 pci_add_dma_alias(pdev
, PCI_DEVFN(0x10, 0x0));
3950 pci_add_dma_alias(pdev
, PCI_DEVFN(0x11, 0x0));
3951 pci_add_dma_alias(pdev
, PCI_DEVFN(0x12, 0x3));
3953 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2260, quirk_mic_x200_dma_alias
);
3954 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x2264, quirk_mic_x200_dma_alias
);
3957 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
3958 * associated not at the root bus, but at a bridge below. This quirk avoids
3959 * generating invalid DMA aliases.
3961 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev
*pdev
)
3963 pdev
->dev_flags
|= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
;
3965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9000,
3966 quirk_bridge_cavm_thrx2_pcie_root
);
3967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM
, 0x9084,
3968 quirk_bridge_cavm_thrx2_pcie_root
);
3971 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3972 * class code. Fix it.
3974 static void quirk_tw686x_class(struct pci_dev
*pdev
)
3976 u32
class = pdev
->class;
3978 /* Use "Multimedia controller" class */
3979 pdev
->class = (PCI_CLASS_MULTIMEDIA_OTHER
<< 8) | 0x01;
3980 pci_info(pdev
, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3981 class, pdev
->class);
3983 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED
, 8,
3984 quirk_tw686x_class
);
3985 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED
, 8,
3986 quirk_tw686x_class
);
3987 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED
, 8,
3988 quirk_tw686x_class
);
3989 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED
, 8,
3990 quirk_tw686x_class
);
3993 * Some devices have problems with Transaction Layer Packets with the Relaxed
3994 * Ordering Attribute set. Such devices should mark themselves and other
3995 * device drivers should check before sending TLPs with RO set.
3997 static void quirk_relaxedordering_disable(struct pci_dev
*dev
)
3999 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_RELAXED_ORDERING
;
4000 pci_info(dev
, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4004 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4005 * Complex have a Flow Control Credit issue which can cause performance
4006 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4008 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f01, PCI_CLASS_NOT_DEFINED
, 8,
4009 quirk_relaxedordering_disable
);
4010 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f02, PCI_CLASS_NOT_DEFINED
, 8,
4011 quirk_relaxedordering_disable
);
4012 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f03, PCI_CLASS_NOT_DEFINED
, 8,
4013 quirk_relaxedordering_disable
);
4014 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f04, PCI_CLASS_NOT_DEFINED
, 8,
4015 quirk_relaxedordering_disable
);
4016 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f05, PCI_CLASS_NOT_DEFINED
, 8,
4017 quirk_relaxedordering_disable
);
4018 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f06, PCI_CLASS_NOT_DEFINED
, 8,
4019 quirk_relaxedordering_disable
);
4020 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f07, PCI_CLASS_NOT_DEFINED
, 8,
4021 quirk_relaxedordering_disable
);
4022 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f08, PCI_CLASS_NOT_DEFINED
, 8,
4023 quirk_relaxedordering_disable
);
4024 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f09, PCI_CLASS_NOT_DEFINED
, 8,
4025 quirk_relaxedordering_disable
);
4026 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0a, PCI_CLASS_NOT_DEFINED
, 8,
4027 quirk_relaxedordering_disable
);
4028 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0b, PCI_CLASS_NOT_DEFINED
, 8,
4029 quirk_relaxedordering_disable
);
4030 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0c, PCI_CLASS_NOT_DEFINED
, 8,
4031 quirk_relaxedordering_disable
);
4032 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0d, PCI_CLASS_NOT_DEFINED
, 8,
4033 quirk_relaxedordering_disable
);
4034 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x6f0e, PCI_CLASS_NOT_DEFINED
, 8,
4035 quirk_relaxedordering_disable
);
4036 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f01, PCI_CLASS_NOT_DEFINED
, 8,
4037 quirk_relaxedordering_disable
);
4038 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f02, PCI_CLASS_NOT_DEFINED
, 8,
4039 quirk_relaxedordering_disable
);
4040 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f03, PCI_CLASS_NOT_DEFINED
, 8,
4041 quirk_relaxedordering_disable
);
4042 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f04, PCI_CLASS_NOT_DEFINED
, 8,
4043 quirk_relaxedordering_disable
);
4044 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f05, PCI_CLASS_NOT_DEFINED
, 8,
4045 quirk_relaxedordering_disable
);
4046 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f06, PCI_CLASS_NOT_DEFINED
, 8,
4047 quirk_relaxedordering_disable
);
4048 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f07, PCI_CLASS_NOT_DEFINED
, 8,
4049 quirk_relaxedordering_disable
);
4050 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f08, PCI_CLASS_NOT_DEFINED
, 8,
4051 quirk_relaxedordering_disable
);
4052 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f09, PCI_CLASS_NOT_DEFINED
, 8,
4053 quirk_relaxedordering_disable
);
4054 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0a, PCI_CLASS_NOT_DEFINED
, 8,
4055 quirk_relaxedordering_disable
);
4056 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0b, PCI_CLASS_NOT_DEFINED
, 8,
4057 quirk_relaxedordering_disable
);
4058 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0c, PCI_CLASS_NOT_DEFINED
, 8,
4059 quirk_relaxedordering_disable
);
4060 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0d, PCI_CLASS_NOT_DEFINED
, 8,
4061 quirk_relaxedordering_disable
);
4062 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL
, 0x2f0e, PCI_CLASS_NOT_DEFINED
, 8,
4063 quirk_relaxedordering_disable
);
4066 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4067 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4068 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4069 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4070 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4071 * November 10, 2010). As a result, on this platform we can't use Relaxed
4072 * Ordering for Upstream TLPs.
4074 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a00, PCI_CLASS_NOT_DEFINED
, 8,
4075 quirk_relaxedordering_disable
);
4076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a01, PCI_CLASS_NOT_DEFINED
, 8,
4077 quirk_relaxedordering_disable
);
4078 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD
, 0x1a02, PCI_CLASS_NOT_DEFINED
, 8,
4079 quirk_relaxedordering_disable
);
4082 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4083 * values for the Attribute as were supplied in the header of the
4084 * corresponding Request, except as explicitly allowed when IDO is used."
4086 * If a non-compliant device generates a completion with a different
4087 * attribute than the request, the receiver may accept it (which itself
4088 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4089 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4090 * device access timeout.
4092 * If the non-compliant device generates completions with zero attributes
4093 * (instead of copying the attributes from the request), we can work around
4094 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4095 * upstream devices so they always generate requests with zero attributes.
4097 * This affects other devices under the same Root Port, but since these
4098 * attributes are performance hints, there should be no functional problem.
4100 * Note that Configuration Space accesses are never supposed to have TLP
4101 * Attributes, so we're safe waiting till after any Configuration Space
4102 * accesses to do the Root Port fixup.
4104 static void quirk_disable_root_port_attributes(struct pci_dev
*pdev
)
4106 struct pci_dev
*root_port
= pci_find_pcie_root_port(pdev
);
4109 pci_warn(pdev
, "PCIe Completion erratum may cause device errors\n");
4113 pci_info(root_port
, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4114 dev_name(&pdev
->dev
));
4115 pcie_capability_clear_and_set_word(root_port
, PCI_EXP_DEVCTL
,
4116 PCI_EXP_DEVCTL_RELAX_EN
|
4117 PCI_EXP_DEVCTL_NOSNOOP_EN
, 0);
4121 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4122 * Completion it generates.
4124 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev
*pdev
)
4127 * This mask/compare operation selects for Physical Function 4 on a
4128 * T5. We only need to fix up the Root Port once for any of the
4129 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4130 * 0x54xx so we use that one.
4132 if ((pdev
->device
& 0xff00) == 0x5400)
4133 quirk_disable_root_port_attributes(pdev
);
4135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO
, PCI_ANY_ID
,
4136 quirk_chelsio_T5_disable_root_port_attributes
);
4139 * AMD has indicated that the devices below do not support peer-to-peer
4140 * in any system where they are found in the southbridge with an AMD
4141 * IOMMU in the system. Multifunction devices that do not support
4142 * peer-to-peer between functions can claim to support a subset of ACS.
4143 * Such devices effectively enable request redirect (RR) and completion
4144 * redirect (CR) since all transactions are redirected to the upstream
4147 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4148 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4149 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4151 * 1002:4385 SBx00 SMBus Controller
4152 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4153 * 1002:4383 SBx00 Azalia (Intel HDA)
4154 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4155 * 1002:4384 SBx00 PCI to PCI Bridge
4156 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4158 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4160 * 1022:780f [AMD] FCH PCI Bridge
4161 * 1022:7809 [AMD] FCH USB OHCI Controller
4163 static int pci_quirk_amd_sb_acs(struct pci_dev
*dev
, u16 acs_flags
)
4166 struct acpi_table_header
*header
= NULL
;
4169 /* Targeting multifunction devices on the SB (appears on root bus) */
4170 if (!dev
->multifunction
|| !pci_is_root_bus(dev
->bus
))
4173 /* The IVRS table describes the AMD IOMMU */
4174 status
= acpi_get_table("IVRS", 0, &header
);
4175 if (ACPI_FAILURE(status
))
4178 /* Filter out flags not applicable to multifunction */
4179 acs_flags
&= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
| PCI_ACS_DT
);
4181 return acs_flags
& ~(PCI_ACS_RR
| PCI_ACS_CR
) ? 0 : 1;
4187 static bool pci_quirk_cavium_acs_match(struct pci_dev
*dev
)
4190 * Effectively selects all downstream ports for whole ThunderX 1
4191 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4192 * bits of device ID are used to indicate which subdevice is used
4195 return (pci_is_pcie(dev
) &&
4196 (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
) &&
4197 ((dev
->device
& 0xf800) == 0xa000));
4200 static int pci_quirk_cavium_acs(struct pci_dev
*dev
, u16 acs_flags
)
4203 * Cavium root ports don't advertise an ACS capability. However,
4204 * the RTL internally implements similar protection as if ACS had
4205 * Request Redirection, Completion Redirection, Source Validation,
4206 * and Upstream Forwarding features enabled. Assert that the
4207 * hardware implements and enables equivalent ACS functionality for
4210 acs_flags
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_SV
| PCI_ACS_UF
);
4212 if (!pci_quirk_cavium_acs_match(dev
))
4215 return acs_flags
? 0 : 1;
4218 static int pci_quirk_xgene_acs(struct pci_dev
*dev
, u16 acs_flags
)
4221 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4222 * transactions with others, allowing masking out these bits as if they
4223 * were unimplemented in the ACS capability.
4225 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
);
4227 return acs_flags
? 0 : 1;
4231 * Many Intel PCH root ports do provide ACS-like features to disable peer
4232 * transactions and validate bus numbers in requests, but do not provide an
4233 * actual PCIe ACS capability. This is the list of device IDs known to fall
4234 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4236 static const u16 pci_quirk_intel_pch_acs_ids
[] = {
4238 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4239 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4240 /* Cougarpoint PCH */
4241 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4242 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4243 /* Pantherpoint PCH */
4244 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4245 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4246 /* Lynxpoint-H PCH */
4247 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4248 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4249 /* Lynxpoint-LP PCH */
4250 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4251 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4253 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4254 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4255 /* Patsburg (X79) PCH */
4256 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4257 /* Wellsburg (X99) PCH */
4258 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4259 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4260 /* Lynx Point (9 series) PCH */
4261 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4264 static bool pci_quirk_intel_pch_acs_match(struct pci_dev
*dev
)
4268 /* Filter out a few obvious non-matches first */
4269 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4272 for (i
= 0; i
< ARRAY_SIZE(pci_quirk_intel_pch_acs_ids
); i
++)
4273 if (pci_quirk_intel_pch_acs_ids
[i
] == dev
->device
)
4279 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4281 static int pci_quirk_intel_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4283 u16 flags
= dev
->dev_flags
& PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
?
4284 INTEL_PCH_ACS_FLAGS
: 0;
4286 if (!pci_quirk_intel_pch_acs_match(dev
))
4289 return acs_flags
& ~flags
? 0 : 1;
4293 * These QCOM root ports do provide ACS-like features to disable peer
4294 * transactions and validate bus numbers in requests, but do not provide an
4295 * actual PCIe ACS capability. Hardware supports source validation but it
4296 * will report the issue as Completer Abort instead of ACS Violation.
4297 * Hardware doesn't support peer-to-peer and each root port is a root
4298 * complex with unique segment numbers. It is not possible for one root
4299 * port to pass traffic to another root port. All PCIe transactions are
4300 * terminated inside the root port.
4302 static int pci_quirk_qcom_rp_acs(struct pci_dev
*dev
, u16 acs_flags
)
4304 u16 flags
= (PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_SV
);
4305 int ret
= acs_flags
& ~flags
? 0 : 1;
4307 pci_info(dev
, "Using QCOM ACS Quirk (%d)\n", ret
);
4313 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4314 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4315 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4316 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4317 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4318 * control register is at offset 8 instead of 6 and we should probably use
4319 * dword accesses to them. This applies to the following PCI Device IDs, as
4320 * found in volume 1 of the datasheet[2]:
4322 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4323 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4325 * N.B. This doesn't fix what lspci shows.
4327 * The 100 series chipset specification update includes this as errata #23[3].
4329 * The 200 series chipset (Union Point) has the same bug according to the
4330 * specification update (Intel 200 Series Chipset Family Platform Controller
4331 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4332 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4335 * 0xa290-0xa29f PCI Express Root port #{0-16}
4336 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4338 * Mobile chipsets are also affected, 7th & 8th Generation
4339 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4340 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4341 * Processor Family I/O for U Quad Core Platforms Specification Update,
4342 * August 2017, Revision 002, Document#: 334660-002)[6]
4343 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4344 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4345 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4347 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4349 * The 300 series chipset suffers from the same bug so include those root
4350 * ports here as well.
4352 * 0xa32c-0xa343 PCI Express Root port #{0-24}
4354 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4355 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4356 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4357 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4358 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4359 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4360 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4362 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev
*dev
)
4364 if (!pci_is_pcie(dev
) || pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
4367 switch (dev
->device
) {
4368 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4369 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4370 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4371 case 0xa32c ... 0xa343: /* 300 series */
4378 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4380 static int pci_quirk_intel_spt_pch_acs(struct pci_dev
*dev
, u16 acs_flags
)
4385 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4388 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
4392 /* see pci_acs_flags_enabled() */
4393 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4394 acs_flags
&= (cap
| PCI_ACS_EC
);
4396 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4398 return acs_flags
& ~ctrl
? 0 : 1;
4401 static int pci_quirk_mf_endpoint_acs(struct pci_dev
*dev
, u16 acs_flags
)
4404 * SV, TB, and UF are not relevant to multifunction endpoints.
4406 * Multifunction devices are only required to implement RR, CR, and DT
4407 * in their ACS capability if they support peer-to-peer transactions.
4408 * Devices matching this quirk have been verified by the vendor to not
4409 * perform peer-to-peer with other functions, allowing us to mask out
4410 * these bits as if they were unimplemented in the ACS capability.
4412 acs_flags
&= ~(PCI_ACS_SV
| PCI_ACS_TB
| PCI_ACS_RR
|
4413 PCI_ACS_CR
| PCI_ACS_UF
| PCI_ACS_DT
);
4415 return acs_flags
? 0 : 1;
4418 static const struct pci_dev_acs_enabled
{
4421 int (*acs_enabled
)(struct pci_dev
*dev
, u16 acs_flags
);
4422 } pci_dev_acs_enabled
[] = {
4423 { PCI_VENDOR_ID_ATI
, 0x4385, pci_quirk_amd_sb_acs
},
4424 { PCI_VENDOR_ID_ATI
, 0x439c, pci_quirk_amd_sb_acs
},
4425 { PCI_VENDOR_ID_ATI
, 0x4383, pci_quirk_amd_sb_acs
},
4426 { PCI_VENDOR_ID_ATI
, 0x439d, pci_quirk_amd_sb_acs
},
4427 { PCI_VENDOR_ID_ATI
, 0x4384, pci_quirk_amd_sb_acs
},
4428 { PCI_VENDOR_ID_ATI
, 0x4399, pci_quirk_amd_sb_acs
},
4429 { PCI_VENDOR_ID_AMD
, 0x780f, pci_quirk_amd_sb_acs
},
4430 { PCI_VENDOR_ID_AMD
, 0x7809, pci_quirk_amd_sb_acs
},
4431 { PCI_VENDOR_ID_SOLARFLARE
, 0x0903, pci_quirk_mf_endpoint_acs
},
4432 { PCI_VENDOR_ID_SOLARFLARE
, 0x0923, pci_quirk_mf_endpoint_acs
},
4433 { PCI_VENDOR_ID_SOLARFLARE
, 0x0A03, pci_quirk_mf_endpoint_acs
},
4434 { PCI_VENDOR_ID_INTEL
, 0x10C6, pci_quirk_mf_endpoint_acs
},
4435 { PCI_VENDOR_ID_INTEL
, 0x10DB, pci_quirk_mf_endpoint_acs
},
4436 { PCI_VENDOR_ID_INTEL
, 0x10DD, pci_quirk_mf_endpoint_acs
},
4437 { PCI_VENDOR_ID_INTEL
, 0x10E1, pci_quirk_mf_endpoint_acs
},
4438 { PCI_VENDOR_ID_INTEL
, 0x10F1, pci_quirk_mf_endpoint_acs
},
4439 { PCI_VENDOR_ID_INTEL
, 0x10F7, pci_quirk_mf_endpoint_acs
},
4440 { PCI_VENDOR_ID_INTEL
, 0x10F8, pci_quirk_mf_endpoint_acs
},
4441 { PCI_VENDOR_ID_INTEL
, 0x10F9, pci_quirk_mf_endpoint_acs
},
4442 { PCI_VENDOR_ID_INTEL
, 0x10FA, pci_quirk_mf_endpoint_acs
},
4443 { PCI_VENDOR_ID_INTEL
, 0x10FB, pci_quirk_mf_endpoint_acs
},
4444 { PCI_VENDOR_ID_INTEL
, 0x10FC, pci_quirk_mf_endpoint_acs
},
4445 { PCI_VENDOR_ID_INTEL
, 0x1507, pci_quirk_mf_endpoint_acs
},
4446 { PCI_VENDOR_ID_INTEL
, 0x1514, pci_quirk_mf_endpoint_acs
},
4447 { PCI_VENDOR_ID_INTEL
, 0x151C, pci_quirk_mf_endpoint_acs
},
4448 { PCI_VENDOR_ID_INTEL
, 0x1529, pci_quirk_mf_endpoint_acs
},
4449 { PCI_VENDOR_ID_INTEL
, 0x152A, pci_quirk_mf_endpoint_acs
},
4450 { PCI_VENDOR_ID_INTEL
, 0x154D, pci_quirk_mf_endpoint_acs
},
4451 { PCI_VENDOR_ID_INTEL
, 0x154F, pci_quirk_mf_endpoint_acs
},
4452 { PCI_VENDOR_ID_INTEL
, 0x1551, pci_quirk_mf_endpoint_acs
},
4453 { PCI_VENDOR_ID_INTEL
, 0x1558, pci_quirk_mf_endpoint_acs
},
4455 { PCI_VENDOR_ID_INTEL
, 0x1509, pci_quirk_mf_endpoint_acs
},
4456 { PCI_VENDOR_ID_INTEL
, 0x150E, pci_quirk_mf_endpoint_acs
},
4457 { PCI_VENDOR_ID_INTEL
, 0x150F, pci_quirk_mf_endpoint_acs
},
4458 { PCI_VENDOR_ID_INTEL
, 0x1510, pci_quirk_mf_endpoint_acs
},
4459 { PCI_VENDOR_ID_INTEL
, 0x1511, pci_quirk_mf_endpoint_acs
},
4460 { PCI_VENDOR_ID_INTEL
, 0x1516, pci_quirk_mf_endpoint_acs
},
4461 { PCI_VENDOR_ID_INTEL
, 0x1527, pci_quirk_mf_endpoint_acs
},
4463 { PCI_VENDOR_ID_INTEL
, 0x10C9, pci_quirk_mf_endpoint_acs
},
4464 { PCI_VENDOR_ID_INTEL
, 0x10E6, pci_quirk_mf_endpoint_acs
},
4465 { PCI_VENDOR_ID_INTEL
, 0x10E7, pci_quirk_mf_endpoint_acs
},
4466 { PCI_VENDOR_ID_INTEL
, 0x10E8, pci_quirk_mf_endpoint_acs
},
4467 { PCI_VENDOR_ID_INTEL
, 0x150A, pci_quirk_mf_endpoint_acs
},
4468 { PCI_VENDOR_ID_INTEL
, 0x150D, pci_quirk_mf_endpoint_acs
},
4469 { PCI_VENDOR_ID_INTEL
, 0x1518, pci_quirk_mf_endpoint_acs
},
4470 { PCI_VENDOR_ID_INTEL
, 0x1526, pci_quirk_mf_endpoint_acs
},
4472 { PCI_VENDOR_ID_INTEL
, 0x10A7, pci_quirk_mf_endpoint_acs
},
4473 { PCI_VENDOR_ID_INTEL
, 0x10A9, pci_quirk_mf_endpoint_acs
},
4474 { PCI_VENDOR_ID_INTEL
, 0x10D6, pci_quirk_mf_endpoint_acs
},
4476 { PCI_VENDOR_ID_INTEL
, 0x1521, pci_quirk_mf_endpoint_acs
},
4477 { PCI_VENDOR_ID_INTEL
, 0x1522, pci_quirk_mf_endpoint_acs
},
4478 { PCI_VENDOR_ID_INTEL
, 0x1523, pci_quirk_mf_endpoint_acs
},
4479 { PCI_VENDOR_ID_INTEL
, 0x1524, pci_quirk_mf_endpoint_acs
},
4480 /* 82571 (Quads omitted due to non-ACS switch) */
4481 { PCI_VENDOR_ID_INTEL
, 0x105E, pci_quirk_mf_endpoint_acs
},
4482 { PCI_VENDOR_ID_INTEL
, 0x105F, pci_quirk_mf_endpoint_acs
},
4483 { PCI_VENDOR_ID_INTEL
, 0x1060, pci_quirk_mf_endpoint_acs
},
4484 { PCI_VENDOR_ID_INTEL
, 0x10D9, pci_quirk_mf_endpoint_acs
},
4486 { PCI_VENDOR_ID_INTEL
, 0x15b7, pci_quirk_mf_endpoint_acs
},
4487 { PCI_VENDOR_ID_INTEL
, 0x15b8, pci_quirk_mf_endpoint_acs
},
4488 /* QCOM QDF2xxx root ports */
4489 { PCI_VENDOR_ID_QCOM
, 0x0400, pci_quirk_qcom_rp_acs
},
4490 { PCI_VENDOR_ID_QCOM
, 0x0401, pci_quirk_qcom_rp_acs
},
4491 /* Intel PCH root ports */
4492 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_pch_acs
},
4493 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, pci_quirk_intel_spt_pch_acs
},
4494 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs
}, /* Emulex BE3-R */
4495 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs
}, /* Emulex Skyhawk-R */
4496 /* Cavium ThunderX */
4497 { PCI_VENDOR_ID_CAVIUM
, PCI_ANY_ID
, pci_quirk_cavium_acs
},
4499 { PCI_VENDOR_ID_AMCC
, 0xE004, pci_quirk_xgene_acs
},
4500 /* Ampere Computing */
4501 { PCI_VENDOR_ID_AMPERE
, 0xE005, pci_quirk_xgene_acs
},
4502 { PCI_VENDOR_ID_AMPERE
, 0xE006, pci_quirk_xgene_acs
},
4503 { PCI_VENDOR_ID_AMPERE
, 0xE007, pci_quirk_xgene_acs
},
4504 { PCI_VENDOR_ID_AMPERE
, 0xE008, pci_quirk_xgene_acs
},
4505 { PCI_VENDOR_ID_AMPERE
, 0xE009, pci_quirk_xgene_acs
},
4506 { PCI_VENDOR_ID_AMPERE
, 0xE00A, pci_quirk_xgene_acs
},
4507 { PCI_VENDOR_ID_AMPERE
, 0xE00B, pci_quirk_xgene_acs
},
4508 { PCI_VENDOR_ID_AMPERE
, 0xE00C, pci_quirk_xgene_acs
},
4512 int pci_dev_specific_acs_enabled(struct pci_dev
*dev
, u16 acs_flags
)
4514 const struct pci_dev_acs_enabled
*i
;
4518 * Allow devices that do not expose standard PCIe ACS capabilities
4519 * or control to indicate their support here. Multi-function express
4520 * devices which do not allow internal peer-to-peer between functions,
4521 * but do not implement PCIe ACS may wish to return true here.
4523 for (i
= pci_dev_acs_enabled
; i
->acs_enabled
; i
++) {
4524 if ((i
->vendor
== dev
->vendor
||
4525 i
->vendor
== (u16
)PCI_ANY_ID
) &&
4526 (i
->device
== dev
->device
||
4527 i
->device
== (u16
)PCI_ANY_ID
)) {
4528 ret
= i
->acs_enabled(dev
, acs_flags
);
4537 /* Config space offset of Root Complex Base Address register */
4538 #define INTEL_LPC_RCBA_REG 0xf0
4539 /* 31:14 RCBA address */
4540 #define INTEL_LPC_RCBA_MASK 0xffffc000
4542 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4544 /* Backbone Scratch Pad Register */
4545 #define INTEL_BSPR_REG 0x1104
4546 /* Backbone Peer Non-Posted Disable */
4547 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4548 /* Backbone Peer Posted Disable */
4549 #define INTEL_BSPR_REG_BPPD (1 << 9)
4551 /* Upstream Peer Decode Configuration Register */
4552 #define INTEL_UPDCR_REG 0x1114
4553 /* 5:0 Peer Decode Enable bits */
4554 #define INTEL_UPDCR_REG_MASK 0x3f
4556 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev
*dev
)
4558 u32 rcba
, bspr
, updcr
;
4559 void __iomem
*rcba_mem
;
4562 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4563 * are D28:F* and therefore get probed before LPC, thus we can't
4564 * use pci_get_slot()/pci_read_config_dword() here.
4566 pci_bus_read_config_dword(dev
->bus
, PCI_DEVFN(31, 0),
4567 INTEL_LPC_RCBA_REG
, &rcba
);
4568 if (!(rcba
& INTEL_LPC_RCBA_ENABLE
))
4571 rcba_mem
= ioremap_nocache(rcba
& INTEL_LPC_RCBA_MASK
,
4572 PAGE_ALIGN(INTEL_UPDCR_REG
));
4577 * The BSPR can disallow peer cycles, but it's set by soft strap and
4578 * therefore read-only. If both posted and non-posted peer cycles are
4579 * disallowed, we're ok. If either are allowed, then we need to use
4580 * the UPDCR to disable peer decodes for each port. This provides the
4581 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4583 bspr
= readl(rcba_mem
+ INTEL_BSPR_REG
);
4584 bspr
&= INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
;
4585 if (bspr
!= (INTEL_BSPR_REG_BPNPD
| INTEL_BSPR_REG_BPPD
)) {
4586 updcr
= readl(rcba_mem
+ INTEL_UPDCR_REG
);
4587 if (updcr
& INTEL_UPDCR_REG_MASK
) {
4588 pci_info(dev
, "Disabling UPDCR peer decodes\n");
4589 updcr
&= ~INTEL_UPDCR_REG_MASK
;
4590 writel(updcr
, rcba_mem
+ INTEL_UPDCR_REG
);
4598 /* Miscellaneous Port Configuration register */
4599 #define INTEL_MPC_REG 0xd8
4600 /* MPC: Invalid Receive Bus Number Check Enable */
4601 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4603 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev
*dev
)
4608 * When enabled, the IRBNCE bit of the MPC register enables the
4609 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4610 * ensures that requester IDs fall within the bus number range
4611 * of the bridge. Enable if not already.
4613 pci_read_config_dword(dev
, INTEL_MPC_REG
, &mpc
);
4614 if (!(mpc
& INTEL_MPC_REG_IRBNCE
)) {
4615 pci_info(dev
, "Enabling MPC IRBNCE\n");
4616 mpc
|= INTEL_MPC_REG_IRBNCE
;
4617 pci_write_config_word(dev
, INTEL_MPC_REG
, mpc
);
4621 static int pci_quirk_enable_intel_pch_acs(struct pci_dev
*dev
)
4623 if (!pci_quirk_intel_pch_acs_match(dev
))
4626 if (pci_quirk_enable_intel_lpc_acs(dev
)) {
4627 pci_warn(dev
, "Failed to enable Intel PCH ACS quirk\n");
4631 pci_quirk_enable_intel_rp_mpc_acs(dev
);
4633 dev
->dev_flags
|= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
;
4635 pci_info(dev
, "Intel PCH root port ACS workaround enabled\n");
4640 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev
*dev
)
4645 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4648 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
4652 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4653 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4655 ctrl
|= (cap
& PCI_ACS_SV
);
4656 ctrl
|= (cap
& PCI_ACS_RR
);
4657 ctrl
|= (cap
& PCI_ACS_CR
);
4658 ctrl
|= (cap
& PCI_ACS_UF
);
4660 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
4662 pci_info(dev
, "Intel SPT PCH root port ACS workaround enabled\n");
4667 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev
*dev
)
4672 if (!pci_quirk_intel_spt_pch_acs_match(dev
))
4675 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
4679 pci_read_config_dword(dev
, pos
+ PCI_ACS_CAP
, &cap
);
4680 pci_read_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, &ctrl
);
4682 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
4684 pci_write_config_dword(dev
, pos
+ INTEL_SPT_ACS_CTRL
, ctrl
);
4686 pci_info(dev
, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
4691 static const struct pci_dev_acs_ops
{
4694 int (*enable_acs
)(struct pci_dev
*dev
);
4695 int (*disable_acs_redir
)(struct pci_dev
*dev
);
4696 } pci_dev_acs_ops
[] = {
4697 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
4698 .enable_acs
= pci_quirk_enable_intel_pch_acs
,
4700 { PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
,
4701 .enable_acs
= pci_quirk_enable_intel_spt_pch_acs
,
4702 .disable_acs_redir
= pci_quirk_disable_intel_spt_pch_acs_redir
,
4706 int pci_dev_specific_enable_acs(struct pci_dev
*dev
)
4708 const struct pci_dev_acs_ops
*p
;
4711 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
4712 p
= &pci_dev_acs_ops
[i
];
4713 if ((p
->vendor
== dev
->vendor
||
4714 p
->vendor
== (u16
)PCI_ANY_ID
) &&
4715 (p
->device
== dev
->device
||
4716 p
->device
== (u16
)PCI_ANY_ID
) &&
4718 ret
= p
->enable_acs(dev
);
4727 int pci_dev_specific_disable_acs_redir(struct pci_dev
*dev
)
4729 const struct pci_dev_acs_ops
*p
;
4732 for (i
= 0; i
< ARRAY_SIZE(pci_dev_acs_ops
); i
++) {
4733 p
= &pci_dev_acs_ops
[i
];
4734 if ((p
->vendor
== dev
->vendor
||
4735 p
->vendor
== (u16
)PCI_ANY_ID
) &&
4736 (p
->device
== dev
->device
||
4737 p
->device
== (u16
)PCI_ANY_ID
) &&
4738 p
->disable_acs_redir
) {
4739 ret
= p
->disable_acs_redir(dev
);
4749 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
4750 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4751 * Next Capability pointer in the MSI Capability Structure should point to
4752 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4755 static void quirk_intel_qat_vf_cap(struct pci_dev
*pdev
)
4760 struct pci_cap_saved_state
*state
;
4762 /* Bail if the hardware bug is fixed */
4763 if (pdev
->pcie_cap
|| pci_find_capability(pdev
, PCI_CAP_ID_EXP
))
4766 /* Bail if MSI Capability Structure is not found for some reason */
4767 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSI
);
4772 * Bail if Next Capability pointer in the MSI Capability Structure
4773 * is not the expected incorrect 0x00.
4775 pci_read_config_byte(pdev
, pos
+ 1, &next_cap
);
4780 * PCIe Capability Structure is expected to be at 0x50 and should
4781 * terminate the list (Next Capability pointer is 0x00). Verify
4782 * Capability Id and Next Capability pointer is as expected.
4783 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4784 * to correctly set kernel data structures which have already been
4785 * set incorrectly due to the hardware bug.
4788 pci_read_config_word(pdev
, pos
, ®16
);
4789 if (reg16
== (0x0000 | PCI_CAP_ID_EXP
)) {
4791 #ifndef PCI_EXP_SAVE_REGS
4792 #define PCI_EXP_SAVE_REGS 7
4794 int size
= PCI_EXP_SAVE_REGS
* sizeof(u16
);
4796 pdev
->pcie_cap
= pos
;
4797 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
4798 pdev
->pcie_flags_reg
= reg16
;
4799 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
4800 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
4802 pdev
->cfg_size
= PCI_CFG_SPACE_EXP_SIZE
;
4803 if (pci_read_config_dword(pdev
, PCI_CFG_SPACE_SIZE
, &status
) !=
4804 PCIBIOS_SUCCESSFUL
|| (status
== 0xffffffff))
4805 pdev
->cfg_size
= PCI_CFG_SPACE_SIZE
;
4807 if (pci_find_saved_cap(pdev
, PCI_CAP_ID_EXP
))
4811 state
= kzalloc(sizeof(*state
) + size
, GFP_KERNEL
);
4815 state
->cap
.cap_nr
= PCI_CAP_ID_EXP
;
4816 state
->cap
.cap_extended
= 0;
4817 state
->cap
.size
= size
;
4818 cap
= (u16
*)&state
->cap
.data
[0];
4819 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
4820 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
4821 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
4822 pcie_capability_read_word(pdev
, PCI_EXP_RTCTL
, &cap
[i
++]);
4823 pcie_capability_read_word(pdev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
4824 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
4825 pcie_capability_read_word(pdev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
4826 hlist_add_head(&state
->next
, &pdev
->saved_cap_space
);
4829 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x443, quirk_intel_qat_vf_cap
);
4831 /* FLR may cause some 82579 devices to hang */
4832 static void quirk_intel_no_flr(struct pci_dev
*dev
)
4834 dev
->dev_flags
|= PCI_DEV_FLAGS_NO_FLR_RESET
;
4836 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1502, quirk_intel_no_flr
);
4837 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, 0x1503, quirk_intel_no_flr
);
4839 static void quirk_no_ext_tags(struct pci_dev
*pdev
)
4841 struct pci_host_bridge
*bridge
= pci_find_host_bridge(pdev
->bus
);
4846 bridge
->no_ext_tags
= 1;
4847 pci_info(pdev
, "disabling Extended Tags (this device can't handle them)\n");
4849 pci_walk_bus(bridge
->bus
, pci_configure_extended_tags
, NULL
);
4851 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0132, quirk_no_ext_tags
);
4852 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0140, quirk_no_ext_tags
);
4853 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0141, quirk_no_ext_tags
);
4854 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0142, quirk_no_ext_tags
);
4855 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0144, quirk_no_ext_tags
);
4856 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0420, quirk_no_ext_tags
);
4857 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, 0x0422, quirk_no_ext_tags
);
4859 #ifdef CONFIG_PCI_ATS
4861 * Some devices have a broken ATS implementation causing IOMMU stalls.
4862 * Don't use ATS for those devices.
4864 static void quirk_no_ats(struct pci_dev
*pdev
)
4866 pci_info(pdev
, "disabling ATS (broken on this device)\n");
4870 /* AMD Stoney platform GPU */
4871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, 0x98e4, quirk_no_ats
);
4872 #endif /* CONFIG_PCI_ATS */
4874 /* Freescale PCIe doesn't support MSI in RC mode */
4875 static void quirk_fsl_no_msi(struct pci_dev
*pdev
)
4877 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
)
4880 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, quirk_fsl_no_msi
);
4883 * GPUs with integrated HDA controller for streaming audio to attached displays
4884 * need a device link from the HDA controller (consumer) to the GPU (supplier)
4885 * so that the GPU is powered up whenever the HDA controller is accessed.
4886 * The GPU and HDA controller are functions 0 and 1 of the same PCI device.
4887 * The device link stays in place until shutdown (or removal of the PCI device
4888 * if it's hotplugged). Runtime PM is allowed by default on the HDA controller
4889 * to prevent it from permanently keeping the GPU awake.
4891 static void quirk_gpu_hda(struct pci_dev
*hda
)
4893 struct pci_dev
*gpu
;
4895 if (PCI_FUNC(hda
->devfn
) != 1)
4898 gpu
= pci_get_domain_bus_and_slot(pci_domain_nr(hda
->bus
),
4900 PCI_DEVFN(PCI_SLOT(hda
->devfn
), 0));
4901 if (!gpu
|| (gpu
->class >> 16) != PCI_BASE_CLASS_DISPLAY
) {
4906 if (!device_link_add(&hda
->dev
, &gpu
->dev
,
4907 DL_FLAG_STATELESS
| DL_FLAG_PM_RUNTIME
))
4908 pci_err(hda
, "cannot link HDA to GPU %s\n", pci_name(gpu
));
4910 pm_runtime_allow(&hda
->dev
);
4913 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
,
4914 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
4915 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
,
4916 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
4917 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
,
4918 PCI_CLASS_MULTIMEDIA_HD_AUDIO
, 8, quirk_gpu_hda
);
4921 * Some IDT switches incorrectly flag an ACS Source Validation error on
4922 * completions for config read requests even though PCIe r4.0, sec
4923 * 6.12.1.1, says that completions are never affected by ACS Source
4924 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
4926 * Item #36 - Downstream port applies ACS Source Validation to Completions
4927 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
4928 * completions are never affected by ACS Source Validation. However,
4929 * completions received by a downstream port of the PCIe switch from a
4930 * device that has not yet captured a PCIe bus number are incorrectly
4931 * dropped by ACS Source Validation by the switch downstream port.
4933 * The workaround suggested by IDT is to issue a config write to the
4934 * downstream device before issuing the first config read. This allows the
4935 * downstream device to capture its bus and device numbers (see PCIe r4.0,
4936 * sec 2.2.9), thus avoiding the ACS error on the completion.
4938 * However, we don't know when the device is ready to accept the config
4939 * write, so we do config reads until we receive a non-Config Request Retry
4940 * Status, then do the config write.
4942 * To avoid hitting the erratum when doing the config reads, we disable ACS
4943 * SV around this process.
4945 int pci_idt_bus_quirk(struct pci_bus
*bus
, int devfn
, u32
*l
, int timeout
)
4950 struct pci_dev
*bridge
= bus
->self
;
4952 pos
= pci_find_ext_capability(bridge
, PCI_EXT_CAP_ID_ACS
);
4954 /* Disable ACS SV before initial config reads */
4956 pci_read_config_word(bridge
, pos
+ PCI_ACS_CTRL
, &ctrl
);
4957 if (ctrl
& PCI_ACS_SV
)
4958 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
,
4959 ctrl
& ~PCI_ACS_SV
);
4962 found
= pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
4964 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
4966 pci_bus_write_config_word(bus
, devfn
, PCI_VENDOR_ID
, 0);
4968 /* Re-enable ACS_SV if it was previously enabled */
4969 if (ctrl
& PCI_ACS_SV
)
4970 pci_write_config_word(bridge
, pos
+ PCI_ACS_CTRL
, ctrl
);
4976 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
4977 * NT endpoints via the internal switch fabric. These IDs replace the
4978 * originating requestor ID TLPs which access host memory on peer NTB
4979 * ports. Therefore, all proxy IDs must be aliased to the NTB device
4980 * to permit access when the IOMMU is turned on.
4982 static void quirk_switchtec_ntb_dma_alias(struct pci_dev
*pdev
)
4985 struct ntb_info_regs __iomem
*mmio_ntb
;
4986 struct ntb_ctrl_regs __iomem
*mmio_ctrl
;
4987 struct sys_info_regs __iomem
*mmio_sys_info
;
4992 if (pci_enable_device(pdev
)) {
4993 pci_err(pdev
, "Cannot enable Switchtec device\n");
4997 mmio
= pci_iomap(pdev
, 0, 0);
4999 pci_disable_device(pdev
);
5000 pci_err(pdev
, "Cannot iomap Switchtec device\n");
5004 pci_info(pdev
, "Setting Switchtec proxy ID aliases\n");
5006 mmio_ntb
= mmio
+ SWITCHTEC_GAS_NTB_OFFSET
;
5007 mmio_ctrl
= (void __iomem
*) mmio_ntb
+ SWITCHTEC_NTB_REG_CTRL_OFFSET
;
5008 mmio_sys_info
= mmio
+ SWITCHTEC_GAS_SYS_INFO_OFFSET
;
5010 partition
= ioread8(&mmio_ntb
->partition_id
);
5012 partition_map
= ioread32(&mmio_ntb
->ep_map
);
5013 partition_map
|= ((u64
) ioread32(&mmio_ntb
->ep_map
+ 4)) << 32;
5014 partition_map
&= ~(1ULL << partition
);
5016 for (pp
= 0; pp
< (sizeof(partition_map
) * 8); pp
++) {
5017 struct ntb_ctrl_regs __iomem
*mmio_peer_ctrl
;
5021 if (!(partition_map
& (1ULL << pp
)))
5024 pci_dbg(pdev
, "Processing partition %d\n", pp
);
5026 mmio_peer_ctrl
= &mmio_ctrl
[pp
];
5028 table_sz
= ioread16(&mmio_peer_ctrl
->req_id_table_size
);
5030 pci_warn(pdev
, "Partition %d table_sz 0\n", pp
);
5034 if (table_sz
> 512) {
5036 "Invalid Switchtec partition %d table_sz %d\n",
5041 for (te
= 0; te
< table_sz
; te
++) {
5045 rid_entry
= ioread32(&mmio_peer_ctrl
->req_id_table
[te
]);
5046 devfn
= (rid_entry
>> 1) & 0xFF;
5048 "Aliasing Partition %d Proxy ID %02x.%d\n",
5049 pp
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5050 pci_add_dma_alias(pdev
, devfn
);
5054 pci_iounmap(pdev
, mmio
);
5055 pci_disable_device(pdev
);
5057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8531,
5058 quirk_switchtec_ntb_dma_alias
);
5059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8532,
5060 quirk_switchtec_ntb_dma_alias
);
5061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8533,
5062 quirk_switchtec_ntb_dma_alias
);
5063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8534,
5064 quirk_switchtec_ntb_dma_alias
);
5065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8535,
5066 quirk_switchtec_ntb_dma_alias
);
5067 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8536,
5068 quirk_switchtec_ntb_dma_alias
);
5069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8543,
5070 quirk_switchtec_ntb_dma_alias
);
5071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8544,
5072 quirk_switchtec_ntb_dma_alias
);
5073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8545,
5074 quirk_switchtec_ntb_dma_alias
);
5075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8546,
5076 quirk_switchtec_ntb_dma_alias
);
5077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8551,
5078 quirk_switchtec_ntb_dma_alias
);
5079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8552,
5080 quirk_switchtec_ntb_dma_alias
);
5081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8553,
5082 quirk_switchtec_ntb_dma_alias
);
5083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8554,
5084 quirk_switchtec_ntb_dma_alias
);
5085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8555,
5086 quirk_switchtec_ntb_dma_alias
);
5087 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8556,
5088 quirk_switchtec_ntb_dma_alias
);
5089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8561,
5090 quirk_switchtec_ntb_dma_alias
);
5091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8562,
5092 quirk_switchtec_ntb_dma_alias
);
5093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8563,
5094 quirk_switchtec_ntb_dma_alias
);
5095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8564,
5096 quirk_switchtec_ntb_dma_alias
);
5097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8565,
5098 quirk_switchtec_ntb_dma_alias
);
5099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8566,
5100 quirk_switchtec_ntb_dma_alias
);
5101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8571,
5102 quirk_switchtec_ntb_dma_alias
);
5103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8572,
5104 quirk_switchtec_ntb_dma_alias
);
5105 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8573,
5106 quirk_switchtec_ntb_dma_alias
);
5107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8574,
5108 quirk_switchtec_ntb_dma_alias
);
5109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8575,
5110 quirk_switchtec_ntb_dma_alias
);
5111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI
, 0x8576,
5112 quirk_switchtec_ntb_dma_alias
);