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PCI: Whitespace cleanup
[mirror_ubuntu-zesty-kernel.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <asm/dma.h> /* isa_dma_bridge_buggy */
28 #include "pci.h"
29
30 /*
31 * Decoding should be disabled for a PCI device during BAR sizing to avoid
32 * conflict. But doing so may cause problems on host bridge and perhaps other
33 * key system devices. For devices that need to have mmio decoding always-on,
34 * we need to set the dev->mmio_always_on bit.
35 */
36 static void quirk_mmio_always_on(struct pci_dev *dev)
37 {
38 dev->mmio_always_on = 1;
39 }
40 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
41 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
42
43 /* The Mellanox Tavor device gives false positive parity errors
44 * Mark this device with a broken_parity_status, to allow
45 * PCI scanning code to "skip" this now blacklisted device.
46 */
47 static void quirk_mellanox_tavor(struct pci_dev *dev)
48 {
49 dev->broken_parity_status = 1; /* This device gives false positives */
50 }
51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
53
54 /* Deal with broken BIOSes that neglect to enable passive release,
55 which can cause problems in combination with the 82441FX/PPro MTRRs */
56 static void quirk_passive_release(struct pci_dev *dev)
57 {
58 struct pci_dev *d = NULL;
59 unsigned char dlc;
60
61 /* We have to make sure a particular bit is set in the PIIX3
62 ISA bridge, so we have to go out and find it. */
63 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
64 pci_read_config_byte(d, 0x82, &dlc);
65 if (!(dlc & 1<<1)) {
66 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
67 dlc |= 1<<1;
68 pci_write_config_byte(d, 0x82, dlc);
69 }
70 }
71 }
72 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
73 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74
75 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
76 but VIA don't answer queries. If you happen to have good contacts at VIA
77 ask them for me please -- Alan
78
79 This appears to be BIOS not version dependent. So presumably there is a
80 chipset level fix */
81
82 static void quirk_isa_dma_hangs(struct pci_dev *dev)
83 {
84 if (!isa_dma_bridge_buggy) {
85 isa_dma_bridge_buggy = 1;
86 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
87 }
88 }
89 /*
90 * Its not totally clear which chipsets are the problematic ones
91 * We know 82C586 and 82C596 variants are affected.
92 */
93 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
100
101 /*
102 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
103 * for some HT machines to use C4 w/o hanging.
104 */
105 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
106 {
107 u32 pmbase;
108 u16 pm1a;
109
110 pci_read_config_dword(dev, 0x40, &pmbase);
111 pmbase = pmbase & 0xff80;
112 pm1a = inw(pmbase);
113
114 if (pm1a & 0x10) {
115 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
116 outw(0x10, pmbase);
117 }
118 }
119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
120
121 /*
122 * Chipsets where PCI->PCI transfers vanish or hang
123 */
124 static void quirk_nopcipci(struct pci_dev *dev)
125 {
126 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
127 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
128 pci_pci_problems |= PCIPCI_FAIL;
129 }
130 }
131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
133
134 static void quirk_nopciamd(struct pci_dev *dev)
135 {
136 u8 rev;
137 pci_read_config_byte(dev, 0x08, &rev);
138 if (rev == 0x13) {
139 /* Erratum 24 */
140 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
141 pci_pci_problems |= PCIAGP_FAIL;
142 }
143 }
144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
145
146 /*
147 * Triton requires workarounds to be used by the drivers
148 */
149 static void quirk_triton(struct pci_dev *dev)
150 {
151 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
152 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
153 pci_pci_problems |= PCIPCI_TRITON;
154 }
155 }
156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
160
161 /*
162 * VIA Apollo KT133 needs PCI latency patch
163 * Made according to a windows driver based patch by George E. Breese
164 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
165 * and http://www.georgebreese.com/net/software/#PCI
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172 static void quirk_vialatency(struct pci_dev *dev)
173 {
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p != NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p == NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214 exit:
215 pci_dev_put(p);
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220 /* Must restore this on a resume from RAM */
221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225 /*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228 static void quirk_viaetbf(struct pci_dev *dev)
229 {
230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234 }
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237 static void quirk_vsfx(struct pci_dev *dev)
238 {
239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243 }
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246 /*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252 static void quirk_alimagik(struct pci_dev *dev)
253 {
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258 }
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262 /*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266 static void quirk_natoma(struct pci_dev *dev)
267 {
268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272 }
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280 /*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284 static void quirk_citrine(struct pci_dev *dev)
285 {
286 dev->cfg_size = 0xA0;
287 }
288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290 /*
291 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
292 * If it's needed, re-allocate the region.
293 */
294 static void quirk_s3_64M(struct pci_dev *dev)
295 {
296 struct resource *r = &dev->resource[0];
297
298 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
299 r->flags |= IORESOURCE_UNSET;
300 r->start = 0;
301 r->end = 0x3ffffff;
302 }
303 }
304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
306
307 /*
308 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
309 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
310 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
311 * (which conflicts w/ BAR1's memory range).
312 */
313 static void quirk_cs5536_vsa(struct pci_dev *dev)
314 {
315 if (pci_resource_len(dev, 0) != 8) {
316 struct resource *res = &dev->resource[0];
317 res->end = res->start + 8 - 1;
318 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
319 "(incorrect header); workaround applied.\n");
320 }
321 }
322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
323
324 static void quirk_io_region(struct pci_dev *dev, int port,
325 unsigned size, int nr, const char *name)
326 {
327 u16 region;
328 struct pci_bus_region bus_region;
329 struct resource *res = dev->resource + nr;
330
331 pci_read_config_word(dev, port, &region);
332 region &= ~(size - 1);
333
334 if (!region)
335 return;
336
337 res->name = pci_name(dev);
338 res->flags = IORESOURCE_IO;
339
340 /* Convert from PCI bus to resource space */
341 bus_region.start = region;
342 bus_region.end = region + size - 1;
343 pcibios_bus_to_resource(dev->bus, res, &bus_region);
344
345 if (!pci_claim_resource(dev, nr))
346 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
347 }
348
349 /*
350 * ATI Northbridge setups MCE the processor if you even
351 * read somewhere between 0x3b0->0x3bb or read 0x3d3
352 */
353 static void quirk_ati_exploding_mce(struct pci_dev *dev)
354 {
355 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
356 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
357 request_region(0x3b0, 0x0C, "RadeonIGP");
358 request_region(0x3d3, 0x01, "RadeonIGP");
359 }
360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
361
362 /*
363 * Let's make the southbridge information explicit instead
364 * of having to worry about people probing the ACPI areas,
365 * for example.. (Yes, it happens, and if you read the wrong
366 * ACPI register it will put the machine to sleep with no
367 * way of waking it up again. Bummer).
368 *
369 * ALI M7101: Two IO regions pointed to by words at
370 * 0xE0 (64 bytes of ACPI registers)
371 * 0xE2 (32 bytes of SMB registers)
372 */
373 static void quirk_ali7101_acpi(struct pci_dev *dev)
374 {
375 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
376 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
377 }
378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
379
380 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
381 {
382 u32 devres;
383 u32 mask, size, base;
384
385 pci_read_config_dword(dev, port, &devres);
386 if ((devres & enable) != enable)
387 return;
388 mask = (devres >> 16) & 15;
389 base = devres & 0xffff;
390 size = 16;
391 for (;;) {
392 unsigned bit = size >> 1;
393 if ((bit & mask) == bit)
394 break;
395 size = bit;
396 }
397 /*
398 * For now we only print it out. Eventually we'll want to
399 * reserve it (at least if it's in the 0x1000+ range), but
400 * let's get enough confirmation reports first.
401 */
402 base &= -size;
403 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
404 }
405
406 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
407 {
408 u32 devres;
409 u32 mask, size, base;
410
411 pci_read_config_dword(dev, port, &devres);
412 if ((devres & enable) != enable)
413 return;
414 base = devres & 0xffff0000;
415 mask = (devres & 0x3f) << 16;
416 size = 128 << 16;
417 for (;;) {
418 unsigned bit = size >> 1;
419 if ((bit & mask) == bit)
420 break;
421 size = bit;
422 }
423 /*
424 * For now we only print it out. Eventually we'll want to
425 * reserve it, but let's get enough confirmation reports first.
426 */
427 base &= -size;
428 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
429 }
430
431 /*
432 * PIIX4 ACPI: Two IO regions pointed to by longwords at
433 * 0x40 (64 bytes of ACPI registers)
434 * 0x90 (16 bytes of SMB registers)
435 * and a few strange programmable PIIX4 device resources.
436 */
437 static void quirk_piix4_acpi(struct pci_dev *dev)
438 {
439 u32 res_a;
440
441 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
442 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
443
444 /* Device resource A has enables for some of the other ones */
445 pci_read_config_dword(dev, 0x5c, &res_a);
446
447 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
448 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
449
450 /* Device resource D is just bitfields for static resources */
451
452 /* Device 12 enabled? */
453 if (res_a & (1 << 29)) {
454 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
455 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
456 }
457 /* Device 13 enabled? */
458 if (res_a & (1 << 30)) {
459 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
460 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
461 }
462 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
463 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
464 }
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
467
468 #define ICH_PMBASE 0x40
469 #define ICH_ACPI_CNTL 0x44
470 #define ICH4_ACPI_EN 0x10
471 #define ICH6_ACPI_EN 0x80
472 #define ICH4_GPIOBASE 0x58
473 #define ICH4_GPIO_CNTL 0x5c
474 #define ICH4_GPIO_EN 0x10
475 #define ICH6_GPIOBASE 0x48
476 #define ICH6_GPIO_CNTL 0x4c
477 #define ICH6_GPIO_EN 0x10
478
479 /*
480 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
481 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
482 * 0x58 (64 bytes of GPIO I/O space)
483 */
484 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
485 {
486 u8 enable;
487
488 /*
489 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
490 * with low legacy (and fixed) ports. We don't know the decoding
491 * priority and can't tell whether the legacy device or the one created
492 * here is really at that address. This happens on boards with broken
493 * BIOSes.
494 */
495
496 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
497 if (enable & ICH4_ACPI_EN)
498 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
499 "ICH4 ACPI/GPIO/TCO");
500
501 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
502 if (enable & ICH4_GPIO_EN)
503 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
504 "ICH4 GPIO");
505 }
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
516
517 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
518 {
519 u8 enable;
520
521 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
522 if (enable & ICH6_ACPI_EN)
523 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
524 "ICH6 ACPI/GPIO/TCO");
525
526 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
527 if (enable & ICH6_GPIO_EN)
528 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
529 "ICH6 GPIO");
530 }
531
532 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
533 {
534 u32 val;
535 u32 size, base;
536
537 pci_read_config_dword(dev, reg, &val);
538
539 /* Enabled? */
540 if (!(val & 1))
541 return;
542 base = val & 0xfffc;
543 if (dynsize) {
544 /*
545 * This is not correct. It is 16, 32 or 64 bytes depending on
546 * register D31:F0:ADh bits 5:4.
547 *
548 * But this gets us at least _part_ of it.
549 */
550 size = 16;
551 } else {
552 size = 128;
553 }
554 base &= ~(size-1);
555
556 /* Just print it out for now. We should reserve it after more debugging */
557 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
558 }
559
560 static void quirk_ich6_lpc(struct pci_dev *dev)
561 {
562 /* Shared ACPI/GPIO decode with all ICH6+ */
563 ich6_lpc_acpi_gpio(dev);
564
565 /* ICH6-specific generic IO decode */
566 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
567 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
568 }
569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
571
572 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
573 {
574 u32 val;
575 u32 mask, base;
576
577 pci_read_config_dword(dev, reg, &val);
578
579 /* Enabled? */
580 if (!(val & 1))
581 return;
582
583 /*
584 * IO base in bits 15:2, mask in bits 23:18, both
585 * are dword-based
586 */
587 base = val & 0xfffc;
588 mask = (val >> 16) & 0xfc;
589 mask |= 3;
590
591 /* Just print it out for now. We should reserve it after more debugging */
592 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
593 }
594
595 /* ICH7-10 has the same common LPC generic IO decode registers */
596 static void quirk_ich7_lpc(struct pci_dev *dev)
597 {
598 /* We share the common ACPI/GPIO decode with ICH6 */
599 ich6_lpc_acpi_gpio(dev);
600
601 /* And have 4 ICH7+ generic decodes */
602 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
603 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
604 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
605 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
606 }
607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
620
621 /*
622 * VIA ACPI: One IO region pointed to by longword at
623 * 0x48 or 0x20 (256 bytes of ACPI registers)
624 */
625 static void quirk_vt82c586_acpi(struct pci_dev *dev)
626 {
627 if (dev->revision & 0x10)
628 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
629 "vt82c586 ACPI");
630 }
631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
632
633 /*
634 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
635 * 0x48 (256 bytes of ACPI registers)
636 * 0x70 (128 bytes of hardware monitoring register)
637 * 0x90 (16 bytes of SMB registers)
638 */
639 static void quirk_vt82c686_acpi(struct pci_dev *dev)
640 {
641 quirk_vt82c586_acpi(dev);
642
643 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
644 "vt82c686 HW-mon");
645
646 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
647 }
648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
649
650 /*
651 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
652 * 0x88 (128 bytes of power management registers)
653 * 0xd0 (16 bytes of SMB registers)
654 */
655 static void quirk_vt8235_acpi(struct pci_dev *dev)
656 {
657 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
658 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
659 }
660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
661
662 /*
663 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
664 * Disable fast back-to-back on the secondary bus segment
665 */
666 static void quirk_xio2000a(struct pci_dev *dev)
667 {
668 struct pci_dev *pdev;
669 u16 command;
670
671 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
672 "secondary bus fast back-to-back transfers disabled\n");
673 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
674 pci_read_config_word(pdev, PCI_COMMAND, &command);
675 if (command & PCI_COMMAND_FAST_BACK)
676 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
677 }
678 }
679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
680 quirk_xio2000a);
681
682 #ifdef CONFIG_X86_IO_APIC
683
684 #include <asm/io_apic.h>
685
686 /*
687 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
688 * devices to the external APIC.
689 *
690 * TODO: When we have device-specific interrupt routers,
691 * this code will go away from quirks.
692 */
693 static void quirk_via_ioapic(struct pci_dev *dev)
694 {
695 u8 tmp;
696
697 if (nr_ioapics < 1)
698 tmp = 0; /* nothing routed to external APIC */
699 else
700 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
701
702 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
703 tmp == 0 ? "Disa" : "Ena");
704
705 /* Offset 0x58: External APIC IRQ output control */
706 pci_write_config_byte(dev, 0x58, tmp);
707 }
708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
709 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
710
711 /*
712 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
713 * This leads to doubled level interrupt rates.
714 * Set this bit to get rid of cycle wastage.
715 * Otherwise uncritical.
716 */
717 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
718 {
719 u8 misc_control2;
720 #define BYPASS_APIC_DEASSERT 8
721
722 pci_read_config_byte(dev, 0x5B, &misc_control2);
723 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
724 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
725 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
726 }
727 }
728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
729 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
730
731 /*
732 * The AMD io apic can hang the box when an apic irq is masked.
733 * We check all revs >= B0 (yet not in the pre production!) as the bug
734 * is currently marked NoFix
735 *
736 * We have multiple reports of hangs with this chipset that went away with
737 * noapic specified. For the moment we assume it's the erratum. We may be wrong
738 * of course. However the advice is demonstrably good even if so..
739 */
740 static void quirk_amd_ioapic(struct pci_dev *dev)
741 {
742 if (dev->revision >= 0x02) {
743 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
744 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
745 }
746 }
747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
748
749 static void quirk_ioapic_rmw(struct pci_dev *dev)
750 {
751 if (dev->devfn == 0 && dev->bus->number == 0)
752 sis_apic_bug = 1;
753 }
754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
755 #endif /* CONFIG_X86_IO_APIC */
756
757 /*
758 * Some settings of MMRBC can lead to data corruption so block changes.
759 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
760 */
761 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
762 {
763 if (dev->subordinate && dev->revision <= 0x12) {
764 dev_info(&dev->dev, "AMD8131 rev %x detected; "
765 "disabling PCI-X MMRBC\n", dev->revision);
766 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
767 }
768 }
769 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
770
771 /*
772 * FIXME: it is questionable that quirk_via_acpi
773 * is needed. It shows up as an ISA bridge, and does not
774 * support the PCI_INTERRUPT_LINE register at all. Therefore
775 * it seems like setting the pci_dev's 'irq' to the
776 * value of the ACPI SCI interrupt is only done for convenience.
777 * -jgarzik
778 */
779 static void quirk_via_acpi(struct pci_dev *d)
780 {
781 /*
782 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
783 */
784 u8 irq;
785 pci_read_config_byte(d, 0x42, &irq);
786 irq &= 0xf;
787 if (irq && (irq != 2))
788 d->irq = irq;
789 }
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
792
793
794 /*
795 * VIA bridges which have VLink
796 */
797
798 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
799
800 static void quirk_via_bridge(struct pci_dev *dev)
801 {
802 /* See what bridge we have and find the device ranges */
803 switch (dev->device) {
804 case PCI_DEVICE_ID_VIA_82C686:
805 /* The VT82C686 is special, it attaches to PCI and can have
806 any device number. All its subdevices are functions of
807 that single device. */
808 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
809 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
810 break;
811 case PCI_DEVICE_ID_VIA_8237:
812 case PCI_DEVICE_ID_VIA_8237A:
813 via_vlink_dev_lo = 15;
814 break;
815 case PCI_DEVICE_ID_VIA_8235:
816 via_vlink_dev_lo = 16;
817 break;
818 case PCI_DEVICE_ID_VIA_8231:
819 case PCI_DEVICE_ID_VIA_8233_0:
820 case PCI_DEVICE_ID_VIA_8233A:
821 case PCI_DEVICE_ID_VIA_8233C_0:
822 via_vlink_dev_lo = 17;
823 break;
824 }
825 }
826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
834
835 /**
836 * quirk_via_vlink - VIA VLink IRQ number update
837 * @dev: PCI device
838 *
839 * If the device we are dealing with is on a PIC IRQ we need to
840 * ensure that the IRQ line register which usually is not relevant
841 * for PCI cards, is actually written so that interrupts get sent
842 * to the right place.
843 * We only do this on systems where a VIA south bridge was detected,
844 * and only for VIA devices on the motherboard (see quirk_via_bridge
845 * above).
846 */
847
848 static void quirk_via_vlink(struct pci_dev *dev)
849 {
850 u8 irq, new_irq;
851
852 /* Check if we have VLink at all */
853 if (via_vlink_dev_lo == -1)
854 return;
855
856 new_irq = dev->irq;
857
858 /* Don't quirk interrupts outside the legacy IRQ range */
859 if (!new_irq || new_irq > 15)
860 return;
861
862 /* Internal device ? */
863 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
864 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
865 return;
866
867 /* This is an internal VLink device on a PIC interrupt. The BIOS
868 ought to have set this but may not have, so we redo it */
869
870 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
871 if (new_irq != irq) {
872 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
873 irq, new_irq);
874 udelay(15); /* unknown if delay really needed */
875 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
876 }
877 }
878 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
879
880 /*
881 * VIA VT82C598 has its device ID settable and many BIOSes
882 * set it to the ID of VT82C597 for backward compatibility.
883 * We need to switch it off to be able to recognize the real
884 * type of the chip.
885 */
886 static void quirk_vt82c598_id(struct pci_dev *dev)
887 {
888 pci_write_config_byte(dev, 0xfc, 0);
889 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
890 }
891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
892
893 /*
894 * CardBus controllers have a legacy base address that enables them
895 * to respond as i82365 pcmcia controllers. We don't want them to
896 * do this even if the Linux CardBus driver is not loaded, because
897 * the Linux i82365 driver does not (and should not) handle CardBus.
898 */
899 static void quirk_cardbus_legacy(struct pci_dev *dev)
900 {
901 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
902 }
903 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
904 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
905 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
906 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
907
908 /*
909 * Following the PCI ordering rules is optional on the AMD762. I'm not
910 * sure what the designers were smoking but let's not inhale...
911 *
912 * To be fair to AMD, it follows the spec by default, its BIOS people
913 * who turn it off!
914 */
915 static void quirk_amd_ordering(struct pci_dev *dev)
916 {
917 u32 pcic;
918 pci_read_config_dword(dev, 0x4C, &pcic);
919 if ((pcic & 6) != 6) {
920 pcic |= 6;
921 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
922 pci_write_config_dword(dev, 0x4C, pcic);
923 pci_read_config_dword(dev, 0x84, &pcic);
924 pcic |= (1 << 23); /* Required in this mode */
925 pci_write_config_dword(dev, 0x84, pcic);
926 }
927 }
928 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
929 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
930
931 /*
932 * DreamWorks provided workaround for Dunord I-3000 problem
933 *
934 * This card decodes and responds to addresses not apparently
935 * assigned to it. We force a larger allocation to ensure that
936 * nothing gets put too close to it.
937 */
938 static void quirk_dunord(struct pci_dev *dev)
939 {
940 struct resource *r = &dev->resource[1];
941
942 r->flags |= IORESOURCE_UNSET;
943 r->start = 0;
944 r->end = 0xffffff;
945 }
946 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
947
948 /*
949 * i82380FB mobile docking controller: its PCI-to-PCI bridge
950 * is subtractive decoding (transparent), and does indicate this
951 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
952 * instead of 0x01.
953 */
954 static void quirk_transparent_bridge(struct pci_dev *dev)
955 {
956 dev->transparent = 1;
957 }
958 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
959 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
960
961 /*
962 * Common misconfiguration of the MediaGX/Geode PCI master that will
963 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
964 * datasheets found at http://www.national.com/analog for info on what
965 * these bits do. <christer@weinigel.se>
966 */
967 static void quirk_mediagx_master(struct pci_dev *dev)
968 {
969 u8 reg;
970
971 pci_read_config_byte(dev, 0x41, &reg);
972 if (reg & 2) {
973 reg &= ~2;
974 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
975 pci_write_config_byte(dev, 0x41, reg);
976 }
977 }
978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
979 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
980
981 /*
982 * Ensure C0 rev restreaming is off. This is normally done by
983 * the BIOS but in the odd case it is not the results are corruption
984 * hence the presence of a Linux check
985 */
986 static void quirk_disable_pxb(struct pci_dev *pdev)
987 {
988 u16 config;
989
990 if (pdev->revision != 0x04) /* Only C0 requires this */
991 return;
992 pci_read_config_word(pdev, 0x40, &config);
993 if (config & (1<<6)) {
994 config &= ~(1<<6);
995 pci_write_config_word(pdev, 0x40, config);
996 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
997 }
998 }
999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1000 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1001
1002 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1003 {
1004 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1005 u8 tmp;
1006
1007 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1008 if (tmp == 0x01) {
1009 pci_read_config_byte(pdev, 0x40, &tmp);
1010 pci_write_config_byte(pdev, 0x40, tmp|1);
1011 pci_write_config_byte(pdev, 0x9, 1);
1012 pci_write_config_byte(pdev, 0xa, 6);
1013 pci_write_config_byte(pdev, 0x40, tmp);
1014
1015 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1016 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1017 }
1018 }
1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1022 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1024 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1026 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1027
1028 /*
1029 * Serverworks CSB5 IDE does not fully support native mode
1030 */
1031 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1032 {
1033 u8 prog;
1034 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1035 if (prog & 5) {
1036 prog &= ~5;
1037 pdev->class &= ~5;
1038 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1039 /* PCI layer will sort out resources */
1040 }
1041 }
1042 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1043
1044 /*
1045 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1046 */
1047 static void quirk_ide_samemode(struct pci_dev *pdev)
1048 {
1049 u8 prog;
1050
1051 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1052
1053 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1054 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1055 prog &= ~5;
1056 pdev->class &= ~5;
1057 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1058 }
1059 }
1060 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1061
1062 /*
1063 * Some ATA devices break if put into D3
1064 */
1065
1066 static void quirk_no_ata_d3(struct pci_dev *pdev)
1067 {
1068 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1069 }
1070 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1071 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1072 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1073 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1074 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1075 /* ALi loses some register settings that we cannot then restore */
1076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1077 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1078 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1079 occur when mode detecting */
1080 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1081 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1082
1083 /* This was originally an Alpha specific thing, but it really fits here.
1084 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1085 */
1086 static void quirk_eisa_bridge(struct pci_dev *dev)
1087 {
1088 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1089 }
1090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1091
1092
1093 /*
1094 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1095 * is not activated. The myth is that Asus said that they do not want the
1096 * users to be irritated by just another PCI Device in the Win98 device
1097 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1098 * package 2.7.0 for details)
1099 *
1100 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1101 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1102 * becomes necessary to do this tweak in two steps -- the chosen trigger
1103 * is either the Host bridge (preferred) or on-board VGA controller.
1104 *
1105 * Note that we used to unhide the SMBus that way on Toshiba laptops
1106 * (Satellite A40 and Tecra M2) but then found that the thermal management
1107 * was done by SMM code, which could cause unsynchronized concurrent
1108 * accesses to the SMBus registers, with potentially bad effects. Thus you
1109 * should be very careful when adding new entries: if SMM is accessing the
1110 * Intel SMBus, this is a very good reason to leave it hidden.
1111 *
1112 * Likewise, many recent laptops use ACPI for thermal management. If the
1113 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1114 * natively, and keeping the SMBus hidden is the right thing to do. If you
1115 * are about to add an entry in the table below, please first disassemble
1116 * the DSDT and double-check that there is no code accessing the SMBus.
1117 */
1118 static int asus_hides_smbus;
1119
1120 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1121 {
1122 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1123 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1124 switch (dev->subsystem_device) {
1125 case 0x8025: /* P4B-LX */
1126 case 0x8070: /* P4B */
1127 case 0x8088: /* P4B533 */
1128 case 0x1626: /* L3C notebook */
1129 asus_hides_smbus = 1;
1130 }
1131 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1132 switch (dev->subsystem_device) {
1133 case 0x80b1: /* P4GE-V */
1134 case 0x80b2: /* P4PE */
1135 case 0x8093: /* P4B533-V */
1136 asus_hides_smbus = 1;
1137 }
1138 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1139 switch (dev->subsystem_device) {
1140 case 0x8030: /* P4T533 */
1141 asus_hides_smbus = 1;
1142 }
1143 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1144 switch (dev->subsystem_device) {
1145 case 0x8070: /* P4G8X Deluxe */
1146 asus_hides_smbus = 1;
1147 }
1148 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1149 switch (dev->subsystem_device) {
1150 case 0x80c9: /* PU-DLS */
1151 asus_hides_smbus = 1;
1152 }
1153 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1154 switch (dev->subsystem_device) {
1155 case 0x1751: /* M2N notebook */
1156 case 0x1821: /* M5N notebook */
1157 case 0x1897: /* A6L notebook */
1158 asus_hides_smbus = 1;
1159 }
1160 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1161 switch (dev->subsystem_device) {
1162 case 0x184b: /* W1N notebook */
1163 case 0x186a: /* M6Ne notebook */
1164 asus_hides_smbus = 1;
1165 }
1166 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1167 switch (dev->subsystem_device) {
1168 case 0x80f2: /* P4P800-X */
1169 asus_hides_smbus = 1;
1170 }
1171 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1172 switch (dev->subsystem_device) {
1173 case 0x1882: /* M6V notebook */
1174 case 0x1977: /* A6VA notebook */
1175 asus_hides_smbus = 1;
1176 }
1177 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1178 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1179 switch (dev->subsystem_device) {
1180 case 0x088C: /* HP Compaq nc8000 */
1181 case 0x0890: /* HP Compaq nc6000 */
1182 asus_hides_smbus = 1;
1183 }
1184 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1185 switch (dev->subsystem_device) {
1186 case 0x12bc: /* HP D330L */
1187 case 0x12bd: /* HP D530 */
1188 case 0x006a: /* HP Compaq nx9500 */
1189 asus_hides_smbus = 1;
1190 }
1191 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1192 switch (dev->subsystem_device) {
1193 case 0x12bf: /* HP xw4100 */
1194 asus_hides_smbus = 1;
1195 }
1196 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1197 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1198 switch (dev->subsystem_device) {
1199 case 0xC00C: /* Samsung P35 notebook */
1200 asus_hides_smbus = 1;
1201 }
1202 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1203 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1204 switch (dev->subsystem_device) {
1205 case 0x0058: /* Compaq Evo N620c */
1206 asus_hides_smbus = 1;
1207 }
1208 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1209 switch (dev->subsystem_device) {
1210 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1211 /* Motherboard doesn't have Host bridge
1212 * subvendor/subdevice IDs, therefore checking
1213 * its on-board VGA controller */
1214 asus_hides_smbus = 1;
1215 }
1216 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1217 switch (dev->subsystem_device) {
1218 case 0x00b8: /* Compaq Evo D510 CMT */
1219 case 0x00b9: /* Compaq Evo D510 SFF */
1220 case 0x00ba: /* Compaq Evo D510 USDT */
1221 /* Motherboard doesn't have Host bridge
1222 * subvendor/subdevice IDs and on-board VGA
1223 * controller is disabled if an AGP card is
1224 * inserted, therefore checking USB UHCI
1225 * Controller #1 */
1226 asus_hides_smbus = 1;
1227 }
1228 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1229 switch (dev->subsystem_device) {
1230 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1231 /* Motherboard doesn't have host bridge
1232 * subvendor/subdevice IDs, therefore checking
1233 * its on-board VGA controller */
1234 asus_hides_smbus = 1;
1235 }
1236 }
1237 }
1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1244 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1248
1249 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1250 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1251 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1252
1253 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1254 {
1255 u16 val;
1256
1257 if (likely(!asus_hides_smbus))
1258 return;
1259
1260 pci_read_config_word(dev, 0xF2, &val);
1261 if (val & 0x8) {
1262 pci_write_config_word(dev, 0xF2, val & (~0x8));
1263 pci_read_config_word(dev, 0xF2, &val);
1264 if (val & 0x8)
1265 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1266 else
1267 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1268 }
1269 }
1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1277 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1278 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1279 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1280 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1281 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1282 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1283 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1284
1285 /* It appears we just have one such device. If not, we have a warning */
1286 static void __iomem *asus_rcba_base;
1287 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1288 {
1289 u32 rcba;
1290
1291 if (likely(!asus_hides_smbus))
1292 return;
1293 WARN_ON(asus_rcba_base);
1294
1295 pci_read_config_dword(dev, 0xF0, &rcba);
1296 /* use bits 31:14, 16 kB aligned */
1297 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1298 if (asus_rcba_base == NULL)
1299 return;
1300 }
1301
1302 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1303 {
1304 u32 val;
1305
1306 if (likely(!asus_hides_smbus || !asus_rcba_base))
1307 return;
1308 /* read the Function Disable register, dword mode only */
1309 val = readl(asus_rcba_base + 0x3418);
1310 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1311 }
1312
1313 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1314 {
1315 if (likely(!asus_hides_smbus || !asus_rcba_base))
1316 return;
1317 iounmap(asus_rcba_base);
1318 asus_rcba_base = NULL;
1319 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1320 }
1321
1322 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1323 {
1324 asus_hides_smbus_lpc_ich6_suspend(dev);
1325 asus_hides_smbus_lpc_ich6_resume_early(dev);
1326 asus_hides_smbus_lpc_ich6_resume(dev);
1327 }
1328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1329 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1330 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1331 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1332
1333 /*
1334 * SiS 96x south bridge: BIOS typically hides SMBus device...
1335 */
1336 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1337 {
1338 u8 val = 0;
1339 pci_read_config_byte(dev, 0x77, &val);
1340 if (val & 0x10) {
1341 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1342 pci_write_config_byte(dev, 0x77, val & ~0x10);
1343 }
1344 }
1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1349 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1350 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1351 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1352 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1353
1354 /*
1355 * ... This is further complicated by the fact that some SiS96x south
1356 * bridges pretend to be 85C503/5513 instead. In that case see if we
1357 * spotted a compatible north bridge to make sure.
1358 * (pci_find_device doesn't work yet)
1359 *
1360 * We can also enable the sis96x bit in the discovery register..
1361 */
1362 #define SIS_DETECT_REGISTER 0x40
1363
1364 static void quirk_sis_503(struct pci_dev *dev)
1365 {
1366 u8 reg;
1367 u16 devid;
1368
1369 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1370 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1371 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1372 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1373 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1374 return;
1375 }
1376
1377 /*
1378 * Ok, it now shows up as a 96x.. run the 96x quirk by
1379 * hand in case it has already been processed.
1380 * (depends on link order, which is apparently not guaranteed)
1381 */
1382 dev->device = devid;
1383 quirk_sis_96x_smbus(dev);
1384 }
1385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1386 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1387
1388
1389 /*
1390 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1391 * and MC97 modem controller are disabled when a second PCI soundcard is
1392 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1393 * -- bjd
1394 */
1395 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1396 {
1397 u8 val;
1398 int asus_hides_ac97 = 0;
1399
1400 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1401 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1402 asus_hides_ac97 = 1;
1403 }
1404
1405 if (!asus_hides_ac97)
1406 return;
1407
1408 pci_read_config_byte(dev, 0x50, &val);
1409 if (val & 0xc0) {
1410 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1411 pci_read_config_byte(dev, 0x50, &val);
1412 if (val & 0xc0)
1413 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1414 else
1415 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1416 }
1417 }
1418 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1419 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1420
1421 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1422
1423 /*
1424 * If we are using libata we can drive this chip properly but must
1425 * do this early on to make the additional device appear during
1426 * the PCI scanning.
1427 */
1428 static void quirk_jmicron_ata(struct pci_dev *pdev)
1429 {
1430 u32 conf1, conf5, class;
1431 u8 hdr;
1432
1433 /* Only poke fn 0 */
1434 if (PCI_FUNC(pdev->devfn))
1435 return;
1436
1437 pci_read_config_dword(pdev, 0x40, &conf1);
1438 pci_read_config_dword(pdev, 0x80, &conf5);
1439
1440 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1441 conf5 &= ~(1 << 24); /* Clear bit 24 */
1442
1443 switch (pdev->device) {
1444 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1445 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1446 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1447 /* The controller should be in single function ahci mode */
1448 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1449 break;
1450
1451 case PCI_DEVICE_ID_JMICRON_JMB365:
1452 case PCI_DEVICE_ID_JMICRON_JMB366:
1453 /* Redirect IDE second PATA port to the right spot */
1454 conf5 |= (1 << 24);
1455 /* Fall through */
1456 case PCI_DEVICE_ID_JMICRON_JMB361:
1457 case PCI_DEVICE_ID_JMICRON_JMB363:
1458 case PCI_DEVICE_ID_JMICRON_JMB369:
1459 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1460 /* Set the class codes correctly and then direct IDE 0 */
1461 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1462 break;
1463
1464 case PCI_DEVICE_ID_JMICRON_JMB368:
1465 /* The controller should be in single function IDE mode */
1466 conf1 |= 0x00C00000; /* Set 22, 23 */
1467 break;
1468 }
1469
1470 pci_write_config_dword(pdev, 0x40, conf1);
1471 pci_write_config_dword(pdev, 0x80, conf5);
1472
1473 /* Update pdev accordingly */
1474 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1475 pdev->hdr_type = hdr & 0x7f;
1476 pdev->multifunction = !!(hdr & 0x80);
1477
1478 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1479 pdev->class = class >> 8;
1480 }
1481 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1482 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1483 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1484 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1485 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1486 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1487 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1488 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1489 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1490 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1491 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1492 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1493 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1494 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1495 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1496 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1497 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1498 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1499
1500 #endif
1501
1502 #ifdef CONFIG_X86_IO_APIC
1503 static void quirk_alder_ioapic(struct pci_dev *pdev)
1504 {
1505 int i;
1506
1507 if ((pdev->class >> 8) != 0xff00)
1508 return;
1509
1510 /* the first BAR is the location of the IO APIC...we must
1511 * not touch this (and it's already covered by the fixmap), so
1512 * forcibly insert it into the resource tree */
1513 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1514 insert_resource(&iomem_resource, &pdev->resource[0]);
1515
1516 /* The next five BARs all seem to be rubbish, so just clean
1517 * them out */
1518 for (i = 1; i < 6; i++)
1519 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1520 }
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1522 #endif
1523
1524 static void quirk_pcie_mch(struct pci_dev *pdev)
1525 {
1526 pci_msi_off(pdev);
1527 pdev->no_msi = 1;
1528 }
1529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1532
1533
1534 /*
1535 * It's possible for the MSI to get corrupted if shpc and acpi
1536 * are used together on certain PXH-based systems.
1537 */
1538 static void quirk_pcie_pxh(struct pci_dev *dev)
1539 {
1540 pci_msi_off(dev);
1541 dev->no_msi = 1;
1542 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1543 }
1544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1546 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1547 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1548 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1549
1550 /*
1551 * Some Intel PCI Express chipsets have trouble with downstream
1552 * device power management.
1553 */
1554 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1555 {
1556 pci_pm_d3_delay = 120;
1557 dev->no_d1d2 = 1;
1558 }
1559
1560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1581
1582 #ifdef CONFIG_X86_IO_APIC
1583 /*
1584 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1585 * remap the original interrupt in the linux kernel to the boot interrupt, so
1586 * that a PCI device's interrupt handler is installed on the boot interrupt
1587 * line instead.
1588 */
1589 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1590 {
1591 if (noioapicquirk || noioapicreroute)
1592 return;
1593
1594 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1595 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1596 dev->vendor, dev->device);
1597 }
1598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1606 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1607 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1608 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1609 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1610 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1612 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1613 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1614
1615 /*
1616 * On some chipsets we can disable the generation of legacy INTx boot
1617 * interrupts.
1618 */
1619
1620 /*
1621 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1622 * 300641-004US, section 5.7.3.
1623 */
1624 #define INTEL_6300_IOAPIC_ABAR 0x40
1625 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1626
1627 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1628 {
1629 u16 pci_config_word;
1630
1631 if (noioapicquirk)
1632 return;
1633
1634 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1635 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1636 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1637
1638 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1639 dev->vendor, dev->device);
1640 }
1641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1642 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1643
1644 /*
1645 * disable boot interrupts on HT-1000
1646 */
1647 #define BC_HT1000_FEATURE_REG 0x64
1648 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1649 #define BC_HT1000_MAP_IDX 0xC00
1650 #define BC_HT1000_MAP_DATA 0xC01
1651
1652 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1653 {
1654 u32 pci_config_dword;
1655 u8 irq;
1656
1657 if (noioapicquirk)
1658 return;
1659
1660 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1661 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1662 BC_HT1000_PIC_REGS_ENABLE);
1663
1664 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1665 outb(irq, BC_HT1000_MAP_IDX);
1666 outb(0x00, BC_HT1000_MAP_DATA);
1667 }
1668
1669 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1670
1671 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1672 dev->vendor, dev->device);
1673 }
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1675 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1676
1677 /*
1678 * disable boot interrupts on AMD and ATI chipsets
1679 */
1680 /*
1681 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1682 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1683 * (due to an erratum).
1684 */
1685 #define AMD_813X_MISC 0x40
1686 #define AMD_813X_NOIOAMODE (1<<0)
1687 #define AMD_813X_REV_B1 0x12
1688 #define AMD_813X_REV_B2 0x13
1689
1690 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1691 {
1692 u32 pci_config_dword;
1693
1694 if (noioapicquirk)
1695 return;
1696 if ((dev->revision == AMD_813X_REV_B1) ||
1697 (dev->revision == AMD_813X_REV_B2))
1698 return;
1699
1700 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1701 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1702 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1703
1704 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1705 dev->vendor, dev->device);
1706 }
1707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1708 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1710 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1711
1712 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1713
1714 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1715 {
1716 u16 pci_config_word;
1717
1718 if (noioapicquirk)
1719 return;
1720
1721 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1722 if (!pci_config_word) {
1723 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1724 "already disabled\n", dev->vendor, dev->device);
1725 return;
1726 }
1727 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1728 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1729 dev->vendor, dev->device);
1730 }
1731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1732 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1733 #endif /* CONFIG_X86_IO_APIC */
1734
1735 /*
1736 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1737 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1738 * Re-allocate the region if needed...
1739 */
1740 static void quirk_tc86c001_ide(struct pci_dev *dev)
1741 {
1742 struct resource *r = &dev->resource[0];
1743
1744 if (r->start & 0x8) {
1745 r->flags |= IORESOURCE_UNSET;
1746 r->start = 0;
1747 r->end = 0xf;
1748 }
1749 }
1750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1751 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1752 quirk_tc86c001_ide);
1753
1754 /*
1755 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1756 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1757 * being read correctly if bit 7 of the base address is set.
1758 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1759 * Re-allocate the regions to a 256-byte boundary if necessary.
1760 */
1761 static void quirk_plx_pci9050(struct pci_dev *dev)
1762 {
1763 unsigned int bar;
1764
1765 /* Fixed in revision 2 (PCI 9052). */
1766 if (dev->revision >= 2)
1767 return;
1768 for (bar = 0; bar <= 1; bar++)
1769 if (pci_resource_len(dev, bar) == 0x80 &&
1770 (pci_resource_start(dev, bar) & 0x80)) {
1771 struct resource *r = &dev->resource[bar];
1772 dev_info(&dev->dev,
1773 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1774 bar);
1775 r->flags |= IORESOURCE_UNSET;
1776 r->start = 0;
1777 r->end = 0xff;
1778 }
1779 }
1780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1781 quirk_plx_pci9050);
1782 /*
1783 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1784 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1785 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1786 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1787 *
1788 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1789 * driver.
1790 */
1791 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1792 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1793
1794 static void quirk_netmos(struct pci_dev *dev)
1795 {
1796 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1797 unsigned int num_serial = dev->subsystem_device & 0xf;
1798
1799 /*
1800 * These Netmos parts are multiport serial devices with optional
1801 * parallel ports. Even when parallel ports are present, they
1802 * are identified as class SERIAL, which means the serial driver
1803 * will claim them. To prevent this, mark them as class OTHER.
1804 * These combo devices should be claimed by parport_serial.
1805 *
1806 * The subdevice ID is of the form 0x00PS, where <P> is the number
1807 * of parallel ports and <S> is the number of serial ports.
1808 */
1809 switch (dev->device) {
1810 case PCI_DEVICE_ID_NETMOS_9835:
1811 /* Well, this rule doesn't hold for the following 9835 device */
1812 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1813 dev->subsystem_device == 0x0299)
1814 return;
1815 case PCI_DEVICE_ID_NETMOS_9735:
1816 case PCI_DEVICE_ID_NETMOS_9745:
1817 case PCI_DEVICE_ID_NETMOS_9845:
1818 case PCI_DEVICE_ID_NETMOS_9855:
1819 if (num_parallel) {
1820 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1821 "%u serial); changing class SERIAL to OTHER "
1822 "(use parport_serial)\n",
1823 dev->device, num_parallel, num_serial);
1824 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1825 (dev->class & 0xff);
1826 }
1827 }
1828 }
1829 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1830 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1831
1832 static void quirk_e100_interrupt(struct pci_dev *dev)
1833 {
1834 u16 command, pmcsr;
1835 u8 __iomem *csr;
1836 u8 cmd_hi;
1837
1838 switch (dev->device) {
1839 /* PCI IDs taken from drivers/net/e100.c */
1840 case 0x1029:
1841 case 0x1030 ... 0x1034:
1842 case 0x1038 ... 0x103E:
1843 case 0x1050 ... 0x1057:
1844 case 0x1059:
1845 case 0x1064 ... 0x106B:
1846 case 0x1091 ... 0x1095:
1847 case 0x1209:
1848 case 0x1229:
1849 case 0x2449:
1850 case 0x2459:
1851 case 0x245D:
1852 case 0x27DC:
1853 break;
1854 default:
1855 return;
1856 }
1857
1858 /*
1859 * Some firmware hands off the e100 with interrupts enabled,
1860 * which can cause a flood of interrupts if packets are
1861 * received before the driver attaches to the device. So
1862 * disable all e100 interrupts here. The driver will
1863 * re-enable them when it's ready.
1864 */
1865 pci_read_config_word(dev, PCI_COMMAND, &command);
1866
1867 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1868 return;
1869
1870 /*
1871 * Check that the device is in the D0 power state. If it's not,
1872 * there is no point to look any further.
1873 */
1874 if (dev->pm_cap) {
1875 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1876 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1877 return;
1878 }
1879
1880 /* Convert from PCI bus to resource space. */
1881 csr = ioremap(pci_resource_start(dev, 0), 8);
1882 if (!csr) {
1883 dev_warn(&dev->dev, "Can't map e100 registers\n");
1884 return;
1885 }
1886
1887 cmd_hi = readb(csr + 3);
1888 if (cmd_hi == 0) {
1889 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1890 "disabling\n");
1891 writeb(1, csr + 3);
1892 }
1893
1894 iounmap(csr);
1895 }
1896 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1897 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1898
1899 /*
1900 * The 82575 and 82598 may experience data corruption issues when transitioning
1901 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1902 */
1903 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1904 {
1905 dev_info(&dev->dev, "Disabling L0s\n");
1906 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1907 }
1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1914 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1915 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1918 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1921 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1922
1923 static void fixup_rev1_53c810(struct pci_dev *dev)
1924 {
1925 /* rev 1 ncr53c810 chips don't set the class at all which means
1926 * they don't get their resources remapped. Fix that here.
1927 */
1928
1929 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1930 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1931 dev->class = PCI_CLASS_STORAGE_SCSI;
1932 }
1933 }
1934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1935
1936 /* Enable 1k I/O space granularity on the Intel P64H2 */
1937 static void quirk_p64h2_1k_io(struct pci_dev *dev)
1938 {
1939 u16 en1k;
1940
1941 pci_read_config_word(dev, 0x40, &en1k);
1942
1943 if (en1k & 0x200) {
1944 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1945 dev->io_window_1k = 1;
1946 }
1947 }
1948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1949
1950 /* Under some circumstances, AER is not linked with extended capabilities.
1951 * Force it to be linked by setting the corresponding control bit in the
1952 * config space.
1953 */
1954 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1955 {
1956 uint8_t b;
1957 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1958 if (!(b & 0x20)) {
1959 pci_write_config_byte(dev, 0xf41, b | 0x20);
1960 dev_info(&dev->dev,
1961 "Linking AER extended capability\n");
1962 }
1963 }
1964 }
1965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1966 quirk_nvidia_ck804_pcie_aer_ext_cap);
1967 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1968 quirk_nvidia_ck804_pcie_aer_ext_cap);
1969
1970 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1971 {
1972 /*
1973 * Disable PCI Bus Parking and PCI Master read caching on CX700
1974 * which causes unspecified timing errors with a VT6212L on the PCI
1975 * bus leading to USB2.0 packet loss.
1976 *
1977 * This quirk is only enabled if a second (on the external PCI bus)
1978 * VT6212L is found -- the CX700 core itself also contains a USB
1979 * host controller with the same PCI ID as the VT6212L.
1980 */
1981
1982 /* Count VT6212L instances */
1983 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1984 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
1985 uint8_t b;
1986
1987 /* p should contain the first (internal) VT6212L -- see if we have
1988 an external one by searching again */
1989 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1990 if (!p)
1991 return;
1992 pci_dev_put(p);
1993
1994 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1995 if (b & 0x40) {
1996 /* Turn off PCI Bus Parking */
1997 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1998
1999 dev_info(&dev->dev,
2000 "Disabling VIA CX700 PCI parking\n");
2001 }
2002 }
2003
2004 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2005 if (b != 0) {
2006 /* Turn off PCI Master read caching */
2007 pci_write_config_byte(dev, 0x72, 0x0);
2008
2009 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2010 pci_write_config_byte(dev, 0x75, 0x1);
2011
2012 /* Disable "Read FIFO Timer" */
2013 pci_write_config_byte(dev, 0x77, 0x0);
2014
2015 dev_info(&dev->dev,
2016 "Disabling VIA CX700 PCI caching\n");
2017 }
2018 }
2019 }
2020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2021
2022 /*
2023 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2024 * VPD end tag will hang the device. This problem was initially
2025 * observed when a vpd entry was created in sysfs
2026 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2027 * will dump 32k of data. Reading a full 32k will cause an access
2028 * beyond the VPD end tag causing the device to hang. Once the device
2029 * is hung, the bnx2 driver will not be able to reset the device.
2030 * We believe that it is legal to read beyond the end tag and
2031 * therefore the solution is to limit the read/write length.
2032 */
2033 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2034 {
2035 /*
2036 * Only disable the VPD capability for 5706, 5706S, 5708,
2037 * 5708S and 5709 rev. A
2038 */
2039 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2040 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2041 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2042 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2043 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2044 (dev->revision & 0xf0) == 0x0)) {
2045 if (dev->vpd)
2046 dev->vpd->len = 0x80;
2047 }
2048 }
2049
2050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2051 PCI_DEVICE_ID_NX2_5706,
2052 quirk_brcm_570x_limit_vpd);
2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2054 PCI_DEVICE_ID_NX2_5706S,
2055 quirk_brcm_570x_limit_vpd);
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2057 PCI_DEVICE_ID_NX2_5708,
2058 quirk_brcm_570x_limit_vpd);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2060 PCI_DEVICE_ID_NX2_5708S,
2061 quirk_brcm_570x_limit_vpd);
2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2063 PCI_DEVICE_ID_NX2_5709,
2064 quirk_brcm_570x_limit_vpd);
2065 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2066 PCI_DEVICE_ID_NX2_5709S,
2067 quirk_brcm_570x_limit_vpd);
2068
2069 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2070 {
2071 u32 rev;
2072
2073 pci_read_config_dword(dev, 0xf4, &rev);
2074
2075 /* Only CAP the MRRS if the device is a 5719 A0 */
2076 if (rev == 0x05719000) {
2077 int readrq = pcie_get_readrq(dev);
2078 if (readrq > 2048)
2079 pcie_set_readrq(dev, 2048);
2080 }
2081 }
2082
2083 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2084 PCI_DEVICE_ID_TIGON3_5719,
2085 quirk_brcm_5719_limit_mrrs);
2086
2087 /* Originally in EDAC sources for i82875P:
2088 * Intel tells BIOS developers to hide device 6 which
2089 * configures the overflow device access containing
2090 * the DRBs - this is where we expose device 6.
2091 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2092 */
2093 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2094 {
2095 u8 reg;
2096
2097 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2098 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2099 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2100 }
2101 }
2102
2103 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2104 quirk_unhide_mch_dev6);
2105 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2106 quirk_unhide_mch_dev6);
2107
2108 #ifdef CONFIG_TILEPRO
2109 /*
2110 * The Tilera TILEmpower tilepro platform needs to set the link speed
2111 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2112 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2113 * capability register of the PEX8624 PCIe switch. The switch
2114 * supports link speed auto negotiation, but falsely sets
2115 * the link speed to 5GT/s.
2116 */
2117 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2118 {
2119 if (tile_plx_gen1) {
2120 pci_write_config_dword(dev, 0x98, 0x1);
2121 mdelay(50);
2122 }
2123 }
2124 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2125 #endif /* CONFIG_TILEPRO */
2126
2127 #ifdef CONFIG_PCI_MSI
2128 /* Some chipsets do not support MSI. We cannot easily rely on setting
2129 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2130 * some other buses controlled by the chipset even if Linux is not
2131 * aware of it. Instead of setting the flag on all buses in the
2132 * machine, simply disable MSI globally.
2133 */
2134 static void quirk_disable_all_msi(struct pci_dev *dev)
2135 {
2136 pci_no_msi();
2137 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2138 }
2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2143 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2146
2147 /* Disable MSI on chipsets that are known to not support it */
2148 static void quirk_disable_msi(struct pci_dev *dev)
2149 {
2150 if (dev->subordinate) {
2151 dev_warn(&dev->dev, "MSI quirk detected; "
2152 "subordinate MSI disabled\n");
2153 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2154 }
2155 }
2156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2159
2160 /*
2161 * The APC bridge device in AMD 780 family northbridges has some random
2162 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2163 * we use the possible vendor/device IDs of the host bridge for the
2164 * declared quirk, and search for the APC bridge by slot number.
2165 */
2166 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2167 {
2168 struct pci_dev *apc_bridge;
2169
2170 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2171 if (apc_bridge) {
2172 if (apc_bridge->device == 0x9602)
2173 quirk_disable_msi(apc_bridge);
2174 pci_dev_put(apc_bridge);
2175 }
2176 }
2177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2178 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2179
2180 /* Go through the list of Hypertransport capabilities and
2181 * return 1 if a HT MSI capability is found and enabled */
2182 static int msi_ht_cap_enabled(struct pci_dev *dev)
2183 {
2184 int pos, ttl = 48;
2185
2186 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2187 while (pos && ttl--) {
2188 u8 flags;
2189
2190 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2191 &flags) == 0) {
2192 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2193 flags & HT_MSI_FLAGS_ENABLE ?
2194 "enabled" : "disabled");
2195 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2196 }
2197
2198 pos = pci_find_next_ht_capability(dev, pos,
2199 HT_CAPTYPE_MSI_MAPPING);
2200 }
2201 return 0;
2202 }
2203
2204 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2205 static void quirk_msi_ht_cap(struct pci_dev *dev)
2206 {
2207 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2208 dev_warn(&dev->dev, "MSI quirk detected; "
2209 "subordinate MSI disabled\n");
2210 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2211 }
2212 }
2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2214 quirk_msi_ht_cap);
2215
2216 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2217 * MSI are supported if the MSI capability set in any of these mappings.
2218 */
2219 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2220 {
2221 struct pci_dev *pdev;
2222
2223 if (!dev->subordinate)
2224 return;
2225
2226 /* check HT MSI cap on this chipset and the root one.
2227 * a single one having MSI is enough to be sure that MSI are supported.
2228 */
2229 pdev = pci_get_slot(dev->bus, 0);
2230 if (!pdev)
2231 return;
2232 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2233 dev_warn(&dev->dev, "MSI quirk detected; "
2234 "subordinate MSI disabled\n");
2235 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2236 }
2237 pci_dev_put(pdev);
2238 }
2239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2240 quirk_nvidia_ck804_msi_ht_cap);
2241
2242 /* Force enable MSI mapping capability on HT bridges */
2243 static void ht_enable_msi_mapping(struct pci_dev *dev)
2244 {
2245 int pos, ttl = 48;
2246
2247 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2248 while (pos && ttl--) {
2249 u8 flags;
2250
2251 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2252 &flags) == 0) {
2253 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2254
2255 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2256 flags | HT_MSI_FLAGS_ENABLE);
2257 }
2258 pos = pci_find_next_ht_capability(dev, pos,
2259 HT_CAPTYPE_MSI_MAPPING);
2260 }
2261 }
2262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2263 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2264 ht_enable_msi_mapping);
2265
2266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2267 ht_enable_msi_mapping);
2268
2269 /* The P5N32-SLI motherboards from Asus have a problem with msi
2270 * for the MCP55 NIC. It is not yet determined whether the msi problem
2271 * also affects other devices. As for now, turn off msi for this device.
2272 */
2273 static void nvenet_msi_disable(struct pci_dev *dev)
2274 {
2275 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2276
2277 if (board_name &&
2278 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2279 strstr(board_name, "P5N32-E SLI"))) {
2280 dev_info(&dev->dev,
2281 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2282 dev->no_msi = 1;
2283 }
2284 }
2285 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2286 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2287 nvenet_msi_disable);
2288
2289 /*
2290 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2291 * config register. This register controls the routing of legacy
2292 * interrupts from devices that route through the MCP55. If this register
2293 * is misprogrammed, interrupts are only sent to the BSP, unlike
2294 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2295 * having this register set properly prevents kdump from booting up
2296 * properly, so let's make sure that we have it set correctly.
2297 * Note that this is an undocumented register.
2298 */
2299 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2300 {
2301 u32 cfg;
2302
2303 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2304 return;
2305
2306 pci_read_config_dword(dev, 0x74, &cfg);
2307
2308 if (cfg & ((1 << 2) | (1 << 15))) {
2309 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2310 cfg &= ~((1 << 2) | (1 << 15));
2311 pci_write_config_dword(dev, 0x74, cfg);
2312 }
2313 }
2314
2315 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2316 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2317 nvbridge_check_legacy_irq_routing);
2318
2319 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2320 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2321 nvbridge_check_legacy_irq_routing);
2322
2323 static int ht_check_msi_mapping(struct pci_dev *dev)
2324 {
2325 int pos, ttl = 48;
2326 int found = 0;
2327
2328 /* check if there is HT MSI cap or enabled on this device */
2329 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2330 while (pos && ttl--) {
2331 u8 flags;
2332
2333 if (found < 1)
2334 found = 1;
2335 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2336 &flags) == 0) {
2337 if (flags & HT_MSI_FLAGS_ENABLE) {
2338 if (found < 2) {
2339 found = 2;
2340 break;
2341 }
2342 }
2343 }
2344 pos = pci_find_next_ht_capability(dev, pos,
2345 HT_CAPTYPE_MSI_MAPPING);
2346 }
2347
2348 return found;
2349 }
2350
2351 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2352 {
2353 struct pci_dev *dev;
2354 int pos;
2355 int i, dev_no;
2356 int found = 0;
2357
2358 dev_no = host_bridge->devfn >> 3;
2359 for (i = dev_no + 1; i < 0x20; i++) {
2360 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2361 if (!dev)
2362 continue;
2363
2364 /* found next host bridge ?*/
2365 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2366 if (pos != 0) {
2367 pci_dev_put(dev);
2368 break;
2369 }
2370
2371 if (ht_check_msi_mapping(dev)) {
2372 found = 1;
2373 pci_dev_put(dev);
2374 break;
2375 }
2376 pci_dev_put(dev);
2377 }
2378
2379 return found;
2380 }
2381
2382 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2383 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2384
2385 static int is_end_of_ht_chain(struct pci_dev *dev)
2386 {
2387 int pos, ctrl_off;
2388 int end = 0;
2389 u16 flags, ctrl;
2390
2391 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2392
2393 if (!pos)
2394 goto out;
2395
2396 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2397
2398 ctrl_off = ((flags >> 10) & 1) ?
2399 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2400 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2401
2402 if (ctrl & (1 << 6))
2403 end = 1;
2404
2405 out:
2406 return end;
2407 }
2408
2409 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2410 {
2411 struct pci_dev *host_bridge;
2412 int pos;
2413 int i, dev_no;
2414 int found = 0;
2415
2416 dev_no = dev->devfn >> 3;
2417 for (i = dev_no; i >= 0; i--) {
2418 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2419 if (!host_bridge)
2420 continue;
2421
2422 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2423 if (pos != 0) {
2424 found = 1;
2425 break;
2426 }
2427 pci_dev_put(host_bridge);
2428 }
2429
2430 if (!found)
2431 return;
2432
2433 /* don't enable end_device/host_bridge with leaf directly here */
2434 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2435 host_bridge_with_leaf(host_bridge))
2436 goto out;
2437
2438 /* root did that ! */
2439 if (msi_ht_cap_enabled(host_bridge))
2440 goto out;
2441
2442 ht_enable_msi_mapping(dev);
2443
2444 out:
2445 pci_dev_put(host_bridge);
2446 }
2447
2448 static void ht_disable_msi_mapping(struct pci_dev *dev)
2449 {
2450 int pos, ttl = 48;
2451
2452 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2453 while (pos && ttl--) {
2454 u8 flags;
2455
2456 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2457 &flags) == 0) {
2458 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2459
2460 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2461 flags & ~HT_MSI_FLAGS_ENABLE);
2462 }
2463 pos = pci_find_next_ht_capability(dev, pos,
2464 HT_CAPTYPE_MSI_MAPPING);
2465 }
2466 }
2467
2468 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2469 {
2470 struct pci_dev *host_bridge;
2471 int pos;
2472 int found;
2473
2474 if (!pci_msi_enabled())
2475 return;
2476
2477 /* check if there is HT MSI cap or enabled on this device */
2478 found = ht_check_msi_mapping(dev);
2479
2480 /* no HT MSI CAP */
2481 if (found == 0)
2482 return;
2483
2484 /*
2485 * HT MSI mapping should be disabled on devices that are below
2486 * a non-Hypertransport host bridge. Locate the host bridge...
2487 */
2488 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2489 if (host_bridge == NULL) {
2490 dev_warn(&dev->dev,
2491 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2492 return;
2493 }
2494
2495 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2496 if (pos != 0) {
2497 /* Host bridge is to HT */
2498 if (found == 1) {
2499 /* it is not enabled, try to enable it */
2500 if (all)
2501 ht_enable_msi_mapping(dev);
2502 else
2503 nv_ht_enable_msi_mapping(dev);
2504 }
2505 goto out;
2506 }
2507
2508 /* HT MSI is not enabled */
2509 if (found == 1)
2510 goto out;
2511
2512 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2513 ht_disable_msi_mapping(dev);
2514
2515 out:
2516 pci_dev_put(host_bridge);
2517 }
2518
2519 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2520 {
2521 return __nv_msi_ht_cap_quirk(dev, 1);
2522 }
2523
2524 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2525 {
2526 return __nv_msi_ht_cap_quirk(dev, 0);
2527 }
2528
2529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2530 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2531
2532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2534
2535 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2536 {
2537 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2538 }
2539 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2540 {
2541 struct pci_dev *p;
2542
2543 /* SB700 MSI issue will be fixed at HW level from revision A21,
2544 * we need check PCI REVISION ID of SMBus controller to get SB700
2545 * revision.
2546 */
2547 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2548 NULL);
2549 if (!p)
2550 return;
2551
2552 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2553 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2554 pci_dev_put(p);
2555 }
2556 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2557 {
2558 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2559 if (dev->revision < 0x18) {
2560 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2561 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2562 }
2563 }
2564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2565 PCI_DEVICE_ID_TIGON3_5780,
2566 quirk_msi_intx_disable_bug);
2567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2568 PCI_DEVICE_ID_TIGON3_5780S,
2569 quirk_msi_intx_disable_bug);
2570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2571 PCI_DEVICE_ID_TIGON3_5714,
2572 quirk_msi_intx_disable_bug);
2573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2574 PCI_DEVICE_ID_TIGON3_5714S,
2575 quirk_msi_intx_disable_bug);
2576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2577 PCI_DEVICE_ID_TIGON3_5715,
2578 quirk_msi_intx_disable_bug);
2579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2580 PCI_DEVICE_ID_TIGON3_5715S,
2581 quirk_msi_intx_disable_bug);
2582
2583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2584 quirk_msi_intx_disable_ati_bug);
2585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2586 quirk_msi_intx_disable_ati_bug);
2587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2588 quirk_msi_intx_disable_ati_bug);
2589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2590 quirk_msi_intx_disable_ati_bug);
2591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2592 quirk_msi_intx_disable_ati_bug);
2593
2594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2595 quirk_msi_intx_disable_bug);
2596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2597 quirk_msi_intx_disable_bug);
2598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2599 quirk_msi_intx_disable_bug);
2600
2601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2602 quirk_msi_intx_disable_bug);
2603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2604 quirk_msi_intx_disable_bug);
2605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2606 quirk_msi_intx_disable_bug);
2607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2608 quirk_msi_intx_disable_bug);
2609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2610 quirk_msi_intx_disable_bug);
2611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2612 quirk_msi_intx_disable_bug);
2613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2614 quirk_msi_intx_disable_qca_bug);
2615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2616 quirk_msi_intx_disable_qca_bug);
2617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2618 quirk_msi_intx_disable_qca_bug);
2619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2620 quirk_msi_intx_disable_qca_bug);
2621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2622 quirk_msi_intx_disable_qca_bug);
2623 #endif /* CONFIG_PCI_MSI */
2624
2625 /* Allow manual resource allocation for PCI hotplug bridges
2626 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2627 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2628 * kernel fails to allocate resources when hotplug device is
2629 * inserted and PCI bus is rescanned.
2630 */
2631 static void quirk_hotplug_bridge(struct pci_dev *dev)
2632 {
2633 dev->is_hotplug_bridge = 1;
2634 }
2635
2636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2637
2638 /*
2639 * This is a quirk for the Ricoh MMC controller found as a part of
2640 * some mulifunction chips.
2641
2642 * This is very similar and based on the ricoh_mmc driver written by
2643 * Philip Langdale. Thank you for these magic sequences.
2644 *
2645 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2646 * and one or both of cardbus or firewire.
2647 *
2648 * It happens that they implement SD and MMC
2649 * support as separate controllers (and PCI functions). The linux SDHCI
2650 * driver supports MMC cards but the chip detects MMC cards in hardware
2651 * and directs them to the MMC controller - so the SDHCI driver never sees
2652 * them.
2653 *
2654 * To get around this, we must disable the useless MMC controller.
2655 * At that point, the SDHCI controller will start seeing them
2656 * It seems to be the case that the relevant PCI registers to deactivate the
2657 * MMC controller live on PCI function 0, which might be the cardbus controller
2658 * or the firewire controller, depending on the particular chip in question
2659 *
2660 * This has to be done early, because as soon as we disable the MMC controller
2661 * other pci functions shift up one level, e.g. function #2 becomes function
2662 * #1, and this will confuse the pci core.
2663 */
2664
2665 #ifdef CONFIG_MMC_RICOH_MMC
2666 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2667 {
2668 /* disable via cardbus interface */
2669 u8 write_enable;
2670 u8 write_target;
2671 u8 disable;
2672
2673 /* disable must be done via function #0 */
2674 if (PCI_FUNC(dev->devfn))
2675 return;
2676
2677 pci_read_config_byte(dev, 0xB7, &disable);
2678 if (disable & 0x02)
2679 return;
2680
2681 pci_read_config_byte(dev, 0x8E, &write_enable);
2682 pci_write_config_byte(dev, 0x8E, 0xAA);
2683 pci_read_config_byte(dev, 0x8D, &write_target);
2684 pci_write_config_byte(dev, 0x8D, 0xB7);
2685 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2686 pci_write_config_byte(dev, 0x8E, write_enable);
2687 pci_write_config_byte(dev, 0x8D, write_target);
2688
2689 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2690 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2691 }
2692 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2693 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2694
2695 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2696 {
2697 /* disable via firewire interface */
2698 u8 write_enable;
2699 u8 disable;
2700
2701 /* disable must be done via function #0 */
2702 if (PCI_FUNC(dev->devfn))
2703 return;
2704 /*
2705 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2706 * certain types of SD/MMC cards. Lowering the SD base
2707 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2708 *
2709 * 0x150 - SD2.0 mode enable for changing base clock
2710 * frequency to 50Mhz
2711 * 0xe1 - Base clock frequency
2712 * 0x32 - 50Mhz new clock frequency
2713 * 0xf9 - Key register for 0x150
2714 * 0xfc - key register for 0xe1
2715 */
2716 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2717 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2718 pci_write_config_byte(dev, 0xf9, 0xfc);
2719 pci_write_config_byte(dev, 0x150, 0x10);
2720 pci_write_config_byte(dev, 0xf9, 0x00);
2721 pci_write_config_byte(dev, 0xfc, 0x01);
2722 pci_write_config_byte(dev, 0xe1, 0x32);
2723 pci_write_config_byte(dev, 0xfc, 0x00);
2724
2725 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2726 }
2727
2728 pci_read_config_byte(dev, 0xCB, &disable);
2729
2730 if (disable & 0x02)
2731 return;
2732
2733 pci_read_config_byte(dev, 0xCA, &write_enable);
2734 pci_write_config_byte(dev, 0xCA, 0x57);
2735 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2736 pci_write_config_byte(dev, 0xCA, write_enable);
2737
2738 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2739 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2740
2741 }
2742 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2743 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2744 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2745 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2746 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2747 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2748 #endif /*CONFIG_MMC_RICOH_MMC*/
2749
2750 #ifdef CONFIG_DMAR_TABLE
2751 #define VTUNCERRMSK_REG 0x1ac
2752 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2753 /*
2754 * This is a quirk for masking vt-d spec defined errors to platform error
2755 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2756 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2757 * on the RAS config settings of the platform) when a vt-d fault happens.
2758 * The resulting SMI caused the system to hang.
2759 *
2760 * VT-d spec related errors are already handled by the VT-d OS code, so no
2761 * need to report the same error through other channels.
2762 */
2763 static void vtd_mask_spec_errors(struct pci_dev *dev)
2764 {
2765 u32 word;
2766
2767 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2768 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2769 }
2770 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2771 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2772 #endif
2773
2774 static void fixup_ti816x_class(struct pci_dev *dev)
2775 {
2776 /* TI 816x devices do not have class code set when in PCIe boot mode */
2777 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2778 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2779 }
2780 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2781 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2782
2783 /* Some PCIe devices do not work reliably with the claimed maximum
2784 * payload size supported.
2785 */
2786 static void fixup_mpss_256(struct pci_dev *dev)
2787 {
2788 dev->pcie_mpss = 1; /* 256 bytes */
2789 }
2790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2791 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2793 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2795 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2796
2797 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2798 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2799 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2800 * until all of the devices are discovered and buses walked, read completion
2801 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2802 * it is possible to hotplug a device with MPS of 256B.
2803 */
2804 static void quirk_intel_mc_errata(struct pci_dev *dev)
2805 {
2806 int err;
2807 u16 rcc;
2808
2809 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2810 return;
2811
2812 /* Intel errata specifies bits to change but does not say what they are.
2813 * Keeping them magical until such time as the registers and values can
2814 * be explained.
2815 */
2816 err = pci_read_config_word(dev, 0x48, &rcc);
2817 if (err) {
2818 dev_err(&dev->dev, "Error attempting to read the read "
2819 "completion coalescing register.\n");
2820 return;
2821 }
2822
2823 if (!(rcc & (1 << 10)))
2824 return;
2825
2826 rcc &= ~(1 << 10);
2827
2828 err = pci_write_config_word(dev, 0x48, rcc);
2829 if (err) {
2830 dev_err(&dev->dev, "Error attempting to write the read "
2831 "completion coalescing register.\n");
2832 return;
2833 }
2834
2835 pr_info_once("Read completion coalescing disabled due to hardware "
2836 "errata relating to 256B MPS.\n");
2837 }
2838 /* Intel 5000 series memory controllers and ports 2-7 */
2839 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2841 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2853 /* Intel 5100 series memory controllers and ports 2-7 */
2854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2862 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2865
2866
2867 /*
2868 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2869 * work around this, query the size it should be configured to by the device and
2870 * modify the resource end to correspond to this new size.
2871 */
2872 static void quirk_intel_ntb(struct pci_dev *dev)
2873 {
2874 int rc;
2875 u8 val;
2876
2877 rc = pci_read_config_byte(dev, 0x00D0, &val);
2878 if (rc)
2879 return;
2880
2881 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2882
2883 rc = pci_read_config_byte(dev, 0x00D1, &val);
2884 if (rc)
2885 return;
2886
2887 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2888 }
2889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2891
2892 static ktime_t fixup_debug_start(struct pci_dev *dev,
2893 void (*fn)(struct pci_dev *dev))
2894 {
2895 ktime_t calltime = ktime_set(0, 0);
2896
2897 dev_dbg(&dev->dev, "calling %pF\n", fn);
2898 if (initcall_debug) {
2899 pr_debug("calling %pF @ %i for %s\n",
2900 fn, task_pid_nr(current), dev_name(&dev->dev));
2901 calltime = ktime_get();
2902 }
2903
2904 return calltime;
2905 }
2906
2907 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2908 void (*fn)(struct pci_dev *dev))
2909 {
2910 ktime_t delta, rettime;
2911 unsigned long long duration;
2912
2913 if (initcall_debug) {
2914 rettime = ktime_get();
2915 delta = ktime_sub(rettime, calltime);
2916 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2917 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2918 fn, duration, dev_name(&dev->dev));
2919 }
2920 }
2921
2922 /*
2923 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2924 * even though no one is handling them (f.e. i915 driver is never loaded).
2925 * Additionally the interrupt destination is not set up properly
2926 * and the interrupt ends up -somewhere-.
2927 *
2928 * These spurious interrupts are "sticky" and the kernel disables
2929 * the (shared) interrupt line after 100.000+ generated interrupts.
2930 *
2931 * Fix it by disabling the still enabled interrupts.
2932 * This resolves crashes often seen on monitor unplug.
2933 */
2934 #define I915_DEIER_REG 0x4400c
2935 static void disable_igfx_irq(struct pci_dev *dev)
2936 {
2937 void __iomem *regs = pci_iomap(dev, 0, 0);
2938 if (regs == NULL) {
2939 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2940 return;
2941 }
2942
2943 /* Check if any interrupt line is still enabled */
2944 if (readl(regs + I915_DEIER_REG) != 0) {
2945 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2946 "disabling\n");
2947
2948 writel(0, regs + I915_DEIER_REG);
2949 }
2950
2951 pci_iounmap(dev, regs);
2952 }
2953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
2956
2957 /*
2958 * PCI devices which are on Intel chips can skip the 10ms delay
2959 * before entering D3 mode.
2960 */
2961 static void quirk_remove_d3_delay(struct pci_dev *dev)
2962 {
2963 dev->d3_delay = 0;
2964 }
2965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
2966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
2967 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
2968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
2969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
2970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
2971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
2972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
2973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
2974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
2975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
2976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
2977 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
2978 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
2979
2980 /*
2981 * Some devices may pass our check in pci_intx_mask_supported if
2982 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2983 * support this feature.
2984 */
2985 static void quirk_broken_intx_masking(struct pci_dev *dev)
2986 {
2987 dev->broken_intx_masking = 1;
2988 }
2989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2990 quirk_broken_intx_masking);
2991 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2992 quirk_broken_intx_masking);
2993 /*
2994 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
2995 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
2996 *
2997 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
2998 */
2999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_REALTEK, 0x8169,
3000 quirk_broken_intx_masking);
3001
3002 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3003 struct pci_fixup *end)
3004 {
3005 ktime_t calltime;
3006
3007 for (; f < end; f++)
3008 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3009 f->class == (u32) PCI_ANY_ID) &&
3010 (f->vendor == dev->vendor ||
3011 f->vendor == (u16) PCI_ANY_ID) &&
3012 (f->device == dev->device ||
3013 f->device == (u16) PCI_ANY_ID)) {
3014 calltime = fixup_debug_start(dev, f->hook);
3015 f->hook(dev);
3016 fixup_debug_report(dev, calltime, f->hook);
3017 }
3018 }
3019
3020 extern struct pci_fixup __start_pci_fixups_early[];
3021 extern struct pci_fixup __end_pci_fixups_early[];
3022 extern struct pci_fixup __start_pci_fixups_header[];
3023 extern struct pci_fixup __end_pci_fixups_header[];
3024 extern struct pci_fixup __start_pci_fixups_final[];
3025 extern struct pci_fixup __end_pci_fixups_final[];
3026 extern struct pci_fixup __start_pci_fixups_enable[];
3027 extern struct pci_fixup __end_pci_fixups_enable[];
3028 extern struct pci_fixup __start_pci_fixups_resume[];
3029 extern struct pci_fixup __end_pci_fixups_resume[];
3030 extern struct pci_fixup __start_pci_fixups_resume_early[];
3031 extern struct pci_fixup __end_pci_fixups_resume_early[];
3032 extern struct pci_fixup __start_pci_fixups_suspend[];
3033 extern struct pci_fixup __end_pci_fixups_suspend[];
3034
3035 static bool pci_apply_fixup_final_quirks;
3036
3037 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3038 {
3039 struct pci_fixup *start, *end;
3040
3041 switch (pass) {
3042 case pci_fixup_early:
3043 start = __start_pci_fixups_early;
3044 end = __end_pci_fixups_early;
3045 break;
3046
3047 case pci_fixup_header:
3048 start = __start_pci_fixups_header;
3049 end = __end_pci_fixups_header;
3050 break;
3051
3052 case pci_fixup_final:
3053 if (!pci_apply_fixup_final_quirks)
3054 return;
3055 start = __start_pci_fixups_final;
3056 end = __end_pci_fixups_final;
3057 break;
3058
3059 case pci_fixup_enable:
3060 start = __start_pci_fixups_enable;
3061 end = __end_pci_fixups_enable;
3062 break;
3063
3064 case pci_fixup_resume:
3065 start = __start_pci_fixups_resume;
3066 end = __end_pci_fixups_resume;
3067 break;
3068
3069 case pci_fixup_resume_early:
3070 start = __start_pci_fixups_resume_early;
3071 end = __end_pci_fixups_resume_early;
3072 break;
3073
3074 case pci_fixup_suspend:
3075 start = __start_pci_fixups_suspend;
3076 end = __end_pci_fixups_suspend;
3077 break;
3078
3079 default:
3080 /* stupid compiler warning, you would think with an enum... */
3081 return;
3082 }
3083 pci_do_fixups(dev, start, end);
3084 }
3085 EXPORT_SYMBOL(pci_fixup_device);
3086
3087
3088 static int __init pci_apply_final_quirks(void)
3089 {
3090 struct pci_dev *dev = NULL;
3091 u8 cls = 0;
3092 u8 tmp;
3093
3094 if (pci_cache_line_size)
3095 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3096 pci_cache_line_size << 2);
3097
3098 pci_apply_fixup_final_quirks = true;
3099 for_each_pci_dev(dev) {
3100 pci_fixup_device(pci_fixup_final, dev);
3101 /*
3102 * If arch hasn't set it explicitly yet, use the CLS
3103 * value shared by all PCI devices. If there's a
3104 * mismatch, fall back to the default value.
3105 */
3106 if (!pci_cache_line_size) {
3107 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3108 if (!cls)
3109 cls = tmp;
3110 if (!tmp || cls == tmp)
3111 continue;
3112
3113 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3114 "using %u bytes\n", cls << 2, tmp << 2,
3115 pci_dfl_cache_line_size << 2);
3116 pci_cache_line_size = pci_dfl_cache_line_size;
3117 }
3118 }
3119
3120 if (!pci_cache_line_size) {
3121 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3122 cls << 2, pci_dfl_cache_line_size << 2);
3123 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3124 }
3125
3126 return 0;
3127 }
3128
3129 fs_initcall_sync(pci_apply_final_quirks);
3130
3131 /*
3132 * Followings are device-specific reset methods which can be used to
3133 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3134 * not available.
3135 */
3136 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3137 {
3138 int pos;
3139
3140 /* only implement PCI_CLASS_SERIAL_USB at present */
3141 if (dev->class == PCI_CLASS_SERIAL_USB) {
3142 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3143 if (!pos)
3144 return -ENOTTY;
3145
3146 if (probe)
3147 return 0;
3148
3149 pci_write_config_byte(dev, pos + 0x4, 1);
3150 msleep(100);
3151
3152 return 0;
3153 } else {
3154 return -ENOTTY;
3155 }
3156 }
3157
3158 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3159 {
3160 /*
3161 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3162 *
3163 * The 82599 supports FLR on VFs, but FLR support is reported only
3164 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3165 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3166 */
3167
3168 if (probe)
3169 return 0;
3170
3171 if (!pci_wait_for_pending_transaction(dev))
3172 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3173
3174 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3175
3176 msleep(100);
3177
3178 return 0;
3179 }
3180
3181 #include "../gpu/drm/i915/i915_reg.h"
3182 #define MSG_CTL 0x45010
3183 #define NSDE_PWR_STATE 0xd0100
3184 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3185
3186 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3187 {
3188 void __iomem *mmio_base;
3189 unsigned long timeout;
3190 u32 val;
3191
3192 if (probe)
3193 return 0;
3194
3195 mmio_base = pci_iomap(dev, 0, 0);
3196 if (!mmio_base)
3197 return -ENOMEM;
3198
3199 iowrite32(0x00000002, mmio_base + MSG_CTL);
3200
3201 /*
3202 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3203 * driver loaded sets the right bits. However, this's a reset and
3204 * the bits have been set by i915 previously, so we clobber
3205 * SOUTH_CHICKEN2 register directly here.
3206 */
3207 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3208
3209 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3210 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3211
3212 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3213 do {
3214 val = ioread32(mmio_base + PCH_PP_STATUS);
3215 if ((val & 0xb0000000) == 0)
3216 goto reset_complete;
3217 msleep(10);
3218 } while (time_before(jiffies, timeout));
3219 dev_warn(&dev->dev, "timeout during reset\n");
3220
3221 reset_complete:
3222 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3223
3224 pci_iounmap(dev, mmio_base);
3225 return 0;
3226 }
3227
3228 /*
3229 * Device-specific reset method for Chelsio T4-based adapters.
3230 */
3231 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3232 {
3233 u16 old_command;
3234 u16 msix_flags;
3235
3236 /*
3237 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3238 * that we have no device-specific reset method.
3239 */
3240 if ((dev->device & 0xf000) != 0x4000)
3241 return -ENOTTY;
3242
3243 /*
3244 * If this is the "probe" phase, return 0 indicating that we can
3245 * reset this device.
3246 */
3247 if (probe)
3248 return 0;
3249
3250 /*
3251 * T4 can wedge if there are DMAs in flight within the chip and Bus
3252 * Master has been disabled. We need to have it on till the Function
3253 * Level Reset completes. (BUS_MASTER is disabled in
3254 * pci_reset_function()).
3255 */
3256 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3257 pci_write_config_word(dev, PCI_COMMAND,
3258 old_command | PCI_COMMAND_MASTER);
3259
3260 /*
3261 * Perform the actual device function reset, saving and restoring
3262 * configuration information around the reset.
3263 */
3264 pci_save_state(dev);
3265
3266 /*
3267 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3268 * are disabled when an MSI-X interrupt message needs to be delivered.
3269 * So we briefly re-enable MSI-X interrupts for the duration of the
3270 * FLR. The pci_restore_state() below will restore the original
3271 * MSI-X state.
3272 */
3273 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3274 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3275 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3276 msix_flags |
3277 PCI_MSIX_FLAGS_ENABLE |
3278 PCI_MSIX_FLAGS_MASKALL);
3279
3280 /*
3281 * Start of pcie_flr() code sequence. This reset code is a copy of
3282 * the guts of pcie_flr() because that's not an exported function.
3283 */
3284
3285 if (!pci_wait_for_pending_transaction(dev))
3286 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3287
3288 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3289 msleep(100);
3290
3291 /*
3292 * End of pcie_flr() code sequence.
3293 */
3294
3295 /*
3296 * Restore the configuration information (BAR values, etc.) including
3297 * the original PCI Configuration Space Command word, and return
3298 * success.
3299 */
3300 pci_restore_state(dev);
3301 pci_write_config_word(dev, PCI_COMMAND, old_command);
3302 return 0;
3303 }
3304
3305 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3306 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3307 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3308
3309 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3310 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3311 reset_intel_82599_sfp_virtfn },
3312 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3313 reset_ivb_igd },
3314 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3315 reset_ivb_igd },
3316 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3317 reset_intel_generic_dev },
3318 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3319 reset_chelsio_generic_dev },
3320 { 0 }
3321 };
3322
3323 /*
3324 * These device-specific reset methods are here rather than in a driver
3325 * because when a host assigns a device to a guest VM, the host may need
3326 * to reset the device but probably doesn't have a driver for it.
3327 */
3328 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3329 {
3330 const struct pci_dev_reset_methods *i;
3331
3332 for (i = pci_dev_reset_methods; i->reset; i++) {
3333 if ((i->vendor == dev->vendor ||
3334 i->vendor == (u16)PCI_ANY_ID) &&
3335 (i->device == dev->device ||
3336 i->device == (u16)PCI_ANY_ID))
3337 return i->reset(dev, probe);
3338 }
3339
3340 return -ENOTTY;
3341 }
3342
3343 static void quirk_dma_func0_alias(struct pci_dev *dev)
3344 {
3345 if (PCI_FUNC(dev->devfn) != 0) {
3346 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 0);
3347 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3348 }
3349 }
3350
3351 /*
3352 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3353 *
3354 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3355 */
3356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3358
3359 static void quirk_dma_func1_alias(struct pci_dev *dev)
3360 {
3361 if (PCI_FUNC(dev->devfn) != 1) {
3362 dev->dma_alias_devfn = PCI_DEVFN(PCI_SLOT(dev->devfn), 1);
3363 dev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
3364 }
3365 }
3366
3367 /*
3368 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3369 * SKUs function 1 is present and is a legacy IDE controller, in other
3370 * SKUs this function is not present, making this a ghost requester.
3371 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3372 */
3373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3374 quirk_dma_func1_alias);
3375 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3377 quirk_dma_func1_alias);
3378 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3380 quirk_dma_func1_alias);
3381 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3383 quirk_dma_func1_alias);
3384 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3386 quirk_dma_func1_alias);
3387 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3389 quirk_dma_func1_alias);
3390 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3391 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3392 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3393 quirk_dma_func1_alias);
3394
3395 /*
3396 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3397 * using the wrong DMA alias for the device. Some of these devices can be
3398 * used as either forward or reverse bridges, so we need to test whether the
3399 * device is operating in the correct mode. We could probably apply this
3400 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3401 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3402 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3403 */
3404 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3405 {
3406 if (!pci_is_root_bus(pdev->bus) &&
3407 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3408 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3409 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3410 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3411 }
3412 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3414 quirk_use_pcie_bridge_dma_alias);
3415 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3416 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3417
3418 static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3419 {
3420 if (!PCI_FUNC(dev->devfn))
3421 return pci_dev_get(dev);
3422
3423 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3424 }
3425
3426 static const struct pci_dev_dma_source {
3427 u16 vendor;
3428 u16 device;
3429 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3430 } pci_dev_dma_source[] = {
3431 /*
3432 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3433 *
3434 * Some Ricoh devices use the function 0 source ID for DMA on
3435 * other functions of a multifunction device. The DMA devices
3436 * is therefore function 0, which will have implications of the
3437 * iommu grouping of these devices.
3438 */
3439 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3440 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3441 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3442 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3443 { 0 }
3444 };
3445
3446 /*
3447 * IOMMUs with isolation capabilities need to be programmed with the
3448 * correct source ID of a device. In most cases, the source ID matches
3449 * the device doing the DMA, but sometimes hardware is broken and will
3450 * tag the DMA as being sourced from a different device. This function
3451 * allows that translation. Note that the reference count of the
3452 * returned device is incremented on all paths.
3453 */
3454 struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3455 {
3456 const struct pci_dev_dma_source *i;
3457
3458 for (i = pci_dev_dma_source; i->dma_source; i++) {
3459 if ((i->vendor == dev->vendor ||
3460 i->vendor == (u16)PCI_ANY_ID) &&
3461 (i->device == dev->device ||
3462 i->device == (u16)PCI_ANY_ID))
3463 return i->dma_source(dev);
3464 }
3465
3466 return pci_dev_get(dev);
3467 }
3468
3469 /*
3470 * AMD has indicated that the devices below do not support peer-to-peer
3471 * in any system where they are found in the southbridge with an AMD
3472 * IOMMU in the system. Multifunction devices that do not support
3473 * peer-to-peer between functions can claim to support a subset of ACS.
3474 * Such devices effectively enable request redirect (RR) and completion
3475 * redirect (CR) since all transactions are redirected to the upstream
3476 * root complex.
3477 *
3478 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3479 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3480 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3481 *
3482 * 1002:4385 SBx00 SMBus Controller
3483 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3484 * 1002:4383 SBx00 Azalia (Intel HDA)
3485 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3486 * 1002:4384 SBx00 PCI to PCI Bridge
3487 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3488 */
3489 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3490 {
3491 #ifdef CONFIG_ACPI
3492 struct acpi_table_header *header = NULL;
3493 acpi_status status;
3494
3495 /* Targeting multifunction devices on the SB (appears on root bus) */
3496 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3497 return -ENODEV;
3498
3499 /* The IVRS table describes the AMD IOMMU */
3500 status = acpi_get_table("IVRS", 0, &header);
3501 if (ACPI_FAILURE(status))
3502 return -ENODEV;
3503
3504 /* Filter out flags not applicable to multifunction */
3505 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3506
3507 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3508 #else
3509 return -ENODEV;
3510 #endif
3511 }
3512
3513 /*
3514 * Many Intel PCH root ports do provide ACS-like features to disable peer
3515 * transactions and validate bus numbers in requests, but do not provide an
3516 * actual PCIe ACS capability. This is the list of device IDs known to fall
3517 * into that category as provided by Intel in Red Hat bugzilla 1037684.
3518 */
3519 static const u16 pci_quirk_intel_pch_acs_ids[] = {
3520 /* Ibexpeak PCH */
3521 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
3522 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
3523 /* Cougarpoint PCH */
3524 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
3525 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
3526 /* Pantherpoint PCH */
3527 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
3528 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
3529 /* Lynxpoint-H PCH */
3530 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
3531 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
3532 /* Lynxpoint-LP PCH */
3533 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
3534 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
3535 /* Wildcat PCH */
3536 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
3537 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
3538 /* Patsburg (X79) PCH */
3539 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
3540 };
3541
3542 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
3543 {
3544 int i;
3545
3546 /* Filter out a few obvious non-matches first */
3547 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
3548 return false;
3549
3550 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
3551 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
3552 return true;
3553
3554 return false;
3555 }
3556
3557 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
3558
3559 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3560 {
3561 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
3562 INTEL_PCH_ACS_FLAGS : 0;
3563
3564 if (!pci_quirk_intel_pch_acs_match(dev))
3565 return -ENOTTY;
3566
3567 return acs_flags & ~flags ? 0 : 1;
3568 }
3569
3570 static const struct pci_dev_acs_enabled {
3571 u16 vendor;
3572 u16 device;
3573 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3574 } pci_dev_acs_enabled[] = {
3575 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3576 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3577 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3578 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3579 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3580 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3581 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
3582 { 0 }
3583 };
3584
3585 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3586 {
3587 const struct pci_dev_acs_enabled *i;
3588 int ret;
3589
3590 /*
3591 * Allow devices that do not expose standard PCIe ACS capabilities
3592 * or control to indicate their support here. Multi-function express
3593 * devices which do not allow internal peer-to-peer between functions,
3594 * but do not implement PCIe ACS may wish to return true here.
3595 */
3596 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3597 if ((i->vendor == dev->vendor ||
3598 i->vendor == (u16)PCI_ANY_ID) &&
3599 (i->device == dev->device ||
3600 i->device == (u16)PCI_ANY_ID)) {
3601 ret = i->acs_enabled(dev, acs_flags);
3602 if (ret >= 0)
3603 return ret;
3604 }
3605 }
3606
3607 return -ENOTTY;
3608 }
3609
3610 /* Config space offset of Root Complex Base Address register */
3611 #define INTEL_LPC_RCBA_REG 0xf0
3612 /* 31:14 RCBA address */
3613 #define INTEL_LPC_RCBA_MASK 0xffffc000
3614 /* RCBA Enable */
3615 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
3616
3617 /* Backbone Scratch Pad Register */
3618 #define INTEL_BSPR_REG 0x1104
3619 /* Backbone Peer Non-Posted Disable */
3620 #define INTEL_BSPR_REG_BPNPD (1 << 8)
3621 /* Backbone Peer Posted Disable */
3622 #define INTEL_BSPR_REG_BPPD (1 << 9)
3623
3624 /* Upstream Peer Decode Configuration Register */
3625 #define INTEL_UPDCR_REG 0x1114
3626 /* 5:0 Peer Decode Enable bits */
3627 #define INTEL_UPDCR_REG_MASK 0x3f
3628
3629 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
3630 {
3631 u32 rcba, bspr, updcr;
3632 void __iomem *rcba_mem;
3633
3634 /*
3635 * Read the RCBA register from the LPC (D31:F0). PCH root ports
3636 * are D28:F* and therefore get probed before LPC, thus we can't
3637 * use pci_get_slot/pci_read_config_dword here.
3638 */
3639 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
3640 INTEL_LPC_RCBA_REG, &rcba);
3641 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
3642 return -EINVAL;
3643
3644 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
3645 PAGE_ALIGN(INTEL_UPDCR_REG));
3646 if (!rcba_mem)
3647 return -ENOMEM;
3648
3649 /*
3650 * The BSPR can disallow peer cycles, but it's set by soft strap and
3651 * therefore read-only. If both posted and non-posted peer cycles are
3652 * disallowed, we're ok. If either are allowed, then we need to use
3653 * the UPDCR to disable peer decodes for each port. This provides the
3654 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
3655 */
3656 bspr = readl(rcba_mem + INTEL_BSPR_REG);
3657 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
3658 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
3659 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
3660 if (updcr & INTEL_UPDCR_REG_MASK) {
3661 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
3662 updcr &= ~INTEL_UPDCR_REG_MASK;
3663 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
3664 }
3665 }
3666
3667 iounmap(rcba_mem);
3668 return 0;
3669 }
3670
3671 /* Miscellaneous Port Configuration register */
3672 #define INTEL_MPC_REG 0xd8
3673 /* MPC: Invalid Receive Bus Number Check Enable */
3674 #define INTEL_MPC_REG_IRBNCE (1 << 26)
3675
3676 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
3677 {
3678 u32 mpc;
3679
3680 /*
3681 * When enabled, the IRBNCE bit of the MPC register enables the
3682 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
3683 * ensures that requester IDs fall within the bus number range
3684 * of the bridge. Enable if not already.
3685 */
3686 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
3687 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
3688 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
3689 mpc |= INTEL_MPC_REG_IRBNCE;
3690 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
3691 }
3692 }
3693
3694 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
3695 {
3696 if (!pci_quirk_intel_pch_acs_match(dev))
3697 return -ENOTTY;
3698
3699 if (pci_quirk_enable_intel_lpc_acs(dev)) {
3700 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
3701 return 0;
3702 }
3703
3704 pci_quirk_enable_intel_rp_mpc_acs(dev);
3705
3706 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
3707
3708 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
3709
3710 return 0;
3711 }
3712
3713 static const struct pci_dev_enable_acs {
3714 u16 vendor;
3715 u16 device;
3716 int (*enable_acs)(struct pci_dev *dev);
3717 } pci_dev_enable_acs[] = {
3718 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
3719 { 0 }
3720 };
3721
3722 void pci_dev_specific_enable_acs(struct pci_dev *dev)
3723 {
3724 const struct pci_dev_enable_acs *i;
3725 int ret;
3726
3727 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
3728 if ((i->vendor == dev->vendor ||
3729 i->vendor == (u16)PCI_ANY_ID) &&
3730 (i->device == dev->device ||
3731 i->device == (u16)PCI_ANY_ID)) {
3732 ret = i->enable_acs(dev);
3733 if (ret >= 0)
3734 return;
3735 }
3736 }
3737 }
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