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UBUNTU: SAUCE: PCI: Disable broken RTIT_BAR of Intel TH
[mirror_ubuntu-artful-kernel.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <linux/mm.h>
28 #include <linux/vgaarb.h>
29 #include <asm/dma.h> /* isa_dma_bridge_buggy */
30 #include "pci.h"
31
32 /*
33 * Decoding should be disabled for a PCI device during BAR sizing to avoid
34 * conflict. But doing so may cause problems on host bridge and perhaps other
35 * key system devices. For devices that need to have mmio decoding always-on,
36 * we need to set the dev->mmio_always_on bit.
37 */
38 static void quirk_mmio_always_on(struct pci_dev *dev)
39 {
40 dev->mmio_always_on = 1;
41 }
42 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
43 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
44
45 /* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed
46 * by IO resource file, and need to skip the files
47 */
48 static void quirk_marvell_mask_bar(struct pci_dev *dev)
49 {
50 int i;
51
52 for (i = 0; i < 5; i++)
53 if (dev->resource[i].start)
54 dev->resource[i].start =
55 dev->resource[i].end = 0;
56 }
57 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
58 quirk_marvell_mask_bar);
59
60 /* The Mellanox Tavor device gives false positive parity errors
61 * Mark this device with a broken_parity_status, to allow
62 * PCI scanning code to "skip" this now blacklisted device.
63 */
64 static void quirk_mellanox_tavor(struct pci_dev *dev)
65 {
66 dev->broken_parity_status = 1; /* This device gives false positives */
67 }
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
70
71 /* Deal with broken BIOSes that neglect to enable passive release,
72 which can cause problems in combination with the 82441FX/PPro MTRRs */
73 static void quirk_passive_release(struct pci_dev *dev)
74 {
75 struct pci_dev *d = NULL;
76 unsigned char dlc;
77
78 /* We have to make sure a particular bit is set in the PIIX3
79 ISA bridge, so we have to go out and find it. */
80 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
81 pci_read_config_byte(d, 0x82, &dlc);
82 if (!(dlc & 1<<1)) {
83 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
84 dlc |= 1<<1;
85 pci_write_config_byte(d, 0x82, dlc);
86 }
87 }
88 }
89 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
90 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
91
92 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
93 but VIA don't answer queries. If you happen to have good contacts at VIA
94 ask them for me please -- Alan
95
96 This appears to be BIOS not version dependent. So presumably there is a
97 chipset level fix */
98
99 static void quirk_isa_dma_hangs(struct pci_dev *dev)
100 {
101 if (!isa_dma_bridge_buggy) {
102 isa_dma_bridge_buggy = 1;
103 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
104 }
105 }
106 /*
107 * Its not totally clear which chipsets are the problematic ones
108 * We know 82C586 and 82C596 variants are affected.
109 */
110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
117
118 /*
119 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
120 * for some HT machines to use C4 w/o hanging.
121 */
122 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
123 {
124 u32 pmbase;
125 u16 pm1a;
126
127 pci_read_config_dword(dev, 0x40, &pmbase);
128 pmbase = pmbase & 0xff80;
129 pm1a = inw(pmbase);
130
131 if (pm1a & 0x10) {
132 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
133 outw(0x10, pmbase);
134 }
135 }
136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
137
138 /*
139 * Chipsets where PCI->PCI transfers vanish or hang
140 */
141 static void quirk_nopcipci(struct pci_dev *dev)
142 {
143 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
144 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
145 pci_pci_problems |= PCIPCI_FAIL;
146 }
147 }
148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
150
151 static void quirk_nopciamd(struct pci_dev *dev)
152 {
153 u8 rev;
154 pci_read_config_byte(dev, 0x08, &rev);
155 if (rev == 0x13) {
156 /* Erratum 24 */
157 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
158 pci_pci_problems |= PCIAGP_FAIL;
159 }
160 }
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
162
163 /*
164 * Triton requires workarounds to be used by the drivers
165 */
166 static void quirk_triton(struct pci_dev *dev)
167 {
168 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
169 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
170 pci_pci_problems |= PCIPCI_TRITON;
171 }
172 }
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
175 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
176 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
177
178 /*
179 * VIA Apollo KT133 needs PCI latency patch
180 * Made according to a windows driver based patch by George E. Breese
181 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
182 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
183 * the info on which Mr Breese based his work.
184 *
185 * Updated based on further information from the site and also on
186 * information provided by VIA
187 */
188 static void quirk_vialatency(struct pci_dev *dev)
189 {
190 struct pci_dev *p;
191 u8 busarb;
192 /* Ok we have a potential problem chipset here. Now see if we have
193 a buggy southbridge */
194
195 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
196 if (p != NULL) {
197 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
198 /* Check for buggy part revisions */
199 if (p->revision < 0x40 || p->revision > 0x42)
200 goto exit;
201 } else {
202 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
203 if (p == NULL) /* No problem parts */
204 goto exit;
205 /* Check for buggy part revisions */
206 if (p->revision < 0x10 || p->revision > 0x12)
207 goto exit;
208 }
209
210 /*
211 * Ok we have the problem. Now set the PCI master grant to
212 * occur every master grant. The apparent bug is that under high
213 * PCI load (quite common in Linux of course) you can get data
214 * loss when the CPU is held off the bus for 3 bus master requests
215 * This happens to include the IDE controllers....
216 *
217 * VIA only apply this fix when an SB Live! is present but under
218 * both Linux and Windows this isn't enough, and we have seen
219 * corruption without SB Live! but with things like 3 UDMA IDE
220 * controllers. So we ignore that bit of the VIA recommendation..
221 */
222
223 pci_read_config_byte(dev, 0x76, &busarb);
224 /* Set bit 4 and bi 5 of byte 76 to 0x01
225 "Master priority rotation on every PCI master grant */
226 busarb &= ~(1<<5);
227 busarb |= (1<<4);
228 pci_write_config_byte(dev, 0x76, busarb);
229 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
230 exit:
231 pci_dev_put(p);
232 }
233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
236 /* Must restore this on a resume from RAM */
237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
238 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
240
241 /*
242 * VIA Apollo VP3 needs ETBF on BT848/878
243 */
244 static void quirk_viaetbf(struct pci_dev *dev)
245 {
246 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
247 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
248 pci_pci_problems |= PCIPCI_VIAETBF;
249 }
250 }
251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
252
253 static void quirk_vsfx(struct pci_dev *dev)
254 {
255 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
256 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
257 pci_pci_problems |= PCIPCI_VSFX;
258 }
259 }
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
261
262 /*
263 * Ali Magik requires workarounds to be used by the drivers
264 * that DMA to AGP space. Latency must be set to 0xA and triton
265 * workaround applied too
266 * [Info kindly provided by ALi]
267 */
268 static void quirk_alimagik(struct pci_dev *dev)
269 {
270 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
271 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
272 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
273 }
274 }
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
277
278 /*
279 * Natoma has some interesting boundary conditions with Zoran stuff
280 * at least
281 */
282 static void quirk_natoma(struct pci_dev *dev)
283 {
284 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
285 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
286 pci_pci_problems |= PCIPCI_NATOMA;
287 }
288 }
289 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
290 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
292 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
293 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
294 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
295
296 /*
297 * This chip can cause PCI parity errors if config register 0xA0 is read
298 * while DMAs are occurring.
299 */
300 static void quirk_citrine(struct pci_dev *dev)
301 {
302 dev->cfg_size = 0xA0;
303 }
304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
305
306 /*
307 * This chip can cause bus lockups if config addresses above 0x600
308 * are read or written.
309 */
310 static void quirk_nfp6000(struct pci_dev *dev)
311 {
312 dev->cfg_size = 0x600;
313 }
314 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
317
318 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
319 static void quirk_extend_bar_to_page(struct pci_dev *dev)
320 {
321 int i;
322
323 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
324 struct resource *r = &dev->resource[i];
325
326 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
327 r->end = PAGE_SIZE - 1;
328 r->start = 0;
329 r->flags |= IORESOURCE_UNSET;
330 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
331 i, r);
332 }
333 }
334 }
335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
336
337 /*
338 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
339 * If it's needed, re-allocate the region.
340 */
341 static void quirk_s3_64M(struct pci_dev *dev)
342 {
343 struct resource *r = &dev->resource[0];
344
345 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
346 r->flags |= IORESOURCE_UNSET;
347 r->start = 0;
348 r->end = 0x3ffffff;
349 }
350 }
351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
353
354 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
355 const char *name)
356 {
357 u32 region;
358 struct pci_bus_region bus_region;
359 struct resource *res = dev->resource + pos;
360
361 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
362
363 if (!region)
364 return;
365
366 res->name = pci_name(dev);
367 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
368 res->flags |=
369 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
370 region &= ~(size - 1);
371
372 /* Convert from PCI bus to resource space */
373 bus_region.start = region;
374 bus_region.end = region + size - 1;
375 pcibios_bus_to_resource(dev->bus, res, &bus_region);
376
377 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
378 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
379 }
380
381 /*
382 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
383 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
384 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
385 * (which conflicts w/ BAR1's memory range).
386 *
387 * CS553x's ISA PCI BARs may also be read-only (ref:
388 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
389 */
390 static void quirk_cs5536_vsa(struct pci_dev *dev)
391 {
392 static char *name = "CS5536 ISA bridge";
393
394 if (pci_resource_len(dev, 0) != 8) {
395 quirk_io(dev, 0, 8, name); /* SMB */
396 quirk_io(dev, 1, 256, name); /* GPIO */
397 quirk_io(dev, 2, 64, name); /* MFGPT */
398 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
399 name);
400 }
401 }
402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
403
404 static void quirk_io_region(struct pci_dev *dev, int port,
405 unsigned size, int nr, const char *name)
406 {
407 u16 region;
408 struct pci_bus_region bus_region;
409 struct resource *res = dev->resource + nr;
410
411 pci_read_config_word(dev, port, &region);
412 region &= ~(size - 1);
413
414 if (!region)
415 return;
416
417 res->name = pci_name(dev);
418 res->flags = IORESOURCE_IO;
419
420 /* Convert from PCI bus to resource space */
421 bus_region.start = region;
422 bus_region.end = region + size - 1;
423 pcibios_bus_to_resource(dev->bus, res, &bus_region);
424
425 if (!pci_claim_resource(dev, nr))
426 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
427 }
428
429 /*
430 * ATI Northbridge setups MCE the processor if you even
431 * read somewhere between 0x3b0->0x3bb or read 0x3d3
432 */
433 static void quirk_ati_exploding_mce(struct pci_dev *dev)
434 {
435 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
436 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
437 request_region(0x3b0, 0x0C, "RadeonIGP");
438 request_region(0x3d3, 0x01, "RadeonIGP");
439 }
440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
441
442 /*
443 * In the AMD NL platform, this device ([1022:7912]) has a class code of
444 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
445 * claim it.
446 * But the dwc3 driver is a more specific driver for this device, and we'd
447 * prefer to use it instead of xhci. To prevent xhci from claiming the
448 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
449 * defines as "USB device (not host controller)". The dwc3 driver can then
450 * claim it based on its Vendor and Device ID.
451 */
452 static void quirk_amd_nl_class(struct pci_dev *pdev)
453 {
454 u32 class = pdev->class;
455
456 /* Use "USB Device (not host controller)" class */
457 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
458 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
459 class, pdev->class);
460 }
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
462 quirk_amd_nl_class);
463
464 /*
465 * Let's make the southbridge information explicit instead
466 * of having to worry about people probing the ACPI areas,
467 * for example.. (Yes, it happens, and if you read the wrong
468 * ACPI register it will put the machine to sleep with no
469 * way of waking it up again. Bummer).
470 *
471 * ALI M7101: Two IO regions pointed to by words at
472 * 0xE0 (64 bytes of ACPI registers)
473 * 0xE2 (32 bytes of SMB registers)
474 */
475 static void quirk_ali7101_acpi(struct pci_dev *dev)
476 {
477 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
478 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
479 }
480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
481
482 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
483 {
484 u32 devres;
485 u32 mask, size, base;
486
487 pci_read_config_dword(dev, port, &devres);
488 if ((devres & enable) != enable)
489 return;
490 mask = (devres >> 16) & 15;
491 base = devres & 0xffff;
492 size = 16;
493 for (;;) {
494 unsigned bit = size >> 1;
495 if ((bit & mask) == bit)
496 break;
497 size = bit;
498 }
499 /*
500 * For now we only print it out. Eventually we'll want to
501 * reserve it (at least if it's in the 0x1000+ range), but
502 * let's get enough confirmation reports first.
503 */
504 base &= -size;
505 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
506 base + size - 1);
507 }
508
509 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
510 {
511 u32 devres;
512 u32 mask, size, base;
513
514 pci_read_config_dword(dev, port, &devres);
515 if ((devres & enable) != enable)
516 return;
517 base = devres & 0xffff0000;
518 mask = (devres & 0x3f) << 16;
519 size = 128 << 16;
520 for (;;) {
521 unsigned bit = size >> 1;
522 if ((bit & mask) == bit)
523 break;
524 size = bit;
525 }
526 /*
527 * For now we only print it out. Eventually we'll want to
528 * reserve it, but let's get enough confirmation reports first.
529 */
530 base &= -size;
531 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
532 base + size - 1);
533 }
534
535 /*
536 * PIIX4 ACPI: Two IO regions pointed to by longwords at
537 * 0x40 (64 bytes of ACPI registers)
538 * 0x90 (16 bytes of SMB registers)
539 * and a few strange programmable PIIX4 device resources.
540 */
541 static void quirk_piix4_acpi(struct pci_dev *dev)
542 {
543 u32 res_a;
544
545 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
546 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
547
548 /* Device resource A has enables for some of the other ones */
549 pci_read_config_dword(dev, 0x5c, &res_a);
550
551 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
552 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
553
554 /* Device resource D is just bitfields for static resources */
555
556 /* Device 12 enabled? */
557 if (res_a & (1 << 29)) {
558 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
559 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
560 }
561 /* Device 13 enabled? */
562 if (res_a & (1 << 30)) {
563 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
564 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
565 }
566 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
567 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
568 }
569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
571
572 #define ICH_PMBASE 0x40
573 #define ICH_ACPI_CNTL 0x44
574 #define ICH4_ACPI_EN 0x10
575 #define ICH6_ACPI_EN 0x80
576 #define ICH4_GPIOBASE 0x58
577 #define ICH4_GPIO_CNTL 0x5c
578 #define ICH4_GPIO_EN 0x10
579 #define ICH6_GPIOBASE 0x48
580 #define ICH6_GPIO_CNTL 0x4c
581 #define ICH6_GPIO_EN 0x10
582
583 /*
584 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
585 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
586 * 0x58 (64 bytes of GPIO I/O space)
587 */
588 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
589 {
590 u8 enable;
591
592 /*
593 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
594 * with low legacy (and fixed) ports. We don't know the decoding
595 * priority and can't tell whether the legacy device or the one created
596 * here is really at that address. This happens on boards with broken
597 * BIOSes.
598 */
599
600 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
601 if (enable & ICH4_ACPI_EN)
602 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
603 "ICH4 ACPI/GPIO/TCO");
604
605 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
606 if (enable & ICH4_GPIO_EN)
607 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
608 "ICH4 GPIO");
609 }
610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
620
621 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
622 {
623 u8 enable;
624
625 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
626 if (enable & ICH6_ACPI_EN)
627 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
628 "ICH6 ACPI/GPIO/TCO");
629
630 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
631 if (enable & ICH6_GPIO_EN)
632 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
633 "ICH6 GPIO");
634 }
635
636 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
637 {
638 u32 val;
639 u32 size, base;
640
641 pci_read_config_dword(dev, reg, &val);
642
643 /* Enabled? */
644 if (!(val & 1))
645 return;
646 base = val & 0xfffc;
647 if (dynsize) {
648 /*
649 * This is not correct. It is 16, 32 or 64 bytes depending on
650 * register D31:F0:ADh bits 5:4.
651 *
652 * But this gets us at least _part_ of it.
653 */
654 size = 16;
655 } else {
656 size = 128;
657 }
658 base &= ~(size-1);
659
660 /* Just print it out for now. We should reserve it after more debugging */
661 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
662 }
663
664 static void quirk_ich6_lpc(struct pci_dev *dev)
665 {
666 /* Shared ACPI/GPIO decode with all ICH6+ */
667 ich6_lpc_acpi_gpio(dev);
668
669 /* ICH6-specific generic IO decode */
670 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
671 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
672 }
673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
675
676 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
677 {
678 u32 val;
679 u32 mask, base;
680
681 pci_read_config_dword(dev, reg, &val);
682
683 /* Enabled? */
684 if (!(val & 1))
685 return;
686
687 /*
688 * IO base in bits 15:2, mask in bits 23:18, both
689 * are dword-based
690 */
691 base = val & 0xfffc;
692 mask = (val >> 16) & 0xfc;
693 mask |= 3;
694
695 /* Just print it out for now. We should reserve it after more debugging */
696 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
697 }
698
699 /* ICH7-10 has the same common LPC generic IO decode registers */
700 static void quirk_ich7_lpc(struct pci_dev *dev)
701 {
702 /* We share the common ACPI/GPIO decode with ICH6 */
703 ich6_lpc_acpi_gpio(dev);
704
705 /* And have 4 ICH7+ generic decodes */
706 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
707 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
708 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
709 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
710 }
711 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
712 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
713 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
716 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
717 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
718 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
719 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
720 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
722 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
724
725 /*
726 * VIA ACPI: One IO region pointed to by longword at
727 * 0x48 or 0x20 (256 bytes of ACPI registers)
728 */
729 static void quirk_vt82c586_acpi(struct pci_dev *dev)
730 {
731 if (dev->revision & 0x10)
732 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
733 "vt82c586 ACPI");
734 }
735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
736
737 /*
738 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
739 * 0x48 (256 bytes of ACPI registers)
740 * 0x70 (128 bytes of hardware monitoring register)
741 * 0x90 (16 bytes of SMB registers)
742 */
743 static void quirk_vt82c686_acpi(struct pci_dev *dev)
744 {
745 quirk_vt82c586_acpi(dev);
746
747 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
748 "vt82c686 HW-mon");
749
750 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
751 }
752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
753
754 /*
755 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
756 * 0x88 (128 bytes of power management registers)
757 * 0xd0 (16 bytes of SMB registers)
758 */
759 static void quirk_vt8235_acpi(struct pci_dev *dev)
760 {
761 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
762 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
763 }
764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
765
766 /*
767 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
768 * Disable fast back-to-back on the secondary bus segment
769 */
770 static void quirk_xio2000a(struct pci_dev *dev)
771 {
772 struct pci_dev *pdev;
773 u16 command;
774
775 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
776 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
777 pci_read_config_word(pdev, PCI_COMMAND, &command);
778 if (command & PCI_COMMAND_FAST_BACK)
779 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
780 }
781 }
782 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
783 quirk_xio2000a);
784
785 #ifdef CONFIG_X86_IO_APIC
786
787 #include <asm/io_apic.h>
788
789 /*
790 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
791 * devices to the external APIC.
792 *
793 * TODO: When we have device-specific interrupt routers,
794 * this code will go away from quirks.
795 */
796 static void quirk_via_ioapic(struct pci_dev *dev)
797 {
798 u8 tmp;
799
800 if (nr_ioapics < 1)
801 tmp = 0; /* nothing routed to external APIC */
802 else
803 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
804
805 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
806 tmp == 0 ? "Disa" : "Ena");
807
808 /* Offset 0x58: External APIC IRQ output control */
809 pci_write_config_byte(dev, 0x58, tmp);
810 }
811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
812 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
813
814 /*
815 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
816 * This leads to doubled level interrupt rates.
817 * Set this bit to get rid of cycle wastage.
818 * Otherwise uncritical.
819 */
820 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
821 {
822 u8 misc_control2;
823 #define BYPASS_APIC_DEASSERT 8
824
825 pci_read_config_byte(dev, 0x5B, &misc_control2);
826 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
827 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
828 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
829 }
830 }
831 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
832 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
833
834 /*
835 * The AMD io apic can hang the box when an apic irq is masked.
836 * We check all revs >= B0 (yet not in the pre production!) as the bug
837 * is currently marked NoFix
838 *
839 * We have multiple reports of hangs with this chipset that went away with
840 * noapic specified. For the moment we assume it's the erratum. We may be wrong
841 * of course. However the advice is demonstrably good even if so..
842 */
843 static void quirk_amd_ioapic(struct pci_dev *dev)
844 {
845 if (dev->revision >= 0x02) {
846 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
847 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
848 }
849 }
850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
851 #endif /* CONFIG_X86_IO_APIC */
852
853 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
854
855 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
856 {
857 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
858 if (dev->subsystem_device == 0xa118)
859 dev->sriov->link = dev->devfn;
860 }
861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
862 #endif
863
864 /*
865 * Some settings of MMRBC can lead to data corruption so block changes.
866 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
867 */
868 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
869 {
870 if (dev->subordinate && dev->revision <= 0x12) {
871 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
872 dev->revision);
873 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
874 }
875 }
876 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
877
878 /*
879 * FIXME: it is questionable that quirk_via_acpi
880 * is needed. It shows up as an ISA bridge, and does not
881 * support the PCI_INTERRUPT_LINE register at all. Therefore
882 * it seems like setting the pci_dev's 'irq' to the
883 * value of the ACPI SCI interrupt is only done for convenience.
884 * -jgarzik
885 */
886 static void quirk_via_acpi(struct pci_dev *d)
887 {
888 /*
889 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
890 */
891 u8 irq;
892 pci_read_config_byte(d, 0x42, &irq);
893 irq &= 0xf;
894 if (irq && (irq != 2))
895 d->irq = irq;
896 }
897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
899
900
901 /*
902 * VIA bridges which have VLink
903 */
904
905 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
906
907 static void quirk_via_bridge(struct pci_dev *dev)
908 {
909 /* See what bridge we have and find the device ranges */
910 switch (dev->device) {
911 case PCI_DEVICE_ID_VIA_82C686:
912 /* The VT82C686 is special, it attaches to PCI and can have
913 any device number. All its subdevices are functions of
914 that single device. */
915 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
916 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
917 break;
918 case PCI_DEVICE_ID_VIA_8237:
919 case PCI_DEVICE_ID_VIA_8237A:
920 via_vlink_dev_lo = 15;
921 break;
922 case PCI_DEVICE_ID_VIA_8235:
923 via_vlink_dev_lo = 16;
924 break;
925 case PCI_DEVICE_ID_VIA_8231:
926 case PCI_DEVICE_ID_VIA_8233_0:
927 case PCI_DEVICE_ID_VIA_8233A:
928 case PCI_DEVICE_ID_VIA_8233C_0:
929 via_vlink_dev_lo = 17;
930 break;
931 }
932 }
933 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
934 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
935 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
938 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
939 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
940 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
941
942 /**
943 * quirk_via_vlink - VIA VLink IRQ number update
944 * @dev: PCI device
945 *
946 * If the device we are dealing with is on a PIC IRQ we need to
947 * ensure that the IRQ line register which usually is not relevant
948 * for PCI cards, is actually written so that interrupts get sent
949 * to the right place.
950 * We only do this on systems where a VIA south bridge was detected,
951 * and only for VIA devices on the motherboard (see quirk_via_bridge
952 * above).
953 */
954
955 static void quirk_via_vlink(struct pci_dev *dev)
956 {
957 u8 irq, new_irq;
958
959 /* Check if we have VLink at all */
960 if (via_vlink_dev_lo == -1)
961 return;
962
963 new_irq = dev->irq;
964
965 /* Don't quirk interrupts outside the legacy IRQ range */
966 if (!new_irq || new_irq > 15)
967 return;
968
969 /* Internal device ? */
970 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
971 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
972 return;
973
974 /* This is an internal VLink device on a PIC interrupt. The BIOS
975 ought to have set this but may not have, so we redo it */
976
977 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
978 if (new_irq != irq) {
979 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
980 irq, new_irq);
981 udelay(15); /* unknown if delay really needed */
982 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
983 }
984 }
985 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
986
987 /*
988 * VIA VT82C598 has its device ID settable and many BIOSes
989 * set it to the ID of VT82C597 for backward compatibility.
990 * We need to switch it off to be able to recognize the real
991 * type of the chip.
992 */
993 static void quirk_vt82c598_id(struct pci_dev *dev)
994 {
995 pci_write_config_byte(dev, 0xfc, 0);
996 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
997 }
998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
999
1000 /*
1001 * CardBus controllers have a legacy base address that enables them
1002 * to respond as i82365 pcmcia controllers. We don't want them to
1003 * do this even if the Linux CardBus driver is not loaded, because
1004 * the Linux i82365 driver does not (and should not) handle CardBus.
1005 */
1006 static void quirk_cardbus_legacy(struct pci_dev *dev)
1007 {
1008 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1009 }
1010 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1011 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1012 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1013 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1014
1015 /*
1016 * Following the PCI ordering rules is optional on the AMD762. I'm not
1017 * sure what the designers were smoking but let's not inhale...
1018 *
1019 * To be fair to AMD, it follows the spec by default, its BIOS people
1020 * who turn it off!
1021 */
1022 static void quirk_amd_ordering(struct pci_dev *dev)
1023 {
1024 u32 pcic;
1025 pci_read_config_dword(dev, 0x4C, &pcic);
1026 if ((pcic & 6) != 6) {
1027 pcic |= 6;
1028 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1029 pci_write_config_dword(dev, 0x4C, pcic);
1030 pci_read_config_dword(dev, 0x84, &pcic);
1031 pcic |= (1 << 23); /* Required in this mode */
1032 pci_write_config_dword(dev, 0x84, pcic);
1033 }
1034 }
1035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1036 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1037
1038 /*
1039 * DreamWorks provided workaround for Dunord I-3000 problem
1040 *
1041 * This card decodes and responds to addresses not apparently
1042 * assigned to it. We force a larger allocation to ensure that
1043 * nothing gets put too close to it.
1044 */
1045 static void quirk_dunord(struct pci_dev *dev)
1046 {
1047 struct resource *r = &dev->resource[1];
1048
1049 r->flags |= IORESOURCE_UNSET;
1050 r->start = 0;
1051 r->end = 0xffffff;
1052 }
1053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1054
1055 /*
1056 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1057 * is subtractive decoding (transparent), and does indicate this
1058 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1059 * instead of 0x01.
1060 */
1061 static void quirk_transparent_bridge(struct pci_dev *dev)
1062 {
1063 dev->transparent = 1;
1064 }
1065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1067
1068 /*
1069 * Common misconfiguration of the MediaGX/Geode PCI master that will
1070 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1071 * datasheets found at http://www.national.com/analog for info on what
1072 * these bits do. <christer@weinigel.se>
1073 */
1074 static void quirk_mediagx_master(struct pci_dev *dev)
1075 {
1076 u8 reg;
1077
1078 pci_read_config_byte(dev, 0x41, &reg);
1079 if (reg & 2) {
1080 reg &= ~2;
1081 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1082 reg);
1083 pci_write_config_byte(dev, 0x41, reg);
1084 }
1085 }
1086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1087 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1088
1089 /*
1090 * Ensure C0 rev restreaming is off. This is normally done by
1091 * the BIOS but in the odd case it is not the results are corruption
1092 * hence the presence of a Linux check
1093 */
1094 static void quirk_disable_pxb(struct pci_dev *pdev)
1095 {
1096 u16 config;
1097
1098 if (pdev->revision != 0x04) /* Only C0 requires this */
1099 return;
1100 pci_read_config_word(pdev, 0x40, &config);
1101 if (config & (1<<6)) {
1102 config &= ~(1<<6);
1103 pci_write_config_word(pdev, 0x40, config);
1104 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1105 }
1106 }
1107 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1108 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1109
1110 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1111 {
1112 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1113 u8 tmp;
1114
1115 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1116 if (tmp == 0x01) {
1117 pci_read_config_byte(pdev, 0x40, &tmp);
1118 pci_write_config_byte(pdev, 0x40, tmp|1);
1119 pci_write_config_byte(pdev, 0x9, 1);
1120 pci_write_config_byte(pdev, 0xa, 6);
1121 pci_write_config_byte(pdev, 0x40, tmp);
1122
1123 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1124 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1125 }
1126 }
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1128 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1129 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1130 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1132 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1134 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1135
1136 /*
1137 * Serverworks CSB5 IDE does not fully support native mode
1138 */
1139 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1140 {
1141 u8 prog;
1142 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1143 if (prog & 5) {
1144 prog &= ~5;
1145 pdev->class &= ~5;
1146 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1147 /* PCI layer will sort out resources */
1148 }
1149 }
1150 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1151
1152 /*
1153 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1154 */
1155 static void quirk_ide_samemode(struct pci_dev *pdev)
1156 {
1157 u8 prog;
1158
1159 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1160
1161 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1162 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1163 prog &= ~5;
1164 pdev->class &= ~5;
1165 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1166 }
1167 }
1168 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1169
1170 /*
1171 * Some ATA devices break if put into D3
1172 */
1173
1174 static void quirk_no_ata_d3(struct pci_dev *pdev)
1175 {
1176 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1177 }
1178 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1179 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1180 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1181 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1182 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1183 /* ALi loses some register settings that we cannot then restore */
1184 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1185 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1186 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1187 occur when mode detecting */
1188 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1189 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1190
1191 /* This was originally an Alpha specific thing, but it really fits here.
1192 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1193 */
1194 static void quirk_eisa_bridge(struct pci_dev *dev)
1195 {
1196 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1197 }
1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1199
1200
1201 /*
1202 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1203 * is not activated. The myth is that Asus said that they do not want the
1204 * users to be irritated by just another PCI Device in the Win98 device
1205 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1206 * package 2.7.0 for details)
1207 *
1208 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1209 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1210 * becomes necessary to do this tweak in two steps -- the chosen trigger
1211 * is either the Host bridge (preferred) or on-board VGA controller.
1212 *
1213 * Note that we used to unhide the SMBus that way on Toshiba laptops
1214 * (Satellite A40 and Tecra M2) but then found that the thermal management
1215 * was done by SMM code, which could cause unsynchronized concurrent
1216 * accesses to the SMBus registers, with potentially bad effects. Thus you
1217 * should be very careful when adding new entries: if SMM is accessing the
1218 * Intel SMBus, this is a very good reason to leave it hidden.
1219 *
1220 * Likewise, many recent laptops use ACPI for thermal management. If the
1221 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1222 * natively, and keeping the SMBus hidden is the right thing to do. If you
1223 * are about to add an entry in the table below, please first disassemble
1224 * the DSDT and double-check that there is no code accessing the SMBus.
1225 */
1226 static int asus_hides_smbus;
1227
1228 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1229 {
1230 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1231 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1232 switch (dev->subsystem_device) {
1233 case 0x8025: /* P4B-LX */
1234 case 0x8070: /* P4B */
1235 case 0x8088: /* P4B533 */
1236 case 0x1626: /* L3C notebook */
1237 asus_hides_smbus = 1;
1238 }
1239 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1240 switch (dev->subsystem_device) {
1241 case 0x80b1: /* P4GE-V */
1242 case 0x80b2: /* P4PE */
1243 case 0x8093: /* P4B533-V */
1244 asus_hides_smbus = 1;
1245 }
1246 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1247 switch (dev->subsystem_device) {
1248 case 0x8030: /* P4T533 */
1249 asus_hides_smbus = 1;
1250 }
1251 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1252 switch (dev->subsystem_device) {
1253 case 0x8070: /* P4G8X Deluxe */
1254 asus_hides_smbus = 1;
1255 }
1256 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1257 switch (dev->subsystem_device) {
1258 case 0x80c9: /* PU-DLS */
1259 asus_hides_smbus = 1;
1260 }
1261 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1262 switch (dev->subsystem_device) {
1263 case 0x1751: /* M2N notebook */
1264 case 0x1821: /* M5N notebook */
1265 case 0x1897: /* A6L notebook */
1266 asus_hides_smbus = 1;
1267 }
1268 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1269 switch (dev->subsystem_device) {
1270 case 0x184b: /* W1N notebook */
1271 case 0x186a: /* M6Ne notebook */
1272 asus_hides_smbus = 1;
1273 }
1274 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1275 switch (dev->subsystem_device) {
1276 case 0x80f2: /* P4P800-X */
1277 asus_hides_smbus = 1;
1278 }
1279 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1280 switch (dev->subsystem_device) {
1281 case 0x1882: /* M6V notebook */
1282 case 0x1977: /* A6VA notebook */
1283 asus_hides_smbus = 1;
1284 }
1285 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1286 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1287 switch (dev->subsystem_device) {
1288 case 0x088C: /* HP Compaq nc8000 */
1289 case 0x0890: /* HP Compaq nc6000 */
1290 asus_hides_smbus = 1;
1291 }
1292 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1293 switch (dev->subsystem_device) {
1294 case 0x12bc: /* HP D330L */
1295 case 0x12bd: /* HP D530 */
1296 case 0x006a: /* HP Compaq nx9500 */
1297 asus_hides_smbus = 1;
1298 }
1299 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1300 switch (dev->subsystem_device) {
1301 case 0x12bf: /* HP xw4100 */
1302 asus_hides_smbus = 1;
1303 }
1304 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1305 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1306 switch (dev->subsystem_device) {
1307 case 0xC00C: /* Samsung P35 notebook */
1308 asus_hides_smbus = 1;
1309 }
1310 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1311 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1312 switch (dev->subsystem_device) {
1313 case 0x0058: /* Compaq Evo N620c */
1314 asus_hides_smbus = 1;
1315 }
1316 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1317 switch (dev->subsystem_device) {
1318 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1319 /* Motherboard doesn't have Host bridge
1320 * subvendor/subdevice IDs, therefore checking
1321 * its on-board VGA controller */
1322 asus_hides_smbus = 1;
1323 }
1324 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1325 switch (dev->subsystem_device) {
1326 case 0x00b8: /* Compaq Evo D510 CMT */
1327 case 0x00b9: /* Compaq Evo D510 SFF */
1328 case 0x00ba: /* Compaq Evo D510 USDT */
1329 /* Motherboard doesn't have Host bridge
1330 * subvendor/subdevice IDs and on-board VGA
1331 * controller is disabled if an AGP card is
1332 * inserted, therefore checking USB UHCI
1333 * Controller #1 */
1334 asus_hides_smbus = 1;
1335 }
1336 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1337 switch (dev->subsystem_device) {
1338 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1339 /* Motherboard doesn't have host bridge
1340 * subvendor/subdevice IDs, therefore checking
1341 * its on-board VGA controller */
1342 asus_hides_smbus = 1;
1343 }
1344 }
1345 }
1346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1352 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1356
1357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1358 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1360
1361 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1362 {
1363 u16 val;
1364
1365 if (likely(!asus_hides_smbus))
1366 return;
1367
1368 pci_read_config_word(dev, 0xF2, &val);
1369 if (val & 0x8) {
1370 pci_write_config_word(dev, 0xF2, val & (~0x8));
1371 pci_read_config_word(dev, 0xF2, &val);
1372 if (val & 0x8)
1373 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1374 val);
1375 else
1376 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1377 }
1378 }
1379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1382 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1386 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1387 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1388 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1389 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1390 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1391 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1392 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1393
1394 /* It appears we just have one such device. If not, we have a warning */
1395 static void __iomem *asus_rcba_base;
1396 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1397 {
1398 u32 rcba;
1399
1400 if (likely(!asus_hides_smbus))
1401 return;
1402 WARN_ON(asus_rcba_base);
1403
1404 pci_read_config_dword(dev, 0xF0, &rcba);
1405 /* use bits 31:14, 16 kB aligned */
1406 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1407 if (asus_rcba_base == NULL)
1408 return;
1409 }
1410
1411 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1412 {
1413 u32 val;
1414
1415 if (likely(!asus_hides_smbus || !asus_rcba_base))
1416 return;
1417 /* read the Function Disable register, dword mode only */
1418 val = readl(asus_rcba_base + 0x3418);
1419 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1420 }
1421
1422 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1423 {
1424 if (likely(!asus_hides_smbus || !asus_rcba_base))
1425 return;
1426 iounmap(asus_rcba_base);
1427 asus_rcba_base = NULL;
1428 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1429 }
1430
1431 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1432 {
1433 asus_hides_smbus_lpc_ich6_suspend(dev);
1434 asus_hides_smbus_lpc_ich6_resume_early(dev);
1435 asus_hides_smbus_lpc_ich6_resume(dev);
1436 }
1437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1438 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1439 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1440 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1441
1442 /*
1443 * SiS 96x south bridge: BIOS typically hides SMBus device...
1444 */
1445 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1446 {
1447 u8 val = 0;
1448 pci_read_config_byte(dev, 0x77, &val);
1449 if (val & 0x10) {
1450 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1451 pci_write_config_byte(dev, 0x77, val & ~0x10);
1452 }
1453 }
1454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1457 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1458 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1459 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1460 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1461 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1462
1463 /*
1464 * ... This is further complicated by the fact that some SiS96x south
1465 * bridges pretend to be 85C503/5513 instead. In that case see if we
1466 * spotted a compatible north bridge to make sure.
1467 * (pci_find_device doesn't work yet)
1468 *
1469 * We can also enable the sis96x bit in the discovery register..
1470 */
1471 #define SIS_DETECT_REGISTER 0x40
1472
1473 static void quirk_sis_503(struct pci_dev *dev)
1474 {
1475 u8 reg;
1476 u16 devid;
1477
1478 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1479 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1480 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1481 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1482 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1483 return;
1484 }
1485
1486 /*
1487 * Ok, it now shows up as a 96x.. run the 96x quirk by
1488 * hand in case it has already been processed.
1489 * (depends on link order, which is apparently not guaranteed)
1490 */
1491 dev->device = devid;
1492 quirk_sis_96x_smbus(dev);
1493 }
1494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1495 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1496
1497
1498 /*
1499 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1500 * and MC97 modem controller are disabled when a second PCI soundcard is
1501 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1502 * -- bjd
1503 */
1504 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1505 {
1506 u8 val;
1507 int asus_hides_ac97 = 0;
1508
1509 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1510 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1511 asus_hides_ac97 = 1;
1512 }
1513
1514 if (!asus_hides_ac97)
1515 return;
1516
1517 pci_read_config_byte(dev, 0x50, &val);
1518 if (val & 0xc0) {
1519 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1520 pci_read_config_byte(dev, 0x50, &val);
1521 if (val & 0xc0)
1522 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1523 val);
1524 else
1525 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1526 }
1527 }
1528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1529 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1530
1531 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1532
1533 /*
1534 * If we are using libata we can drive this chip properly but must
1535 * do this early on to make the additional device appear during
1536 * the PCI scanning.
1537 */
1538 static void quirk_jmicron_ata(struct pci_dev *pdev)
1539 {
1540 u32 conf1, conf5, class;
1541 u8 hdr;
1542
1543 /* Only poke fn 0 */
1544 if (PCI_FUNC(pdev->devfn))
1545 return;
1546
1547 pci_read_config_dword(pdev, 0x40, &conf1);
1548 pci_read_config_dword(pdev, 0x80, &conf5);
1549
1550 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1551 conf5 &= ~(1 << 24); /* Clear bit 24 */
1552
1553 switch (pdev->device) {
1554 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1555 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1556 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1557 /* The controller should be in single function ahci mode */
1558 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1559 break;
1560
1561 case PCI_DEVICE_ID_JMICRON_JMB365:
1562 case PCI_DEVICE_ID_JMICRON_JMB366:
1563 /* Redirect IDE second PATA port to the right spot */
1564 conf5 |= (1 << 24);
1565 /* Fall through */
1566 case PCI_DEVICE_ID_JMICRON_JMB361:
1567 case PCI_DEVICE_ID_JMICRON_JMB363:
1568 case PCI_DEVICE_ID_JMICRON_JMB369:
1569 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1570 /* Set the class codes correctly and then direct IDE 0 */
1571 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1572 break;
1573
1574 case PCI_DEVICE_ID_JMICRON_JMB368:
1575 /* The controller should be in single function IDE mode */
1576 conf1 |= 0x00C00000; /* Set 22, 23 */
1577 break;
1578 }
1579
1580 pci_write_config_dword(pdev, 0x40, conf1);
1581 pci_write_config_dword(pdev, 0x80, conf5);
1582
1583 /* Update pdev accordingly */
1584 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1585 pdev->hdr_type = hdr & 0x7f;
1586 pdev->multifunction = !!(hdr & 0x80);
1587
1588 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1589 pdev->class = class >> 8;
1590 }
1591 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1593 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1594 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1595 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1596 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1597 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1598 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1599 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1600 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1601 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1602 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1603 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1604 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1605 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1606 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1608 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1609
1610 #endif
1611
1612 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1613 {
1614 if (dev->multifunction) {
1615 device_disable_async_suspend(&dev->dev);
1616 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1617 }
1618 }
1619 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1620 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1623
1624 #ifdef CONFIG_X86_IO_APIC
1625 static void quirk_alder_ioapic(struct pci_dev *pdev)
1626 {
1627 int i;
1628
1629 if ((pdev->class >> 8) != 0xff00)
1630 return;
1631
1632 /* the first BAR is the location of the IO APIC...we must
1633 * not touch this (and it's already covered by the fixmap), so
1634 * forcibly insert it into the resource tree */
1635 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1636 insert_resource(&iomem_resource, &pdev->resource[0]);
1637
1638 /* The next five BARs all seem to be rubbish, so just clean
1639 * them out */
1640 for (i = 1; i < 6; i++)
1641 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1642 }
1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1644 #endif
1645
1646 static void quirk_pcie_mch(struct pci_dev *pdev)
1647 {
1648 pdev->no_msi = 1;
1649 }
1650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
1654
1655
1656 /*
1657 * It's possible for the MSI to get corrupted if shpc and acpi
1658 * are used together on certain PXH-based systems.
1659 */
1660 static void quirk_pcie_pxh(struct pci_dev *dev)
1661 {
1662 dev->no_msi = 1;
1663 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1664 }
1665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1666 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1667 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1668 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1669 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1670
1671 /*
1672 * Some Intel PCI Express chipsets have trouble with downstream
1673 * device power management.
1674 */
1675 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1676 {
1677 pci_pm_d3_delay = 120;
1678 dev->no_d1d2 = 1;
1679 }
1680
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1691 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1698 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1702
1703 static void quirk_radeon_pm(struct pci_dev *dev)
1704 {
1705 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1706 dev->subsystem_device == 0x00e2) {
1707 if (dev->d3_delay < 20) {
1708 dev->d3_delay = 20;
1709 dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n",
1710 dev->d3_delay);
1711 }
1712 }
1713 }
1714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1715
1716 #ifdef CONFIG_X86_IO_APIC
1717 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1718 {
1719 noioapicreroute = 1;
1720 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1721
1722 return 0;
1723 }
1724
1725 static struct dmi_system_id boot_interrupt_dmi_table[] = {
1726 /*
1727 * Systems to exclude from boot interrupt reroute quirks
1728 */
1729 {
1730 .callback = dmi_disable_ioapicreroute,
1731 .ident = "ASUSTek Computer INC. M2N-LR",
1732 .matches = {
1733 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1734 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1735 },
1736 },
1737 {}
1738 };
1739
1740 /*
1741 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1742 * remap the original interrupt in the linux kernel to the boot interrupt, so
1743 * that a PCI device's interrupt handler is installed on the boot interrupt
1744 * line instead.
1745 */
1746 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1747 {
1748 dmi_check_system(boot_interrupt_dmi_table);
1749 if (noioapicquirk || noioapicreroute)
1750 return;
1751
1752 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1753 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1754 dev->vendor, dev->device);
1755 }
1756 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1758 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1759 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1760 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1761 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1762 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1763 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1764 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1765 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1766 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1767 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1768 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1769 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1770 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1771 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1772
1773 /*
1774 * On some chipsets we can disable the generation of legacy INTx boot
1775 * interrupts.
1776 */
1777
1778 /*
1779 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1780 * 300641-004US, section 5.7.3.
1781 */
1782 #define INTEL_6300_IOAPIC_ABAR 0x40
1783 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1784
1785 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1786 {
1787 u16 pci_config_word;
1788
1789 if (noioapicquirk)
1790 return;
1791
1792 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1793 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1794 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1795
1796 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1797 dev->vendor, dev->device);
1798 }
1799 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1800 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1801
1802 /*
1803 * disable boot interrupts on HT-1000
1804 */
1805 #define BC_HT1000_FEATURE_REG 0x64
1806 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1807 #define BC_HT1000_MAP_IDX 0xC00
1808 #define BC_HT1000_MAP_DATA 0xC01
1809
1810 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1811 {
1812 u32 pci_config_dword;
1813 u8 irq;
1814
1815 if (noioapicquirk)
1816 return;
1817
1818 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1819 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1820 BC_HT1000_PIC_REGS_ENABLE);
1821
1822 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1823 outb(irq, BC_HT1000_MAP_IDX);
1824 outb(0x00, BC_HT1000_MAP_DATA);
1825 }
1826
1827 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1828
1829 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1830 dev->vendor, dev->device);
1831 }
1832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1833 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1834
1835 /*
1836 * disable boot interrupts on AMD and ATI chipsets
1837 */
1838 /*
1839 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1840 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1841 * (due to an erratum).
1842 */
1843 #define AMD_813X_MISC 0x40
1844 #define AMD_813X_NOIOAMODE (1<<0)
1845 #define AMD_813X_REV_B1 0x12
1846 #define AMD_813X_REV_B2 0x13
1847
1848 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1849 {
1850 u32 pci_config_dword;
1851
1852 if (noioapicquirk)
1853 return;
1854 if ((dev->revision == AMD_813X_REV_B1) ||
1855 (dev->revision == AMD_813X_REV_B2))
1856 return;
1857
1858 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1859 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1860 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1861
1862 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1863 dev->vendor, dev->device);
1864 }
1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1866 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1868 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1869
1870 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1871
1872 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1873 {
1874 u16 pci_config_word;
1875
1876 if (noioapicquirk)
1877 return;
1878
1879 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1880 if (!pci_config_word) {
1881 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1882 dev->vendor, dev->device);
1883 return;
1884 }
1885 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1886 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1887 dev->vendor, dev->device);
1888 }
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1890 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1891 #endif /* CONFIG_X86_IO_APIC */
1892
1893 /*
1894 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1895 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1896 * Re-allocate the region if needed...
1897 */
1898 static void quirk_tc86c001_ide(struct pci_dev *dev)
1899 {
1900 struct resource *r = &dev->resource[0];
1901
1902 if (r->start & 0x8) {
1903 r->flags |= IORESOURCE_UNSET;
1904 r->start = 0;
1905 r->end = 0xf;
1906 }
1907 }
1908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1909 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1910 quirk_tc86c001_ide);
1911
1912 /*
1913 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1914 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1915 * being read correctly if bit 7 of the base address is set.
1916 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1917 * Re-allocate the regions to a 256-byte boundary if necessary.
1918 */
1919 static void quirk_plx_pci9050(struct pci_dev *dev)
1920 {
1921 unsigned int bar;
1922
1923 /* Fixed in revision 2 (PCI 9052). */
1924 if (dev->revision >= 2)
1925 return;
1926 for (bar = 0; bar <= 1; bar++)
1927 if (pci_resource_len(dev, bar) == 0x80 &&
1928 (pci_resource_start(dev, bar) & 0x80)) {
1929 struct resource *r = &dev->resource[bar];
1930 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1931 bar);
1932 r->flags |= IORESOURCE_UNSET;
1933 r->start = 0;
1934 r->end = 0xff;
1935 }
1936 }
1937 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1938 quirk_plx_pci9050);
1939 /*
1940 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1941 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1942 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1943 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1944 *
1945 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1946 * driver.
1947 */
1948 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1949 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1950
1951 static void quirk_netmos(struct pci_dev *dev)
1952 {
1953 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1954 unsigned int num_serial = dev->subsystem_device & 0xf;
1955
1956 /*
1957 * These Netmos parts are multiport serial devices with optional
1958 * parallel ports. Even when parallel ports are present, they
1959 * are identified as class SERIAL, which means the serial driver
1960 * will claim them. To prevent this, mark them as class OTHER.
1961 * These combo devices should be claimed by parport_serial.
1962 *
1963 * The subdevice ID is of the form 0x00PS, where <P> is the number
1964 * of parallel ports and <S> is the number of serial ports.
1965 */
1966 switch (dev->device) {
1967 case PCI_DEVICE_ID_NETMOS_9835:
1968 /* Well, this rule doesn't hold for the following 9835 device */
1969 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1970 dev->subsystem_device == 0x0299)
1971 return;
1972 case PCI_DEVICE_ID_NETMOS_9735:
1973 case PCI_DEVICE_ID_NETMOS_9745:
1974 case PCI_DEVICE_ID_NETMOS_9845:
1975 case PCI_DEVICE_ID_NETMOS_9855:
1976 if (num_parallel) {
1977 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1978 dev->device, num_parallel, num_serial);
1979 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1980 (dev->class & 0xff);
1981 }
1982 }
1983 }
1984 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1985 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1986
1987 /*
1988 * Quirk non-zero PCI functions to route VPD access through function 0 for
1989 * devices that share VPD resources between functions. The functions are
1990 * expected to be identical devices.
1991 */
1992 static void quirk_f0_vpd_link(struct pci_dev *dev)
1993 {
1994 struct pci_dev *f0;
1995
1996 if (!PCI_FUNC(dev->devfn))
1997 return;
1998
1999 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
2000 if (!f0)
2001 return;
2002
2003 if (f0->vpd && dev->class == f0->class &&
2004 dev->vendor == f0->vendor && dev->device == f0->device)
2005 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
2006
2007 pci_dev_put(f0);
2008 }
2009 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2010 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
2011
2012 static void quirk_e100_interrupt(struct pci_dev *dev)
2013 {
2014 u16 command, pmcsr;
2015 u8 __iomem *csr;
2016 u8 cmd_hi;
2017
2018 switch (dev->device) {
2019 /* PCI IDs taken from drivers/net/e100.c */
2020 case 0x1029:
2021 case 0x1030 ... 0x1034:
2022 case 0x1038 ... 0x103E:
2023 case 0x1050 ... 0x1057:
2024 case 0x1059:
2025 case 0x1064 ... 0x106B:
2026 case 0x1091 ... 0x1095:
2027 case 0x1209:
2028 case 0x1229:
2029 case 0x2449:
2030 case 0x2459:
2031 case 0x245D:
2032 case 0x27DC:
2033 break;
2034 default:
2035 return;
2036 }
2037
2038 /*
2039 * Some firmware hands off the e100 with interrupts enabled,
2040 * which can cause a flood of interrupts if packets are
2041 * received before the driver attaches to the device. So
2042 * disable all e100 interrupts here. The driver will
2043 * re-enable them when it's ready.
2044 */
2045 pci_read_config_word(dev, PCI_COMMAND, &command);
2046
2047 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2048 return;
2049
2050 /*
2051 * Check that the device is in the D0 power state. If it's not,
2052 * there is no point to look any further.
2053 */
2054 if (dev->pm_cap) {
2055 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2056 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2057 return;
2058 }
2059
2060 /* Convert from PCI bus to resource space. */
2061 csr = ioremap(pci_resource_start(dev, 0), 8);
2062 if (!csr) {
2063 dev_warn(&dev->dev, "Can't map e100 registers\n");
2064 return;
2065 }
2066
2067 cmd_hi = readb(csr + 3);
2068 if (cmd_hi == 0) {
2069 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2070 writeb(1, csr + 3);
2071 }
2072
2073 iounmap(csr);
2074 }
2075 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2076 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2077
2078 /*
2079 * The 82575 and 82598 may experience data corruption issues when transitioning
2080 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2081 */
2082 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2083 {
2084 dev_info(&dev->dev, "Disabling L0s\n");
2085 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2086 }
2087 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2089 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2095 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2097 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2101
2102 static void fixup_rev1_53c810(struct pci_dev *dev)
2103 {
2104 u32 class = dev->class;
2105
2106 /*
2107 * rev 1 ncr53c810 chips don't set the class at all which means
2108 * they don't get their resources remapped. Fix that here.
2109 */
2110 if (class)
2111 return;
2112
2113 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2114 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2115 class, dev->class);
2116 }
2117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2118
2119 /* Enable 1k I/O space granularity on the Intel P64H2 */
2120 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2121 {
2122 u16 en1k;
2123
2124 pci_read_config_word(dev, 0x40, &en1k);
2125
2126 if (en1k & 0x200) {
2127 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2128 dev->io_window_1k = 1;
2129 }
2130 }
2131 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2132
2133 /* Under some circumstances, AER is not linked with extended capabilities.
2134 * Force it to be linked by setting the corresponding control bit in the
2135 * config space.
2136 */
2137 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2138 {
2139 uint8_t b;
2140 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2141 if (!(b & 0x20)) {
2142 pci_write_config_byte(dev, 0xf41, b | 0x20);
2143 dev_info(&dev->dev, "Linking AER extended capability\n");
2144 }
2145 }
2146 }
2147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2148 quirk_nvidia_ck804_pcie_aer_ext_cap);
2149 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2150 quirk_nvidia_ck804_pcie_aer_ext_cap);
2151
2152 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2153 {
2154 /*
2155 * Disable PCI Bus Parking and PCI Master read caching on CX700
2156 * which causes unspecified timing errors with a VT6212L on the PCI
2157 * bus leading to USB2.0 packet loss.
2158 *
2159 * This quirk is only enabled if a second (on the external PCI bus)
2160 * VT6212L is found -- the CX700 core itself also contains a USB
2161 * host controller with the same PCI ID as the VT6212L.
2162 */
2163
2164 /* Count VT6212L instances */
2165 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2166 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2167 uint8_t b;
2168
2169 /* p should contain the first (internal) VT6212L -- see if we have
2170 an external one by searching again */
2171 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2172 if (!p)
2173 return;
2174 pci_dev_put(p);
2175
2176 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2177 if (b & 0x40) {
2178 /* Turn off PCI Bus Parking */
2179 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2180
2181 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2182 }
2183 }
2184
2185 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2186 if (b != 0) {
2187 /* Turn off PCI Master read caching */
2188 pci_write_config_byte(dev, 0x72, 0x0);
2189
2190 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2191 pci_write_config_byte(dev, 0x75, 0x1);
2192
2193 /* Disable "Read FIFO Timer" */
2194 pci_write_config_byte(dev, 0x77, 0x0);
2195
2196 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2197 }
2198 }
2199 }
2200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2201
2202 /*
2203 * If a device follows the VPD format spec, the PCI core will not read or
2204 * write past the VPD End Tag. But some vendors do not follow the VPD
2205 * format spec, so we can't tell how much data is safe to access. Devices
2206 * may behave unpredictably if we access too much. Blacklist these devices
2207 * so we don't touch VPD at all.
2208 */
2209 static void quirk_blacklist_vpd(struct pci_dev *dev)
2210 {
2211 if (dev->vpd) {
2212 dev->vpd->len = 0;
2213 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2214 }
2215 }
2216
2217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2229 quirk_blacklist_vpd);
2230 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2231
2232 /*
2233 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2234 * VPD end tag will hang the device. This problem was initially
2235 * observed when a vpd entry was created in sysfs
2236 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2237 * will dump 32k of data. Reading a full 32k will cause an access
2238 * beyond the VPD end tag causing the device to hang. Once the device
2239 * is hung, the bnx2 driver will not be able to reset the device.
2240 * We believe that it is legal to read beyond the end tag and
2241 * therefore the solution is to limit the read/write length.
2242 */
2243 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2244 {
2245 /*
2246 * Only disable the VPD capability for 5706, 5706S, 5708,
2247 * 5708S and 5709 rev. A
2248 */
2249 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2250 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2251 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2252 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2253 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2254 (dev->revision & 0xf0) == 0x0)) {
2255 if (dev->vpd)
2256 dev->vpd->len = 0x80;
2257 }
2258 }
2259
2260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2261 PCI_DEVICE_ID_NX2_5706,
2262 quirk_brcm_570x_limit_vpd);
2263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2264 PCI_DEVICE_ID_NX2_5706S,
2265 quirk_brcm_570x_limit_vpd);
2266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2267 PCI_DEVICE_ID_NX2_5708,
2268 quirk_brcm_570x_limit_vpd);
2269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2270 PCI_DEVICE_ID_NX2_5708S,
2271 quirk_brcm_570x_limit_vpd);
2272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2273 PCI_DEVICE_ID_NX2_5709,
2274 quirk_brcm_570x_limit_vpd);
2275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2276 PCI_DEVICE_ID_NX2_5709S,
2277 quirk_brcm_570x_limit_vpd);
2278
2279 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2280 {
2281 u32 rev;
2282
2283 pci_read_config_dword(dev, 0xf4, &rev);
2284
2285 /* Only CAP the MRRS if the device is a 5719 A0 */
2286 if (rev == 0x05719000) {
2287 int readrq = pcie_get_readrq(dev);
2288 if (readrq > 2048)
2289 pcie_set_readrq(dev, 2048);
2290 }
2291 }
2292
2293 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2294 PCI_DEVICE_ID_TIGON3_5719,
2295 quirk_brcm_5719_limit_mrrs);
2296
2297 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2298 static void quirk_paxc_bridge(struct pci_dev *pdev)
2299 {
2300 /* The PCI config space is shared with the PAXC root port and the first
2301 * Ethernet device. So, we need to workaround this by telling the PCI
2302 * code that the bridge is not an Ethernet device.
2303 */
2304 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2305 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2306
2307 /* MPSS is not being set properly (as it is currently 0). This is
2308 * because that area of the PCI config space is hard coded to zero, and
2309 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2310 * so that the MPS can be set to the real max value.
2311 */
2312 pdev->pcie_mpss = 2;
2313 }
2314 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2315 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2316 #endif
2317
2318 /* Originally in EDAC sources for i82875P:
2319 * Intel tells BIOS developers to hide device 6 which
2320 * configures the overflow device access containing
2321 * the DRBs - this is where we expose device 6.
2322 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2323 */
2324 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2325 {
2326 u8 reg;
2327
2328 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2329 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2330 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2331 }
2332 }
2333
2334 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2335 quirk_unhide_mch_dev6);
2336 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2337 quirk_unhide_mch_dev6);
2338
2339 #ifdef CONFIG_TILEPRO
2340 /*
2341 * The Tilera TILEmpower tilepro platform needs to set the link speed
2342 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2343 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2344 * capability register of the PEX8624 PCIe switch. The switch
2345 * supports link speed auto negotiation, but falsely sets
2346 * the link speed to 5GT/s.
2347 */
2348 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2349 {
2350 if (tile_plx_gen1) {
2351 pci_write_config_dword(dev, 0x98, 0x1);
2352 mdelay(50);
2353 }
2354 }
2355 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2356 #endif /* CONFIG_TILEPRO */
2357
2358 #ifdef CONFIG_PCI_MSI
2359 /* Some chipsets do not support MSI. We cannot easily rely on setting
2360 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2361 * some other buses controlled by the chipset even if Linux is not
2362 * aware of it. Instead of setting the flag on all buses in the
2363 * machine, simply disable MSI globally.
2364 */
2365 static void quirk_disable_all_msi(struct pci_dev *dev)
2366 {
2367 pci_no_msi();
2368 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2369 }
2370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2378
2379 /* Disable MSI on chipsets that are known to not support it */
2380 static void quirk_disable_msi(struct pci_dev *dev)
2381 {
2382 if (dev->subordinate) {
2383 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2384 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2385 }
2386 }
2387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2390
2391 /*
2392 * The APC bridge device in AMD 780 family northbridges has some random
2393 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2394 * we use the possible vendor/device IDs of the host bridge for the
2395 * declared quirk, and search for the APC bridge by slot number.
2396 */
2397 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2398 {
2399 struct pci_dev *apc_bridge;
2400
2401 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2402 if (apc_bridge) {
2403 if (apc_bridge->device == 0x9602)
2404 quirk_disable_msi(apc_bridge);
2405 pci_dev_put(apc_bridge);
2406 }
2407 }
2408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2410
2411 /* Go through the list of Hypertransport capabilities and
2412 * return 1 if a HT MSI capability is found and enabled */
2413 static int msi_ht_cap_enabled(struct pci_dev *dev)
2414 {
2415 int pos, ttl = PCI_FIND_CAP_TTL;
2416
2417 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2418 while (pos && ttl--) {
2419 u8 flags;
2420
2421 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2422 &flags) == 0) {
2423 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2424 flags & HT_MSI_FLAGS_ENABLE ?
2425 "enabled" : "disabled");
2426 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2427 }
2428
2429 pos = pci_find_next_ht_capability(dev, pos,
2430 HT_CAPTYPE_MSI_MAPPING);
2431 }
2432 return 0;
2433 }
2434
2435 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2436 static void quirk_msi_ht_cap(struct pci_dev *dev)
2437 {
2438 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2439 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2440 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2441 }
2442 }
2443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2444 quirk_msi_ht_cap);
2445
2446 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2447 * MSI are supported if the MSI capability set in any of these mappings.
2448 */
2449 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2450 {
2451 struct pci_dev *pdev;
2452
2453 if (!dev->subordinate)
2454 return;
2455
2456 /* check HT MSI cap on this chipset and the root one.
2457 * a single one having MSI is enough to be sure that MSI are supported.
2458 */
2459 pdev = pci_get_slot(dev->bus, 0);
2460 if (!pdev)
2461 return;
2462 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2463 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2464 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2465 }
2466 pci_dev_put(pdev);
2467 }
2468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2469 quirk_nvidia_ck804_msi_ht_cap);
2470
2471 /* Force enable MSI mapping capability on HT bridges */
2472 static void ht_enable_msi_mapping(struct pci_dev *dev)
2473 {
2474 int pos, ttl = PCI_FIND_CAP_TTL;
2475
2476 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2477 while (pos && ttl--) {
2478 u8 flags;
2479
2480 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2481 &flags) == 0) {
2482 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2483
2484 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2485 flags | HT_MSI_FLAGS_ENABLE);
2486 }
2487 pos = pci_find_next_ht_capability(dev, pos,
2488 HT_CAPTYPE_MSI_MAPPING);
2489 }
2490 }
2491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2492 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2493 ht_enable_msi_mapping);
2494
2495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2496 ht_enable_msi_mapping);
2497
2498 /* The P5N32-SLI motherboards from Asus have a problem with msi
2499 * for the MCP55 NIC. It is not yet determined whether the msi problem
2500 * also affects other devices. As for now, turn off msi for this device.
2501 */
2502 static void nvenet_msi_disable(struct pci_dev *dev)
2503 {
2504 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2505
2506 if (board_name &&
2507 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2508 strstr(board_name, "P5N32-E SLI"))) {
2509 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2510 dev->no_msi = 1;
2511 }
2512 }
2513 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2514 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2515 nvenet_msi_disable);
2516
2517 /*
2518 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2519 * config register. This register controls the routing of legacy
2520 * interrupts from devices that route through the MCP55. If this register
2521 * is misprogrammed, interrupts are only sent to the BSP, unlike
2522 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2523 * having this register set properly prevents kdump from booting up
2524 * properly, so let's make sure that we have it set correctly.
2525 * Note that this is an undocumented register.
2526 */
2527 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2528 {
2529 u32 cfg;
2530
2531 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2532 return;
2533
2534 pci_read_config_dword(dev, 0x74, &cfg);
2535
2536 if (cfg & ((1 << 2) | (1 << 15))) {
2537 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2538 cfg &= ~((1 << 2) | (1 << 15));
2539 pci_write_config_dword(dev, 0x74, cfg);
2540 }
2541 }
2542
2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2544 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2545 nvbridge_check_legacy_irq_routing);
2546
2547 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2548 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2549 nvbridge_check_legacy_irq_routing);
2550
2551 static int ht_check_msi_mapping(struct pci_dev *dev)
2552 {
2553 int pos, ttl = PCI_FIND_CAP_TTL;
2554 int found = 0;
2555
2556 /* check if there is HT MSI cap or enabled on this device */
2557 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2558 while (pos && ttl--) {
2559 u8 flags;
2560
2561 if (found < 1)
2562 found = 1;
2563 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2564 &flags) == 0) {
2565 if (flags & HT_MSI_FLAGS_ENABLE) {
2566 if (found < 2) {
2567 found = 2;
2568 break;
2569 }
2570 }
2571 }
2572 pos = pci_find_next_ht_capability(dev, pos,
2573 HT_CAPTYPE_MSI_MAPPING);
2574 }
2575
2576 return found;
2577 }
2578
2579 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2580 {
2581 struct pci_dev *dev;
2582 int pos;
2583 int i, dev_no;
2584 int found = 0;
2585
2586 dev_no = host_bridge->devfn >> 3;
2587 for (i = dev_no + 1; i < 0x20; i++) {
2588 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2589 if (!dev)
2590 continue;
2591
2592 /* found next host bridge ?*/
2593 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2594 if (pos != 0) {
2595 pci_dev_put(dev);
2596 break;
2597 }
2598
2599 if (ht_check_msi_mapping(dev)) {
2600 found = 1;
2601 pci_dev_put(dev);
2602 break;
2603 }
2604 pci_dev_put(dev);
2605 }
2606
2607 return found;
2608 }
2609
2610 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2611 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2612
2613 static int is_end_of_ht_chain(struct pci_dev *dev)
2614 {
2615 int pos, ctrl_off;
2616 int end = 0;
2617 u16 flags, ctrl;
2618
2619 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2620
2621 if (!pos)
2622 goto out;
2623
2624 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2625
2626 ctrl_off = ((flags >> 10) & 1) ?
2627 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2628 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2629
2630 if (ctrl & (1 << 6))
2631 end = 1;
2632
2633 out:
2634 return end;
2635 }
2636
2637 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2638 {
2639 struct pci_dev *host_bridge;
2640 int pos;
2641 int i, dev_no;
2642 int found = 0;
2643
2644 dev_no = dev->devfn >> 3;
2645 for (i = dev_no; i >= 0; i--) {
2646 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2647 if (!host_bridge)
2648 continue;
2649
2650 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2651 if (pos != 0) {
2652 found = 1;
2653 break;
2654 }
2655 pci_dev_put(host_bridge);
2656 }
2657
2658 if (!found)
2659 return;
2660
2661 /* don't enable end_device/host_bridge with leaf directly here */
2662 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2663 host_bridge_with_leaf(host_bridge))
2664 goto out;
2665
2666 /* root did that ! */
2667 if (msi_ht_cap_enabled(host_bridge))
2668 goto out;
2669
2670 ht_enable_msi_mapping(dev);
2671
2672 out:
2673 pci_dev_put(host_bridge);
2674 }
2675
2676 static void ht_disable_msi_mapping(struct pci_dev *dev)
2677 {
2678 int pos, ttl = PCI_FIND_CAP_TTL;
2679
2680 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2681 while (pos && ttl--) {
2682 u8 flags;
2683
2684 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2685 &flags) == 0) {
2686 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2687
2688 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2689 flags & ~HT_MSI_FLAGS_ENABLE);
2690 }
2691 pos = pci_find_next_ht_capability(dev, pos,
2692 HT_CAPTYPE_MSI_MAPPING);
2693 }
2694 }
2695
2696 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2697 {
2698 struct pci_dev *host_bridge;
2699 int pos;
2700 int found;
2701
2702 if (!pci_msi_enabled())
2703 return;
2704
2705 /* check if there is HT MSI cap or enabled on this device */
2706 found = ht_check_msi_mapping(dev);
2707
2708 /* no HT MSI CAP */
2709 if (found == 0)
2710 return;
2711
2712 /*
2713 * HT MSI mapping should be disabled on devices that are below
2714 * a non-Hypertransport host bridge. Locate the host bridge...
2715 */
2716 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2717 if (host_bridge == NULL) {
2718 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2719 return;
2720 }
2721
2722 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2723 if (pos != 0) {
2724 /* Host bridge is to HT */
2725 if (found == 1) {
2726 /* it is not enabled, try to enable it */
2727 if (all)
2728 ht_enable_msi_mapping(dev);
2729 else
2730 nv_ht_enable_msi_mapping(dev);
2731 }
2732 goto out;
2733 }
2734
2735 /* HT MSI is not enabled */
2736 if (found == 1)
2737 goto out;
2738
2739 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2740 ht_disable_msi_mapping(dev);
2741
2742 out:
2743 pci_dev_put(host_bridge);
2744 }
2745
2746 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2747 {
2748 return __nv_msi_ht_cap_quirk(dev, 1);
2749 }
2750
2751 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2752 {
2753 return __nv_msi_ht_cap_quirk(dev, 0);
2754 }
2755
2756 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2757 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2758
2759 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2760 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2761
2762 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2763 {
2764 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2765 }
2766 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2767 {
2768 struct pci_dev *p;
2769
2770 /* SB700 MSI issue will be fixed at HW level from revision A21,
2771 * we need check PCI REVISION ID of SMBus controller to get SB700
2772 * revision.
2773 */
2774 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2775 NULL);
2776 if (!p)
2777 return;
2778
2779 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2780 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2781 pci_dev_put(p);
2782 }
2783 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2784 {
2785 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2786 if (dev->revision < 0x18) {
2787 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2788 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2789 }
2790 }
2791 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2792 PCI_DEVICE_ID_TIGON3_5780,
2793 quirk_msi_intx_disable_bug);
2794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2795 PCI_DEVICE_ID_TIGON3_5780S,
2796 quirk_msi_intx_disable_bug);
2797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2798 PCI_DEVICE_ID_TIGON3_5714,
2799 quirk_msi_intx_disable_bug);
2800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2801 PCI_DEVICE_ID_TIGON3_5714S,
2802 quirk_msi_intx_disable_bug);
2803 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2804 PCI_DEVICE_ID_TIGON3_5715,
2805 quirk_msi_intx_disable_bug);
2806 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2807 PCI_DEVICE_ID_TIGON3_5715S,
2808 quirk_msi_intx_disable_bug);
2809
2810 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2811 quirk_msi_intx_disable_ati_bug);
2812 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2813 quirk_msi_intx_disable_ati_bug);
2814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2815 quirk_msi_intx_disable_ati_bug);
2816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2817 quirk_msi_intx_disable_ati_bug);
2818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2819 quirk_msi_intx_disable_ati_bug);
2820
2821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2822 quirk_msi_intx_disable_bug);
2823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2824 quirk_msi_intx_disable_bug);
2825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2826 quirk_msi_intx_disable_bug);
2827
2828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2829 quirk_msi_intx_disable_bug);
2830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2831 quirk_msi_intx_disable_bug);
2832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2833 quirk_msi_intx_disable_bug);
2834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2835 quirk_msi_intx_disable_bug);
2836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2837 quirk_msi_intx_disable_bug);
2838 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2839 quirk_msi_intx_disable_bug);
2840 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2841 quirk_msi_intx_disable_qca_bug);
2842 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2843 quirk_msi_intx_disable_qca_bug);
2844 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2845 quirk_msi_intx_disable_qca_bug);
2846 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2847 quirk_msi_intx_disable_qca_bug);
2848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2849 quirk_msi_intx_disable_qca_bug);
2850 #endif /* CONFIG_PCI_MSI */
2851
2852 /* Allow manual resource allocation for PCI hotplug bridges
2853 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2854 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2855 * kernel fails to allocate resources when hotplug device is
2856 * inserted and PCI bus is rescanned.
2857 */
2858 static void quirk_hotplug_bridge(struct pci_dev *dev)
2859 {
2860 dev->is_hotplug_bridge = 1;
2861 }
2862
2863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2864
2865 /*
2866 * This is a quirk for the Ricoh MMC controller found as a part of
2867 * some mulifunction chips.
2868
2869 * This is very similar and based on the ricoh_mmc driver written by
2870 * Philip Langdale. Thank you for these magic sequences.
2871 *
2872 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2873 * and one or both of cardbus or firewire.
2874 *
2875 * It happens that they implement SD and MMC
2876 * support as separate controllers (and PCI functions). The linux SDHCI
2877 * driver supports MMC cards but the chip detects MMC cards in hardware
2878 * and directs them to the MMC controller - so the SDHCI driver never sees
2879 * them.
2880 *
2881 * To get around this, we must disable the useless MMC controller.
2882 * At that point, the SDHCI controller will start seeing them
2883 * It seems to be the case that the relevant PCI registers to deactivate the
2884 * MMC controller live on PCI function 0, which might be the cardbus controller
2885 * or the firewire controller, depending on the particular chip in question
2886 *
2887 * This has to be done early, because as soon as we disable the MMC controller
2888 * other pci functions shift up one level, e.g. function #2 becomes function
2889 * #1, and this will confuse the pci core.
2890 */
2891
2892 #ifdef CONFIG_MMC_RICOH_MMC
2893 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2894 {
2895 /* disable via cardbus interface */
2896 u8 write_enable;
2897 u8 write_target;
2898 u8 disable;
2899
2900 /* disable must be done via function #0 */
2901 if (PCI_FUNC(dev->devfn))
2902 return;
2903
2904 pci_read_config_byte(dev, 0xB7, &disable);
2905 if (disable & 0x02)
2906 return;
2907
2908 pci_read_config_byte(dev, 0x8E, &write_enable);
2909 pci_write_config_byte(dev, 0x8E, 0xAA);
2910 pci_read_config_byte(dev, 0x8D, &write_target);
2911 pci_write_config_byte(dev, 0x8D, 0xB7);
2912 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2913 pci_write_config_byte(dev, 0x8E, write_enable);
2914 pci_write_config_byte(dev, 0x8D, write_target);
2915
2916 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2917 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2918 }
2919 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2920 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2921
2922 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2923 {
2924 /* disable via firewire interface */
2925 u8 write_enable;
2926 u8 disable;
2927
2928 /* disable must be done via function #0 */
2929 if (PCI_FUNC(dev->devfn))
2930 return;
2931 /*
2932 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2933 * certain types of SD/MMC cards. Lowering the SD base
2934 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2935 *
2936 * 0x150 - SD2.0 mode enable for changing base clock
2937 * frequency to 50Mhz
2938 * 0xe1 - Base clock frequency
2939 * 0x32 - 50Mhz new clock frequency
2940 * 0xf9 - Key register for 0x150
2941 * 0xfc - key register for 0xe1
2942 */
2943 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2944 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2945 pci_write_config_byte(dev, 0xf9, 0xfc);
2946 pci_write_config_byte(dev, 0x150, 0x10);
2947 pci_write_config_byte(dev, 0xf9, 0x00);
2948 pci_write_config_byte(dev, 0xfc, 0x01);
2949 pci_write_config_byte(dev, 0xe1, 0x32);
2950 pci_write_config_byte(dev, 0xfc, 0x00);
2951
2952 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2953 }
2954
2955 pci_read_config_byte(dev, 0xCB, &disable);
2956
2957 if (disable & 0x02)
2958 return;
2959
2960 pci_read_config_byte(dev, 0xCA, &write_enable);
2961 pci_write_config_byte(dev, 0xCA, 0x57);
2962 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2963 pci_write_config_byte(dev, 0xCA, write_enable);
2964
2965 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2966 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2967
2968 }
2969 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2970 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2971 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2972 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2973 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2974 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2975 #endif /*CONFIG_MMC_RICOH_MMC*/
2976
2977 #ifdef CONFIG_DMAR_TABLE
2978 #define VTUNCERRMSK_REG 0x1ac
2979 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2980 /*
2981 * This is a quirk for masking vt-d spec defined errors to platform error
2982 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2983 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2984 * on the RAS config settings of the platform) when a vt-d fault happens.
2985 * The resulting SMI caused the system to hang.
2986 *
2987 * VT-d spec related errors are already handled by the VT-d OS code, so no
2988 * need to report the same error through other channels.
2989 */
2990 static void vtd_mask_spec_errors(struct pci_dev *dev)
2991 {
2992 u32 word;
2993
2994 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2995 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2996 }
2997 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2998 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2999 #endif
3000
3001 static void fixup_ti816x_class(struct pci_dev *dev)
3002 {
3003 u32 class = dev->class;
3004
3005 /* TI 816x devices do not have class code set when in PCIe boot mode */
3006 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3007 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
3008 class, dev->class);
3009 }
3010 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3011 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3012
3013 /* Some PCIe devices do not work reliably with the claimed maximum
3014 * payload size supported.
3015 */
3016 static void fixup_mpss_256(struct pci_dev *dev)
3017 {
3018 dev->pcie_mpss = 1; /* 256 bytes */
3019 }
3020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3021 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3023 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3025 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3026
3027 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
3028 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3029 * Since there is no way of knowing what the PCIE MPS on each fabric will be
3030 * until all of the devices are discovered and buses walked, read completion
3031 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3032 * it is possible to hotplug a device with MPS of 256B.
3033 */
3034 static void quirk_intel_mc_errata(struct pci_dev *dev)
3035 {
3036 int err;
3037 u16 rcc;
3038
3039 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3040 pcie_bus_config == PCIE_BUS_DEFAULT)
3041 return;
3042
3043 /* Intel errata specifies bits to change but does not say what they are.
3044 * Keeping them magical until such time as the registers and values can
3045 * be explained.
3046 */
3047 err = pci_read_config_word(dev, 0x48, &rcc);
3048 if (err) {
3049 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3050 return;
3051 }
3052
3053 if (!(rcc & (1 << 10)))
3054 return;
3055
3056 rcc &= ~(1 << 10);
3057
3058 err = pci_write_config_word(dev, 0x48, rcc);
3059 if (err) {
3060 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3061 return;
3062 }
3063
3064 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3065 }
3066 /* Intel 5000 series memory controllers and ports 2-7 */
3067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3080 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3081 /* Intel 5100 series memory controllers and ports 2-7 */
3082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3090 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3091 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3093
3094
3095 /*
3096 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3097 * work around this, query the size it should be configured to by the device and
3098 * modify the resource end to correspond to this new size.
3099 */
3100 static void quirk_intel_ntb(struct pci_dev *dev)
3101 {
3102 int rc;
3103 u8 val;
3104
3105 rc = pci_read_config_byte(dev, 0x00D0, &val);
3106 if (rc)
3107 return;
3108
3109 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3110
3111 rc = pci_read_config_byte(dev, 0x00D1, &val);
3112 if (rc)
3113 return;
3114
3115 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3116 }
3117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3119
3120 static ktime_t fixup_debug_start(struct pci_dev *dev,
3121 void (*fn)(struct pci_dev *dev))
3122 {
3123 ktime_t calltime = 0;
3124
3125 dev_dbg(&dev->dev, "calling %pF\n", fn);
3126 if (initcall_debug) {
3127 pr_debug("calling %pF @ %i for %s\n",
3128 fn, task_pid_nr(current), dev_name(&dev->dev));
3129 calltime = ktime_get();
3130 }
3131
3132 return calltime;
3133 }
3134
3135 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3136 void (*fn)(struct pci_dev *dev))
3137 {
3138 ktime_t delta, rettime;
3139 unsigned long long duration;
3140
3141 if (initcall_debug) {
3142 rettime = ktime_get();
3143 delta = ktime_sub(rettime, calltime);
3144 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3145 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3146 fn, duration, dev_name(&dev->dev));
3147 }
3148 }
3149
3150 /*
3151 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3152 * even though no one is handling them (f.e. i915 driver is never loaded).
3153 * Additionally the interrupt destination is not set up properly
3154 * and the interrupt ends up -somewhere-.
3155 *
3156 * These spurious interrupts are "sticky" and the kernel disables
3157 * the (shared) interrupt line after 100.000+ generated interrupts.
3158 *
3159 * Fix it by disabling the still enabled interrupts.
3160 * This resolves crashes often seen on monitor unplug.
3161 */
3162 #define I915_DEIER_REG 0x4400c
3163 static void disable_igfx_irq(struct pci_dev *dev)
3164 {
3165 void __iomem *regs = pci_iomap(dev, 0, 0);
3166 if (regs == NULL) {
3167 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3168 return;
3169 }
3170
3171 /* Check if any interrupt line is still enabled */
3172 if (readl(regs + I915_DEIER_REG) != 0) {
3173 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3174
3175 writel(0, regs + I915_DEIER_REG);
3176 }
3177
3178 pci_iounmap(dev, regs);
3179 }
3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3183
3184 /*
3185 * PCI devices which are on Intel chips can skip the 10ms delay
3186 * before entering D3 mode.
3187 */
3188 static void quirk_remove_d3_delay(struct pci_dev *dev)
3189 {
3190 dev->d3_delay = 0;
3191 }
3192 /* C600 Series devices do not need 10ms d3_delay */
3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3196 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3208 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3218
3219 /*
3220 * Some devices may pass our check in pci_intx_mask_supported() if
3221 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3222 * support this feature.
3223 */
3224 static void quirk_broken_intx_masking(struct pci_dev *dev)
3225 {
3226 dev->broken_intx_masking = 1;
3227 }
3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3229 quirk_broken_intx_masking);
3230 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3231 quirk_broken_intx_masking);
3232
3233 /*
3234 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3235 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3236 *
3237 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3238 */
3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3240 quirk_broken_intx_masking);
3241
3242 /*
3243 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3244 * DisINTx can be set but the interrupt status bit is non-functional.
3245 */
3246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3247 quirk_broken_intx_masking);
3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3249 quirk_broken_intx_masking);
3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3251 quirk_broken_intx_masking);
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3253 quirk_broken_intx_masking);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3255 quirk_broken_intx_masking);
3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3257 quirk_broken_intx_masking);
3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3259 quirk_broken_intx_masking);
3260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3261 quirk_broken_intx_masking);
3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3263 quirk_broken_intx_masking);
3264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3265 quirk_broken_intx_masking);
3266 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3267 quirk_broken_intx_masking);
3268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3269 quirk_broken_intx_masking);
3270 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3271 quirk_broken_intx_masking);
3272 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3273 quirk_broken_intx_masking);
3274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3275 quirk_broken_intx_masking);
3276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3277 quirk_broken_intx_masking);
3278
3279 static u16 mellanox_broken_intx_devs[] = {
3280 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3281 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3282 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3283 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3284 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3285 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3286 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3287 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3288 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3289 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3290 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3291 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3292 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3293 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3294 };
3295
3296 #define CONNECTX_4_CURR_MAX_MINOR 99
3297 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3298
3299 /*
3300 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3301 * If so, don't mark it as broken.
3302 * FW minor > 99 means older FW version format and no INTx masking support.
3303 * FW minor < 14 means new FW version format and no INTx masking support.
3304 */
3305 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3306 {
3307 __be32 __iomem *fw_ver;
3308 u16 fw_major;
3309 u16 fw_minor;
3310 u16 fw_subminor;
3311 u32 fw_maj_min;
3312 u32 fw_sub_min;
3313 int i;
3314
3315 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3316 if (pdev->device == mellanox_broken_intx_devs[i]) {
3317 pdev->broken_intx_masking = 1;
3318 return;
3319 }
3320 }
3321
3322 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3323 * support so shouldn't be checked further
3324 */
3325 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3326 return;
3327
3328 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3329 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3330 return;
3331
3332 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3333 if (pci_enable_device_mem(pdev)) {
3334 dev_warn(&pdev->dev, "Can't enable device memory\n");
3335 return;
3336 }
3337
3338 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3339 if (!fw_ver) {
3340 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3341 goto out;
3342 }
3343
3344 /* Reading from resource space should be 32b aligned */
3345 fw_maj_min = ioread32be(fw_ver);
3346 fw_sub_min = ioread32be(fw_ver + 1);
3347 fw_major = fw_maj_min & 0xffff;
3348 fw_minor = fw_maj_min >> 16;
3349 fw_subminor = fw_sub_min & 0xffff;
3350 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3351 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3352 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3353 fw_major, fw_minor, fw_subminor, pdev->device ==
3354 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3355 pdev->broken_intx_masking = 1;
3356 }
3357
3358 iounmap(fw_ver);
3359
3360 out:
3361 pci_disable_device(pdev);
3362 }
3363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3364 mellanox_check_broken_intx_masking);
3365
3366 static void quirk_no_bus_reset(struct pci_dev *dev)
3367 {
3368 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3369 }
3370
3371 /*
3372 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3373 * The device will throw a Link Down error on AER-capable systems and
3374 * regardless of AER, config space of the device is never accessible again
3375 * and typically causes the system to hang or reset when access is attempted.
3376 * http://www.spinics.net/lists/linux-pci/msg34797.html
3377 */
3378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3379 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3380 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3382
3383 static void quirk_no_pm_reset(struct pci_dev *dev)
3384 {
3385 /*
3386 * We can't do a bus reset on root bus devices, but an ineffective
3387 * PM reset may be better than nothing.
3388 */
3389 if (!pci_is_root_bus(dev->bus))
3390 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3391 }
3392
3393 /*
3394 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3395 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3396 * to have no effect on the device: it retains the framebuffer contents and
3397 * monitor sync. Advertising this support makes other layers, like VFIO,
3398 * assume pci_reset_function() is viable for this device. Mark it as
3399 * unavailable to skip it when testing reset methods.
3400 */
3401 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3402 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3403
3404 /*
3405 * Thunderbolt controllers with broken MSI hotplug signaling:
3406 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3407 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3408 */
3409 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3410 {
3411 if (pdev->is_hotplug_bridge &&
3412 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3413 pdev->revision <= 1))
3414 pdev->no_msi = 1;
3415 }
3416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3417 quirk_thunderbolt_hotplug_msi);
3418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3419 quirk_thunderbolt_hotplug_msi);
3420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3421 quirk_thunderbolt_hotplug_msi);
3422 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3423 quirk_thunderbolt_hotplug_msi);
3424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3425 quirk_thunderbolt_hotplug_msi);
3426
3427 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3428 {
3429 pci_set_vpd_size(dev, 8192);
3430 }
3431
3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
3434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
3436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
3437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
3438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
3439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
3440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
3441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
3442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
3443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
3444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
3445
3446 #ifdef CONFIG_ACPI
3447 /*
3448 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3449 *
3450 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3451 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3452 * be present after resume if a device was plugged in before suspend.
3453 *
3454 * The thunderbolt controller consists of a pcie switch with downstream
3455 * bridges leading to the NHI and to the tunnel pci bridges.
3456 *
3457 * This quirk cuts power to the whole chip. Therefore we have to apply it
3458 * during suspend_noirq of the upstream bridge.
3459 *
3460 * Power is automagically restored before resume. No action is needed.
3461 */
3462 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3463 {
3464 acpi_handle bridge, SXIO, SXFP, SXLV;
3465
3466 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3467 return;
3468 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3469 return;
3470 bridge = ACPI_HANDLE(&dev->dev);
3471 if (!bridge)
3472 return;
3473 /*
3474 * SXIO and SXLV are present only on machines requiring this quirk.
3475 * TB bridges in external devices might have the same device id as those
3476 * on the host, but they will not have the associated ACPI methods. This
3477 * implicitly checks that we are at the right bridge.
3478 */
3479 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3480 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3481 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3482 return;
3483 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3484
3485 /* magic sequence */
3486 acpi_execute_simple_method(SXIO, NULL, 1);
3487 acpi_execute_simple_method(SXFP, NULL, 0);
3488 msleep(300);
3489 acpi_execute_simple_method(SXLV, NULL, 0);
3490 acpi_execute_simple_method(SXIO, NULL, 0);
3491 acpi_execute_simple_method(SXLV, NULL, 0);
3492 }
3493 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3494 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3495 quirk_apple_poweroff_thunderbolt);
3496
3497 /*
3498 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3499 *
3500 * During suspend the thunderbolt controller is reset and all pci
3501 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3502 * during resume. We have to manually wait for the NHI since there is
3503 * no parent child relationship between the NHI and the tunneled
3504 * bridges.
3505 */
3506 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3507 {
3508 struct pci_dev *sibling = NULL;
3509 struct pci_dev *nhi = NULL;
3510
3511 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3512 return;
3513 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3514 return;
3515 /*
3516 * Find the NHI and confirm that we are a bridge on the tb host
3517 * controller and not on a tb endpoint.
3518 */
3519 sibling = pci_get_slot(dev->bus, 0x0);
3520 if (sibling == dev)
3521 goto out; /* we are the downstream bridge to the NHI */
3522 if (!sibling || !sibling->subordinate)
3523 goto out;
3524 nhi = pci_get_slot(sibling->subordinate, 0x0);
3525 if (!nhi)
3526 goto out;
3527 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3528 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3529 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3530 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3531 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3532 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3533 goto out;
3534 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3535 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3536 out:
3537 pci_dev_put(nhi);
3538 pci_dev_put(sibling);
3539 }
3540 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3541 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3542 quirk_apple_wait_for_thunderbolt);
3543 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3544 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3545 quirk_apple_wait_for_thunderbolt);
3546 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3547 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3548 quirk_apple_wait_for_thunderbolt);
3549 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3550 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3551 quirk_apple_wait_for_thunderbolt);
3552 #endif
3553
3554 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3555 struct pci_fixup *end)
3556 {
3557 ktime_t calltime;
3558
3559 for (; f < end; f++)
3560 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3561 f->class == (u32) PCI_ANY_ID) &&
3562 (f->vendor == dev->vendor ||
3563 f->vendor == (u16) PCI_ANY_ID) &&
3564 (f->device == dev->device ||
3565 f->device == (u16) PCI_ANY_ID)) {
3566 calltime = fixup_debug_start(dev, f->hook);
3567 f->hook(dev);
3568 fixup_debug_report(dev, calltime, f->hook);
3569 }
3570 }
3571
3572 extern struct pci_fixup __start_pci_fixups_early[];
3573 extern struct pci_fixup __end_pci_fixups_early[];
3574 extern struct pci_fixup __start_pci_fixups_header[];
3575 extern struct pci_fixup __end_pci_fixups_header[];
3576 extern struct pci_fixup __start_pci_fixups_final[];
3577 extern struct pci_fixup __end_pci_fixups_final[];
3578 extern struct pci_fixup __start_pci_fixups_enable[];
3579 extern struct pci_fixup __end_pci_fixups_enable[];
3580 extern struct pci_fixup __start_pci_fixups_resume[];
3581 extern struct pci_fixup __end_pci_fixups_resume[];
3582 extern struct pci_fixup __start_pci_fixups_resume_early[];
3583 extern struct pci_fixup __end_pci_fixups_resume_early[];
3584 extern struct pci_fixup __start_pci_fixups_suspend[];
3585 extern struct pci_fixup __end_pci_fixups_suspend[];
3586 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3587 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3588
3589 static bool pci_apply_fixup_final_quirks;
3590
3591 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3592 {
3593 struct pci_fixup *start, *end;
3594
3595 switch (pass) {
3596 case pci_fixup_early:
3597 start = __start_pci_fixups_early;
3598 end = __end_pci_fixups_early;
3599 break;
3600
3601 case pci_fixup_header:
3602 start = __start_pci_fixups_header;
3603 end = __end_pci_fixups_header;
3604 break;
3605
3606 case pci_fixup_final:
3607 if (!pci_apply_fixup_final_quirks)
3608 return;
3609 start = __start_pci_fixups_final;
3610 end = __end_pci_fixups_final;
3611 break;
3612
3613 case pci_fixup_enable:
3614 start = __start_pci_fixups_enable;
3615 end = __end_pci_fixups_enable;
3616 break;
3617
3618 case pci_fixup_resume:
3619 start = __start_pci_fixups_resume;
3620 end = __end_pci_fixups_resume;
3621 break;
3622
3623 case pci_fixup_resume_early:
3624 start = __start_pci_fixups_resume_early;
3625 end = __end_pci_fixups_resume_early;
3626 break;
3627
3628 case pci_fixup_suspend:
3629 start = __start_pci_fixups_suspend;
3630 end = __end_pci_fixups_suspend;
3631 break;
3632
3633 case pci_fixup_suspend_late:
3634 start = __start_pci_fixups_suspend_late;
3635 end = __end_pci_fixups_suspend_late;
3636 break;
3637
3638 default:
3639 /* stupid compiler warning, you would think with an enum... */
3640 return;
3641 }
3642 pci_do_fixups(dev, start, end);
3643 }
3644 EXPORT_SYMBOL(pci_fixup_device);
3645
3646
3647 static int __init pci_apply_final_quirks(void)
3648 {
3649 struct pci_dev *dev = NULL;
3650 u8 cls = 0;
3651 u8 tmp;
3652
3653 if (pci_cache_line_size)
3654 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3655 pci_cache_line_size << 2);
3656
3657 pci_apply_fixup_final_quirks = true;
3658 for_each_pci_dev(dev) {
3659 pci_fixup_device(pci_fixup_final, dev);
3660 /*
3661 * If arch hasn't set it explicitly yet, use the CLS
3662 * value shared by all PCI devices. If there's a
3663 * mismatch, fall back to the default value.
3664 */
3665 if (!pci_cache_line_size) {
3666 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3667 if (!cls)
3668 cls = tmp;
3669 if (!tmp || cls == tmp)
3670 continue;
3671
3672 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3673 cls << 2, tmp << 2,
3674 pci_dfl_cache_line_size << 2);
3675 pci_cache_line_size = pci_dfl_cache_line_size;
3676 }
3677 }
3678
3679 if (!pci_cache_line_size) {
3680 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3681 cls << 2, pci_dfl_cache_line_size << 2);
3682 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3683 }
3684
3685 return 0;
3686 }
3687
3688 fs_initcall_sync(pci_apply_final_quirks);
3689
3690 /*
3691 * Following are device-specific reset methods which can be used to
3692 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3693 * not available.
3694 */
3695 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3696 {
3697 /*
3698 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3699 *
3700 * The 82599 supports FLR on VFs, but FLR support is reported only
3701 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3702 * Thus we must call pcie_flr() directly without first checking if it is
3703 * supported.
3704 */
3705 if (!probe)
3706 pcie_flr(dev);
3707 return 0;
3708 }
3709
3710 #define SOUTH_CHICKEN2 0xc2004
3711 #define PCH_PP_STATUS 0xc7200
3712 #define PCH_PP_CONTROL 0xc7204
3713 #define MSG_CTL 0x45010
3714 #define NSDE_PWR_STATE 0xd0100
3715 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3716
3717 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3718 {
3719 void __iomem *mmio_base;
3720 unsigned long timeout;
3721 u32 val;
3722
3723 if (probe)
3724 return 0;
3725
3726 mmio_base = pci_iomap(dev, 0, 0);
3727 if (!mmio_base)
3728 return -ENOMEM;
3729
3730 iowrite32(0x00000002, mmio_base + MSG_CTL);
3731
3732 /*
3733 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3734 * driver loaded sets the right bits. However, this's a reset and
3735 * the bits have been set by i915 previously, so we clobber
3736 * SOUTH_CHICKEN2 register directly here.
3737 */
3738 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3739
3740 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3741 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3742
3743 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3744 do {
3745 val = ioread32(mmio_base + PCH_PP_STATUS);
3746 if ((val & 0xb0000000) == 0)
3747 goto reset_complete;
3748 msleep(10);
3749 } while (time_before(jiffies, timeout));
3750 dev_warn(&dev->dev, "timeout during reset\n");
3751
3752 reset_complete:
3753 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3754
3755 pci_iounmap(dev, mmio_base);
3756 return 0;
3757 }
3758
3759 /*
3760 * Device-specific reset method for Chelsio T4-based adapters.
3761 */
3762 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3763 {
3764 u16 old_command;
3765 u16 msix_flags;
3766
3767 /*
3768 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3769 * that we have no device-specific reset method.
3770 */
3771 if ((dev->device & 0xf000) != 0x4000)
3772 return -ENOTTY;
3773
3774 /*
3775 * If this is the "probe" phase, return 0 indicating that we can
3776 * reset this device.
3777 */
3778 if (probe)
3779 return 0;
3780
3781 /*
3782 * T4 can wedge if there are DMAs in flight within the chip and Bus
3783 * Master has been disabled. We need to have it on till the Function
3784 * Level Reset completes. (BUS_MASTER is disabled in
3785 * pci_reset_function()).
3786 */
3787 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3788 pci_write_config_word(dev, PCI_COMMAND,
3789 old_command | PCI_COMMAND_MASTER);
3790
3791 /*
3792 * Perform the actual device function reset, saving and restoring
3793 * configuration information around the reset.
3794 */
3795 pci_save_state(dev);
3796
3797 /*
3798 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3799 * are disabled when an MSI-X interrupt message needs to be delivered.
3800 * So we briefly re-enable MSI-X interrupts for the duration of the
3801 * FLR. The pci_restore_state() below will restore the original
3802 * MSI-X state.
3803 */
3804 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3805 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3806 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3807 msix_flags |
3808 PCI_MSIX_FLAGS_ENABLE |
3809 PCI_MSIX_FLAGS_MASKALL);
3810
3811 pcie_flr(dev);
3812
3813 /*
3814 * Restore the configuration information (BAR values, etc.) including
3815 * the original PCI Configuration Space Command word, and return
3816 * success.
3817 */
3818 pci_restore_state(dev);
3819 pci_write_config_word(dev, PCI_COMMAND, old_command);
3820 return 0;
3821 }
3822
3823 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3824 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3825 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3826
3827 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3828 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3829 reset_intel_82599_sfp_virtfn },
3830 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3831 reset_ivb_igd },
3832 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3833 reset_ivb_igd },
3834 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3835 reset_chelsio_generic_dev },
3836 { 0 }
3837 };
3838
3839 /*
3840 * These device-specific reset methods are here rather than in a driver
3841 * because when a host assigns a device to a guest VM, the host may need
3842 * to reset the device but probably doesn't have a driver for it.
3843 */
3844 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3845 {
3846 const struct pci_dev_reset_methods *i;
3847
3848 for (i = pci_dev_reset_methods; i->reset; i++) {
3849 if ((i->vendor == dev->vendor ||
3850 i->vendor == (u16)PCI_ANY_ID) &&
3851 (i->device == dev->device ||
3852 i->device == (u16)PCI_ANY_ID))
3853 return i->reset(dev, probe);
3854 }
3855
3856 return -ENOTTY;
3857 }
3858
3859 static void quirk_dma_func0_alias(struct pci_dev *dev)
3860 {
3861 if (PCI_FUNC(dev->devfn) != 0)
3862 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3863 }
3864
3865 /*
3866 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3867 *
3868 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3869 */
3870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3871 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3872
3873 static void quirk_dma_func1_alias(struct pci_dev *dev)
3874 {
3875 if (PCI_FUNC(dev->devfn) != 1)
3876 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3877 }
3878
3879 /*
3880 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3881 * SKUs function 1 is present and is a legacy IDE controller, in other
3882 * SKUs this function is not present, making this a ghost requester.
3883 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3884 */
3885 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3886 quirk_dma_func1_alias);
3887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3888 quirk_dma_func1_alias);
3889 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3891 quirk_dma_func1_alias);
3892 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3894 quirk_dma_func1_alias);
3895 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3897 quirk_dma_func1_alias);
3898 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3900 quirk_dma_func1_alias);
3901 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3903 quirk_dma_func1_alias);
3904 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3905 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3906 quirk_dma_func1_alias);
3907 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3908 quirk_dma_func1_alias);
3909 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3911 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3912 quirk_dma_func1_alias);
3913 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3914 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3915 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3916 quirk_dma_func1_alias);
3917
3918 /*
3919 * Some devices DMA with the wrong devfn, not just the wrong function.
3920 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3921 * the alias is "fixed" and independent of the device devfn.
3922 *
3923 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3924 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3925 * single device on the secondary bus. In reality, the single exposed
3926 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3927 * that provides a bridge to the internal bus of the I/O processor. The
3928 * controller supports private devices, which can be hidden from PCI config
3929 * space. In the case of the Adaptec 3405, a private device at 01.0
3930 * appears to be the DMA engine, which therefore needs to become a DMA
3931 * alias for the device.
3932 */
3933 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3934 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3935 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3936 .driver_data = PCI_DEVFN(1, 0) },
3937 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3938 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3939 .driver_data = PCI_DEVFN(1, 0) },
3940 { 0 }
3941 };
3942
3943 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3944 {
3945 const struct pci_device_id *id;
3946
3947 id = pci_match_id(fixed_dma_alias_tbl, dev);
3948 if (id)
3949 pci_add_dma_alias(dev, id->driver_data);
3950 }
3951
3952 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3953
3954 /*
3955 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3956 * using the wrong DMA alias for the device. Some of these devices can be
3957 * used as either forward or reverse bridges, so we need to test whether the
3958 * device is operating in the correct mode. We could probably apply this
3959 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3960 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3961 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3962 */
3963 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3964 {
3965 if (!pci_is_root_bus(pdev->bus) &&
3966 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3967 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3968 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3969 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3970 }
3971 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3972 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3973 quirk_use_pcie_bridge_dma_alias);
3974 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3975 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3976 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3977 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3978 /* ITE 8893 has the same problem as the 8892 */
3979 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
3980 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3981 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3982
3983 /*
3984 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3985 * be added as aliases to the DMA device in order to allow buffer access
3986 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3987 * programmed in the EEPROM.
3988 */
3989 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3990 {
3991 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3992 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3993 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3994 }
3995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3997
3998 /*
3999 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4000 * associated not at the root bus, but at a bridge below. This quirk avoids
4001 * generating invalid DMA aliases.
4002 */
4003 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4004 {
4005 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4006 }
4007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4008 quirk_bridge_cavm_thrx2_pcie_root);
4009 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4010 quirk_bridge_cavm_thrx2_pcie_root);
4011
4012 /*
4013 * PCI BAR 5 is not setup correctly for the on-board AHCI controller
4014 * on Broadcom's Vulcan processor. Added a quirk to fix BAR 5 by
4015 * using BAR 4's resources which are populated correctly and NOT
4016 * actually used by the AHCI controller.
4017 */
4018 static void quirk_fix_vulcan_ahci_bars(struct pci_dev *dev)
4019 {
4020 struct resource *r = &dev->resource[4];
4021
4022 if (!(r->flags & IORESOURCE_MEM) || (r->start == 0))
4023 return;
4024
4025 /* Set BAR5 resource to BAR4 */
4026 dev->resource[5] = *r;
4027
4028 /* Update BAR5 in pci config space */
4029 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, r->start);
4030
4031 /* Clear BAR4's resource */
4032 memset(r, 0, sizeof(*r));
4033 }
4034 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9027, quirk_fix_vulcan_ahci_bars);
4035
4036 /*
4037 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4038 * class code. Fix it.
4039 */
4040 static void quirk_tw686x_class(struct pci_dev *pdev)
4041 {
4042 u32 class = pdev->class;
4043
4044 /* Use "Multimedia controller" class */
4045 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4046 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4047 class, pdev->class);
4048 }
4049 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4050 quirk_tw686x_class);
4051 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4052 quirk_tw686x_class);
4053 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4054 quirk_tw686x_class);
4055 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4056 quirk_tw686x_class);
4057
4058 /*
4059 * Some devices have problems with Transaction Layer Packets with the Relaxed
4060 * Ordering Attribute set. Such devices should mark themselves and other
4061 * Device Drivers should check before sending TLPs with RO set.
4062 */
4063 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4064 {
4065 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4066 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4067 }
4068
4069 /*
4070 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4071 * Complex has a Flow Control Credit issue which can cause performance
4072 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4073 */
4074 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4075 quirk_relaxedordering_disable);
4076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4077 quirk_relaxedordering_disable);
4078 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4079 quirk_relaxedordering_disable);
4080 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4081 quirk_relaxedordering_disable);
4082 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4083 quirk_relaxedordering_disable);
4084 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4085 quirk_relaxedordering_disable);
4086 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4087 quirk_relaxedordering_disable);
4088 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4089 quirk_relaxedordering_disable);
4090 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4091 quirk_relaxedordering_disable);
4092 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4093 quirk_relaxedordering_disable);
4094 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4095 quirk_relaxedordering_disable);
4096 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4097 quirk_relaxedordering_disable);
4098 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4099 quirk_relaxedordering_disable);
4100 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4101 quirk_relaxedordering_disable);
4102 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4103 quirk_relaxedordering_disable);
4104 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4105 quirk_relaxedordering_disable);
4106 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4107 quirk_relaxedordering_disable);
4108 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4109 quirk_relaxedordering_disable);
4110 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4111 quirk_relaxedordering_disable);
4112 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4113 quirk_relaxedordering_disable);
4114 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4115 quirk_relaxedordering_disable);
4116 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4117 quirk_relaxedordering_disable);
4118 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4119 quirk_relaxedordering_disable);
4120 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4121 quirk_relaxedordering_disable);
4122 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4123 quirk_relaxedordering_disable);
4124 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4125 quirk_relaxedordering_disable);
4126 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4127 quirk_relaxedordering_disable);
4128 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4129 quirk_relaxedordering_disable);
4130
4131 /*
4132 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4133 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4134 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4135 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4136 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4137 * November 10, 2010). As a result, on this platform we can't use Relaxed
4138 * Ordering for Upstream TLPs.
4139 */
4140 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4141 quirk_relaxedordering_disable);
4142 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4143 quirk_relaxedordering_disable);
4144 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4145 quirk_relaxedordering_disable);
4146
4147 /*
4148 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4149 * values for the Attribute as were supplied in the header of the
4150 * corresponding Request, except as explicitly allowed when IDO is used."
4151 *
4152 * If a non-compliant device generates a completion with a different
4153 * attribute than the request, the receiver may accept it (which itself
4154 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4155 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4156 * device access timeout.
4157 *
4158 * If the non-compliant device generates completions with zero attributes
4159 * (instead of copying the attributes from the request), we can work around
4160 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4161 * upstream devices so they always generate requests with zero attributes.
4162 *
4163 * This affects other devices under the same Root Port, but since these
4164 * attributes are performance hints, there should be no functional problem.
4165 *
4166 * Note that Configuration Space accesses are never supposed to have TLP
4167 * Attributes, so we're safe waiting till after any Configuration Space
4168 * accesses to do the Root Port fixup.
4169 */
4170 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4171 {
4172 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4173
4174 if (!root_port) {
4175 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4176 return;
4177 }
4178
4179 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4180 dev_name(&pdev->dev));
4181 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4182 PCI_EXP_DEVCTL_RELAX_EN |
4183 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4184 }
4185
4186 /*
4187 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4188 * Completion it generates.
4189 */
4190 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4191 {
4192 /*
4193 * This mask/compare operation selects for Physical Function 4 on a
4194 * T5. We only need to fix up the Root Port once for any of the
4195 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4196 * 0x54xx so we use that one,
4197 */
4198 if ((pdev->device & 0xff00) == 0x5400)
4199 quirk_disable_root_port_attributes(pdev);
4200 }
4201 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4202 quirk_chelsio_T5_disable_root_port_attributes);
4203
4204 /*
4205 * AMD has indicated that the devices below do not support peer-to-peer
4206 * in any system where they are found in the southbridge with an AMD
4207 * IOMMU in the system. Multifunction devices that do not support
4208 * peer-to-peer between functions can claim to support a subset of ACS.
4209 * Such devices effectively enable request redirect (RR) and completion
4210 * redirect (CR) since all transactions are redirected to the upstream
4211 * root complex.
4212 *
4213 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4214 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4215 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4216 *
4217 * 1002:4385 SBx00 SMBus Controller
4218 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4219 * 1002:4383 SBx00 Azalia (Intel HDA)
4220 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4221 * 1002:4384 SBx00 PCI to PCI Bridge
4222 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4223 *
4224 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4225 *
4226 * 1022:780f [AMD] FCH PCI Bridge
4227 * 1022:7809 [AMD] FCH USB OHCI Controller
4228 */
4229 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4230 {
4231 #ifdef CONFIG_ACPI
4232 struct acpi_table_header *header = NULL;
4233 acpi_status status;
4234
4235 /* Targeting multifunction devices on the SB (appears on root bus) */
4236 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4237 return -ENODEV;
4238
4239 /* The IVRS table describes the AMD IOMMU */
4240 status = acpi_get_table("IVRS", 0, &header);
4241 if (ACPI_FAILURE(status))
4242 return -ENODEV;
4243
4244 /* Filter out flags not applicable to multifunction */
4245 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4246
4247 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4248 #else
4249 return -ENODEV;
4250 #endif
4251 }
4252
4253 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4254 {
4255 /*
4256 * Cavium devices matching this quirk do not perform peer-to-peer
4257 * with other functions, allowing masking out these bits as if they
4258 * were unimplemented in the ACS capability.
4259 */
4260 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4261 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4262
4263 if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))
4264 return -ENOTTY;
4265
4266 return acs_flags ? 0 : 1;
4267 }
4268
4269 /*
4270 * Many Intel PCH root ports do provide ACS-like features to disable peer
4271 * transactions and validate bus numbers in requests, but do not provide an
4272 * actual PCIe ACS capability. This is the list of device IDs known to fall
4273 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4274 */
4275 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4276 /* Ibexpeak PCH */
4277 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4278 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4279 /* Cougarpoint PCH */
4280 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4281 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4282 /* Pantherpoint PCH */
4283 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4284 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4285 /* Lynxpoint-H PCH */
4286 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4287 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4288 /* Lynxpoint-LP PCH */
4289 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4290 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4291 /* Wildcat PCH */
4292 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4293 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4294 /* Patsburg (X79) PCH */
4295 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4296 /* Wellsburg (X99) PCH */
4297 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4298 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4299 /* Lynx Point (9 series) PCH */
4300 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4301 };
4302
4303 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4304 {
4305 int i;
4306
4307 /* Filter out a few obvious non-matches first */
4308 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4309 return false;
4310
4311 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4312 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4313 return true;
4314
4315 return false;
4316 }
4317
4318 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4319
4320 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4321 {
4322 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4323 INTEL_PCH_ACS_FLAGS : 0;
4324
4325 if (!pci_quirk_intel_pch_acs_match(dev))
4326 return -ENOTTY;
4327
4328 return acs_flags & ~flags ? 0 : 1;
4329 }
4330
4331 /*
4332 * These QCOM root ports do provide ACS-like features to disable peer
4333 * transactions and validate bus numbers in requests, but do not provide an
4334 * actual PCIe ACS capability. Hardware supports source validation but it
4335 * will report the issue as Completer Abort instead of ACS Violation.
4336 * Hardware doesn't support peer-to-peer and each root port is a root
4337 * complex with unique segment numbers. It is not possible for one root
4338 * port to pass traffic to another root port. All PCIe transactions are
4339 * terminated inside the root port.
4340 */
4341 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4342 {
4343 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4344 int ret = acs_flags & ~flags ? 0 : 1;
4345
4346 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4347
4348 return ret;
4349 }
4350
4351 /*
4352 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4353 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4354 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4355 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4356 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4357 * control register is at offset 8 instead of 6 and we should probably use
4358 * dword accesses to them. This applies to the following PCI Device IDs, as
4359 * found in volume 1 of the datasheet[2]:
4360 *
4361 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4362 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4363 *
4364 * N.B. This doesn't fix what lspci shows.
4365 *
4366 * The 100 series chipset specification update includes this as errata #23[3].
4367 *
4368 * The 200 series chipset (Union Point) has the same bug according to the
4369 * specification update (Intel 200 Series Chipset Family Platform Controller
4370 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4371 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4372 * chipset include:
4373 *
4374 * 0xa290-0xa29f PCI Express Root port #{0-16}
4375 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4376 *
4377 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4378 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4379 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4380 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4381 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4382 */
4383 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4384 {
4385 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4386 return false;
4387
4388 switch (dev->device) {
4389 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4390 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4391 return true;
4392 }
4393
4394 return false;
4395 }
4396
4397 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4398
4399 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4400 {
4401 int pos;
4402 u32 cap, ctrl;
4403
4404 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4405 return -ENOTTY;
4406
4407 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4408 if (!pos)
4409 return -ENOTTY;
4410
4411 /* see pci_acs_flags_enabled() */
4412 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4413 acs_flags &= (cap | PCI_ACS_EC);
4414
4415 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4416
4417 return acs_flags & ~ctrl ? 0 : 1;
4418 }
4419
4420 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4421 {
4422 /*
4423 * SV, TB, and UF are not relevant to multifunction endpoints.
4424 *
4425 * Multifunction devices are only required to implement RR, CR, and DT
4426 * in their ACS capability if they support peer-to-peer transactions.
4427 * Devices matching this quirk have been verified by the vendor to not
4428 * perform peer-to-peer with other functions, allowing us to mask out
4429 * these bits as if they were unimplemented in the ACS capability.
4430 */
4431 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4432 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4433
4434 return acs_flags ? 0 : 1;
4435 }
4436
4437 static const struct pci_dev_acs_enabled {
4438 u16 vendor;
4439 u16 device;
4440 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4441 } pci_dev_acs_enabled[] = {
4442 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4443 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4444 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4445 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4446 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4447 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4448 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4449 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4450 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4451 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4452 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4453 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4454 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4455 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4456 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4457 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4458 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4459 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4460 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4461 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4462 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4463 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4464 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4465 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4466 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4467 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4468 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4469 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4470 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4471 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4472 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4473 /* 82580 */
4474 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4475 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4476 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4477 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4478 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4479 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4480 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4481 /* 82576 */
4482 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4483 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4484 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4485 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4486 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4487 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4488 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4489 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4490 /* 82575 */
4491 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4492 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4493 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4494 /* I350 */
4495 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4496 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4497 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4498 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4499 /* 82571 (Quads omitted due to non-ACS switch) */
4500 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4501 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4502 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4503 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4504 /* I219 */
4505 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4506 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4507 /* QCOM QDF2xxx root ports */
4508 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4509 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4510 /* Intel PCH root ports */
4511 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4512 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4513 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4514 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4515 /* Cavium ThunderX */
4516 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4517 { 0 }
4518 };
4519
4520 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4521 {
4522 const struct pci_dev_acs_enabled *i;
4523 int ret;
4524
4525 /*
4526 * Allow devices that do not expose standard PCIe ACS capabilities
4527 * or control to indicate their support here. Multi-function express
4528 * devices which do not allow internal peer-to-peer between functions,
4529 * but do not implement PCIe ACS may wish to return true here.
4530 */
4531 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4532 if ((i->vendor == dev->vendor ||
4533 i->vendor == (u16)PCI_ANY_ID) &&
4534 (i->device == dev->device ||
4535 i->device == (u16)PCI_ANY_ID)) {
4536 ret = i->acs_enabled(dev, acs_flags);
4537 if (ret >= 0)
4538 return ret;
4539 }
4540 }
4541
4542 return -ENOTTY;
4543 }
4544
4545 /* Config space offset of Root Complex Base Address register */
4546 #define INTEL_LPC_RCBA_REG 0xf0
4547 /* 31:14 RCBA address */
4548 #define INTEL_LPC_RCBA_MASK 0xffffc000
4549 /* RCBA Enable */
4550 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4551
4552 /* Backbone Scratch Pad Register */
4553 #define INTEL_BSPR_REG 0x1104
4554 /* Backbone Peer Non-Posted Disable */
4555 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4556 /* Backbone Peer Posted Disable */
4557 #define INTEL_BSPR_REG_BPPD (1 << 9)
4558
4559 /* Upstream Peer Decode Configuration Register */
4560 #define INTEL_UPDCR_REG 0x1114
4561 /* 5:0 Peer Decode Enable bits */
4562 #define INTEL_UPDCR_REG_MASK 0x3f
4563
4564 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4565 {
4566 u32 rcba, bspr, updcr;
4567 void __iomem *rcba_mem;
4568
4569 /*
4570 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4571 * are D28:F* and therefore get probed before LPC, thus we can't
4572 * use pci_get_slot/pci_read_config_dword here.
4573 */
4574 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4575 INTEL_LPC_RCBA_REG, &rcba);
4576 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4577 return -EINVAL;
4578
4579 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4580 PAGE_ALIGN(INTEL_UPDCR_REG));
4581 if (!rcba_mem)
4582 return -ENOMEM;
4583
4584 /*
4585 * The BSPR can disallow peer cycles, but it's set by soft strap and
4586 * therefore read-only. If both posted and non-posted peer cycles are
4587 * disallowed, we're ok. If either are allowed, then we need to use
4588 * the UPDCR to disable peer decodes for each port. This provides the
4589 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4590 */
4591 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4592 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4593 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4594 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4595 if (updcr & INTEL_UPDCR_REG_MASK) {
4596 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4597 updcr &= ~INTEL_UPDCR_REG_MASK;
4598 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4599 }
4600 }
4601
4602 iounmap(rcba_mem);
4603 return 0;
4604 }
4605
4606 /* Miscellaneous Port Configuration register */
4607 #define INTEL_MPC_REG 0xd8
4608 /* MPC: Invalid Receive Bus Number Check Enable */
4609 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4610
4611 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4612 {
4613 u32 mpc;
4614
4615 /*
4616 * When enabled, the IRBNCE bit of the MPC register enables the
4617 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4618 * ensures that requester IDs fall within the bus number range
4619 * of the bridge. Enable if not already.
4620 */
4621 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4622 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4623 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4624 mpc |= INTEL_MPC_REG_IRBNCE;
4625 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4626 }
4627 }
4628
4629 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4630 {
4631 if (!pci_quirk_intel_pch_acs_match(dev))
4632 return -ENOTTY;
4633
4634 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4635 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4636 return 0;
4637 }
4638
4639 pci_quirk_enable_intel_rp_mpc_acs(dev);
4640
4641 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4642
4643 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4644
4645 return 0;
4646 }
4647
4648 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4649 {
4650 int pos;
4651 u32 cap, ctrl;
4652
4653 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4654 return -ENOTTY;
4655
4656 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4657 if (!pos)
4658 return -ENOTTY;
4659
4660 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4661 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4662
4663 ctrl |= (cap & PCI_ACS_SV);
4664 ctrl |= (cap & PCI_ACS_RR);
4665 ctrl |= (cap & PCI_ACS_CR);
4666 ctrl |= (cap & PCI_ACS_UF);
4667
4668 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4669
4670 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4671
4672 return 0;
4673 }
4674
4675 static const struct pci_dev_enable_acs {
4676 u16 vendor;
4677 u16 device;
4678 int (*enable_acs)(struct pci_dev *dev);
4679 } pci_dev_enable_acs[] = {
4680 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4681 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4682 { 0 }
4683 };
4684
4685 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4686 {
4687 const struct pci_dev_enable_acs *i;
4688 int ret;
4689
4690 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4691 if ((i->vendor == dev->vendor ||
4692 i->vendor == (u16)PCI_ANY_ID) &&
4693 (i->device == dev->device ||
4694 i->device == (u16)PCI_ANY_ID)) {
4695 ret = i->enable_acs(dev);
4696 if (ret >= 0)
4697 return ret;
4698 }
4699 }
4700
4701 return -ENOTTY;
4702 }
4703
4704 /*
4705 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4706 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4707 * Next Capability pointer in the MSI Capability Structure should point to
4708 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4709 * the list.
4710 */
4711 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4712 {
4713 int pos, i = 0;
4714 u8 next_cap;
4715 u16 reg16, *cap;
4716 struct pci_cap_saved_state *state;
4717
4718 /* Bail if the hardware bug is fixed */
4719 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4720 return;
4721
4722 /* Bail if MSI Capability Structure is not found for some reason */
4723 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4724 if (!pos)
4725 return;
4726
4727 /*
4728 * Bail if Next Capability pointer in the MSI Capability Structure
4729 * is not the expected incorrect 0x00.
4730 */
4731 pci_read_config_byte(pdev, pos + 1, &next_cap);
4732 if (next_cap)
4733 return;
4734
4735 /*
4736 * PCIe Capability Structure is expected to be at 0x50 and should
4737 * terminate the list (Next Capability pointer is 0x00). Verify
4738 * Capability Id and Next Capability pointer is as expected.
4739 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4740 * to correctly set kernel data structures which have already been
4741 * set incorrectly due to the hardware bug.
4742 */
4743 pos = 0x50;
4744 pci_read_config_word(pdev, pos, &reg16);
4745 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4746 u32 status;
4747 #ifndef PCI_EXP_SAVE_REGS
4748 #define PCI_EXP_SAVE_REGS 7
4749 #endif
4750 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4751
4752 pdev->pcie_cap = pos;
4753 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4754 pdev->pcie_flags_reg = reg16;
4755 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4756 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4757
4758 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4759 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4760 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4761 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4762
4763 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4764 return;
4765
4766 /*
4767 * Save PCIE cap
4768 */
4769 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4770 if (!state)
4771 return;
4772
4773 state->cap.cap_nr = PCI_CAP_ID_EXP;
4774 state->cap.cap_extended = 0;
4775 state->cap.size = size;
4776 cap = (u16 *)&state->cap.data[0];
4777 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4778 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4779 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4780 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4781 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4782 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4783 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4784 hlist_add_head(&state->next, &pdev->saved_cap_space);
4785 }
4786 }
4787 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4788
4789 /*
4790 * VMD-enabled root ports will change the source ID for all messages
4791 * to the VMD device. Rather than doing device matching with the source
4792 * ID, the AER driver should traverse the child device tree, reading
4793 * AER registers to find the faulting device.
4794 */
4795 static void quirk_no_aersid(struct pci_dev *pdev)
4796 {
4797 /* VMD Domain */
4798 if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
4799 pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
4800 }
4801 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
4802 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
4803 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
4804 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
4805
4806 /* FLR may cause some 82579 devices to hang. */
4807 static void quirk_intel_no_flr(struct pci_dev *dev)
4808 {
4809 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4810 }
4811 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4812 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4813
4814 static void quirk_intel_th_rtit_bar(struct pci_dev *dev)
4815 {
4816 struct resource *r = &dev->resource[4];
4817
4818 /*
4819 * Hello, Denverton!
4820 * Denverton reports 2k of RTIT_BAR (resource 4), which can't be
4821 * right given the 16 threads. When Intel TH gets enabled, the
4822 * actual resource overlaps the XHCI MMIO space and causes it
4823 * to die.
4824 * We're not really using RTIT_BAR at all at the moment, so it's
4825 * a safe choice to disable this resource.
4826 */
4827 if (r->end == r->start + 0x7ff) {
4828 r->flags = 0;
4829 r->start = 0;
4830 r->end = 0;
4831 }
4832 }
4833 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_rtit_bar);
4834
4835 /*
4836 * The hibmc card on a HiSilicon D05 board sits behind a non-compliant
4837 * bridge. The bridge has the PCI_BRIDGE_CTL_VGA config bit fixed at 0
4838 * in hardware. This prevents the vgaarb from marking a card behind it
4839 * as boot VGA device.
4840 *
4841 * However, the hibmc card is known to still work, so if we have that
4842 * card behind that particular bridge (19e5:1610), mark it as the
4843 * default device if none has been detected.
4844 */
4845 static void hibmc_fixup_vgaarb(struct pci_dev *pdev)
4846 {
4847 struct pci_dev *bridge;
4848 struct pci_bus *bus;
4849 u16 config;
4850
4851 bus = pdev->bus;
4852 bridge = bus->self;
4853 if (!bridge)
4854 return;
4855
4856 if (!pci_is_bridge(bridge))
4857 return;
4858
4859 if (bridge->vendor != PCI_VENDOR_ID_HUAWEI ||
4860 bridge->device != 0x1610)
4861 return;
4862
4863 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4864 &config);
4865 if (config & PCI_BRIDGE_CTL_VGA) {
4866 /*
4867 * Weirdly, this bridge *is* spec compliant, so bail
4868 * and let vgaarb do its job
4869 */
4870 return;
4871 }
4872
4873 if (vga_default_device())
4874 return;
4875
4876 vga_set_default_device(pdev);
4877 }
4878 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1711, hibmc_fixup_vgaarb);
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