2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
26 /* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
30 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
32 dev
->broken_parity_status
= 1; /* This device gives false positives */
34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
37 /* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39 static void quirk_passive_release(struct pci_dev
*dev
)
41 struct pci_dev
*d
= NULL
;
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
47 pci_read_config_byte(d
, 0x82, &dlc
);
49 printk(KERN_ERR
"PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d
));
51 pci_write_config_byte(d
, 0x82, dlc
);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
56 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
58 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA
60 ask them for me please -- Alan
62 This appears to be BIOS not version dependent. So presumably there is a
64 int isa_dma_bridge_buggy
; /* Exported */
66 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
68 if (!isa_dma_bridge_buggy
) {
69 isa_dma_bridge_buggy
=1;
70 printk(KERN_INFO
"Activating ISA DMA hang workarounds.\n");
74 * Its not totally clear which chipsets are the problematic ones
75 * We know 82C586 and 82C596 variants are affected.
77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
88 * Chipsets where PCI->PCI transfers vanish or hang
90 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
92 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
93 printk(KERN_INFO
"Disabling direct PCI/PCI transfers.\n");
94 pci_pci_problems
|= PCIPCI_FAIL
;
98 static void __devinit
quirk_nopciamd(struct pci_dev
*dev
)
101 pci_read_config_byte(dev
, 0x08, &rev
);
104 printk(KERN_INFO
"Chipset erratum: Disabling direct PCI/AGP transfers.\n");
105 pci_pci_problems
|= PCIAGP_FAIL
;
109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8151_0
, quirk_nopciamd
);
114 * Triton requires workarounds to be used by the drivers
116 static void __devinit
quirk_triton(struct pci_dev
*dev
)
118 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
119 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
120 pci_pci_problems
|= PCIPCI_TRITON
;
123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
125 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
126 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
129 * VIA Apollo KT133 needs PCI latency patch
130 * Made according to a windows driver based patch by George E. Breese
131 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
132 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
133 * the info on which Mr Breese based his work.
135 * Updated based on further information from the site and also on
136 * information provided by VIA
138 static void quirk_vialatency(struct pci_dev
*dev
)
143 /* Ok we have a potential problem chipset here. Now see if we have
144 a buggy southbridge */
146 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
148 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
150 /* Check for buggy part revisions */
151 if (rev
< 0x40 || rev
> 0x42)
154 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
155 if (p
==NULL
) /* No problem parts */
157 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
158 /* Check for buggy part revisions */
159 if (rev
< 0x10 || rev
> 0x12)
164 * Ok we have the problem. Now set the PCI master grant to
165 * occur every master grant. The apparent bug is that under high
166 * PCI load (quite common in Linux of course) you can get data
167 * loss when the CPU is held off the bus for 3 bus master requests
168 * This happens to include the IDE controllers....
170 * VIA only apply this fix when an SB Live! is present but under
171 * both Linux and Windows this isnt enough, and we have seen
172 * corruption without SB Live! but with things like 3 UDMA IDE
173 * controllers. So we ignore that bit of the VIA recommendation..
176 pci_read_config_byte(dev
, 0x76, &busarb
);
177 /* Set bit 4 and bi 5 of byte 76 to 0x01
178 "Master priority rotation on every PCI master grant */
181 pci_write_config_byte(dev
, 0x76, busarb
);
182 printk(KERN_INFO
"Applying VIA southbridge workaround.\n");
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
189 /* Must restore this on a resume from RAM */
190 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
191 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
192 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
195 * VIA Apollo VP3 needs ETBF on BT848/878
197 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
199 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
200 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
201 pci_pci_problems
|= PCIPCI_VIAETBF
;
204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
206 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
208 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
209 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
210 pci_pci_problems
|= PCIPCI_VSFX
;
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
216 * Ali Magik requires workarounds to be used by the drivers
217 * that DMA to AGP space. Latency must be set to 0xA and triton
218 * workaround applied too
219 * [Info kindly provided by ALi]
221 static void __init
quirk_alimagik(struct pci_dev
*dev
)
223 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
224 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
225 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
232 * Natoma has some interesting boundary conditions with Zoran stuff
235 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
237 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
238 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
239 pci_pci_problems
|= PCIPCI_NATOMA
;
242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
250 * This chip can cause PCI parity errors if config register 0xA0 is read
251 * while DMAs are occurring.
253 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
255 dev
->cfg_size
= 0xA0;
257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
260 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
261 * If it's needed, re-allocate the region.
263 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
265 struct resource
*r
= &dev
->resource
[0];
267 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
275 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
276 unsigned size
, int nr
, const char *name
)
280 struct pci_bus_region bus_region
;
281 struct resource
*res
= dev
->resource
+ nr
;
283 res
->name
= pci_name(dev
);
285 res
->end
= region
+ size
- 1;
286 res
->flags
= IORESOURCE_IO
;
288 /* Convert from PCI bus to resource space. */
289 bus_region
.start
= res
->start
;
290 bus_region
.end
= res
->end
;
291 pcibios_bus_to_resource(dev
, res
, &bus_region
);
293 pci_claim_resource(dev
, nr
);
294 printk("PCI quirk: region %04x-%04x claimed by %s\n", region
, region
+ size
- 1, name
);
299 * ATI Northbridge setups MCE the processor if you even
300 * read somewhere between 0x3b0->0x3bb or read 0x3d3
302 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
304 printk(KERN_INFO
"ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
305 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
306 request_region(0x3b0, 0x0C, "RadeonIGP");
307 request_region(0x3d3, 0x01, "RadeonIGP");
309 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
312 * Let's make the southbridge information explicit instead
313 * of having to worry about people probing the ACPI areas,
314 * for example.. (Yes, it happens, and if you read the wrong
315 * ACPI register it will put the machine to sleep with no
316 * way of waking it up again. Bummer).
318 * ALI M7101: Two IO regions pointed to by words at
319 * 0xE0 (64 bytes of ACPI registers)
320 * 0xE2 (32 bytes of SMB registers)
322 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
326 pci_read_config_word(dev
, 0xE0, ®ion
);
327 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
328 pci_read_config_word(dev
, 0xE2, ®ion
);
329 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
333 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
336 u32 mask
, size
, base
;
338 pci_read_config_dword(dev
, port
, &devres
);
339 if ((devres
& enable
) != enable
)
341 mask
= (devres
>> 16) & 15;
342 base
= devres
& 0xffff;
345 unsigned bit
= size
>> 1;
346 if ((bit
& mask
) == bit
)
351 * For now we only print it out. Eventually we'll want to
352 * reserve it (at least if it's in the 0x1000+ range), but
353 * let's get enough confirmation reports first.
356 printk("%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
359 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
362 u32 mask
, size
, base
;
364 pci_read_config_dword(dev
, port
, &devres
);
365 if ((devres
& enable
) != enable
)
367 base
= devres
& 0xffff0000;
368 mask
= (devres
& 0x3f) << 16;
371 unsigned bit
= size
>> 1;
372 if ((bit
& mask
) == bit
)
377 * For now we only print it out. Eventually we'll want to
378 * reserve it, but let's get enough confirmation reports first.
381 printk("%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
385 * PIIX4 ACPI: Two IO regions pointed to by longwords at
386 * 0x40 (64 bytes of ACPI registers)
387 * 0x90 (16 bytes of SMB registers)
388 * and a few strange programmable PIIX4 device resources.
390 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
394 pci_read_config_dword(dev
, 0x40, ®ion
);
395 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
396 pci_read_config_dword(dev
, 0x90, ®ion
);
397 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
399 /* Device resource A has enables for some of the other ones */
400 pci_read_config_dword(dev
, 0x5c, &res_a
);
402 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
403 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
405 /* Device resource D is just bitfields for static resources */
407 /* Device 12 enabled? */
408 if (res_a
& (1 << 29)) {
409 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
410 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
412 /* Device 13 enabled? */
413 if (res_a
& (1 << 30)) {
414 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
415 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
417 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
418 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
424 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
425 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
426 * 0x58 (64 bytes of GPIO I/O space)
428 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
432 pci_read_config_dword(dev
, 0x40, ®ion
);
433 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH4 ACPI/GPIO/TCO");
435 pci_read_config_dword(dev
, 0x58, ®ion
);
436 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH4 GPIO");
438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
445 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
449 static void __devinit
quirk_ich6_lpc_acpi(struct pci_dev
*dev
)
453 pci_read_config_dword(dev
, 0x40, ®ion
);
454 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH6 ACPI/GPIO/TCO");
456 pci_read_config_dword(dev
, 0x48, ®ion
);
457 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH6 GPIO");
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
, quirk_ich6_lpc_acpi
);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc_acpi
);
461 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
, quirk_ich6_lpc_acpi
);
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
, quirk_ich6_lpc_acpi
);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
, quirk_ich6_lpc_acpi
);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_0
, quirk_ich6_lpc_acpi
);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_2
, quirk_ich6_lpc_acpi
);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_3
, quirk_ich6_lpc_acpi
);
469 * VIA ACPI: One IO region pointed to by longword at
470 * 0x48 or 0x20 (256 bytes of ACPI registers)
472 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
477 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rev
);
479 pci_read_config_dword(dev
, 0x48, ®ion
);
480 region
&= PCI_BASE_ADDRESS_IO_MASK
;
481 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
487 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
488 * 0x48 (256 bytes of ACPI registers)
489 * 0x70 (128 bytes of hardware monitoring register)
490 * 0x90 (16 bytes of SMB registers)
492 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
497 quirk_vt82c586_acpi(dev
);
499 pci_read_config_word(dev
, 0x70, &hm
);
500 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
501 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
503 pci_read_config_dword(dev
, 0x90, &smb
);
504 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
505 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
510 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
511 * 0x88 (128 bytes of power management registers)
512 * 0xd0 (16 bytes of SMB registers)
514 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
518 pci_read_config_word(dev
, 0x88, &pm
);
519 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
520 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
522 pci_read_config_word(dev
, 0xd0, &smb
);
523 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
524 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
526 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
529 #ifdef CONFIG_X86_IO_APIC
531 #include <asm/io_apic.h>
534 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
535 * devices to the external APIC.
537 * TODO: When we have device-specific interrupt routers,
538 * this code will go away from quirks.
540 static void quirk_via_ioapic(struct pci_dev
*dev
)
545 tmp
= 0; /* nothing routed to external APIC */
547 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
549 printk(KERN_INFO
"PCI: %sbling Via external APIC routing\n",
550 tmp
== 0 ? "Disa" : "Ena");
552 /* Offset 0x58: External APIC IRQ output control */
553 pci_write_config_byte (dev
, 0x58, tmp
);
555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
556 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
559 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
560 * This leads to doubled level interrupt rates.
561 * Set this bit to get rid of cycle wastage.
562 * Otherwise uncritical.
564 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
567 #define BYPASS_APIC_DEASSERT 8
569 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
570 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
571 printk(KERN_INFO
"PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
572 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
576 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
579 * The AMD io apic can hang the box when an apic irq is masked.
580 * We check all revs >= B0 (yet not in the pre production!) as the bug
581 * is currently marked NoFix
583 * We have multiple reports of hangs with this chipset that went away with
584 * noapic specified. For the moment we assume it's the erratum. We may be wrong
585 * of course. However the advice is demonstrably good even if so..
587 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
591 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
593 printk(KERN_WARNING
"I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
594 printk(KERN_WARNING
" : booting with the \"noapic\" option.\n");
597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
599 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
601 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
606 #define AMD8131_revA0 0x01
607 #define AMD8131_revB0 0x11
608 #define AMD8131_MISC 0x40
609 #define AMD8131_NIOAMODE_BIT 0
610 static void quirk_amd_8131_ioapic(struct pci_dev
*dev
)
612 unsigned char revid
, tmp
;
617 pci_read_config_byte(dev
, PCI_REVISION_ID
, &revid
);
618 if (revid
== AMD8131_revA0
|| revid
== AMD8131_revB0
) {
619 printk(KERN_INFO
"Fixing up AMD8131 IOAPIC mode\n");
620 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
621 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
622 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
626 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
627 #endif /* CONFIG_X86_IO_APIC */
631 * FIXME: it is questionable that quirk_via_acpi
632 * is needed. It shows up as an ISA bridge, and does not
633 * support the PCI_INTERRUPT_LINE register at all. Therefore
634 * it seems like setting the pci_dev's 'irq' to the
635 * value of the ACPI SCI interrupt is only done for convenience.
638 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
641 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
644 pci_read_config_byte(d
, 0x42, &irq
);
646 if (irq
&& (irq
!= 2))
649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
654 * VIA bridges which have VLink
657 static const struct pci_device_id via_vlink_fixup_tbl
[] = {
658 /* Internal devices need IRQ line routing, pre VLink */
659 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_82C686
), 0 },
660 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8231
), 17 },
661 /* Devices with VLink */
662 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8233_0
), 17},
663 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8233A
), 17 },
664 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8233C_0
), 17 },
665 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8235
), 16 },
666 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8237
), 15 },
667 { PCI_VDEVICE(VIA
, PCI_DEVICE_ID_VIA_8237A
), 15 },
672 * quirk_via_vlink - VIA VLink IRQ number update
675 * If the device we are dealing with is on a PIC IRQ we need to
676 * ensure that the IRQ line register which usually is not relevant
677 * for PCI cards, is actually written so that interrupts get sent
681 static void quirk_via_vlink(struct pci_dev
*dev
)
683 const struct pci_device_id
*via_vlink_fixup
;
684 static int dev_lo
= -1, dev_hi
= 18;
687 /* Check if we have VLink and cache the result */
689 /* Checked already - no */
693 /* Not checked - see what bridge we have and find the device
697 via_vlink_fixup
= pci_find_present(via_vlink_fixup_tbl
);
698 if (via_vlink_fixup
== NULL
) {
702 dev_lo
= via_vlink_fixup
->driver_data
;
703 /* 82C686 is special - 0/0 */
709 /* Don't quirk interrupts outside the legacy IRQ range */
710 if (!new_irq
|| new_irq
> 15)
713 /* Internal device ? */
714 if (dev
->bus
->number
!= 0 || PCI_SLOT(dev
->devfn
) > dev_hi
||
715 PCI_SLOT(dev
->devfn
) < dev_lo
)
718 /* This is an internal VLink device on a PIC interrupt. The BIOS
719 ought to have set this but may not have, so we redo it */
721 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
722 if (new_irq
!= irq
) {
723 printk(KERN_INFO
"PCI: VIA VLink IRQ fixup for %s, from %d to %d\n",
724 pci_name(dev
), irq
, new_irq
);
725 udelay(15); /* unknown if delay really needed */
726 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
729 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_ANY_ID
, quirk_via_vlink
);
732 * VIA VT82C598 has its device ID settable and many BIOSes
733 * set it to the ID of VT82C597 for backward compatibility.
734 * We need to switch it off to be able to recognize the real
737 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
739 pci_write_config_byte(dev
, 0xfc, 0);
740 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
742 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
745 * CardBus controllers have a legacy base address that enables them
746 * to respond as i82365 pcmcia controllers. We don't want them to
747 * do this even if the Linux CardBus driver is not loaded, because
748 * the Linux i82365 driver does not (and should not) handle CardBus.
750 static void quirk_cardbus_legacy(struct pci_dev
*dev
)
752 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
754 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
756 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
757 DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
760 * Following the PCI ordering rules is optional on the AMD762. I'm not
761 * sure what the designers were smoking but let's not inhale...
763 * To be fair to AMD, it follows the spec by default, its BIOS people
766 static void quirk_amd_ordering(struct pci_dev
*dev
)
769 pci_read_config_dword(dev
, 0x4C, &pcic
);
772 printk(KERN_WARNING
"BIOS failed to enable PCI standards compliance, fixing this error.\n");
773 pci_write_config_dword(dev
, 0x4C, pcic
);
774 pci_read_config_dword(dev
, 0x84, &pcic
);
775 pcic
|= (1<<23); /* Required in this mode */
776 pci_write_config_dword(dev
, 0x84, pcic
);
779 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
780 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
783 * DreamWorks provided workaround for Dunord I-3000 problem
785 * This card decodes and responds to addresses not apparently
786 * assigned to it. We force a larger allocation to ensure that
787 * nothing gets put too close to it.
789 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
791 struct resource
*r
= &dev
->resource
[1];
795 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
798 * i82380FB mobile docking controller: its PCI-to-PCI bridge
799 * is subtractive decoding (transparent), and does indicate this
800 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
803 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
805 dev
->transparent
= 1;
807 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
808 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
811 * Common misconfiguration of the MediaGX/Geode PCI master that will
812 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
813 * datasheets found at http://www.national.com/ds/GX for info on what
814 * these bits do. <christer@weinigel.se>
816 static void quirk_mediagx_master(struct pci_dev
*dev
)
819 pci_read_config_byte(dev
, 0x41, ®
);
822 printk(KERN_INFO
"PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
823 pci_write_config_byte(dev
, 0x41, reg
);
826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
827 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
830 * Ensure C0 rev restreaming is off. This is normally done by
831 * the BIOS but in the odd case it is not the results are corruption
832 * hence the presence of a Linux check
834 static void quirk_disable_pxb(struct pci_dev
*pdev
)
839 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
840 if (rev
!= 0x04) /* Only C0 requires this */
842 pci_read_config_word(pdev
, 0x40, &config
);
843 if (config
& (1<<6)) {
845 pci_write_config_word(pdev
, 0x40, config
);
846 printk(KERN_INFO
"PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
850 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
853 static void __devinit
quirk_sb600_sata(struct pci_dev
*pdev
)
855 /* set sb600 sata to ahci mode */
856 if ((pdev
->class >> 8) == PCI_CLASS_STORAGE_IDE
) {
859 pci_read_config_byte(pdev
, 0x40, &tmp
);
860 pci_write_config_byte(pdev
, 0x40, tmp
|1);
861 pci_write_config_byte(pdev
, 0x9, 1);
862 pci_write_config_byte(pdev
, 0xa, 6);
863 pci_write_config_byte(pdev
, 0x40, tmp
);
865 pdev
->class = 0x010601;
868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP600_SATA
, quirk_sb600_sata
);
871 * Serverworks CSB5 IDE does not fully support native mode
873 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
876 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
880 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
881 /* PCI layer will sort out resources */
884 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
887 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
889 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
893 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
895 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
896 printk(KERN_INFO
"PCI: IDE mode mismatch; forcing legacy mode\n");
899 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
902 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
904 /* This was originally an Alpha specific thing, but it really fits here.
905 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
907 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
909 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
914 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
915 * when a PCI-Soundcard is added. The BIOS only gives Options
916 * "Disabled" and "AUTO". This Quirk Sets the corresponding
917 * Register-Value to enable the Soundcard.
919 * FIXME: Presently this quirk will run on anything that has an 8237
920 * which isn't correct, we need to check DMI tables or something in
921 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
922 * runs everywhere at present we suppress the printk output in most
925 static void k8t_sound_hostbridge(struct pci_dev
*dev
)
929 pci_read_config_byte(dev
, 0x50, &val
);
930 if (val
== 0x88 || val
== 0xc8) {
931 /* Assume it's probably a MSI-K8T-Neo2Fir */
932 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
933 pci_write_config_byte(dev
, 0x50, val
& (~0x40));
935 /* Verify the Change for Status output */
936 pci_read_config_byte(dev
, 0x50, &val
);
938 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
940 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, soundcard on\n");
943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, k8t_sound_hostbridge
);
944 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, k8t_sound_hostbridge
);
947 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
948 * is not activated. The myth is that Asus said that they do not want the
949 * users to be irritated by just another PCI Device in the Win98 device
950 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
951 * package 2.7.0 for details)
953 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
954 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
955 * becomes necessary to do this tweak in two steps -- I've chosen the Host
958 static int __initdata asus_hides_smbus
;
960 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
962 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
963 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
964 switch(dev
->subsystem_device
) {
965 case 0x8025: /* P4B-LX */
966 case 0x8070: /* P4B */
967 case 0x8088: /* P4B533 */
968 case 0x1626: /* L3C notebook */
969 asus_hides_smbus
= 1;
971 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
972 switch(dev
->subsystem_device
) {
973 case 0x80b1: /* P4GE-V */
974 case 0x80b2: /* P4PE */
975 case 0x8093: /* P4B533-V */
976 asus_hides_smbus
= 1;
978 if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
979 switch(dev
->subsystem_device
) {
980 case 0x8030: /* P4T533 */
981 asus_hides_smbus
= 1;
983 if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
984 switch (dev
->subsystem_device
) {
985 case 0x8070: /* P4G8X Deluxe */
986 asus_hides_smbus
= 1;
988 if (dev
->device
== PCI_DEVICE_ID_INTEL_E7501_MCH
)
989 switch (dev
->subsystem_device
) {
990 case 0x80c9: /* PU-DLS */
991 asus_hides_smbus
= 1;
993 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
994 switch (dev
->subsystem_device
) {
995 case 0x1751: /* M2N notebook */
996 case 0x1821: /* M5N notebook */
997 asus_hides_smbus
= 1;
999 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1000 switch (dev
->subsystem_device
) {
1001 case 0x184b: /* W1N notebook */
1002 case 0x186a: /* M6Ne notebook */
1003 asus_hides_smbus
= 1;
1005 if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
) {
1006 switch (dev
->subsystem_device
) {
1007 case 0x1882: /* M6V notebook */
1008 case 0x1977: /* A6VA notebook */
1009 asus_hides_smbus
= 1;
1012 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1013 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1014 switch(dev
->subsystem_device
) {
1015 case 0x088C: /* HP Compaq nc8000 */
1016 case 0x0890: /* HP Compaq nc6000 */
1017 asus_hides_smbus
= 1;
1019 if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1020 switch (dev
->subsystem_device
) {
1021 case 0x12bc: /* HP D330L */
1022 case 0x12bd: /* HP D530 */
1023 asus_hides_smbus
= 1;
1025 if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
) {
1026 switch (dev
->subsystem_device
) {
1027 case 0x099c: /* HP Compaq nx6110 */
1028 asus_hides_smbus
= 1;
1031 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_TOSHIBA
)) {
1032 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1033 switch(dev
->subsystem_device
) {
1034 case 0x0001: /* Toshiba Satellite A40 */
1035 asus_hides_smbus
= 1;
1037 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1038 switch(dev
->subsystem_device
) {
1039 case 0x0001: /* Toshiba Tecra M2 */
1040 asus_hides_smbus
= 1;
1042 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1043 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1044 switch(dev
->subsystem_device
) {
1045 case 0xC00C: /* Samsung P35 notebook */
1046 asus_hides_smbus
= 1;
1048 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1049 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1050 switch(dev
->subsystem_device
) {
1051 case 0x0058: /* Compaq Evo N620c */
1052 asus_hides_smbus
= 1;
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7501_MCH
, asus_hides_smbus_hostbridge
);
1062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1066 static void asus_hides_smbus_lpc(struct pci_dev
*dev
)
1070 if (likely(!asus_hides_smbus
))
1073 pci_read_config_word(dev
, 0xF2, &val
);
1075 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1076 pci_read_config_word(dev
, 0xF2, &val
);
1078 printk(KERN_INFO
"PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1080 printk(KERN_INFO
"PCI: Enabled i801 SMBus device\n");
1083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1088 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1089 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1090 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1091 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, asus_hides_smbus_lpc
);
1092 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1093 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1094 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1096 static void asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1101 if (likely(!asus_hides_smbus
))
1103 pci_read_config_dword(dev
, 0xF0, &rcba
);
1104 base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1105 if (base
== NULL
) return;
1106 val
=readl(base
+ 0x3418); /* read the Function Disable register, dword mode only */
1107 writel(val
& 0xFFFFFFF7, base
+ 0x3418); /* enable the SMBus device */
1109 printk(KERN_INFO
"PCI: Enabled ICH6/i801 SMBus device\n");
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1112 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1115 * SiS 96x south bridge: BIOS typically hides SMBus device...
1117 static void quirk_sis_96x_smbus(struct pci_dev
*dev
)
1120 pci_read_config_byte(dev
, 0x77, &val
);
1122 printk(KERN_INFO
"Enabling SiS 96x SMBus.\n");
1123 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1128 * ... This is further complicated by the fact that some SiS96x south
1129 * bridges pretend to be 85C503/5513 instead. In that case see if we
1130 * spotted a compatible north bridge to make sure.
1131 * (pci_find_device doesn't work yet)
1133 * We can also enable the sis96x bit in the discovery register..
1135 static int __devinitdata sis_96x_compatible
= 0;
1137 #define SIS_DETECT_REGISTER 0x40
1139 static void quirk_sis_503(struct pci_dev
*dev
)
1144 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1145 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1146 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1147 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1148 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1152 /* Make people aware that we changed the config.. */
1153 printk(KERN_WARNING
"Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid
, sis_96x_compatible
);
1156 * Ok, it now shows up as a 96x.. run the 96x quirk by
1157 * hand in case it has already been processed.
1158 * (depends on link order, which is apparently not guaranteed)
1160 dev
->device
= devid
;
1161 quirk_sis_96x_smbus(dev
);
1164 static void __init
quirk_sis_96x_compatible(struct pci_dev
*dev
)
1166 sis_96x_compatible
= 1;
1168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_645
, quirk_sis_96x_compatible
);
1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_646
, quirk_sis_96x_compatible
);
1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_648
, quirk_sis_96x_compatible
);
1171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_650
, quirk_sis_96x_compatible
);
1172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_651
, quirk_sis_96x_compatible
);
1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_735
, quirk_sis_96x_compatible
);
1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1176 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1178 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1179 * and MC97 modem controller are disabled when a second PCI soundcard is
1180 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1183 static void asus_hides_ac97_lpc(struct pci_dev
*dev
)
1186 int asus_hides_ac97
= 0;
1188 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1189 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1190 asus_hides_ac97
= 1;
1193 if (!asus_hides_ac97
)
1196 pci_read_config_byte(dev
, 0x50, &val
);
1198 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1199 pci_read_config_byte(dev
, 0x50, &val
);
1201 printk(KERN_INFO
"PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1203 printk(KERN_INFO
"PCI: enabled onboard AC97/MC97 devices\n");
1206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1214 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1217 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1218 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1219 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1220 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1222 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1225 * If we are using libata we can drive this chip properly but must
1226 * do this early on to make the additional device appear during
1230 static void quirk_jmicron_dualfn(struct pci_dev
*pdev
)
1235 /* Only poke fn 0 */
1236 if (PCI_FUNC(pdev
->devfn
))
1239 switch(pdev
->device
) {
1240 case PCI_DEVICE_ID_JMICRON_JMB365
:
1241 case PCI_DEVICE_ID_JMICRON_JMB366
:
1242 /* Redirect IDE second PATA port to the right spot */
1243 pci_read_config_dword(pdev
, 0x80, &conf
);
1246 pci_write_config_dword(pdev
, 0x80, conf
);
1247 case PCI_DEVICE_ID_JMICRON_JMB361
:
1248 case PCI_DEVICE_ID_JMICRON_JMB363
:
1249 pci_read_config_dword(pdev
, 0x40, &conf
);
1250 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1251 /* Set the class codes correctly and then direct IDE 0 */
1252 conf
&= ~0x000F0200; /* Clear bit 9 and 16-19 */
1253 conf
|= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1254 pci_write_config_dword(pdev
, 0x40, conf
);
1256 /* Reconfigure so that the PCI scanner discovers the
1257 device is now multifunction */
1259 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1260 pdev
->hdr_type
= hdr
& 0x7f;
1261 pdev
->multifunction
= !!(hdr
& 0x80);
1267 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, quirk_jmicron_dualfn
);
1268 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, quirk_jmicron_dualfn
);
1272 #ifdef CONFIG_X86_IO_APIC
1273 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1277 if ((pdev
->class >> 8) != 0xff00)
1280 /* the first BAR is the location of the IO APIC...we must
1281 * not touch this (and it's already covered by the fixmap), so
1282 * forcibly insert it into the resource tree */
1283 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1284 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1286 /* The next five BARs all seem to be rubbish, so just clean
1288 for (i
=1; i
< 6; i
++) {
1289 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1296 enum ide_combined_type
{ COMBINED
= 0, IDE
= 1, LIBATA
= 2 };
1297 /* Defaults to combined */
1298 static enum ide_combined_type combined_mode
;
1300 static int __init
combined_setup(char *str
)
1302 if (!strncmp(str
, "ide", 3))
1303 combined_mode
= IDE
;
1304 else if (!strncmp(str
, "libata", 6))
1305 combined_mode
= LIBATA
;
1306 else /* "combined" or anything else defaults to old behavior */
1307 combined_mode
= COMBINED
;
1311 __setup("combined_mode=", combined_setup
);
1313 #ifdef CONFIG_SATA_INTEL_COMBINED
1314 static void __devinit
quirk_intel_ide_combined(struct pci_dev
*pdev
)
1320 * Narrow down to Intel SATA PCI devices.
1322 switch (pdev
->device
) {
1323 /* PCI ids taken from drivers/scsi/ata_piix.c */
1333 case 0x2680: /* ESB2 */
1340 case 0x2828: /* ICH8M */
1344 /* we do not handle this PCI device */
1349 * Read combined mode register.
1351 pci_read_config_byte(pdev
, 0x90, &tmp
); /* combined mode reg */
1354 tmp
&= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1355 if (tmp
== 0x4) /* bits 10x */
1356 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1357 else if (tmp
== 0x6) /* bits 11x */
1358 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1360 return; /* not in combined mode */
1362 WARN_ON((ich
!= 6) && (ich
!= 7) && (ich
!= 8));
1363 tmp
&= 0x3; /* interesting bits 1:0 */
1365 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1366 else if (tmp
& (1 << 1))
1367 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1369 return; /* not in combined mode */
1373 * Read programming interface register.
1374 * (Tells us if it's legacy or native mode)
1376 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1378 /* if SATA port is in native mode, we're ok. */
1382 /* Don't reserve any so the IDE driver can get them (but only if
1383 * combined_mode=ide).
1385 if (combined_mode
== IDE
)
1388 /* Grab them both for libata if combined_mode=libata. */
1389 if (combined_mode
== LIBATA
) {
1390 request_region(0x1f0, 8, "libata"); /* port 0 */
1391 request_region(0x170, 8, "libata"); /* port 1 */
1395 /* SATA port is in legacy mode. Reserve port so that
1396 * IDE driver does not attempt to use it. If request_region
1397 * fails, it will be obvious at boot time, so we don't bother
1398 * checking return values.
1400 if (comb
== (1 << 0))
1401 request_region(0x1f0, 8, "libata"); /* port 0 */
1403 request_region(0x170, 8, "libata"); /* port 1 */
1405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_intel_ide_combined
);
1406 #endif /* CONFIG_SATA_INTEL_COMBINED */
1411 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1416 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1421 * It's possible for the MSI to get corrupted if shpc and acpi
1422 * are used together on certain PXH-based systems.
1424 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1426 disable_msi_mode(dev
, pci_find_capability(dev
, PCI_CAP_ID_MSI
),
1430 printk(KERN_WARNING
"PCI: PXH quirk detected, "
1431 "disabling MSI for SHPC device\n");
1433 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1434 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1435 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1436 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1437 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1440 * Some Intel PCI Express chipsets have trouble with downstream
1441 * device power management.
1443 static void quirk_intel_pcie_pm(struct pci_dev
* dev
)
1445 pci_pm_d3_delay
= 120;
1449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e2, quirk_intel_pcie_pm
);
1450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e3, quirk_intel_pcie_pm
);
1451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e4, quirk_intel_pcie_pm
);
1452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e5, quirk_intel_pcie_pm
);
1453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e6, quirk_intel_pcie_pm
);
1454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25e7, quirk_intel_pcie_pm
);
1455 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f7, quirk_intel_pcie_pm
);
1456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f8, quirk_intel_pcie_pm
);
1457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25f9, quirk_intel_pcie_pm
);
1458 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x25fa, quirk_intel_pcie_pm
);
1459 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2601, quirk_intel_pcie_pm
);
1460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2602, quirk_intel_pcie_pm
);
1461 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2603, quirk_intel_pcie_pm
);
1462 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2604, quirk_intel_pcie_pm
);
1463 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2605, quirk_intel_pcie_pm
);
1464 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2606, quirk_intel_pcie_pm
);
1465 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2607, quirk_intel_pcie_pm
);
1466 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2608, quirk_intel_pcie_pm
);
1467 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x2609, quirk_intel_pcie_pm
);
1468 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260a, quirk_intel_pcie_pm
);
1469 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, 0x260b, quirk_intel_pcie_pm
);
1471 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1473 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1474 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1477 * These Netmos parts are multiport serial devices with optional
1478 * parallel ports. Even when parallel ports are present, they
1479 * are identified as class SERIAL, which means the serial driver
1480 * will claim them. To prevent this, mark them as class OTHER.
1481 * These combo devices should be claimed by parport_serial.
1483 * The subdevice ID is of the form 0x00PS, where <P> is the number
1484 * of parallel ports and <S> is the number of serial ports.
1486 switch (dev
->device
) {
1487 case PCI_DEVICE_ID_NETMOS_9735
:
1488 case PCI_DEVICE_ID_NETMOS_9745
:
1489 case PCI_DEVICE_ID_NETMOS_9835
:
1490 case PCI_DEVICE_ID_NETMOS_9845
:
1491 case PCI_DEVICE_ID_NETMOS_9855
:
1492 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1494 printk(KERN_INFO
"PCI: Netmos %04x (%u parallel, "
1495 "%u serial); changing class SERIAL to OTHER "
1496 "(use parport_serial)\n",
1497 dev
->device
, num_parallel
, num_serial
);
1498 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1499 (dev
->class & 0xff);
1503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1505 static void __devinit
quirk_e100_interrupt(struct pci_dev
*dev
)
1512 switch (dev
->device
) {
1513 /* PCI IDs taken from drivers/net/e100.c */
1515 case 0x1030 ... 0x1034:
1516 case 0x1038 ... 0x103E:
1517 case 0x1050 ... 0x1057:
1519 case 0x1064 ... 0x106B:
1520 case 0x1091 ... 0x1095:
1533 * Some firmware hands off the e100 with interrupts enabled,
1534 * which can cause a flood of interrupts if packets are
1535 * received before the driver attaches to the device. So
1536 * disable all e100 interrupts here. The driver will
1537 * re-enable them when it's ready.
1539 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1540 pci_read_config_dword(dev
, PCI_BASE_ADDRESS_0
, &bar
);
1542 if (!(command
& PCI_COMMAND_MEMORY
) || !bar
)
1545 csr
= ioremap(bar
, 8);
1547 printk(KERN_WARNING
"PCI: Can't map %s e100 registers\n",
1552 cmd_hi
= readb(csr
+ 3);
1554 printk(KERN_WARNING
"PCI: Firmware left %s e100 interrupts "
1555 "enabled, disabling\n", pci_name(dev
));
1561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_e100_interrupt
);
1563 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1565 /* rev 1 ncr53c810 chips don't set the class at all which means
1566 * they don't get their resources remapped. Fix that here.
1569 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1570 printk(KERN_INFO
"NCR 53c810 rev 1 detected, setting PCI class.\n");
1571 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1574 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1576 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
1579 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
1580 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
1581 pr_debug("PCI: Calling quirk %p for %s\n", f
->hook
, pci_name(dev
));
1588 extern struct pci_fixup __start_pci_fixups_early
[];
1589 extern struct pci_fixup __end_pci_fixups_early
[];
1590 extern struct pci_fixup __start_pci_fixups_header
[];
1591 extern struct pci_fixup __end_pci_fixups_header
[];
1592 extern struct pci_fixup __start_pci_fixups_final
[];
1593 extern struct pci_fixup __end_pci_fixups_final
[];
1594 extern struct pci_fixup __start_pci_fixups_enable
[];
1595 extern struct pci_fixup __end_pci_fixups_enable
[];
1596 extern struct pci_fixup __start_pci_fixups_resume
[];
1597 extern struct pci_fixup __end_pci_fixups_resume
[];
1600 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1602 struct pci_fixup
*start
, *end
;
1605 case pci_fixup_early
:
1606 start
= __start_pci_fixups_early
;
1607 end
= __end_pci_fixups_early
;
1610 case pci_fixup_header
:
1611 start
= __start_pci_fixups_header
;
1612 end
= __end_pci_fixups_header
;
1615 case pci_fixup_final
:
1616 start
= __start_pci_fixups_final
;
1617 end
= __end_pci_fixups_final
;
1620 case pci_fixup_enable
:
1621 start
= __start_pci_fixups_enable
;
1622 end
= __end_pci_fixups_enable
;
1625 case pci_fixup_resume
:
1626 start
= __start_pci_fixups_resume
;
1627 end
= __end_pci_fixups_resume
;
1631 /* stupid compiler warning, you would think with an enum... */
1634 pci_do_fixups(dev
, start
, end
);
1637 /* Enable 1k I/O space granularity on the Intel P64H2 */
1638 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1641 u8 io_base_lo
, io_limit_lo
;
1642 unsigned long base
, limit
;
1643 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1645 pci_read_config_word(dev
, 0x40, &en1k
);
1648 printk(KERN_INFO
"PCI: Enable I/O Space to 1 KB Granularity\n");
1650 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1651 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1652 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1653 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1655 if (base
<= limit
) {
1657 res
->end
= limit
+ 0x3ff;
1661 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1663 /* Under some circumstances, AER is not linked with extended capabilities.
1664 * Force it to be linked by setting the corresponding control bit in the
1667 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
1670 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
1672 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
1674 "PCI: Linking AER extended capability on %s\n",
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1680 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1681 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1682 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1684 #ifdef CONFIG_PCI_MSI
1685 /* To disable MSI globally */
1688 /* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely
1689 * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1690 * some other busses controlled by the chipset even if Linux is not aware of it.
1691 * Instead of setting the flag on all busses in the machine, simply disable MSI
1694 static void __init
quirk_svw_msi(struct pci_dev
*dev
)
1697 printk(KERN_WARNING
"PCI: MSI quirk detected. pci_msi_quirk set.\n");
1699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_svw_msi
);
1701 /* Disable MSI on chipsets that are known to not support it */
1702 static void __devinit
quirk_disable_msi(struct pci_dev
*dev
)
1704 if (dev
->subordinate
) {
1705 printk(KERN_WARNING
"PCI: MSI quirk detected. "
1706 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1708 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_disable_msi
);
1713 /* Go through the list of Hypertransport capabilities and
1714 * return 1 if a HT MSI capability is found and enabled */
1715 static int __devinit
msi_ht_cap_enabled(struct pci_dev
*dev
)
1719 pos
= pci_find_ht_capability(dev
, HT_CAPTYPE_MSI_MAPPING
);
1720 while (pos
&& ttl
--) {
1723 if (pci_read_config_byte(dev
, pos
+ HT_MSI_FLAGS
,
1726 printk(KERN_INFO
"PCI: Found %s HT MSI Mapping on %s\n",
1727 flags
& HT_MSI_FLAGS_ENABLE
?
1728 "enabled" : "disabled", pci_name(dev
));
1729 return (flags
& HT_MSI_FLAGS_ENABLE
) != 0;
1732 pos
= pci_find_next_ht_capability(dev
, pos
,
1733 HT_CAPTYPE_MSI_MAPPING
);
1738 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1739 static void __devinit
quirk_msi_ht_cap(struct pci_dev
*dev
)
1741 if (dev
->subordinate
&& !msi_ht_cap_enabled(dev
)) {
1742 printk(KERN_WARNING
"PCI: MSI quirk detected. "
1743 "MSI disabled on chipset %s.\n",
1745 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1748 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
,
1751 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
1752 * MSI are supported if the MSI capability set in any of these mappings.
1754 static void __devinit
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev
*dev
)
1756 struct pci_dev
*pdev
;
1758 if (!dev
->subordinate
)
1761 /* check HT MSI cap on this chipset and the root one.
1762 * a single one having MSI is enough to be sure that MSI are supported.
1764 pdev
= pci_get_slot(dev
->bus
, 0);
1767 if (!msi_ht_cap_enabled(dev
) && !msi_ht_cap_enabled(pdev
)) {
1768 printk(KERN_WARNING
"PCI: MSI quirk detected. "
1769 "MSI disabled on chipset %s.\n",
1771 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
1775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1776 quirk_nvidia_ck804_msi_ht_cap
);
1777 #endif /* CONFIG_PCI_MSI */
1779 EXPORT_SYMBOL(pcie_mch_quirk
);
1780 #ifdef CONFIG_HOTPLUG
1781 EXPORT_SYMBOL(pci_fixup_device
);