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Merge branch 'xfs-O_TMPFILE-support' into for-next
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
1 /*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/export.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/acpi.h>
21 #include <linux/kallsyms.h>
22 #include <linux/dmi.h>
23 #include <linux/pci-aspm.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/ktime.h>
27 #include <asm/dma.h> /* isa_dma_bridge_buggy */
28 #include "pci.h"
29
30 /*
31 * Decoding should be disabled for a PCI device during BAR sizing to avoid
32 * conflict. But doing so may cause problems on host bridge and perhaps other
33 * key system devices. For devices that need to have mmio decoding always-on,
34 * we need to set the dev->mmio_always_on bit.
35 */
36 static void quirk_mmio_always_on(struct pci_dev *dev)
37 {
38 dev->mmio_always_on = 1;
39 }
40 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
41 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
42
43 /* The Mellanox Tavor device gives false positive parity errors
44 * Mark this device with a broken_parity_status, to allow
45 * PCI scanning code to "skip" this now blacklisted device.
46 */
47 static void quirk_mellanox_tavor(struct pci_dev *dev)
48 {
49 dev->broken_parity_status = 1; /* This device gives false positives */
50 }
51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
52 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
53
54 /* Deal with broken BIOSes that neglect to enable passive release,
55 which can cause problems in combination with the 82441FX/PPro MTRRs */
56 static void quirk_passive_release(struct pci_dev *dev)
57 {
58 struct pci_dev *d = NULL;
59 unsigned char dlc;
60
61 /* We have to make sure a particular bit is set in the PIIX3
62 ISA bridge, so we have to go out and find it. */
63 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
64 pci_read_config_byte(d, 0x82, &dlc);
65 if (!(dlc & 1<<1)) {
66 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
67 dlc |= 1<<1;
68 pci_write_config_byte(d, 0x82, dlc);
69 }
70 }
71 }
72 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
73 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74
75 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
76 but VIA don't answer queries. If you happen to have good contacts at VIA
77 ask them for me please -- Alan
78
79 This appears to be BIOS not version dependent. So presumably there is a
80 chipset level fix */
81
82 static void quirk_isa_dma_hangs(struct pci_dev *dev)
83 {
84 if (!isa_dma_bridge_buggy) {
85 isa_dma_bridge_buggy=1;
86 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
87 }
88 }
89 /*
90 * Its not totally clear which chipsets are the problematic ones
91 * We know 82C586 and 82C596 variants are affected.
92 */
93 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
94 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
100
101 /*
102 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
103 * for some HT machines to use C4 w/o hanging.
104 */
105 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
106 {
107 u32 pmbase;
108 u16 pm1a;
109
110 pci_read_config_dword(dev, 0x40, &pmbase);
111 pmbase = pmbase & 0xff80;
112 pm1a = inw(pmbase);
113
114 if (pm1a & 0x10) {
115 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
116 outw(0x10, pmbase);
117 }
118 }
119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
120
121 /*
122 * Chipsets where PCI->PCI transfers vanish or hang
123 */
124 static void quirk_nopcipci(struct pci_dev *dev)
125 {
126 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
127 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
128 pci_pci_problems |= PCIPCI_FAIL;
129 }
130 }
131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
133
134 static void quirk_nopciamd(struct pci_dev *dev)
135 {
136 u8 rev;
137 pci_read_config_byte(dev, 0x08, &rev);
138 if (rev == 0x13) {
139 /* Erratum 24 */
140 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
141 pci_pci_problems |= PCIAGP_FAIL;
142 }
143 }
144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
145
146 /*
147 * Triton requires workarounds to be used by the drivers
148 */
149 static void quirk_triton(struct pci_dev *dev)
150 {
151 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
152 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
153 pci_pci_problems |= PCIPCI_TRITON;
154 }
155 }
156 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
160
161 /*
162 * VIA Apollo KT133 needs PCI latency patch
163 * Made according to a windows driver based patch by George E. Breese
164 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
165 * and http://www.georgebreese.com/net/software/#PCI
166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
168 *
169 * Updated based on further information from the site and also on
170 * information provided by VIA
171 */
172 static void quirk_vialatency(struct pci_dev *dev)
173 {
174 struct pci_dev *p;
175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
178
179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
180 if (p!=NULL) {
181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
183 if (p->revision < 0x40 || p->revision > 0x42)
184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
187 if (p==NULL) /* No problem parts */
188 goto exit;
189 /* Check for buggy part revisions */
190 if (p->revision < 0x10 || p->revision > 0x12)
191 goto exit;
192 }
193
194 /*
195 * Ok we have the problem. Now set the PCI master grant to
196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
202 * both Linux and Windows this isn't enough, and we have seen
203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
208 /* Set bit 4 and bi 5 of byte 76 to 0x01
209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
214 exit:
215 pci_dev_put(p);
216 }
217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
220 /* Must restore this on a resume from RAM */
221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
224
225 /*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
228 static void quirk_viaetbf(struct pci_dev *dev)
229 {
230 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234 }
235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
236
237 static void quirk_vsfx(struct pci_dev *dev)
238 {
239 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243 }
244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
245
246 /*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
251 */
252 static void quirk_alimagik(struct pci_dev *dev)
253 {
254 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258 }
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
261
262 /*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
266 static void quirk_natoma(struct pci_dev *dev)
267 {
268 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272 }
273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
279
280 /*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
284 static void quirk_citrine(struct pci_dev *dev)
285 {
286 dev->cfg_size = 0xA0;
287 }
288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
289
290 /*
291 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
292 * If it's needed, re-allocate the region.
293 */
294 static void quirk_s3_64M(struct pci_dev *dev)
295 {
296 struct resource *r = &dev->resource[0];
297
298 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
299 r->start = 0;
300 r->end = 0x3ffffff;
301 }
302 }
303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
305
306 /*
307 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
308 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
309 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
310 * (which conflicts w/ BAR1's memory range).
311 */
312 static void quirk_cs5536_vsa(struct pci_dev *dev)
313 {
314 if (pci_resource_len(dev, 0) != 8) {
315 struct resource *res = &dev->resource[0];
316 res->end = res->start + 8 - 1;
317 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
318 "(incorrect header); workaround applied.\n");
319 }
320 }
321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
322
323 static void quirk_io_region(struct pci_dev *dev, int port,
324 unsigned size, int nr, const char *name)
325 {
326 u16 region;
327 struct pci_bus_region bus_region;
328 struct resource *res = dev->resource + nr;
329
330 pci_read_config_word(dev, port, &region);
331 region &= ~(size - 1);
332
333 if (!region)
334 return;
335
336 res->name = pci_name(dev);
337 res->flags = IORESOURCE_IO;
338
339 /* Convert from PCI bus to resource space */
340 bus_region.start = region;
341 bus_region.end = region + size - 1;
342 pcibios_bus_to_resource(dev->bus, res, &bus_region);
343
344 if (!pci_claim_resource(dev, nr))
345 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
346 }
347
348 /*
349 * ATI Northbridge setups MCE the processor if you even
350 * read somewhere between 0x3b0->0x3bb or read 0x3d3
351 */
352 static void quirk_ati_exploding_mce(struct pci_dev *dev)
353 {
354 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
355 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
356 request_region(0x3b0, 0x0C, "RadeonIGP");
357 request_region(0x3d3, 0x01, "RadeonIGP");
358 }
359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
360
361 /*
362 * Let's make the southbridge information explicit instead
363 * of having to worry about people probing the ACPI areas,
364 * for example.. (Yes, it happens, and if you read the wrong
365 * ACPI register it will put the machine to sleep with no
366 * way of waking it up again. Bummer).
367 *
368 * ALI M7101: Two IO regions pointed to by words at
369 * 0xE0 (64 bytes of ACPI registers)
370 * 0xE2 (32 bytes of SMB registers)
371 */
372 static void quirk_ali7101_acpi(struct pci_dev *dev)
373 {
374 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
375 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
376 }
377 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
378
379 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
380 {
381 u32 devres;
382 u32 mask, size, base;
383
384 pci_read_config_dword(dev, port, &devres);
385 if ((devres & enable) != enable)
386 return;
387 mask = (devres >> 16) & 15;
388 base = devres & 0xffff;
389 size = 16;
390 for (;;) {
391 unsigned bit = size >> 1;
392 if ((bit & mask) == bit)
393 break;
394 size = bit;
395 }
396 /*
397 * For now we only print it out. Eventually we'll want to
398 * reserve it (at least if it's in the 0x1000+ range), but
399 * let's get enough confirmation reports first.
400 */
401 base &= -size;
402 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
403 }
404
405 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
406 {
407 u32 devres;
408 u32 mask, size, base;
409
410 pci_read_config_dword(dev, port, &devres);
411 if ((devres & enable) != enable)
412 return;
413 base = devres & 0xffff0000;
414 mask = (devres & 0x3f) << 16;
415 size = 128 << 16;
416 for (;;) {
417 unsigned bit = size >> 1;
418 if ((bit & mask) == bit)
419 break;
420 size = bit;
421 }
422 /*
423 * For now we only print it out. Eventually we'll want to
424 * reserve it, but let's get enough confirmation reports first.
425 */
426 base &= -size;
427 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
428 }
429
430 /*
431 * PIIX4 ACPI: Two IO regions pointed to by longwords at
432 * 0x40 (64 bytes of ACPI registers)
433 * 0x90 (16 bytes of SMB registers)
434 * and a few strange programmable PIIX4 device resources.
435 */
436 static void quirk_piix4_acpi(struct pci_dev *dev)
437 {
438 u32 res_a;
439
440 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
441 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
442
443 /* Device resource A has enables for some of the other ones */
444 pci_read_config_dword(dev, 0x5c, &res_a);
445
446 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
447 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
448
449 /* Device resource D is just bitfields for static resources */
450
451 /* Device 12 enabled? */
452 if (res_a & (1 << 29)) {
453 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
454 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
455 }
456 /* Device 13 enabled? */
457 if (res_a & (1 << 30)) {
458 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
459 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
460 }
461 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
462 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
463 }
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
466
467 #define ICH_PMBASE 0x40
468 #define ICH_ACPI_CNTL 0x44
469 #define ICH4_ACPI_EN 0x10
470 #define ICH6_ACPI_EN 0x80
471 #define ICH4_GPIOBASE 0x58
472 #define ICH4_GPIO_CNTL 0x5c
473 #define ICH4_GPIO_EN 0x10
474 #define ICH6_GPIOBASE 0x48
475 #define ICH6_GPIO_CNTL 0x4c
476 #define ICH6_GPIO_EN 0x10
477
478 /*
479 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
480 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
481 * 0x58 (64 bytes of GPIO I/O space)
482 */
483 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
484 {
485 u8 enable;
486
487 /*
488 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
489 * with low legacy (and fixed) ports. We don't know the decoding
490 * priority and can't tell whether the legacy device or the one created
491 * here is really at that address. This happens on boards with broken
492 * BIOSes.
493 */
494
495 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
496 if (enable & ICH4_ACPI_EN)
497 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
498 "ICH4 ACPI/GPIO/TCO");
499
500 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
501 if (enable & ICH4_GPIO_EN)
502 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
503 "ICH4 GPIO");
504 }
505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
515
516 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
517 {
518 u8 enable;
519
520 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
521 if (enable & ICH6_ACPI_EN)
522 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
523 "ICH6 ACPI/GPIO/TCO");
524
525 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
526 if (enable & ICH6_GPIO_EN)
527 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
528 "ICH6 GPIO");
529 }
530
531 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
532 {
533 u32 val;
534 u32 size, base;
535
536 pci_read_config_dword(dev, reg, &val);
537
538 /* Enabled? */
539 if (!(val & 1))
540 return;
541 base = val & 0xfffc;
542 if (dynsize) {
543 /*
544 * This is not correct. It is 16, 32 or 64 bytes depending on
545 * register D31:F0:ADh bits 5:4.
546 *
547 * But this gets us at least _part_ of it.
548 */
549 size = 16;
550 } else {
551 size = 128;
552 }
553 base &= ~(size-1);
554
555 /* Just print it out for now. We should reserve it after more debugging */
556 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
557 }
558
559 static void quirk_ich6_lpc(struct pci_dev *dev)
560 {
561 /* Shared ACPI/GPIO decode with all ICH6+ */
562 ich6_lpc_acpi_gpio(dev);
563
564 /* ICH6-specific generic IO decode */
565 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
566 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
567 }
568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
570
571 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
572 {
573 u32 val;
574 u32 mask, base;
575
576 pci_read_config_dword(dev, reg, &val);
577
578 /* Enabled? */
579 if (!(val & 1))
580 return;
581
582 /*
583 * IO base in bits 15:2, mask in bits 23:18, both
584 * are dword-based
585 */
586 base = val & 0xfffc;
587 mask = (val >> 16) & 0xfc;
588 mask |= 3;
589
590 /* Just print it out for now. We should reserve it after more debugging */
591 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
592 }
593
594 /* ICH7-10 has the same common LPC generic IO decode registers */
595 static void quirk_ich7_lpc(struct pci_dev *dev)
596 {
597 /* We share the common ACPI/GPIO decode with ICH6 */
598 ich6_lpc_acpi_gpio(dev);
599
600 /* And have 4 ICH7+ generic decodes */
601 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
602 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
603 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
604 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
605 }
606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
607 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
608 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
609 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
610 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
619
620 /*
621 * VIA ACPI: One IO region pointed to by longword at
622 * 0x48 or 0x20 (256 bytes of ACPI registers)
623 */
624 static void quirk_vt82c586_acpi(struct pci_dev *dev)
625 {
626 if (dev->revision & 0x10)
627 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
628 "vt82c586 ACPI");
629 }
630 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
631
632 /*
633 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
634 * 0x48 (256 bytes of ACPI registers)
635 * 0x70 (128 bytes of hardware monitoring register)
636 * 0x90 (16 bytes of SMB registers)
637 */
638 static void quirk_vt82c686_acpi(struct pci_dev *dev)
639 {
640 quirk_vt82c586_acpi(dev);
641
642 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
643 "vt82c686 HW-mon");
644
645 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
646 }
647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
648
649 /*
650 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
651 * 0x88 (128 bytes of power management registers)
652 * 0xd0 (16 bytes of SMB registers)
653 */
654 static void quirk_vt8235_acpi(struct pci_dev *dev)
655 {
656 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
657 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
658 }
659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
660
661 /*
662 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
663 * Disable fast back-to-back on the secondary bus segment
664 */
665 static void quirk_xio2000a(struct pci_dev *dev)
666 {
667 struct pci_dev *pdev;
668 u16 command;
669
670 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
671 "secondary bus fast back-to-back transfers disabled\n");
672 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
673 pci_read_config_word(pdev, PCI_COMMAND, &command);
674 if (command & PCI_COMMAND_FAST_BACK)
675 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
676 }
677 }
678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
679 quirk_xio2000a);
680
681 #ifdef CONFIG_X86_IO_APIC
682
683 #include <asm/io_apic.h>
684
685 /*
686 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
687 * devices to the external APIC.
688 *
689 * TODO: When we have device-specific interrupt routers,
690 * this code will go away from quirks.
691 */
692 static void quirk_via_ioapic(struct pci_dev *dev)
693 {
694 u8 tmp;
695
696 if (nr_ioapics < 1)
697 tmp = 0; /* nothing routed to external APIC */
698 else
699 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
700
701 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
702 tmp == 0 ? "Disa" : "Ena");
703
704 /* Offset 0x58: External APIC IRQ output control */
705 pci_write_config_byte (dev, 0x58, tmp);
706 }
707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
708 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
709
710 /*
711 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
712 * This leads to doubled level interrupt rates.
713 * Set this bit to get rid of cycle wastage.
714 * Otherwise uncritical.
715 */
716 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
717 {
718 u8 misc_control2;
719 #define BYPASS_APIC_DEASSERT 8
720
721 pci_read_config_byte(dev, 0x5B, &misc_control2);
722 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
723 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
724 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
725 }
726 }
727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
728 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
729
730 /*
731 * The AMD io apic can hang the box when an apic irq is masked.
732 * We check all revs >= B0 (yet not in the pre production!) as the bug
733 * is currently marked NoFix
734 *
735 * We have multiple reports of hangs with this chipset that went away with
736 * noapic specified. For the moment we assume it's the erratum. We may be wrong
737 * of course. However the advice is demonstrably good even if so..
738 */
739 static void quirk_amd_ioapic(struct pci_dev *dev)
740 {
741 if (dev->revision >= 0x02) {
742 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
743 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
744 }
745 }
746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
747
748 static void quirk_ioapic_rmw(struct pci_dev *dev)
749 {
750 if (dev->devfn == 0 && dev->bus->number == 0)
751 sis_apic_bug = 1;
752 }
753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
754 #endif /* CONFIG_X86_IO_APIC */
755
756 /*
757 * Some settings of MMRBC can lead to data corruption so block changes.
758 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
759 */
760 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
761 {
762 if (dev->subordinate && dev->revision <= 0x12) {
763 dev_info(&dev->dev, "AMD8131 rev %x detected; "
764 "disabling PCI-X MMRBC\n", dev->revision);
765 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
766 }
767 }
768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
769
770 /*
771 * FIXME: it is questionable that quirk_via_acpi
772 * is needed. It shows up as an ISA bridge, and does not
773 * support the PCI_INTERRUPT_LINE register at all. Therefore
774 * it seems like setting the pci_dev's 'irq' to the
775 * value of the ACPI SCI interrupt is only done for convenience.
776 * -jgarzik
777 */
778 static void quirk_via_acpi(struct pci_dev *d)
779 {
780 /*
781 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
782 */
783 u8 irq;
784 pci_read_config_byte(d, 0x42, &irq);
785 irq &= 0xf;
786 if (irq && (irq != 2))
787 d->irq = irq;
788 }
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
791
792
793 /*
794 * VIA bridges which have VLink
795 */
796
797 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
798
799 static void quirk_via_bridge(struct pci_dev *dev)
800 {
801 /* See what bridge we have and find the device ranges */
802 switch (dev->device) {
803 case PCI_DEVICE_ID_VIA_82C686:
804 /* The VT82C686 is special, it attaches to PCI and can have
805 any device number. All its subdevices are functions of
806 that single device. */
807 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
808 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
809 break;
810 case PCI_DEVICE_ID_VIA_8237:
811 case PCI_DEVICE_ID_VIA_8237A:
812 via_vlink_dev_lo = 15;
813 break;
814 case PCI_DEVICE_ID_VIA_8235:
815 via_vlink_dev_lo = 16;
816 break;
817 case PCI_DEVICE_ID_VIA_8231:
818 case PCI_DEVICE_ID_VIA_8233_0:
819 case PCI_DEVICE_ID_VIA_8233A:
820 case PCI_DEVICE_ID_VIA_8233C_0:
821 via_vlink_dev_lo = 17;
822 break;
823 }
824 }
825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
833
834 /**
835 * quirk_via_vlink - VIA VLink IRQ number update
836 * @dev: PCI device
837 *
838 * If the device we are dealing with is on a PIC IRQ we need to
839 * ensure that the IRQ line register which usually is not relevant
840 * for PCI cards, is actually written so that interrupts get sent
841 * to the right place.
842 * We only do this on systems where a VIA south bridge was detected,
843 * and only for VIA devices on the motherboard (see quirk_via_bridge
844 * above).
845 */
846
847 static void quirk_via_vlink(struct pci_dev *dev)
848 {
849 u8 irq, new_irq;
850
851 /* Check if we have VLink at all */
852 if (via_vlink_dev_lo == -1)
853 return;
854
855 new_irq = dev->irq;
856
857 /* Don't quirk interrupts outside the legacy IRQ range */
858 if (!new_irq || new_irq > 15)
859 return;
860
861 /* Internal device ? */
862 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
863 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
864 return;
865
866 /* This is an internal VLink device on a PIC interrupt. The BIOS
867 ought to have set this but may not have, so we redo it */
868
869 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
870 if (new_irq != irq) {
871 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
872 irq, new_irq);
873 udelay(15); /* unknown if delay really needed */
874 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
875 }
876 }
877 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
878
879 /*
880 * VIA VT82C598 has its device ID settable and many BIOSes
881 * set it to the ID of VT82C597 for backward compatibility.
882 * We need to switch it off to be able to recognize the real
883 * type of the chip.
884 */
885 static void quirk_vt82c598_id(struct pci_dev *dev)
886 {
887 pci_write_config_byte(dev, 0xfc, 0);
888 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
889 }
890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
891
892 /*
893 * CardBus controllers have a legacy base address that enables them
894 * to respond as i82365 pcmcia controllers. We don't want them to
895 * do this even if the Linux CardBus driver is not loaded, because
896 * the Linux i82365 driver does not (and should not) handle CardBus.
897 */
898 static void quirk_cardbus_legacy(struct pci_dev *dev)
899 {
900 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
901 }
902 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
903 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
904 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
905 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
906
907 /*
908 * Following the PCI ordering rules is optional on the AMD762. I'm not
909 * sure what the designers were smoking but let's not inhale...
910 *
911 * To be fair to AMD, it follows the spec by default, its BIOS people
912 * who turn it off!
913 */
914 static void quirk_amd_ordering(struct pci_dev *dev)
915 {
916 u32 pcic;
917 pci_read_config_dword(dev, 0x4C, &pcic);
918 if ((pcic&6)!=6) {
919 pcic |= 6;
920 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
921 pci_write_config_dword(dev, 0x4C, pcic);
922 pci_read_config_dword(dev, 0x84, &pcic);
923 pcic |= (1<<23); /* Required in this mode */
924 pci_write_config_dword(dev, 0x84, pcic);
925 }
926 }
927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
928 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
929
930 /*
931 * DreamWorks provided workaround for Dunord I-3000 problem
932 *
933 * This card decodes and responds to addresses not apparently
934 * assigned to it. We force a larger allocation to ensure that
935 * nothing gets put too close to it.
936 */
937 static void quirk_dunord(struct pci_dev *dev)
938 {
939 struct resource *r = &dev->resource [1];
940 r->start = 0;
941 r->end = 0xffffff;
942 }
943 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
944
945 /*
946 * i82380FB mobile docking controller: its PCI-to-PCI bridge
947 * is subtractive decoding (transparent), and does indicate this
948 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
949 * instead of 0x01.
950 */
951 static void quirk_transparent_bridge(struct pci_dev *dev)
952 {
953 dev->transparent = 1;
954 }
955 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
956 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
957
958 /*
959 * Common misconfiguration of the MediaGX/Geode PCI master that will
960 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
961 * datasheets found at http://www.national.com/analog for info on what
962 * these bits do. <christer@weinigel.se>
963 */
964 static void quirk_mediagx_master(struct pci_dev *dev)
965 {
966 u8 reg;
967 pci_read_config_byte(dev, 0x41, &reg);
968 if (reg & 2) {
969 reg &= ~2;
970 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
971 pci_write_config_byte(dev, 0x41, reg);
972 }
973 }
974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
975 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
976
977 /*
978 * Ensure C0 rev restreaming is off. This is normally done by
979 * the BIOS but in the odd case it is not the results are corruption
980 * hence the presence of a Linux check
981 */
982 static void quirk_disable_pxb(struct pci_dev *pdev)
983 {
984 u16 config;
985
986 if (pdev->revision != 0x04) /* Only C0 requires this */
987 return;
988 pci_read_config_word(pdev, 0x40, &config);
989 if (config & (1<<6)) {
990 config &= ~(1<<6);
991 pci_write_config_word(pdev, 0x40, config);
992 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
993 }
994 }
995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
996 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
997
998 static void quirk_amd_ide_mode(struct pci_dev *pdev)
999 {
1000 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1001 u8 tmp;
1002
1003 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1004 if (tmp == 0x01) {
1005 pci_read_config_byte(pdev, 0x40, &tmp);
1006 pci_write_config_byte(pdev, 0x40, tmp|1);
1007 pci_write_config_byte(pdev, 0x9, 1);
1008 pci_write_config_byte(pdev, 0xa, 6);
1009 pci_write_config_byte(pdev, 0x40, tmp);
1010
1011 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1012 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1013 }
1014 }
1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1016 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1018 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1020 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1022 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1023
1024 /*
1025 * Serverworks CSB5 IDE does not fully support native mode
1026 */
1027 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1028 {
1029 u8 prog;
1030 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1031 if (prog & 5) {
1032 prog &= ~5;
1033 pdev->class &= ~5;
1034 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1035 /* PCI layer will sort out resources */
1036 }
1037 }
1038 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1039
1040 /*
1041 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1042 */
1043 static void quirk_ide_samemode(struct pci_dev *pdev)
1044 {
1045 u8 prog;
1046
1047 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1048
1049 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1050 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1051 prog &= ~5;
1052 pdev->class &= ~5;
1053 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1054 }
1055 }
1056 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1057
1058 /*
1059 * Some ATA devices break if put into D3
1060 */
1061
1062 static void quirk_no_ata_d3(struct pci_dev *pdev)
1063 {
1064 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1065 }
1066 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1067 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1068 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1069 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1070 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1071 /* ALi loses some register settings that we cannot then restore */
1072 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1073 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1074 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1075 occur when mode detecting */
1076 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1077 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1078
1079 /* This was originally an Alpha specific thing, but it really fits here.
1080 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1081 */
1082 static void quirk_eisa_bridge(struct pci_dev *dev)
1083 {
1084 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1085 }
1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1087
1088
1089 /*
1090 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1091 * is not activated. The myth is that Asus said that they do not want the
1092 * users to be irritated by just another PCI Device in the Win98 device
1093 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1094 * package 2.7.0 for details)
1095 *
1096 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1097 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1098 * becomes necessary to do this tweak in two steps -- the chosen trigger
1099 * is either the Host bridge (preferred) or on-board VGA controller.
1100 *
1101 * Note that we used to unhide the SMBus that way on Toshiba laptops
1102 * (Satellite A40 and Tecra M2) but then found that the thermal management
1103 * was done by SMM code, which could cause unsynchronized concurrent
1104 * accesses to the SMBus registers, with potentially bad effects. Thus you
1105 * should be very careful when adding new entries: if SMM is accessing the
1106 * Intel SMBus, this is a very good reason to leave it hidden.
1107 *
1108 * Likewise, many recent laptops use ACPI for thermal management. If the
1109 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1110 * natively, and keeping the SMBus hidden is the right thing to do. If you
1111 * are about to add an entry in the table below, please first disassemble
1112 * the DSDT and double-check that there is no code accessing the SMBus.
1113 */
1114 static int asus_hides_smbus;
1115
1116 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1117 {
1118 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1119 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1120 switch(dev->subsystem_device) {
1121 case 0x8025: /* P4B-LX */
1122 case 0x8070: /* P4B */
1123 case 0x8088: /* P4B533 */
1124 case 0x1626: /* L3C notebook */
1125 asus_hides_smbus = 1;
1126 }
1127 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1128 switch(dev->subsystem_device) {
1129 case 0x80b1: /* P4GE-V */
1130 case 0x80b2: /* P4PE */
1131 case 0x8093: /* P4B533-V */
1132 asus_hides_smbus = 1;
1133 }
1134 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1135 switch(dev->subsystem_device) {
1136 case 0x8030: /* P4T533 */
1137 asus_hides_smbus = 1;
1138 }
1139 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1140 switch (dev->subsystem_device) {
1141 case 0x8070: /* P4G8X Deluxe */
1142 asus_hides_smbus = 1;
1143 }
1144 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1145 switch (dev->subsystem_device) {
1146 case 0x80c9: /* PU-DLS */
1147 asus_hides_smbus = 1;
1148 }
1149 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1150 switch (dev->subsystem_device) {
1151 case 0x1751: /* M2N notebook */
1152 case 0x1821: /* M5N notebook */
1153 case 0x1897: /* A6L notebook */
1154 asus_hides_smbus = 1;
1155 }
1156 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1157 switch (dev->subsystem_device) {
1158 case 0x184b: /* W1N notebook */
1159 case 0x186a: /* M6Ne notebook */
1160 asus_hides_smbus = 1;
1161 }
1162 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1163 switch (dev->subsystem_device) {
1164 case 0x80f2: /* P4P800-X */
1165 asus_hides_smbus = 1;
1166 }
1167 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1168 switch (dev->subsystem_device) {
1169 case 0x1882: /* M6V notebook */
1170 case 0x1977: /* A6VA notebook */
1171 asus_hides_smbus = 1;
1172 }
1173 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1174 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1175 switch(dev->subsystem_device) {
1176 case 0x088C: /* HP Compaq nc8000 */
1177 case 0x0890: /* HP Compaq nc6000 */
1178 asus_hides_smbus = 1;
1179 }
1180 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1181 switch (dev->subsystem_device) {
1182 case 0x12bc: /* HP D330L */
1183 case 0x12bd: /* HP D530 */
1184 case 0x006a: /* HP Compaq nx9500 */
1185 asus_hides_smbus = 1;
1186 }
1187 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1188 switch (dev->subsystem_device) {
1189 case 0x12bf: /* HP xw4100 */
1190 asus_hides_smbus = 1;
1191 }
1192 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1193 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1194 switch(dev->subsystem_device) {
1195 case 0xC00C: /* Samsung P35 notebook */
1196 asus_hides_smbus = 1;
1197 }
1198 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1199 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1200 switch(dev->subsystem_device) {
1201 case 0x0058: /* Compaq Evo N620c */
1202 asus_hides_smbus = 1;
1203 }
1204 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1205 switch(dev->subsystem_device) {
1206 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1207 /* Motherboard doesn't have Host bridge
1208 * subvendor/subdevice IDs, therefore checking
1209 * its on-board VGA controller */
1210 asus_hides_smbus = 1;
1211 }
1212 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1213 switch(dev->subsystem_device) {
1214 case 0x00b8: /* Compaq Evo D510 CMT */
1215 case 0x00b9: /* Compaq Evo D510 SFF */
1216 case 0x00ba: /* Compaq Evo D510 USDT */
1217 /* Motherboard doesn't have Host bridge
1218 * subvendor/subdevice IDs and on-board VGA
1219 * controller is disabled if an AGP card is
1220 * inserted, therefore checking USB UHCI
1221 * Controller #1 */
1222 asus_hides_smbus = 1;
1223 }
1224 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1225 switch (dev->subsystem_device) {
1226 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1227 /* Motherboard doesn't have host bridge
1228 * subvendor/subdevice IDs, therefore checking
1229 * its on-board VGA controller */
1230 asus_hides_smbus = 1;
1231 }
1232 }
1233 }
1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1244
1245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1248
1249 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1250 {
1251 u16 val;
1252
1253 if (likely(!asus_hides_smbus))
1254 return;
1255
1256 pci_read_config_word(dev, 0xF2, &val);
1257 if (val & 0x8) {
1258 pci_write_config_word(dev, 0xF2, val & (~0x8));
1259 pci_read_config_word(dev, 0xF2, &val);
1260 if (val & 0x8)
1261 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1262 else
1263 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1264 }
1265 }
1266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1273 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1274 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1275 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1276 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1277 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1278 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1279 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1280
1281 /* It appears we just have one such device. If not, we have a warning */
1282 static void __iomem *asus_rcba_base;
1283 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1284 {
1285 u32 rcba;
1286
1287 if (likely(!asus_hides_smbus))
1288 return;
1289 WARN_ON(asus_rcba_base);
1290
1291 pci_read_config_dword(dev, 0xF0, &rcba);
1292 /* use bits 31:14, 16 kB aligned */
1293 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1294 if (asus_rcba_base == NULL)
1295 return;
1296 }
1297
1298 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1299 {
1300 u32 val;
1301
1302 if (likely(!asus_hides_smbus || !asus_rcba_base))
1303 return;
1304 /* read the Function Disable register, dword mode only */
1305 val = readl(asus_rcba_base + 0x3418);
1306 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1307 }
1308
1309 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1310 {
1311 if (likely(!asus_hides_smbus || !asus_rcba_base))
1312 return;
1313 iounmap(asus_rcba_base);
1314 asus_rcba_base = NULL;
1315 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1316 }
1317
1318 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1319 {
1320 asus_hides_smbus_lpc_ich6_suspend(dev);
1321 asus_hides_smbus_lpc_ich6_resume_early(dev);
1322 asus_hides_smbus_lpc_ich6_resume(dev);
1323 }
1324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1325 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1326 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1327 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1328
1329 /*
1330 * SiS 96x south bridge: BIOS typically hides SMBus device...
1331 */
1332 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1333 {
1334 u8 val = 0;
1335 pci_read_config_byte(dev, 0x77, &val);
1336 if (val & 0x10) {
1337 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1338 pci_write_config_byte(dev, 0x77, val & ~0x10);
1339 }
1340 }
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1345 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1346 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1347 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1348 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1349
1350 /*
1351 * ... This is further complicated by the fact that some SiS96x south
1352 * bridges pretend to be 85C503/5513 instead. In that case see if we
1353 * spotted a compatible north bridge to make sure.
1354 * (pci_find_device doesn't work yet)
1355 *
1356 * We can also enable the sis96x bit in the discovery register..
1357 */
1358 #define SIS_DETECT_REGISTER 0x40
1359
1360 static void quirk_sis_503(struct pci_dev *dev)
1361 {
1362 u8 reg;
1363 u16 devid;
1364
1365 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1366 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1367 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1368 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1369 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1370 return;
1371 }
1372
1373 /*
1374 * Ok, it now shows up as a 96x.. run the 96x quirk by
1375 * hand in case it has already been processed.
1376 * (depends on link order, which is apparently not guaranteed)
1377 */
1378 dev->device = devid;
1379 quirk_sis_96x_smbus(dev);
1380 }
1381 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1382 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1383
1384
1385 /*
1386 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1387 * and MC97 modem controller are disabled when a second PCI soundcard is
1388 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1389 * -- bjd
1390 */
1391 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1392 {
1393 u8 val;
1394 int asus_hides_ac97 = 0;
1395
1396 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1397 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1398 asus_hides_ac97 = 1;
1399 }
1400
1401 if (!asus_hides_ac97)
1402 return;
1403
1404 pci_read_config_byte(dev, 0x50, &val);
1405 if (val & 0xc0) {
1406 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1407 pci_read_config_byte(dev, 0x50, &val);
1408 if (val & 0xc0)
1409 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1410 else
1411 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1412 }
1413 }
1414 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1415 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1416
1417 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1418
1419 /*
1420 * If we are using libata we can drive this chip properly but must
1421 * do this early on to make the additional device appear during
1422 * the PCI scanning.
1423 */
1424 static void quirk_jmicron_ata(struct pci_dev *pdev)
1425 {
1426 u32 conf1, conf5, class;
1427 u8 hdr;
1428
1429 /* Only poke fn 0 */
1430 if (PCI_FUNC(pdev->devfn))
1431 return;
1432
1433 pci_read_config_dword(pdev, 0x40, &conf1);
1434 pci_read_config_dword(pdev, 0x80, &conf5);
1435
1436 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1437 conf5 &= ~(1 << 24); /* Clear bit 24 */
1438
1439 switch (pdev->device) {
1440 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1441 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1442 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1443 /* The controller should be in single function ahci mode */
1444 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1445 break;
1446
1447 case PCI_DEVICE_ID_JMICRON_JMB365:
1448 case PCI_DEVICE_ID_JMICRON_JMB366:
1449 /* Redirect IDE second PATA port to the right spot */
1450 conf5 |= (1 << 24);
1451 /* Fall through */
1452 case PCI_DEVICE_ID_JMICRON_JMB361:
1453 case PCI_DEVICE_ID_JMICRON_JMB363:
1454 case PCI_DEVICE_ID_JMICRON_JMB369:
1455 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1456 /* Set the class codes correctly and then direct IDE 0 */
1457 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1458 break;
1459
1460 case PCI_DEVICE_ID_JMICRON_JMB368:
1461 /* The controller should be in single function IDE mode */
1462 conf1 |= 0x00C00000; /* Set 22, 23 */
1463 break;
1464 }
1465
1466 pci_write_config_dword(pdev, 0x40, conf1);
1467 pci_write_config_dword(pdev, 0x80, conf5);
1468
1469 /* Update pdev accordingly */
1470 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1471 pdev->hdr_type = hdr & 0x7f;
1472 pdev->multifunction = !!(hdr & 0x80);
1473
1474 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1475 pdev->class = class >> 8;
1476 }
1477 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1478 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1479 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1480 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1481 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1482 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1483 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1484 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1485 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1486 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1487 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1488 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1489 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1490 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1491 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1492 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1493 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1494 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1495
1496 #endif
1497
1498 #ifdef CONFIG_X86_IO_APIC
1499 static void quirk_alder_ioapic(struct pci_dev *pdev)
1500 {
1501 int i;
1502
1503 if ((pdev->class >> 8) != 0xff00)
1504 return;
1505
1506 /* the first BAR is the location of the IO APIC...we must
1507 * not touch this (and it's already covered by the fixmap), so
1508 * forcibly insert it into the resource tree */
1509 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1510 insert_resource(&iomem_resource, &pdev->resource[0]);
1511
1512 /* The next five BARs all seem to be rubbish, so just clean
1513 * them out */
1514 for (i=1; i < 6; i++) {
1515 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1516 }
1517
1518 }
1519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1520 #endif
1521
1522 static void quirk_pcie_mch(struct pci_dev *pdev)
1523 {
1524 pci_msi_off(pdev);
1525 pdev->no_msi = 1;
1526 }
1527 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1530
1531
1532 /*
1533 * It's possible for the MSI to get corrupted if shpc and acpi
1534 * are used together on certain PXH-based systems.
1535 */
1536 static void quirk_pcie_pxh(struct pci_dev *dev)
1537 {
1538 pci_msi_off(dev);
1539 dev->no_msi = 1;
1540 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1541 }
1542 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1546 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1547
1548 /*
1549 * Some Intel PCI Express chipsets have trouble with downstream
1550 * device power management.
1551 */
1552 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1553 {
1554 pci_pm_d3_delay = 120;
1555 dev->no_d1d2 = 1;
1556 }
1557
1558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1579
1580 #ifdef CONFIG_X86_IO_APIC
1581 /*
1582 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1583 * remap the original interrupt in the linux kernel to the boot interrupt, so
1584 * that a PCI device's interrupt handler is installed on the boot interrupt
1585 * line instead.
1586 */
1587 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1588 {
1589 if (noioapicquirk || noioapicreroute)
1590 return;
1591
1592 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1593 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1594 dev->vendor, dev->device);
1595 }
1596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1604 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1605 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1606 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1607 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1608 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1609 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1610 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1611 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1612
1613 /*
1614 * On some chipsets we can disable the generation of legacy INTx boot
1615 * interrupts.
1616 */
1617
1618 /*
1619 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1620 * 300641-004US, section 5.7.3.
1621 */
1622 #define INTEL_6300_IOAPIC_ABAR 0x40
1623 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1624
1625 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1626 {
1627 u16 pci_config_word;
1628
1629 if (noioapicquirk)
1630 return;
1631
1632 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1633 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1634 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1635
1636 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1637 dev->vendor, dev->device);
1638 }
1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1640 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1641
1642 /*
1643 * disable boot interrupts on HT-1000
1644 */
1645 #define BC_HT1000_FEATURE_REG 0x64
1646 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1647 #define BC_HT1000_MAP_IDX 0xC00
1648 #define BC_HT1000_MAP_DATA 0xC01
1649
1650 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1651 {
1652 u32 pci_config_dword;
1653 u8 irq;
1654
1655 if (noioapicquirk)
1656 return;
1657
1658 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1659 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1660 BC_HT1000_PIC_REGS_ENABLE);
1661
1662 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1663 outb(irq, BC_HT1000_MAP_IDX);
1664 outb(0x00, BC_HT1000_MAP_DATA);
1665 }
1666
1667 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1668
1669 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1670 dev->vendor, dev->device);
1671 }
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1673 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1674
1675 /*
1676 * disable boot interrupts on AMD and ATI chipsets
1677 */
1678 /*
1679 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1680 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1681 * (due to an erratum).
1682 */
1683 #define AMD_813X_MISC 0x40
1684 #define AMD_813X_NOIOAMODE (1<<0)
1685 #define AMD_813X_REV_B1 0x12
1686 #define AMD_813X_REV_B2 0x13
1687
1688 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1689 {
1690 u32 pci_config_dword;
1691
1692 if (noioapicquirk)
1693 return;
1694 if ((dev->revision == AMD_813X_REV_B1) ||
1695 (dev->revision == AMD_813X_REV_B2))
1696 return;
1697
1698 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1699 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1700 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1701
1702 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1703 dev->vendor, dev->device);
1704 }
1705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1706 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1708 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1709
1710 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1711
1712 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1713 {
1714 u16 pci_config_word;
1715
1716 if (noioapicquirk)
1717 return;
1718
1719 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1720 if (!pci_config_word) {
1721 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1722 "already disabled\n", dev->vendor, dev->device);
1723 return;
1724 }
1725 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1726 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1727 dev->vendor, dev->device);
1728 }
1729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1730 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1731 #endif /* CONFIG_X86_IO_APIC */
1732
1733 /*
1734 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1735 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1736 * Re-allocate the region if needed...
1737 */
1738 static void quirk_tc86c001_ide(struct pci_dev *dev)
1739 {
1740 struct resource *r = &dev->resource[0];
1741
1742 if (r->start & 0x8) {
1743 r->start = 0;
1744 r->end = 0xf;
1745 }
1746 }
1747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1748 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1749 quirk_tc86c001_ide);
1750
1751 /*
1752 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1753 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1754 * being read correctly if bit 7 of the base address is set.
1755 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1756 * Re-allocate the regions to a 256-byte boundary if necessary.
1757 */
1758 static void quirk_plx_pci9050(struct pci_dev *dev)
1759 {
1760 unsigned int bar;
1761
1762 /* Fixed in revision 2 (PCI 9052). */
1763 if (dev->revision >= 2)
1764 return;
1765 for (bar = 0; bar <= 1; bar++)
1766 if (pci_resource_len(dev, bar) == 0x80 &&
1767 (pci_resource_start(dev, bar) & 0x80)) {
1768 struct resource *r = &dev->resource[bar];
1769 dev_info(&dev->dev,
1770 "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1771 bar);
1772 r->start = 0;
1773 r->end = 0xff;
1774 }
1775 }
1776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1777 quirk_plx_pci9050);
1778 /*
1779 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1780 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1781 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1782 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1783 *
1784 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1785 * driver.
1786 */
1787 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1788 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1789
1790 static void quirk_netmos(struct pci_dev *dev)
1791 {
1792 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1793 unsigned int num_serial = dev->subsystem_device & 0xf;
1794
1795 /*
1796 * These Netmos parts are multiport serial devices with optional
1797 * parallel ports. Even when parallel ports are present, they
1798 * are identified as class SERIAL, which means the serial driver
1799 * will claim them. To prevent this, mark them as class OTHER.
1800 * These combo devices should be claimed by parport_serial.
1801 *
1802 * The subdevice ID is of the form 0x00PS, where <P> is the number
1803 * of parallel ports and <S> is the number of serial ports.
1804 */
1805 switch (dev->device) {
1806 case PCI_DEVICE_ID_NETMOS_9835:
1807 /* Well, this rule doesn't hold for the following 9835 device */
1808 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1809 dev->subsystem_device == 0x0299)
1810 return;
1811 case PCI_DEVICE_ID_NETMOS_9735:
1812 case PCI_DEVICE_ID_NETMOS_9745:
1813 case PCI_DEVICE_ID_NETMOS_9845:
1814 case PCI_DEVICE_ID_NETMOS_9855:
1815 if (num_parallel) {
1816 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1817 "%u serial); changing class SERIAL to OTHER "
1818 "(use parport_serial)\n",
1819 dev->device, num_parallel, num_serial);
1820 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1821 (dev->class & 0xff);
1822 }
1823 }
1824 }
1825 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1826 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1827
1828 static void quirk_e100_interrupt(struct pci_dev *dev)
1829 {
1830 u16 command, pmcsr;
1831 u8 __iomem *csr;
1832 u8 cmd_hi;
1833
1834 switch (dev->device) {
1835 /* PCI IDs taken from drivers/net/e100.c */
1836 case 0x1029:
1837 case 0x1030 ... 0x1034:
1838 case 0x1038 ... 0x103E:
1839 case 0x1050 ... 0x1057:
1840 case 0x1059:
1841 case 0x1064 ... 0x106B:
1842 case 0x1091 ... 0x1095:
1843 case 0x1209:
1844 case 0x1229:
1845 case 0x2449:
1846 case 0x2459:
1847 case 0x245D:
1848 case 0x27DC:
1849 break;
1850 default:
1851 return;
1852 }
1853
1854 /*
1855 * Some firmware hands off the e100 with interrupts enabled,
1856 * which can cause a flood of interrupts if packets are
1857 * received before the driver attaches to the device. So
1858 * disable all e100 interrupts here. The driver will
1859 * re-enable them when it's ready.
1860 */
1861 pci_read_config_word(dev, PCI_COMMAND, &command);
1862
1863 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1864 return;
1865
1866 /*
1867 * Check that the device is in the D0 power state. If it's not,
1868 * there is no point to look any further.
1869 */
1870 if (dev->pm_cap) {
1871 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1872 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1873 return;
1874 }
1875
1876 /* Convert from PCI bus to resource space. */
1877 csr = ioremap(pci_resource_start(dev, 0), 8);
1878 if (!csr) {
1879 dev_warn(&dev->dev, "Can't map e100 registers\n");
1880 return;
1881 }
1882
1883 cmd_hi = readb(csr + 3);
1884 if (cmd_hi == 0) {
1885 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1886 "disabling\n");
1887 writeb(1, csr + 3);
1888 }
1889
1890 iounmap(csr);
1891 }
1892 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1893 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
1894
1895 /*
1896 * The 82575 and 82598 may experience data corruption issues when transitioning
1897 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1898 */
1899 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
1900 {
1901 dev_info(&dev->dev, "Disabling L0s\n");
1902 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1903 }
1904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1905 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1906 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1907 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1908 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1909 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1912 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1913 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1914 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1915 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1916 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1917 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1918
1919 static void fixup_rev1_53c810(struct pci_dev *dev)
1920 {
1921 /* rev 1 ncr53c810 chips don't set the class at all which means
1922 * they don't get their resources remapped. Fix that here.
1923 */
1924
1925 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1926 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1927 dev->class = PCI_CLASS_STORAGE_SCSI;
1928 }
1929 }
1930 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1931
1932 /* Enable 1k I/O space granularity on the Intel P64H2 */
1933 static void quirk_p64h2_1k_io(struct pci_dev *dev)
1934 {
1935 u16 en1k;
1936
1937 pci_read_config_word(dev, 0x40, &en1k);
1938
1939 if (en1k & 0x200) {
1940 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1941 dev->io_window_1k = 1;
1942 }
1943 }
1944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1945
1946 /* Under some circumstances, AER is not linked with extended capabilities.
1947 * Force it to be linked by setting the corresponding control bit in the
1948 * config space.
1949 */
1950 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1951 {
1952 uint8_t b;
1953 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1954 if (!(b & 0x20)) {
1955 pci_write_config_byte(dev, 0xf41, b | 0x20);
1956 dev_info(&dev->dev,
1957 "Linking AER extended capability\n");
1958 }
1959 }
1960 }
1961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1962 quirk_nvidia_ck804_pcie_aer_ext_cap);
1963 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1964 quirk_nvidia_ck804_pcie_aer_ext_cap);
1965
1966 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1967 {
1968 /*
1969 * Disable PCI Bus Parking and PCI Master read caching on CX700
1970 * which causes unspecified timing errors with a VT6212L on the PCI
1971 * bus leading to USB2.0 packet loss.
1972 *
1973 * This quirk is only enabled if a second (on the external PCI bus)
1974 * VT6212L is found -- the CX700 core itself also contains a USB
1975 * host controller with the same PCI ID as the VT6212L.
1976 */
1977
1978 /* Count VT6212L instances */
1979 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
1980 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
1981 uint8_t b;
1982
1983 /* p should contain the first (internal) VT6212L -- see if we have
1984 an external one by searching again */
1985 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
1986 if (!p)
1987 return;
1988 pci_dev_put(p);
1989
1990 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1991 if (b & 0x40) {
1992 /* Turn off PCI Bus Parking */
1993 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1994
1995 dev_info(&dev->dev,
1996 "Disabling VIA CX700 PCI parking\n");
1997 }
1998 }
1999
2000 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2001 if (b != 0) {
2002 /* Turn off PCI Master read caching */
2003 pci_write_config_byte(dev, 0x72, 0x0);
2004
2005 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2006 pci_write_config_byte(dev, 0x75, 0x1);
2007
2008 /* Disable "Read FIFO Timer" */
2009 pci_write_config_byte(dev, 0x77, 0x0);
2010
2011 dev_info(&dev->dev,
2012 "Disabling VIA CX700 PCI caching\n");
2013 }
2014 }
2015 }
2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2017
2018 /*
2019 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2020 * VPD end tag will hang the device. This problem was initially
2021 * observed when a vpd entry was created in sysfs
2022 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2023 * will dump 32k of data. Reading a full 32k will cause an access
2024 * beyond the VPD end tag causing the device to hang. Once the device
2025 * is hung, the bnx2 driver will not be able to reset the device.
2026 * We believe that it is legal to read beyond the end tag and
2027 * therefore the solution is to limit the read/write length.
2028 */
2029 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2030 {
2031 /*
2032 * Only disable the VPD capability for 5706, 5706S, 5708,
2033 * 5708S and 5709 rev. A
2034 */
2035 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2036 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2037 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2038 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2039 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2040 (dev->revision & 0xf0) == 0x0)) {
2041 if (dev->vpd)
2042 dev->vpd->len = 0x80;
2043 }
2044 }
2045
2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2047 PCI_DEVICE_ID_NX2_5706,
2048 quirk_brcm_570x_limit_vpd);
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2050 PCI_DEVICE_ID_NX2_5706S,
2051 quirk_brcm_570x_limit_vpd);
2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2053 PCI_DEVICE_ID_NX2_5708,
2054 quirk_brcm_570x_limit_vpd);
2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2056 PCI_DEVICE_ID_NX2_5708S,
2057 quirk_brcm_570x_limit_vpd);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2059 PCI_DEVICE_ID_NX2_5709,
2060 quirk_brcm_570x_limit_vpd);
2061 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2062 PCI_DEVICE_ID_NX2_5709S,
2063 quirk_brcm_570x_limit_vpd);
2064
2065 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2066 {
2067 u32 rev;
2068
2069 pci_read_config_dword(dev, 0xf4, &rev);
2070
2071 /* Only CAP the MRRS if the device is a 5719 A0 */
2072 if (rev == 0x05719000) {
2073 int readrq = pcie_get_readrq(dev);
2074 if (readrq > 2048)
2075 pcie_set_readrq(dev, 2048);
2076 }
2077 }
2078
2079 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2080 PCI_DEVICE_ID_TIGON3_5719,
2081 quirk_brcm_5719_limit_mrrs);
2082
2083 /* Originally in EDAC sources for i82875P:
2084 * Intel tells BIOS developers to hide device 6 which
2085 * configures the overflow device access containing
2086 * the DRBs - this is where we expose device 6.
2087 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2088 */
2089 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2090 {
2091 u8 reg;
2092
2093 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2094 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2095 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2096 }
2097 }
2098
2099 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2100 quirk_unhide_mch_dev6);
2101 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2102 quirk_unhide_mch_dev6);
2103
2104 #ifdef CONFIG_TILEPRO
2105 /*
2106 * The Tilera TILEmpower tilepro platform needs to set the link speed
2107 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2108 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2109 * capability register of the PEX8624 PCIe switch. The switch
2110 * supports link speed auto negotiation, but falsely sets
2111 * the link speed to 5GT/s.
2112 */
2113 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2114 {
2115 if (tile_plx_gen1) {
2116 pci_write_config_dword(dev, 0x98, 0x1);
2117 mdelay(50);
2118 }
2119 }
2120 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2121 #endif /* CONFIG_TILEPRO */
2122
2123 #ifdef CONFIG_PCI_MSI
2124 /* Some chipsets do not support MSI. We cannot easily rely on setting
2125 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2126 * some other buses controlled by the chipset even if Linux is not
2127 * aware of it. Instead of setting the flag on all buses in the
2128 * machine, simply disable MSI globally.
2129 */
2130 static void quirk_disable_all_msi(struct pci_dev *dev)
2131 {
2132 pci_no_msi();
2133 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2134 }
2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2142
2143 /* Disable MSI on chipsets that are known to not support it */
2144 static void quirk_disable_msi(struct pci_dev *dev)
2145 {
2146 if (dev->subordinate) {
2147 dev_warn(&dev->dev, "MSI quirk detected; "
2148 "subordinate MSI disabled\n");
2149 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2150 }
2151 }
2152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2155
2156 /*
2157 * The APC bridge device in AMD 780 family northbridges has some random
2158 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2159 * we use the possible vendor/device IDs of the host bridge for the
2160 * declared quirk, and search for the APC bridge by slot number.
2161 */
2162 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2163 {
2164 struct pci_dev *apc_bridge;
2165
2166 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2167 if (apc_bridge) {
2168 if (apc_bridge->device == 0x9602)
2169 quirk_disable_msi(apc_bridge);
2170 pci_dev_put(apc_bridge);
2171 }
2172 }
2173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2175
2176 /* Go through the list of Hypertransport capabilities and
2177 * return 1 if a HT MSI capability is found and enabled */
2178 static int msi_ht_cap_enabled(struct pci_dev *dev)
2179 {
2180 int pos, ttl = 48;
2181
2182 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2183 while (pos && ttl--) {
2184 u8 flags;
2185
2186 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2187 &flags) == 0)
2188 {
2189 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2190 flags & HT_MSI_FLAGS_ENABLE ?
2191 "enabled" : "disabled");
2192 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2193 }
2194
2195 pos = pci_find_next_ht_capability(dev, pos,
2196 HT_CAPTYPE_MSI_MAPPING);
2197 }
2198 return 0;
2199 }
2200
2201 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2202 static void quirk_msi_ht_cap(struct pci_dev *dev)
2203 {
2204 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2205 dev_warn(&dev->dev, "MSI quirk detected; "
2206 "subordinate MSI disabled\n");
2207 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2208 }
2209 }
2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2211 quirk_msi_ht_cap);
2212
2213 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2214 * MSI are supported if the MSI capability set in any of these mappings.
2215 */
2216 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2217 {
2218 struct pci_dev *pdev;
2219
2220 if (!dev->subordinate)
2221 return;
2222
2223 /* check HT MSI cap on this chipset and the root one.
2224 * a single one having MSI is enough to be sure that MSI are supported.
2225 */
2226 pdev = pci_get_slot(dev->bus, 0);
2227 if (!pdev)
2228 return;
2229 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2230 dev_warn(&dev->dev, "MSI quirk detected; "
2231 "subordinate MSI disabled\n");
2232 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2233 }
2234 pci_dev_put(pdev);
2235 }
2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2237 quirk_nvidia_ck804_msi_ht_cap);
2238
2239 /* Force enable MSI mapping capability on HT bridges */
2240 static void ht_enable_msi_mapping(struct pci_dev *dev)
2241 {
2242 int pos, ttl = 48;
2243
2244 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2245 while (pos && ttl--) {
2246 u8 flags;
2247
2248 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2249 &flags) == 0) {
2250 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2251
2252 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2253 flags | HT_MSI_FLAGS_ENABLE);
2254 }
2255 pos = pci_find_next_ht_capability(dev, pos,
2256 HT_CAPTYPE_MSI_MAPPING);
2257 }
2258 }
2259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2260 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2261 ht_enable_msi_mapping);
2262
2263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2264 ht_enable_msi_mapping);
2265
2266 /* The P5N32-SLI motherboards from Asus have a problem with msi
2267 * for the MCP55 NIC. It is not yet determined whether the msi problem
2268 * also affects other devices. As for now, turn off msi for this device.
2269 */
2270 static void nvenet_msi_disable(struct pci_dev *dev)
2271 {
2272 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2273
2274 if (board_name &&
2275 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2276 strstr(board_name, "P5N32-E SLI"))) {
2277 dev_info(&dev->dev,
2278 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2279 dev->no_msi = 1;
2280 }
2281 }
2282 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2283 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2284 nvenet_msi_disable);
2285
2286 /*
2287 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2288 * config register. This register controls the routing of legacy
2289 * interrupts from devices that route through the MCP55. If this register
2290 * is misprogrammed, interrupts are only sent to the BSP, unlike
2291 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2292 * having this register set properly prevents kdump from booting up
2293 * properly, so let's make sure that we have it set correctly.
2294 * Note that this is an undocumented register.
2295 */
2296 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2297 {
2298 u32 cfg;
2299
2300 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2301 return;
2302
2303 pci_read_config_dword(dev, 0x74, &cfg);
2304
2305 if (cfg & ((1 << 2) | (1 << 15))) {
2306 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2307 cfg &= ~((1 << 2) | (1 << 15));
2308 pci_write_config_dword(dev, 0x74, cfg);
2309 }
2310 }
2311
2312 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2313 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2314 nvbridge_check_legacy_irq_routing);
2315
2316 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2317 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2318 nvbridge_check_legacy_irq_routing);
2319
2320 static int ht_check_msi_mapping(struct pci_dev *dev)
2321 {
2322 int pos, ttl = 48;
2323 int found = 0;
2324
2325 /* check if there is HT MSI cap or enabled on this device */
2326 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2327 while (pos && ttl--) {
2328 u8 flags;
2329
2330 if (found < 1)
2331 found = 1;
2332 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2333 &flags) == 0) {
2334 if (flags & HT_MSI_FLAGS_ENABLE) {
2335 if (found < 2) {
2336 found = 2;
2337 break;
2338 }
2339 }
2340 }
2341 pos = pci_find_next_ht_capability(dev, pos,
2342 HT_CAPTYPE_MSI_MAPPING);
2343 }
2344
2345 return found;
2346 }
2347
2348 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2349 {
2350 struct pci_dev *dev;
2351 int pos;
2352 int i, dev_no;
2353 int found = 0;
2354
2355 dev_no = host_bridge->devfn >> 3;
2356 for (i = dev_no + 1; i < 0x20; i++) {
2357 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2358 if (!dev)
2359 continue;
2360
2361 /* found next host bridge ?*/
2362 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2363 if (pos != 0) {
2364 pci_dev_put(dev);
2365 break;
2366 }
2367
2368 if (ht_check_msi_mapping(dev)) {
2369 found = 1;
2370 pci_dev_put(dev);
2371 break;
2372 }
2373 pci_dev_put(dev);
2374 }
2375
2376 return found;
2377 }
2378
2379 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2380 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2381
2382 static int is_end_of_ht_chain(struct pci_dev *dev)
2383 {
2384 int pos, ctrl_off;
2385 int end = 0;
2386 u16 flags, ctrl;
2387
2388 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2389
2390 if (!pos)
2391 goto out;
2392
2393 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2394
2395 ctrl_off = ((flags >> 10) & 1) ?
2396 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2397 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2398
2399 if (ctrl & (1 << 6))
2400 end = 1;
2401
2402 out:
2403 return end;
2404 }
2405
2406 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2407 {
2408 struct pci_dev *host_bridge;
2409 int pos;
2410 int i, dev_no;
2411 int found = 0;
2412
2413 dev_no = dev->devfn >> 3;
2414 for (i = dev_no; i >= 0; i--) {
2415 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2416 if (!host_bridge)
2417 continue;
2418
2419 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2420 if (pos != 0) {
2421 found = 1;
2422 break;
2423 }
2424 pci_dev_put(host_bridge);
2425 }
2426
2427 if (!found)
2428 return;
2429
2430 /* don't enable end_device/host_bridge with leaf directly here */
2431 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2432 host_bridge_with_leaf(host_bridge))
2433 goto out;
2434
2435 /* root did that ! */
2436 if (msi_ht_cap_enabled(host_bridge))
2437 goto out;
2438
2439 ht_enable_msi_mapping(dev);
2440
2441 out:
2442 pci_dev_put(host_bridge);
2443 }
2444
2445 static void ht_disable_msi_mapping(struct pci_dev *dev)
2446 {
2447 int pos, ttl = 48;
2448
2449 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2450 while (pos && ttl--) {
2451 u8 flags;
2452
2453 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2454 &flags) == 0) {
2455 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2456
2457 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2458 flags & ~HT_MSI_FLAGS_ENABLE);
2459 }
2460 pos = pci_find_next_ht_capability(dev, pos,
2461 HT_CAPTYPE_MSI_MAPPING);
2462 }
2463 }
2464
2465 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2466 {
2467 struct pci_dev *host_bridge;
2468 int pos;
2469 int found;
2470
2471 if (!pci_msi_enabled())
2472 return;
2473
2474 /* check if there is HT MSI cap or enabled on this device */
2475 found = ht_check_msi_mapping(dev);
2476
2477 /* no HT MSI CAP */
2478 if (found == 0)
2479 return;
2480
2481 /*
2482 * HT MSI mapping should be disabled on devices that are below
2483 * a non-Hypertransport host bridge. Locate the host bridge...
2484 */
2485 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2486 if (host_bridge == NULL) {
2487 dev_warn(&dev->dev,
2488 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2489 return;
2490 }
2491
2492 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2493 if (pos != 0) {
2494 /* Host bridge is to HT */
2495 if (found == 1) {
2496 /* it is not enabled, try to enable it */
2497 if (all)
2498 ht_enable_msi_mapping(dev);
2499 else
2500 nv_ht_enable_msi_mapping(dev);
2501 }
2502 goto out;
2503 }
2504
2505 /* HT MSI is not enabled */
2506 if (found == 1)
2507 goto out;
2508
2509 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2510 ht_disable_msi_mapping(dev);
2511
2512 out:
2513 pci_dev_put(host_bridge);
2514 }
2515
2516 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2517 {
2518 return __nv_msi_ht_cap_quirk(dev, 1);
2519 }
2520
2521 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2522 {
2523 return __nv_msi_ht_cap_quirk(dev, 0);
2524 }
2525
2526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2527 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2528
2529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2530 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2531
2532 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2533 {
2534 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2535 }
2536 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2537 {
2538 struct pci_dev *p;
2539
2540 /* SB700 MSI issue will be fixed at HW level from revision A21,
2541 * we need check PCI REVISION ID of SMBus controller to get SB700
2542 * revision.
2543 */
2544 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2545 NULL);
2546 if (!p)
2547 return;
2548
2549 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2550 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2551 pci_dev_put(p);
2552 }
2553 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2554 {
2555 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2556 if (dev->revision < 0x18) {
2557 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2558 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2559 }
2560 }
2561 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2562 PCI_DEVICE_ID_TIGON3_5780,
2563 quirk_msi_intx_disable_bug);
2564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2565 PCI_DEVICE_ID_TIGON3_5780S,
2566 quirk_msi_intx_disable_bug);
2567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2568 PCI_DEVICE_ID_TIGON3_5714,
2569 quirk_msi_intx_disable_bug);
2570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2571 PCI_DEVICE_ID_TIGON3_5714S,
2572 quirk_msi_intx_disable_bug);
2573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2574 PCI_DEVICE_ID_TIGON3_5715,
2575 quirk_msi_intx_disable_bug);
2576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2577 PCI_DEVICE_ID_TIGON3_5715S,
2578 quirk_msi_intx_disable_bug);
2579
2580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2581 quirk_msi_intx_disable_ati_bug);
2582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2583 quirk_msi_intx_disable_ati_bug);
2584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2585 quirk_msi_intx_disable_ati_bug);
2586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2587 quirk_msi_intx_disable_ati_bug);
2588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2589 quirk_msi_intx_disable_ati_bug);
2590
2591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2592 quirk_msi_intx_disable_bug);
2593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2594 quirk_msi_intx_disable_bug);
2595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2596 quirk_msi_intx_disable_bug);
2597
2598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2599 quirk_msi_intx_disable_bug);
2600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2601 quirk_msi_intx_disable_bug);
2602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2603 quirk_msi_intx_disable_bug);
2604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2605 quirk_msi_intx_disable_bug);
2606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2607 quirk_msi_intx_disable_bug);
2608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2609 quirk_msi_intx_disable_bug);
2610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2611 quirk_msi_intx_disable_qca_bug);
2612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2613 quirk_msi_intx_disable_qca_bug);
2614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2615 quirk_msi_intx_disable_qca_bug);
2616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2617 quirk_msi_intx_disable_qca_bug);
2618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2619 quirk_msi_intx_disable_qca_bug);
2620 #endif /* CONFIG_PCI_MSI */
2621
2622 /* Allow manual resource allocation for PCI hotplug bridges
2623 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2624 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2625 * kernel fails to allocate resources when hotplug device is
2626 * inserted and PCI bus is rescanned.
2627 */
2628 static void quirk_hotplug_bridge(struct pci_dev *dev)
2629 {
2630 dev->is_hotplug_bridge = 1;
2631 }
2632
2633 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2634
2635 /*
2636 * This is a quirk for the Ricoh MMC controller found as a part of
2637 * some mulifunction chips.
2638
2639 * This is very similar and based on the ricoh_mmc driver written by
2640 * Philip Langdale. Thank you for these magic sequences.
2641 *
2642 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2643 * and one or both of cardbus or firewire.
2644 *
2645 * It happens that they implement SD and MMC
2646 * support as separate controllers (and PCI functions). The linux SDHCI
2647 * driver supports MMC cards but the chip detects MMC cards in hardware
2648 * and directs them to the MMC controller - so the SDHCI driver never sees
2649 * them.
2650 *
2651 * To get around this, we must disable the useless MMC controller.
2652 * At that point, the SDHCI controller will start seeing them
2653 * It seems to be the case that the relevant PCI registers to deactivate the
2654 * MMC controller live on PCI function 0, which might be the cardbus controller
2655 * or the firewire controller, depending on the particular chip in question
2656 *
2657 * This has to be done early, because as soon as we disable the MMC controller
2658 * other pci functions shift up one level, e.g. function #2 becomes function
2659 * #1, and this will confuse the pci core.
2660 */
2661
2662 #ifdef CONFIG_MMC_RICOH_MMC
2663 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2664 {
2665 /* disable via cardbus interface */
2666 u8 write_enable;
2667 u8 write_target;
2668 u8 disable;
2669
2670 /* disable must be done via function #0 */
2671 if (PCI_FUNC(dev->devfn))
2672 return;
2673
2674 pci_read_config_byte(dev, 0xB7, &disable);
2675 if (disable & 0x02)
2676 return;
2677
2678 pci_read_config_byte(dev, 0x8E, &write_enable);
2679 pci_write_config_byte(dev, 0x8E, 0xAA);
2680 pci_read_config_byte(dev, 0x8D, &write_target);
2681 pci_write_config_byte(dev, 0x8D, 0xB7);
2682 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2683 pci_write_config_byte(dev, 0x8E, write_enable);
2684 pci_write_config_byte(dev, 0x8D, write_target);
2685
2686 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2687 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2688 }
2689 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2690 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2691
2692 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2693 {
2694 /* disable via firewire interface */
2695 u8 write_enable;
2696 u8 disable;
2697
2698 /* disable must be done via function #0 */
2699 if (PCI_FUNC(dev->devfn))
2700 return;
2701 /*
2702 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2703 * certain types of SD/MMC cards. Lowering the SD base
2704 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2705 *
2706 * 0x150 - SD2.0 mode enable for changing base clock
2707 * frequency to 50Mhz
2708 * 0xe1 - Base clock frequency
2709 * 0x32 - 50Mhz new clock frequency
2710 * 0xf9 - Key register for 0x150
2711 * 0xfc - key register for 0xe1
2712 */
2713 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2714 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2715 pci_write_config_byte(dev, 0xf9, 0xfc);
2716 pci_write_config_byte(dev, 0x150, 0x10);
2717 pci_write_config_byte(dev, 0xf9, 0x00);
2718 pci_write_config_byte(dev, 0xfc, 0x01);
2719 pci_write_config_byte(dev, 0xe1, 0x32);
2720 pci_write_config_byte(dev, 0xfc, 0x00);
2721
2722 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2723 }
2724
2725 pci_read_config_byte(dev, 0xCB, &disable);
2726
2727 if (disable & 0x02)
2728 return;
2729
2730 pci_read_config_byte(dev, 0xCA, &write_enable);
2731 pci_write_config_byte(dev, 0xCA, 0x57);
2732 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2733 pci_write_config_byte(dev, 0xCA, write_enable);
2734
2735 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2736 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2737
2738 }
2739 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2740 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2741 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2742 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2743 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2744 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2745 #endif /*CONFIG_MMC_RICOH_MMC*/
2746
2747 #ifdef CONFIG_DMAR_TABLE
2748 #define VTUNCERRMSK_REG 0x1ac
2749 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2750 /*
2751 * This is a quirk for masking vt-d spec defined errors to platform error
2752 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2753 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2754 * on the RAS config settings of the platform) when a vt-d fault happens.
2755 * The resulting SMI caused the system to hang.
2756 *
2757 * VT-d spec related errors are already handled by the VT-d OS code, so no
2758 * need to report the same error through other channels.
2759 */
2760 static void vtd_mask_spec_errors(struct pci_dev *dev)
2761 {
2762 u32 word;
2763
2764 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2765 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2766 }
2767 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2768 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2769 #endif
2770
2771 static void fixup_ti816x_class(struct pci_dev *dev)
2772 {
2773 /* TI 816x devices do not have class code set when in PCIe boot mode */
2774 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2775 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2776 }
2777 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2778 PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
2779
2780 /* Some PCIe devices do not work reliably with the claimed maximum
2781 * payload size supported.
2782 */
2783 static void fixup_mpss_256(struct pci_dev *dev)
2784 {
2785 dev->pcie_mpss = 1; /* 256 bytes */
2786 }
2787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2788 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2790 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2792 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2793
2794 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2795 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2796 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2797 * until all of the devices are discovered and buses walked, read completion
2798 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2799 * it is possible to hotplug a device with MPS of 256B.
2800 */
2801 static void quirk_intel_mc_errata(struct pci_dev *dev)
2802 {
2803 int err;
2804 u16 rcc;
2805
2806 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2807 return;
2808
2809 /* Intel errata specifies bits to change but does not say what they are.
2810 * Keeping them magical until such time as the registers and values can
2811 * be explained.
2812 */
2813 err = pci_read_config_word(dev, 0x48, &rcc);
2814 if (err) {
2815 dev_err(&dev->dev, "Error attempting to read the read "
2816 "completion coalescing register.\n");
2817 return;
2818 }
2819
2820 if (!(rcc & (1 << 10)))
2821 return;
2822
2823 rcc &= ~(1 << 10);
2824
2825 err = pci_write_config_word(dev, 0x48, rcc);
2826 if (err) {
2827 dev_err(&dev->dev, "Error attempting to write the read "
2828 "completion coalescing register.\n");
2829 return;
2830 }
2831
2832 pr_info_once("Read completion coalescing disabled due to hardware "
2833 "errata relating to 256B MPS.\n");
2834 }
2835 /* Intel 5000 series memory controllers and ports 2-7 */
2836 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2837 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2838 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2839 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2840 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2841 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2842 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2843 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2844 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2845 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2848 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2850 /* Intel 5100 series memory controllers and ports 2-7 */
2851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2856 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2857 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2858 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2859 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2860 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2861 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2862
2863
2864 /*
2865 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
2866 * work around this, query the size it should be configured to by the device and
2867 * modify the resource end to correspond to this new size.
2868 */
2869 static void quirk_intel_ntb(struct pci_dev *dev)
2870 {
2871 int rc;
2872 u8 val;
2873
2874 rc = pci_read_config_byte(dev, 0x00D0, &val);
2875 if (rc)
2876 return;
2877
2878 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2879
2880 rc = pci_read_config_byte(dev, 0x00D1, &val);
2881 if (rc)
2882 return;
2883
2884 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2885 }
2886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2888
2889 static ktime_t fixup_debug_start(struct pci_dev *dev,
2890 void (*fn)(struct pci_dev *dev))
2891 {
2892 ktime_t calltime = ktime_set(0, 0);
2893
2894 dev_dbg(&dev->dev, "calling %pF\n", fn);
2895 if (initcall_debug) {
2896 pr_debug("calling %pF @ %i for %s\n",
2897 fn, task_pid_nr(current), dev_name(&dev->dev));
2898 calltime = ktime_get();
2899 }
2900
2901 return calltime;
2902 }
2903
2904 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2905 void (*fn)(struct pci_dev *dev))
2906 {
2907 ktime_t delta, rettime;
2908 unsigned long long duration;
2909
2910 if (initcall_debug) {
2911 rettime = ktime_get();
2912 delta = ktime_sub(rettime, calltime);
2913 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
2914 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
2915 fn, duration, dev_name(&dev->dev));
2916 }
2917 }
2918
2919 /*
2920 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2921 * even though no one is handling them (f.e. i915 driver is never loaded).
2922 * Additionally the interrupt destination is not set up properly
2923 * and the interrupt ends up -somewhere-.
2924 *
2925 * These spurious interrupts are "sticky" and the kernel disables
2926 * the (shared) interrupt line after 100.000+ generated interrupts.
2927 *
2928 * Fix it by disabling the still enabled interrupts.
2929 * This resolves crashes often seen on monitor unplug.
2930 */
2931 #define I915_DEIER_REG 0x4400c
2932 static void disable_igfx_irq(struct pci_dev *dev)
2933 {
2934 void __iomem *regs = pci_iomap(dev, 0, 0);
2935 if (regs == NULL) {
2936 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
2937 return;
2938 }
2939
2940 /* Check if any interrupt line is still enabled */
2941 if (readl(regs + I915_DEIER_REG) != 0) {
2942 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
2943 "disabling\n");
2944
2945 writel(0, regs + I915_DEIER_REG);
2946 }
2947
2948 pci_iounmap(dev, regs);
2949 }
2950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
2951 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
2952
2953 /*
2954 * PCI devices which are on Intel chips can skip the 10ms delay
2955 * before entering D3 mode.
2956 */
2957 static void quirk_remove_d3_delay(struct pci_dev *dev)
2958 {
2959 dev->d3_delay = 0;
2960 }
2961 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
2962 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
2963 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
2964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
2965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
2966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
2967 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
2968 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
2969 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
2970 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
2971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
2972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
2973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
2974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
2975
2976 /*
2977 * Some devices may pass our check in pci_intx_mask_supported if
2978 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
2979 * support this feature.
2980 */
2981 static void quirk_broken_intx_masking(struct pci_dev *dev)
2982 {
2983 dev->broken_intx_masking = 1;
2984 }
2985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, 0x0030,
2986 quirk_broken_intx_masking);
2987 DECLARE_PCI_FIXUP_HEADER(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
2988 quirk_broken_intx_masking);
2989
2990 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2991 struct pci_fixup *end)
2992 {
2993 ktime_t calltime;
2994
2995 for (; f < end; f++)
2996 if ((f->class == (u32) (dev->class >> f->class_shift) ||
2997 f->class == (u32) PCI_ANY_ID) &&
2998 (f->vendor == dev->vendor ||
2999 f->vendor == (u16) PCI_ANY_ID) &&
3000 (f->device == dev->device ||
3001 f->device == (u16) PCI_ANY_ID)) {
3002 calltime = fixup_debug_start(dev, f->hook);
3003 f->hook(dev);
3004 fixup_debug_report(dev, calltime, f->hook);
3005 }
3006 }
3007
3008 extern struct pci_fixup __start_pci_fixups_early[];
3009 extern struct pci_fixup __end_pci_fixups_early[];
3010 extern struct pci_fixup __start_pci_fixups_header[];
3011 extern struct pci_fixup __end_pci_fixups_header[];
3012 extern struct pci_fixup __start_pci_fixups_final[];
3013 extern struct pci_fixup __end_pci_fixups_final[];
3014 extern struct pci_fixup __start_pci_fixups_enable[];
3015 extern struct pci_fixup __end_pci_fixups_enable[];
3016 extern struct pci_fixup __start_pci_fixups_resume[];
3017 extern struct pci_fixup __end_pci_fixups_resume[];
3018 extern struct pci_fixup __start_pci_fixups_resume_early[];
3019 extern struct pci_fixup __end_pci_fixups_resume_early[];
3020 extern struct pci_fixup __start_pci_fixups_suspend[];
3021 extern struct pci_fixup __end_pci_fixups_suspend[];
3022
3023 static bool pci_apply_fixup_final_quirks;
3024
3025 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3026 {
3027 struct pci_fixup *start, *end;
3028
3029 switch(pass) {
3030 case pci_fixup_early:
3031 start = __start_pci_fixups_early;
3032 end = __end_pci_fixups_early;
3033 break;
3034
3035 case pci_fixup_header:
3036 start = __start_pci_fixups_header;
3037 end = __end_pci_fixups_header;
3038 break;
3039
3040 case pci_fixup_final:
3041 if (!pci_apply_fixup_final_quirks)
3042 return;
3043 start = __start_pci_fixups_final;
3044 end = __end_pci_fixups_final;
3045 break;
3046
3047 case pci_fixup_enable:
3048 start = __start_pci_fixups_enable;
3049 end = __end_pci_fixups_enable;
3050 break;
3051
3052 case pci_fixup_resume:
3053 start = __start_pci_fixups_resume;
3054 end = __end_pci_fixups_resume;
3055 break;
3056
3057 case pci_fixup_resume_early:
3058 start = __start_pci_fixups_resume_early;
3059 end = __end_pci_fixups_resume_early;
3060 break;
3061
3062 case pci_fixup_suspend:
3063 start = __start_pci_fixups_suspend;
3064 end = __end_pci_fixups_suspend;
3065 break;
3066
3067 default:
3068 /* stupid compiler warning, you would think with an enum... */
3069 return;
3070 }
3071 pci_do_fixups(dev, start, end);
3072 }
3073 EXPORT_SYMBOL(pci_fixup_device);
3074
3075
3076 static int __init pci_apply_final_quirks(void)
3077 {
3078 struct pci_dev *dev = NULL;
3079 u8 cls = 0;
3080 u8 tmp;
3081
3082 if (pci_cache_line_size)
3083 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3084 pci_cache_line_size << 2);
3085
3086 pci_apply_fixup_final_quirks = true;
3087 for_each_pci_dev(dev) {
3088 pci_fixup_device(pci_fixup_final, dev);
3089 /*
3090 * If arch hasn't set it explicitly yet, use the CLS
3091 * value shared by all PCI devices. If there's a
3092 * mismatch, fall back to the default value.
3093 */
3094 if (!pci_cache_line_size) {
3095 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3096 if (!cls)
3097 cls = tmp;
3098 if (!tmp || cls == tmp)
3099 continue;
3100
3101 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3102 "using %u bytes\n", cls << 2, tmp << 2,
3103 pci_dfl_cache_line_size << 2);
3104 pci_cache_line_size = pci_dfl_cache_line_size;
3105 }
3106 }
3107
3108 if (!pci_cache_line_size) {
3109 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3110 cls << 2, pci_dfl_cache_line_size << 2);
3111 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3112 }
3113
3114 return 0;
3115 }
3116
3117 fs_initcall_sync(pci_apply_final_quirks);
3118
3119 /*
3120 * Followings are device-specific reset methods which can be used to
3121 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3122 * not available.
3123 */
3124 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3125 {
3126 int pos;
3127
3128 /* only implement PCI_CLASS_SERIAL_USB at present */
3129 if (dev->class == PCI_CLASS_SERIAL_USB) {
3130 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3131 if (!pos)
3132 return -ENOTTY;
3133
3134 if (probe)
3135 return 0;
3136
3137 pci_write_config_byte(dev, pos + 0x4, 1);
3138 msleep(100);
3139
3140 return 0;
3141 } else {
3142 return -ENOTTY;
3143 }
3144 }
3145
3146 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3147 {
3148 /*
3149 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3150 *
3151 * The 82599 supports FLR on VFs, but FLR support is reported only
3152 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3153 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3154 */
3155
3156 if (probe)
3157 return 0;
3158
3159 if (!pci_wait_for_pending_transaction(dev))
3160 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3161
3162 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3163
3164 msleep(100);
3165
3166 return 0;
3167 }
3168
3169 #include "../gpu/drm/i915/i915_reg.h"
3170 #define MSG_CTL 0x45010
3171 #define NSDE_PWR_STATE 0xd0100
3172 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3173
3174 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3175 {
3176 void __iomem *mmio_base;
3177 unsigned long timeout;
3178 u32 val;
3179
3180 if (probe)
3181 return 0;
3182
3183 mmio_base = pci_iomap(dev, 0, 0);
3184 if (!mmio_base)
3185 return -ENOMEM;
3186
3187 iowrite32(0x00000002, mmio_base + MSG_CTL);
3188
3189 /*
3190 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3191 * driver loaded sets the right bits. However, this's a reset and
3192 * the bits have been set by i915 previously, so we clobber
3193 * SOUTH_CHICKEN2 register directly here.
3194 */
3195 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3196
3197 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3198 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3199
3200 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3201 do {
3202 val = ioread32(mmio_base + PCH_PP_STATUS);
3203 if ((val & 0xb0000000) == 0)
3204 goto reset_complete;
3205 msleep(10);
3206 } while (time_before(jiffies, timeout));
3207 dev_warn(&dev->dev, "timeout during reset\n");
3208
3209 reset_complete:
3210 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3211
3212 pci_iounmap(dev, mmio_base);
3213 return 0;
3214 }
3215
3216 /*
3217 * Device-specific reset method for Chelsio T4-based adapters.
3218 */
3219 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3220 {
3221 u16 old_command;
3222 u16 msix_flags;
3223
3224 /*
3225 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3226 * that we have no device-specific reset method.
3227 */
3228 if ((dev->device & 0xf000) != 0x4000)
3229 return -ENOTTY;
3230
3231 /*
3232 * If this is the "probe" phase, return 0 indicating that we can
3233 * reset this device.
3234 */
3235 if (probe)
3236 return 0;
3237
3238 /*
3239 * T4 can wedge if there are DMAs in flight within the chip and Bus
3240 * Master has been disabled. We need to have it on till the Function
3241 * Level Reset completes. (BUS_MASTER is disabled in
3242 * pci_reset_function()).
3243 */
3244 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3245 pci_write_config_word(dev, PCI_COMMAND,
3246 old_command | PCI_COMMAND_MASTER);
3247
3248 /*
3249 * Perform the actual device function reset, saving and restoring
3250 * configuration information around the reset.
3251 */
3252 pci_save_state(dev);
3253
3254 /*
3255 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3256 * are disabled when an MSI-X interrupt message needs to be delivered.
3257 * So we briefly re-enable MSI-X interrupts for the duration of the
3258 * FLR. The pci_restore_state() below will restore the original
3259 * MSI-X state.
3260 */
3261 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3262 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3263 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3264 msix_flags |
3265 PCI_MSIX_FLAGS_ENABLE |
3266 PCI_MSIX_FLAGS_MASKALL);
3267
3268 /*
3269 * Start of pcie_flr() code sequence. This reset code is a copy of
3270 * the guts of pcie_flr() because that's not an exported function.
3271 */
3272
3273 if (!pci_wait_for_pending_transaction(dev))
3274 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3275
3276 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3277 msleep(100);
3278
3279 /*
3280 * End of pcie_flr() code sequence.
3281 */
3282
3283 /*
3284 * Restore the configuration information (BAR values, etc.) including
3285 * the original PCI Configuration Space Command word, and return
3286 * success.
3287 */
3288 pci_restore_state(dev);
3289 pci_write_config_word(dev, PCI_COMMAND, old_command);
3290 return 0;
3291 }
3292
3293 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3294 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3295 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3296
3297 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3298 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3299 reset_intel_82599_sfp_virtfn },
3300 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3301 reset_ivb_igd },
3302 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3303 reset_ivb_igd },
3304 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3305 reset_intel_generic_dev },
3306 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3307 reset_chelsio_generic_dev },
3308 { 0 }
3309 };
3310
3311 /*
3312 * These device-specific reset methods are here rather than in a driver
3313 * because when a host assigns a device to a guest VM, the host may need
3314 * to reset the device but probably doesn't have a driver for it.
3315 */
3316 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3317 {
3318 const struct pci_dev_reset_methods *i;
3319
3320 for (i = pci_dev_reset_methods; i->reset; i++) {
3321 if ((i->vendor == dev->vendor ||
3322 i->vendor == (u16)PCI_ANY_ID) &&
3323 (i->device == dev->device ||
3324 i->device == (u16)PCI_ANY_ID))
3325 return i->reset(dev, probe);
3326 }
3327
3328 return -ENOTTY;
3329 }
3330
3331 static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
3332 {
3333 if (!PCI_FUNC(dev->devfn))
3334 return pci_dev_get(dev);
3335
3336 return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3337 }
3338
3339 static const struct pci_dev_dma_source {
3340 u16 vendor;
3341 u16 device;
3342 struct pci_dev *(*dma_source)(struct pci_dev *dev);
3343 } pci_dev_dma_source[] = {
3344 /*
3345 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3346 *
3347 * Some Ricoh devices use the function 0 source ID for DMA on
3348 * other functions of a multifunction device. The DMA devices
3349 * is therefore function 0, which will have implications of the
3350 * iommu grouping of these devices.
3351 */
3352 { PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
3353 { PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
3354 { PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
3355 { PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
3356 { 0 }
3357 };
3358
3359 /*
3360 * IOMMUs with isolation capabilities need to be programmed with the
3361 * correct source ID of a device. In most cases, the source ID matches
3362 * the device doing the DMA, but sometimes hardware is broken and will
3363 * tag the DMA as being sourced from a different device. This function
3364 * allows that translation. Note that the reference count of the
3365 * returned device is incremented on all paths.
3366 */
3367 struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
3368 {
3369 const struct pci_dev_dma_source *i;
3370
3371 for (i = pci_dev_dma_source; i->dma_source; i++) {
3372 if ((i->vendor == dev->vendor ||
3373 i->vendor == (u16)PCI_ANY_ID) &&
3374 (i->device == dev->device ||
3375 i->device == (u16)PCI_ANY_ID))
3376 return i->dma_source(dev);
3377 }
3378
3379 return pci_dev_get(dev);
3380 }
3381
3382 /*
3383 * AMD has indicated that the devices below do not support peer-to-peer
3384 * in any system where they are found in the southbridge with an AMD
3385 * IOMMU in the system. Multifunction devices that do not support
3386 * peer-to-peer between functions can claim to support a subset of ACS.
3387 * Such devices effectively enable request redirect (RR) and completion
3388 * redirect (CR) since all transactions are redirected to the upstream
3389 * root complex.
3390 *
3391 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
3392 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
3393 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
3394 *
3395 * 1002:4385 SBx00 SMBus Controller
3396 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
3397 * 1002:4383 SBx00 Azalia (Intel HDA)
3398 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
3399 * 1002:4384 SBx00 PCI to PCI Bridge
3400 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
3401 */
3402 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
3403 {
3404 #ifdef CONFIG_ACPI
3405 struct acpi_table_header *header = NULL;
3406 acpi_status status;
3407
3408 /* Targeting multifunction devices on the SB (appears on root bus) */
3409 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
3410 return -ENODEV;
3411
3412 /* The IVRS table describes the AMD IOMMU */
3413 status = acpi_get_table("IVRS", 0, &header);
3414 if (ACPI_FAILURE(status))
3415 return -ENODEV;
3416
3417 /* Filter out flags not applicable to multifunction */
3418 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
3419
3420 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
3421 #else
3422 return -ENODEV;
3423 #endif
3424 }
3425
3426 static const struct pci_dev_acs_enabled {
3427 u16 vendor;
3428 u16 device;
3429 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
3430 } pci_dev_acs_enabled[] = {
3431 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
3432 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
3433 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
3434 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3435 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3436 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3437 { 0 }
3438 };
3439
3440 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
3441 {
3442 const struct pci_dev_acs_enabled *i;
3443 int ret;
3444
3445 /*
3446 * Allow devices that do not expose standard PCIe ACS capabilities
3447 * or control to indicate their support here. Multi-function express
3448 * devices which do not allow internal peer-to-peer between functions,
3449 * but do not implement PCIe ACS may wish to return true here.
3450 */
3451 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
3452 if ((i->vendor == dev->vendor ||
3453 i->vendor == (u16)PCI_ANY_ID) &&
3454 (i->device == dev->device ||
3455 i->device == (u16)PCI_ANY_ID)) {
3456 ret = i->acs_enabled(dev, acs_flags);
3457 if (ret >= 0)
3458 return ret;
3459 }
3460 }
3461
3462 return -ENOTTY;
3463 }
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