2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include <asm-generic/pci-bridge.h>
31 unsigned int pci_flags
;
33 struct pci_dev_resource
{
34 struct list_head list
;
37 resource_size_t start
;
39 resource_size_t add_size
;
40 resource_size_t min_align
;
44 static void free_list(struct list_head
*head
)
46 struct pci_dev_resource
*dev_res
, *tmp
;
48 list_for_each_entry_safe(dev_res
, tmp
, head
, list
) {
49 list_del(&dev_res
->list
);
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
63 static int add_to_list(struct list_head
*head
,
64 struct pci_dev
*dev
, struct resource
*res
,
65 resource_size_t add_size
, resource_size_t min_align
)
67 struct pci_dev_resource
*tmp
;
69 tmp
= kzalloc(sizeof(*tmp
), GFP_KERNEL
);
71 pr_warning("add_to_list: kmalloc() failed!\n");
77 tmp
->start
= res
->start
;
79 tmp
->flags
= res
->flags
;
80 tmp
->add_size
= add_size
;
81 tmp
->min_align
= min_align
;
83 list_add(&tmp
->list
, head
);
88 static void remove_from_list(struct list_head
*head
,
91 struct pci_dev_resource
*dev_res
, *tmp
;
93 list_for_each_entry_safe(dev_res
, tmp
, head
, list
) {
94 if (dev_res
->res
== res
) {
95 list_del(&dev_res
->list
);
102 static resource_size_t
get_res_add_size(struct list_head
*head
,
103 struct resource
*res
)
105 struct pci_dev_resource
*dev_res
;
107 list_for_each_entry(dev_res
, head
, list
) {
108 if (dev_res
->res
== res
) {
109 int idx
= res
- &dev_res
->dev
->resource
[0];
111 dev_printk(KERN_DEBUG
, &dev_res
->dev
->dev
,
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
114 (unsigned long long)dev_res
->add_size
);
116 return dev_res
->add_size
;
123 /* Sort resources by alignment */
124 static void pdev_sort_resources(struct pci_dev
*dev
, struct list_head
*head
)
128 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
130 struct pci_dev_resource
*dev_res
, *tmp
;
131 resource_size_t r_align
;
134 r
= &dev
->resource
[i
];
136 if (r
->flags
& IORESOURCE_PCI_FIXED
)
139 if (!(r
->flags
) || r
->parent
)
142 r_align
= pci_resource_alignment(dev
, r
);
144 dev_warn(&dev
->dev
, "BAR %d: %pR has bogus alignment\n",
149 tmp
= kzalloc(sizeof(*tmp
), GFP_KERNEL
);
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
156 /* fallback is smallest one or list is empty*/
158 list_for_each_entry(dev_res
, head
, list
) {
159 resource_size_t align
;
161 align
= pci_resource_alignment(dev_res
->dev
,
164 if (r_align
> align
) {
169 /* Insert it just before n*/
170 list_add_tail(&tmp
->list
, n
);
174 static void __dev_sort_resources(struct pci_dev
*dev
,
175 struct list_head
*head
)
177 u16
class = dev
->class >> 8;
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED
|| class == PCI_CLASS_BRIDGE_HOST
)
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC
) {
186 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
187 if (command
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
))
191 pdev_sort_resources(dev
, head
);
194 static inline void reset_resource(struct resource
*res
)
202 * reassign_resources_sorted() - satisfy any additional resource requests
204 * @realloc_head : head of the list tracking requests requiring additional
206 * @head : head of the list tracking requests with allocated
209 * Walk through each element of the realloc_head and try to procure
210 * additional resources for the element, provided the element
211 * is in the head list.
213 static void reassign_resources_sorted(struct list_head
*realloc_head
,
214 struct list_head
*head
)
216 struct resource
*res
;
217 struct pci_dev_resource
*add_res
, *tmp
;
218 struct pci_dev_resource
*dev_res
;
219 resource_size_t add_size
;
222 list_for_each_entry_safe(add_res
, tmp
, realloc_head
, list
) {
223 bool found_match
= false;
226 /* skip resource that has been reset */
230 /* skip this resource if not found in head list */
231 list_for_each_entry(dev_res
, head
, list
) {
232 if (dev_res
->res
== res
) {
237 if (!found_match
)/* just skip */
240 idx
= res
- &add_res
->dev
->resource
[0];
241 add_size
= add_res
->add_size
;
242 if (!resource_size(res
)) {
243 res
->start
= add_res
->start
;
244 res
->end
= res
->start
+ add_size
- 1;
245 if (pci_assign_resource(add_res
->dev
, idx
))
248 resource_size_t align
= add_res
->min_align
;
249 res
->flags
|= add_res
->flags
&
250 (IORESOURCE_STARTALIGN
|IORESOURCE_SIZEALIGN
);
251 if (pci_reassign_resource(add_res
->dev
, idx
,
253 dev_printk(KERN_DEBUG
, &add_res
->dev
->dev
,
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size
,
259 list_del(&add_res
->list
);
265 * assign_requested_resources_sorted() - satisfy resource requests
267 * @head : head of the list tracking requests for resources
268 * @fail_head : head of the list tracking requests that could
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
274 static void assign_requested_resources_sorted(struct list_head
*head
,
275 struct list_head
*fail_head
)
277 struct resource
*res
;
278 struct pci_dev_resource
*dev_res
;
281 list_for_each_entry(dev_res
, head
, list
) {
283 idx
= res
- &dev_res
->dev
->resource
[0];
284 if (resource_size(res
) &&
285 pci_assign_resource(dev_res
->dev
, idx
)) {
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
291 if (!((idx
== PCI_ROM_RESOURCE
) &&
292 (!(res
->flags
& IORESOURCE_ROM_ENABLE
))))
293 add_to_list(fail_head
,
303 static unsigned long pci_fail_res_type_mask(struct list_head
*fail_head
)
305 struct pci_dev_resource
*fail_res
;
306 unsigned long mask
= 0;
308 /* check failed type */
309 list_for_each_entry(fail_res
, fail_head
, list
)
310 mask
|= fail_res
->flags
;
313 * one pref failed resource will set IORESOURCE_MEM,
314 * as we can allocate pref in non-pref range.
315 * Will release all assigned non-pref sibling resources
316 * according to that bit.
318 return mask
& (IORESOURCE_IO
| IORESOURCE_MEM
| IORESOURCE_PREFETCH
);
321 static bool pci_need_to_release(unsigned long mask
, struct resource
*res
)
323 if (res
->flags
& IORESOURCE_IO
)
324 return !!(mask
& IORESOURCE_IO
);
326 /* check pref at first */
327 if (res
->flags
& IORESOURCE_PREFETCH
) {
328 if (mask
& IORESOURCE_PREFETCH
)
330 /* count pref if its parent is non-pref */
331 else if ((mask
& IORESOURCE_MEM
) &&
332 !(res
->parent
->flags
& IORESOURCE_PREFETCH
))
338 if (res
->flags
& IORESOURCE_MEM
)
339 return !!(mask
& IORESOURCE_MEM
);
341 return false; /* should not get here */
344 static void __assign_resources_sorted(struct list_head
*head
,
345 struct list_head
*realloc_head
,
346 struct list_head
*fail_head
)
349 * Should not assign requested resources at first.
350 * they could be adjacent, so later reassign can not reallocate
351 * them one by one in parent resource window.
352 * Try to assign requested + add_size at beginning
353 * if could do that, could get out early.
354 * if could not do that, we still try to assign requested at first,
355 * then try to reassign add_size for some resources.
357 * Separate three resource type checking if we need to release
358 * assigned resource after requested + add_size try.
359 * 1. if there is io port assign fail, will release assigned
361 * 2. if there is pref mmio assign fail, release assigned
363 * if assigned pref mmio's parent is non-pref mmio and there
364 * is non-pref mmio assign fail, will release that assigned
366 * 3. if there is non-pref mmio assign fail or pref mmio
367 * assigned fail, will release assigned non-pref mmio.
369 LIST_HEAD(save_head
);
370 LIST_HEAD(local_fail_head
);
371 struct pci_dev_resource
*save_res
;
372 struct pci_dev_resource
*dev_res
, *tmp_res
;
373 unsigned long fail_type
;
375 /* Check if optional add_size is there */
376 if (!realloc_head
|| list_empty(realloc_head
))
377 goto requested_and_reassign
;
379 /* Save original start, end, flags etc at first */
380 list_for_each_entry(dev_res
, head
, list
) {
381 if (add_to_list(&save_head
, dev_res
->dev
, dev_res
->res
, 0, 0)) {
382 free_list(&save_head
);
383 goto requested_and_reassign
;
387 /* Update res in head list with add_size in realloc_head list */
388 list_for_each_entry(dev_res
, head
, list
)
389 dev_res
->res
->end
+= get_res_add_size(realloc_head
,
392 /* Try updated head list with add_size added */
393 assign_requested_resources_sorted(head
, &local_fail_head
);
395 /* all assigned with add_size ? */
396 if (list_empty(&local_fail_head
)) {
397 /* Remove head list from realloc_head list */
398 list_for_each_entry(dev_res
, head
, list
)
399 remove_from_list(realloc_head
, dev_res
->res
);
400 free_list(&save_head
);
405 /* check failed type */
406 fail_type
= pci_fail_res_type_mask(&local_fail_head
);
407 /* remove not need to be released assigned res from head list etc */
408 list_for_each_entry_safe(dev_res
, tmp_res
, head
, list
)
409 if (dev_res
->res
->parent
&&
410 !pci_need_to_release(fail_type
, dev_res
->res
)) {
411 /* remove it from realloc_head list */
412 remove_from_list(realloc_head
, dev_res
->res
);
413 remove_from_list(&save_head
, dev_res
->res
);
414 list_del(&dev_res
->list
);
418 free_list(&local_fail_head
);
419 /* Release assigned resource */
420 list_for_each_entry(dev_res
, head
, list
)
421 if (dev_res
->res
->parent
)
422 release_resource(dev_res
->res
);
423 /* Restore start/end/flags from saved list */
424 list_for_each_entry(save_res
, &save_head
, list
) {
425 struct resource
*res
= save_res
->res
;
427 res
->start
= save_res
->start
;
428 res
->end
= save_res
->end
;
429 res
->flags
= save_res
->flags
;
431 free_list(&save_head
);
433 requested_and_reassign
:
434 /* Satisfy the must-have resource requests */
435 assign_requested_resources_sorted(head
, fail_head
);
437 /* Try to satisfy any additional optional resource
440 reassign_resources_sorted(realloc_head
, head
);
444 static void pdev_assign_resources_sorted(struct pci_dev
*dev
,
445 struct list_head
*add_head
,
446 struct list_head
*fail_head
)
450 __dev_sort_resources(dev
, &head
);
451 __assign_resources_sorted(&head
, add_head
, fail_head
);
455 static void pbus_assign_resources_sorted(const struct pci_bus
*bus
,
456 struct list_head
*realloc_head
,
457 struct list_head
*fail_head
)
462 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
463 __dev_sort_resources(dev
, &head
);
465 __assign_resources_sorted(&head
, realloc_head
, fail_head
);
468 void pci_setup_cardbus(struct pci_bus
*bus
)
470 struct pci_dev
*bridge
= bus
->self
;
471 struct resource
*res
;
472 struct pci_bus_region region
;
474 dev_info(&bridge
->dev
, "CardBus bridge to %pR\n",
477 res
= bus
->resource
[0];
478 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
479 if (res
->flags
& IORESOURCE_IO
) {
481 * The IO resource is allocated a range twice as large as it
482 * would normally need. This allows us to set both IO regs.
484 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
485 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_0
,
487 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_0
,
491 res
= bus
->resource
[1];
492 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
493 if (res
->flags
& IORESOURCE_IO
) {
494 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
495 pci_write_config_dword(bridge
, PCI_CB_IO_BASE_1
,
497 pci_write_config_dword(bridge
, PCI_CB_IO_LIMIT_1
,
501 res
= bus
->resource
[2];
502 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
503 if (res
->flags
& IORESOURCE_MEM
) {
504 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
505 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_0
,
507 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_0
,
511 res
= bus
->resource
[3];
512 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
513 if (res
->flags
& IORESOURCE_MEM
) {
514 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
515 pci_write_config_dword(bridge
, PCI_CB_MEMORY_BASE_1
,
517 pci_write_config_dword(bridge
, PCI_CB_MEMORY_LIMIT_1
,
521 EXPORT_SYMBOL(pci_setup_cardbus
);
523 /* Initialize bridges with base/limit values we have collected.
524 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
525 requires that if there is no I/O ports or memory behind the
526 bridge, corresponding range must be turned off by writing base
527 value greater than limit to the bridge's base/limit registers.
529 Note: care must be taken when updating I/O base/limit registers
530 of bridges which support 32-bit I/O. This update requires two
531 config space writes, so it's quite possible that an I/O window of
532 the bridge will have some undesirable address (e.g. 0) after the
533 first write. Ditto 64-bit prefetchable MMIO. */
534 static void pci_setup_bridge_io(struct pci_bus
*bus
)
536 struct pci_dev
*bridge
= bus
->self
;
537 struct resource
*res
;
538 struct pci_bus_region region
;
539 unsigned long io_mask
;
540 u8 io_base_lo
, io_limit_lo
;
544 io_mask
= PCI_IO_RANGE_MASK
;
545 if (bridge
->io_window_1k
)
546 io_mask
= PCI_IO_1K_RANGE_MASK
;
548 /* Set up the top and bottom of the PCI I/O segment for this bus. */
549 res
= bus
->resource
[0];
550 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
551 if (res
->flags
& IORESOURCE_IO
) {
552 pci_read_config_word(bridge
, PCI_IO_BASE
, &l
);
553 io_base_lo
= (region
.start
>> 8) & io_mask
;
554 io_limit_lo
= (region
.end
>> 8) & io_mask
;
555 l
= ((u16
) io_limit_lo
<< 8) | io_base_lo
;
556 /* Set up upper 16 bits of I/O base/limit. */
557 io_upper16
= (region
.end
& 0xffff0000) | (region
.start
>> 16);
558 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
560 /* Clear upper 16 bits of I/O base/limit. */
564 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
565 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, 0x0000ffff);
566 /* Update lower 16 bits of I/O base/limit. */
567 pci_write_config_word(bridge
, PCI_IO_BASE
, l
);
568 /* Update upper 16 bits of I/O base/limit. */
569 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, io_upper16
);
572 static void pci_setup_bridge_mmio(struct pci_bus
*bus
)
574 struct pci_dev
*bridge
= bus
->self
;
575 struct resource
*res
;
576 struct pci_bus_region region
;
579 /* Set up the top and bottom of the PCI Memory segment for this bus. */
580 res
= bus
->resource
[1];
581 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
582 if (res
->flags
& IORESOURCE_MEM
) {
583 l
= (region
.start
>> 16) & 0xfff0;
584 l
|= region
.end
& 0xfff00000;
585 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
589 pci_write_config_dword(bridge
, PCI_MEMORY_BASE
, l
);
592 static void pci_setup_bridge_mmio_pref(struct pci_bus
*bus
)
594 struct pci_dev
*bridge
= bus
->self
;
595 struct resource
*res
;
596 struct pci_bus_region region
;
599 /* Clear out the upper 32 bits of PREF limit.
600 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
601 disables PREF range, which is ok. */
602 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, 0);
604 /* Set up PREF base/limit. */
606 res
= bus
->resource
[2];
607 pcibios_resource_to_bus(bridge
->bus
, ®ion
, res
);
608 if (res
->flags
& IORESOURCE_PREFETCH
) {
609 l
= (region
.start
>> 16) & 0xfff0;
610 l
|= region
.end
& 0xfff00000;
611 if (res
->flags
& IORESOURCE_MEM_64
) {
612 bu
= upper_32_bits(region
.start
);
613 lu
= upper_32_bits(region
.end
);
615 dev_info(&bridge
->dev
, " bridge window %pR\n", res
);
619 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, l
);
621 /* Set the upper 32 bits of PREF base & limit. */
622 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, bu
);
623 pci_write_config_dword(bridge
, PCI_PREF_LIMIT_UPPER32
, lu
);
626 static void __pci_setup_bridge(struct pci_bus
*bus
, unsigned long type
)
628 struct pci_dev
*bridge
= bus
->self
;
630 dev_info(&bridge
->dev
, "PCI bridge to %pR\n",
633 if (type
& IORESOURCE_IO
)
634 pci_setup_bridge_io(bus
);
636 if (type
& IORESOURCE_MEM
)
637 pci_setup_bridge_mmio(bus
);
639 if (type
& IORESOURCE_PREFETCH
)
640 pci_setup_bridge_mmio_pref(bus
);
642 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, bus
->bridge_ctl
);
645 void pci_setup_bridge(struct pci_bus
*bus
)
647 unsigned long type
= IORESOURCE_IO
| IORESOURCE_MEM
|
650 __pci_setup_bridge(bus
, type
);
653 /* Check whether the bridge supports optional I/O and
654 prefetchable memory ranges. If not, the respective
655 base/limit registers must be read-only and read as 0. */
656 static void pci_bridge_check_ranges(struct pci_bus
*bus
)
660 struct pci_dev
*bridge
= bus
->self
;
661 struct resource
*b_res
;
663 b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
664 b_res
[1].flags
|= IORESOURCE_MEM
;
666 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
668 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xe0f0);
669 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
670 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
673 b_res
[0].flags
|= IORESOURCE_IO
;
675 /* DECchip 21050 pass 2 errata: the bridge may miss an address
676 disconnect boundary by one PCI data phase.
677 Workaround: do not use prefetching on this device. */
678 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
681 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
683 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
685 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
686 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
689 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
690 if ((pmem
& PCI_PREF_RANGE_TYPE_MASK
) ==
691 PCI_PREF_RANGE_TYPE_64
) {
692 b_res
[2].flags
|= IORESOURCE_MEM_64
;
693 b_res
[2].flags
|= PCI_PREF_RANGE_TYPE_64
;
697 /* double check if bridge does support 64 bit pref */
698 if (b_res
[2].flags
& IORESOURCE_MEM_64
) {
699 u32 mem_base_hi
, tmp
;
700 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
702 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
704 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &tmp
);
706 b_res
[2].flags
&= ~IORESOURCE_MEM_64
;
707 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
712 /* Helper function for sizing routines: find first available
713 bus resource of a given type. Note: we intentionally skip
714 the bus resources which have already been assigned (that is,
715 have non-NULL parent resource). */
716 static struct resource
*find_free_bus_resource(struct pci_bus
*bus
,
717 unsigned long type_mask
, unsigned long type
)
722 pci_bus_for_each_resource(bus
, r
, i
) {
723 if (r
== &ioport_resource
|| r
== &iomem_resource
)
725 if (r
&& (r
->flags
& type_mask
) == type
&& !r
->parent
)
731 static resource_size_t
calculate_iosize(resource_size_t size
,
732 resource_size_t min_size
,
733 resource_size_t size1
,
734 resource_size_t old_size
,
735 resource_size_t align
)
741 /* To be fixed in 2.5: we should have sort of HAVE_ISA
742 flag in the struct pci_bus. */
743 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
744 size
= (size
& 0xff) + ((size
& ~0xffUL
) << 2);
746 size
= ALIGN(size
+ size1
, align
);
752 static resource_size_t
calculate_memsize(resource_size_t size
,
753 resource_size_t min_size
,
754 resource_size_t size1
,
755 resource_size_t old_size
,
756 resource_size_t align
)
764 size
= ALIGN(size
+ size1
, align
);
768 resource_size_t __weak
pcibios_window_alignment(struct pci_bus
*bus
,
774 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
775 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
776 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
778 static resource_size_t
window_alignment(struct pci_bus
*bus
,
781 resource_size_t align
= 1, arch_align
;
783 if (type
& IORESOURCE_MEM
)
784 align
= PCI_P2P_DEFAULT_MEM_ALIGN
;
785 else if (type
& IORESOURCE_IO
) {
787 * Per spec, I/O windows are 4K-aligned, but some
788 * bridges have an extension to support 1K alignment.
790 if (bus
->self
->io_window_1k
)
791 align
= PCI_P2P_DEFAULT_IO_ALIGN_1K
;
793 align
= PCI_P2P_DEFAULT_IO_ALIGN
;
796 arch_align
= pcibios_window_alignment(bus
, type
);
797 return max(align
, arch_align
);
801 * pbus_size_io() - size the io window of a given bus
804 * @min_size : the minimum io window that must to be allocated
805 * @add_size : additional optional io window
806 * @realloc_head : track the additional io window on this list
808 * Sizing the IO windows of the PCI-PCI bridge is trivial,
809 * since these windows have 1K or 4K granularity and the IO ranges
810 * of non-bridge PCI devices are limited to 256 bytes.
811 * We must be careful with the ISA aliasing though.
813 static void pbus_size_io(struct pci_bus
*bus
, resource_size_t min_size
,
814 resource_size_t add_size
, struct list_head
*realloc_head
)
817 struct resource
*b_res
= find_free_bus_resource(bus
, IORESOURCE_IO
,
819 resource_size_t size
= 0, size0
= 0, size1
= 0;
820 resource_size_t children_add_size
= 0;
821 resource_size_t min_align
, align
;
826 min_align
= window_alignment(bus
, IORESOURCE_IO
);
827 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
830 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
831 struct resource
*r
= &dev
->resource
[i
];
832 unsigned long r_size
;
834 if (r
->parent
|| !(r
->flags
& IORESOURCE_IO
))
836 r_size
= resource_size(r
);
839 /* Might be re-aligned for ISA */
844 align
= pci_resource_alignment(dev
, r
);
845 if (align
> min_align
)
849 children_add_size
+= get_res_add_size(realloc_head
, r
);
853 size0
= calculate_iosize(size
, min_size
, size1
,
854 resource_size(b_res
), min_align
);
855 if (children_add_size
> add_size
)
856 add_size
= children_add_size
;
857 size1
= (!realloc_head
|| (realloc_head
&& !add_size
)) ? size0
:
858 calculate_iosize(size
, min_size
, add_size
+ size1
,
859 resource_size(b_res
), min_align
);
860 if (!size0
&& !size1
) {
861 if (b_res
->start
|| b_res
->end
)
862 dev_info(&bus
->self
->dev
, "disabling bridge window "
863 "%pR to %pR (unused)\n", b_res
,
869 b_res
->start
= min_align
;
870 b_res
->end
= b_res
->start
+ size0
- 1;
871 b_res
->flags
|= IORESOURCE_STARTALIGN
;
872 if (size1
> size0
&& realloc_head
) {
873 add_to_list(realloc_head
, bus
->self
, b_res
, size1
-size0
,
875 dev_printk(KERN_DEBUG
, &bus
->self
->dev
, "bridge window "
876 "%pR to %pR add_size %llx\n", b_res
,
878 (unsigned long long)size1
-size0
);
882 static inline resource_size_t
calculate_mem_align(resource_size_t
*aligns
,
885 resource_size_t align
= 0;
886 resource_size_t min_align
= 0;
889 for (order
= 0; order
<= max_order
; order
++) {
890 resource_size_t align1
= 1;
892 align1
<<= (order
+ 20);
896 else if (ALIGN(align
+ min_align
, min_align
) < align1
)
897 min_align
= align1
>> 1;
898 align
+= aligns
[order
];
905 * pbus_size_mem() - size the memory window of a given bus
908 * @mask: mask the resource flag, then compare it with type
909 * @type: the type of free resource from bridge
910 * @type2: second match type
911 * @type3: third match type
912 * @min_size : the minimum memory window that must to be allocated
913 * @add_size : additional optional memory window
914 * @realloc_head : track the additional memory window on this list
916 * Calculate the size of the bus and minimal alignment which
917 * guarantees that all child resources fit in this size.
919 static int pbus_size_mem(struct pci_bus
*bus
, unsigned long mask
,
920 unsigned long type
, unsigned long type2
,
922 resource_size_t min_size
, resource_size_t add_size
,
923 struct list_head
*realloc_head
)
926 resource_size_t min_align
, align
, size
, size0
, size1
;
927 resource_size_t aligns
[14]; /* Alignments from 1Mb to 8Gb */
928 int order
, max_order
;
929 struct resource
*b_res
= find_free_bus_resource(bus
,
930 mask
| IORESOURCE_PREFETCH
, type
);
931 resource_size_t children_add_size
= 0;
936 memset(aligns
, 0, sizeof(aligns
));
940 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
943 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
944 struct resource
*r
= &dev
->resource
[i
];
945 resource_size_t r_size
;
947 if (r
->parent
|| ((r
->flags
& mask
) != type
&&
948 (r
->flags
& mask
) != type2
&&
949 (r
->flags
& mask
) != type3
))
951 r_size
= resource_size(r
);
952 #ifdef CONFIG_PCI_IOV
953 /* put SRIOV requested res to the optional list */
954 if (realloc_head
&& i
>= PCI_IOV_RESOURCES
&&
955 i
<= PCI_IOV_RESOURCE_END
) {
956 r
->end
= r
->start
- 1;
957 add_to_list(realloc_head
, dev
, r
, r_size
, 0/* don't care */);
958 children_add_size
+= r_size
;
963 * aligns[0] is for 1MB (since bridge memory
964 * windows are always at least 1MB aligned), so
965 * keep "order" from being negative for smaller
968 align
= pci_resource_alignment(dev
, r
);
969 order
= __ffs(align
) - 20;
972 if (order
>= ARRAY_SIZE(aligns
)) {
973 dev_warn(&dev
->dev
, "disabling BAR %d: %pR "
974 "(bad alignment %#llx)\n", i
, r
,
975 (unsigned long long) align
);
980 /* Exclude ranges with size > align from
981 calculation of the alignment. */
983 aligns
[order
] += align
;
984 if (order
> max_order
)
988 children_add_size
+= get_res_add_size(realloc_head
, r
);
992 min_align
= calculate_mem_align(aligns
, max_order
);
993 min_align
= max(min_align
, window_alignment(bus
, b_res
->flags
));
994 size0
= calculate_memsize(size
, min_size
, 0, resource_size(b_res
), min_align
);
995 if (children_add_size
> add_size
)
996 add_size
= children_add_size
;
997 size1
= (!realloc_head
|| (realloc_head
&& !add_size
)) ? size0
:
998 calculate_memsize(size
, min_size
, add_size
,
999 resource_size(b_res
), min_align
);
1000 if (!size0
&& !size1
) {
1001 if (b_res
->start
|| b_res
->end
)
1002 dev_info(&bus
->self
->dev
, "disabling bridge window "
1003 "%pR to %pR (unused)\n", b_res
,
1008 b_res
->start
= min_align
;
1009 b_res
->end
= size0
+ min_align
- 1;
1010 b_res
->flags
|= IORESOURCE_STARTALIGN
;
1011 if (size1
> size0
&& realloc_head
) {
1012 add_to_list(realloc_head
, bus
->self
, b_res
, size1
-size0
, min_align
);
1013 dev_printk(KERN_DEBUG
, &bus
->self
->dev
, "bridge window "
1014 "%pR to %pR add_size %llx\n", b_res
,
1015 &bus
->busn_res
, (unsigned long long)size1
-size0
);
1020 unsigned long pci_cardbus_resource_alignment(struct resource
*res
)
1022 if (res
->flags
& IORESOURCE_IO
)
1023 return pci_cardbus_io_size
;
1024 if (res
->flags
& IORESOURCE_MEM
)
1025 return pci_cardbus_mem_size
;
1029 static void pci_bus_size_cardbus(struct pci_bus
*bus
,
1030 struct list_head
*realloc_head
)
1032 struct pci_dev
*bridge
= bus
->self
;
1033 struct resource
*b_res
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
];
1034 resource_size_t b_res_3_size
= pci_cardbus_mem_size
* 2;
1037 if (b_res
[0].parent
)
1038 goto handle_b_res_1
;
1040 * Reserve some resources for CardBus. We reserve
1041 * a fixed amount of bus space for CardBus bridges.
1043 b_res
[0].start
= pci_cardbus_io_size
;
1044 b_res
[0].end
= b_res
[0].start
+ pci_cardbus_io_size
- 1;
1045 b_res
[0].flags
|= IORESOURCE_IO
| IORESOURCE_STARTALIGN
;
1047 b_res
[0].end
-= pci_cardbus_io_size
;
1048 add_to_list(realloc_head
, bridge
, b_res
, pci_cardbus_io_size
,
1049 pci_cardbus_io_size
);
1053 if (b_res
[1].parent
)
1054 goto handle_b_res_2
;
1055 b_res
[1].start
= pci_cardbus_io_size
;
1056 b_res
[1].end
= b_res
[1].start
+ pci_cardbus_io_size
- 1;
1057 b_res
[1].flags
|= IORESOURCE_IO
| IORESOURCE_STARTALIGN
;
1059 b_res
[1].end
-= pci_cardbus_io_size
;
1060 add_to_list(realloc_head
, bridge
, b_res
+1, pci_cardbus_io_size
,
1061 pci_cardbus_io_size
);
1065 /* MEM1 must not be pref mmio */
1066 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
1067 if (ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM1
) {
1068 ctrl
&= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1
;
1069 pci_write_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, ctrl
);
1070 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
1074 * Check whether prefetchable memory is supported
1077 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
1078 if (!(ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
)) {
1079 ctrl
|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
;
1080 pci_write_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, ctrl
);
1081 pci_read_config_word(bridge
, PCI_CB_BRIDGE_CONTROL
, &ctrl
);
1084 if (b_res
[2].parent
)
1085 goto handle_b_res_3
;
1087 * If we have prefetchable memory support, allocate
1088 * two regions. Otherwise, allocate one region of
1091 if (ctrl
& PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
) {
1092 b_res
[2].start
= pci_cardbus_mem_size
;
1093 b_res
[2].end
= b_res
[2].start
+ pci_cardbus_mem_size
- 1;
1094 b_res
[2].flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
1095 IORESOURCE_STARTALIGN
;
1097 b_res
[2].end
-= pci_cardbus_mem_size
;
1098 add_to_list(realloc_head
, bridge
, b_res
+2,
1099 pci_cardbus_mem_size
, pci_cardbus_mem_size
);
1102 /* reduce that to half */
1103 b_res_3_size
= pci_cardbus_mem_size
;
1107 if (b_res
[3].parent
)
1109 b_res
[3].start
= pci_cardbus_mem_size
;
1110 b_res
[3].end
= b_res
[3].start
+ b_res_3_size
- 1;
1111 b_res
[3].flags
|= IORESOURCE_MEM
| IORESOURCE_STARTALIGN
;
1113 b_res
[3].end
-= b_res_3_size
;
1114 add_to_list(realloc_head
, bridge
, b_res
+3, b_res_3_size
,
1115 pci_cardbus_mem_size
);
1122 void __ref
__pci_bus_size_bridges(struct pci_bus
*bus
,
1123 struct list_head
*realloc_head
)
1125 struct pci_dev
*dev
;
1126 unsigned long mask
, prefmask
, type2
= 0, type3
= 0;
1127 resource_size_t additional_mem_size
= 0, additional_io_size
= 0;
1128 struct resource
*b_res
;
1130 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1131 struct pci_bus
*b
= dev
->subordinate
;
1135 switch (dev
->class >> 8) {
1136 case PCI_CLASS_BRIDGE_CARDBUS
:
1137 pci_bus_size_cardbus(b
, realloc_head
);
1140 case PCI_CLASS_BRIDGE_PCI
:
1142 __pci_bus_size_bridges(b
, realloc_head
);
1148 if (pci_is_root_bus(bus
))
1151 switch (bus
->self
->class >> 8) {
1152 case PCI_CLASS_BRIDGE_CARDBUS
:
1153 /* don't size cardbuses yet. */
1156 case PCI_CLASS_BRIDGE_PCI
:
1157 pci_bridge_check_ranges(bus
);
1158 if (bus
->self
->is_hotplug_bridge
) {
1159 additional_io_size
= pci_hotplug_io_size
;
1160 additional_mem_size
= pci_hotplug_mem_size
;
1166 pbus_size_io(bus
, realloc_head
? 0 : additional_io_size
,
1167 additional_io_size
, realloc_head
);
1168 /* If the bridge supports prefetchable range, size it
1169 separately. If it doesn't, or its prefetchable window
1170 has already been allocated by arch code, try
1171 non-prefetchable range for both types of PCI memory
1173 b_res
= &bus
->self
->resource
[PCI_BRIDGE_RESOURCES
];
1174 mask
= IORESOURCE_MEM
;
1175 prefmask
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
1176 if (b_res
[2].flags
& IORESOURCE_MEM_64
) {
1177 prefmask
|= IORESOURCE_MEM_64
;
1178 if (pbus_size_mem(bus
, prefmask
, prefmask
,
1180 realloc_head
? 0 : additional_mem_size
,
1181 additional_mem_size
, realloc_head
)) {
1183 * Success, with pref mmio64,
1184 * next will size non-pref or
1187 type2
= prefmask
& ~IORESOURCE_MEM_64
;
1188 type3
= prefmask
& ~IORESOURCE_PREFETCH
;
1192 prefmask
&= ~IORESOURCE_MEM_64
;
1193 if (pbus_size_mem(bus
, prefmask
, prefmask
,
1195 realloc_head
? 0 : additional_mem_size
,
1196 additional_mem_size
, realloc_head
)) {
1197 /* Success, next will size non-prefetch. */
1200 additional_mem_size
+= additional_mem_size
;
1201 type2
= type3
= IORESOURCE_MEM
;
1203 pbus_size_mem(bus
, mask
, IORESOURCE_MEM
, type2
, type3
,
1204 realloc_head
? 0 : additional_mem_size
,
1205 additional_mem_size
, realloc_head
);
1210 void __ref
pci_bus_size_bridges(struct pci_bus
*bus
)
1212 __pci_bus_size_bridges(bus
, NULL
);
1214 EXPORT_SYMBOL(pci_bus_size_bridges
);
1216 void __ref
__pci_bus_assign_resources(const struct pci_bus
*bus
,
1217 struct list_head
*realloc_head
,
1218 struct list_head
*fail_head
)
1221 struct pci_dev
*dev
;
1223 pbus_assign_resources_sorted(bus
, realloc_head
, fail_head
);
1225 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1226 b
= dev
->subordinate
;
1230 __pci_bus_assign_resources(b
, realloc_head
, fail_head
);
1232 switch (dev
->class >> 8) {
1233 case PCI_CLASS_BRIDGE_PCI
:
1234 if (!pci_is_enabled(dev
))
1235 pci_setup_bridge(b
);
1238 case PCI_CLASS_BRIDGE_CARDBUS
:
1239 pci_setup_cardbus(b
);
1243 dev_info(&dev
->dev
, "not setting up bridge for bus "
1244 "%04x:%02x\n", pci_domain_nr(b
), b
->number
);
1250 void __ref
pci_bus_assign_resources(const struct pci_bus
*bus
)
1252 __pci_bus_assign_resources(bus
, NULL
, NULL
);
1254 EXPORT_SYMBOL(pci_bus_assign_resources
);
1256 static void __ref
__pci_bridge_assign_resources(const struct pci_dev
*bridge
,
1257 struct list_head
*add_head
,
1258 struct list_head
*fail_head
)
1262 pdev_assign_resources_sorted((struct pci_dev
*)bridge
,
1263 add_head
, fail_head
);
1265 b
= bridge
->subordinate
;
1269 __pci_bus_assign_resources(b
, add_head
, fail_head
);
1271 switch (bridge
->class >> 8) {
1272 case PCI_CLASS_BRIDGE_PCI
:
1273 pci_setup_bridge(b
);
1276 case PCI_CLASS_BRIDGE_CARDBUS
:
1277 pci_setup_cardbus(b
);
1281 dev_info(&bridge
->dev
, "not setting up bridge for bus "
1282 "%04x:%02x\n", pci_domain_nr(b
), b
->number
);
1286 static void pci_bridge_release_resources(struct pci_bus
*bus
,
1289 struct pci_dev
*dev
= bus
->self
;
1291 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
|
1292 IORESOURCE_PREFETCH
| IORESOURCE_MEM_64
;
1293 unsigned old_flags
= 0;
1294 struct resource
*b_res
;
1297 b_res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
1300 * 1. if there is io port assign fail, will release bridge
1302 * 2. if there is non pref mmio assign fail, release bridge
1304 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1305 * is 64bit, release bridge pref mmio.
1306 * 4. if there is pref mmio assign fail, and bridge pref is
1307 * 32bit mmio, release bridge pref mmio
1308 * 5. if there is pref mmio assign fail, and bridge pref is not
1309 * assigned, release bridge nonpref mmio.
1311 if (type
& IORESOURCE_IO
)
1313 else if (!(type
& IORESOURCE_PREFETCH
))
1315 else if ((type
& IORESOURCE_MEM_64
) &&
1316 (b_res
[2].flags
& IORESOURCE_MEM_64
))
1318 else if (!(b_res
[2].flags
& IORESOURCE_MEM_64
) &&
1319 (b_res
[2].flags
& IORESOURCE_PREFETCH
))
1330 * if there are children under that, we should release them
1333 release_child_resources(r
);
1334 if (!release_resource(r
)) {
1335 type
= old_flags
= r
->flags
& type_mask
;
1336 dev_printk(KERN_DEBUG
, &dev
->dev
, "resource %d %pR released\n",
1337 PCI_BRIDGE_RESOURCES
+ idx
, r
);
1338 /* keep the old size */
1339 r
->end
= resource_size(r
) - 1;
1343 /* avoiding touch the one without PREF */
1344 if (type
& IORESOURCE_PREFETCH
)
1345 type
= IORESOURCE_PREFETCH
;
1346 __pci_setup_bridge(bus
, type
);
1347 /* for next child res under same bridge */
1348 r
->flags
= old_flags
;
1357 * try to release pci bridge resources that is from leaf bridge,
1358 * so we can allocate big new one later
1360 static void __ref
pci_bus_release_bridge_resources(struct pci_bus
*bus
,
1362 enum release_type rel_type
)
1364 struct pci_dev
*dev
;
1365 bool is_leaf_bridge
= true;
1367 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1368 struct pci_bus
*b
= dev
->subordinate
;
1372 is_leaf_bridge
= false;
1374 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1377 if (rel_type
== whole_subtree
)
1378 pci_bus_release_bridge_resources(b
, type
,
1382 if (pci_is_root_bus(bus
))
1385 if ((bus
->self
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1388 if ((rel_type
== whole_subtree
) || is_leaf_bridge
)
1389 pci_bridge_release_resources(bus
, type
);
1392 static void pci_bus_dump_res(struct pci_bus
*bus
)
1394 struct resource
*res
;
1397 pci_bus_for_each_resource(bus
, res
, i
) {
1398 if (!res
|| !res
->end
|| !res
->flags
)
1401 dev_printk(KERN_DEBUG
, &bus
->dev
, "resource %d %pR\n", i
, res
);
1405 static void pci_bus_dump_resources(struct pci_bus
*bus
)
1408 struct pci_dev
*dev
;
1411 pci_bus_dump_res(bus
);
1413 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1414 b
= dev
->subordinate
;
1418 pci_bus_dump_resources(b
);
1422 static int pci_bus_get_depth(struct pci_bus
*bus
)
1425 struct pci_bus
*child_bus
;
1427 list_for_each_entry(child_bus
, &bus
->children
, node
){
1430 ret
= pci_bus_get_depth(child_bus
);
1431 if (ret
+ 1 > depth
)
1439 * -1: undefined, will auto detect later
1440 * 0: disabled by user
1441 * 1: disabled by auto detect
1442 * 2: enabled by user
1443 * 3: enabled by auto detect
1453 static enum enable_type pci_realloc_enable
= undefined
;
1454 void __init
pci_realloc_get_opt(char *str
)
1456 if (!strncmp(str
, "off", 3))
1457 pci_realloc_enable
= user_disabled
;
1458 else if (!strncmp(str
, "on", 2))
1459 pci_realloc_enable
= user_enabled
;
1461 static bool pci_realloc_enabled(enum enable_type enable
)
1463 return enable
>= user_enabled
;
1466 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1467 static int iov_resources_unassigned(struct pci_dev
*dev
, void *data
)
1470 bool *unassigned
= data
;
1472 for (i
= PCI_IOV_RESOURCES
; i
<= PCI_IOV_RESOURCE_END
; i
++) {
1473 struct resource
*r
= &dev
->resource
[i
];
1474 struct pci_bus_region region
;
1476 /* Not assigned or rejected by kernel? */
1480 pcibios_resource_to_bus(dev
->bus
, ®ion
, r
);
1481 if (!region
.start
) {
1483 return 1; /* return early from pci_walk_bus() */
1490 static enum enable_type
pci_realloc_detect(struct pci_bus
*bus
,
1491 enum enable_type enable_local
)
1493 bool unassigned
= false;
1495 if (enable_local
!= undefined
)
1496 return enable_local
;
1498 pci_walk_bus(bus
, iov_resources_unassigned
, &unassigned
);
1500 return auto_enabled
;
1502 return enable_local
;
1505 static enum enable_type
pci_realloc_detect(struct pci_bus
*bus
,
1506 enum enable_type enable_local
)
1508 return enable_local
;
1513 * first try will not touch pci bridge res
1514 * second and later try will clear small leaf bridge res
1515 * will stop till to the max depth if can not find good one
1517 void pci_assign_unassigned_root_bus_resources(struct pci_bus
*bus
)
1519 LIST_HEAD(realloc_head
); /* list of resources that
1520 want additional resources */
1521 struct list_head
*add_list
= NULL
;
1522 int tried_times
= 0;
1523 enum release_type rel_type
= leaf_only
;
1524 LIST_HEAD(fail_head
);
1525 struct pci_dev_resource
*fail_res
;
1526 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
|
1527 IORESOURCE_PREFETCH
| IORESOURCE_MEM_64
;
1528 int pci_try_num
= 1;
1529 enum enable_type enable_local
;
1531 /* don't realloc if asked to do so */
1532 enable_local
= pci_realloc_detect(bus
, pci_realloc_enable
);
1533 if (pci_realloc_enabled(enable_local
)) {
1534 int max_depth
= pci_bus_get_depth(bus
);
1536 pci_try_num
= max_depth
+ 1;
1537 dev_printk(KERN_DEBUG
, &bus
->dev
,
1538 "max bus depth: %d pci_try_num: %d\n",
1539 max_depth
, pci_try_num
);
1544 * last try will use add_list, otherwise will try good to have as
1545 * must have, so can realloc parent bridge resource
1547 if (tried_times
+ 1 == pci_try_num
)
1548 add_list
= &realloc_head
;
1549 /* Depth first, calculate sizes and alignments of all
1550 subordinate buses. */
1551 __pci_bus_size_bridges(bus
, add_list
);
1553 /* Depth last, allocate resources and update the hardware. */
1554 __pci_bus_assign_resources(bus
, add_list
, &fail_head
);
1556 BUG_ON(!list_empty(add_list
));
1559 /* any device complain? */
1560 if (list_empty(&fail_head
))
1563 if (tried_times
>= pci_try_num
) {
1564 if (enable_local
== undefined
)
1565 dev_info(&bus
->dev
, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1566 else if (enable_local
== auto_enabled
)
1567 dev_info(&bus
->dev
, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1569 free_list(&fail_head
);
1573 dev_printk(KERN_DEBUG
, &bus
->dev
,
1574 "No. %d try to assign unassigned res\n", tried_times
+ 1);
1576 /* third times and later will not check if it is leaf */
1577 if ((tried_times
+ 1) > 2)
1578 rel_type
= whole_subtree
;
1581 * Try to release leaf bridge's resources that doesn't fit resource of
1582 * child device under that bridge
1584 list_for_each_entry(fail_res
, &fail_head
, list
)
1585 pci_bus_release_bridge_resources(fail_res
->dev
->bus
,
1586 fail_res
->flags
& type_mask
,
1589 /* restore size and flags */
1590 list_for_each_entry(fail_res
, &fail_head
, list
) {
1591 struct resource
*res
= fail_res
->res
;
1593 res
->start
= fail_res
->start
;
1594 res
->end
= fail_res
->end
;
1595 res
->flags
= fail_res
->flags
;
1596 if (fail_res
->dev
->subordinate
)
1599 free_list(&fail_head
);
1604 /* dump the resource on buses */
1605 pci_bus_dump_resources(bus
);
1608 void __init
pci_assign_unassigned_resources(void)
1610 struct pci_bus
*root_bus
;
1612 list_for_each_entry(root_bus
, &pci_root_buses
, node
)
1613 pci_assign_unassigned_root_bus_resources(root_bus
);
1616 void pci_assign_unassigned_bridge_resources(struct pci_dev
*bridge
)
1618 struct pci_bus
*parent
= bridge
->subordinate
;
1619 LIST_HEAD(add_list
); /* list of resources that
1620 want additional resources */
1621 int tried_times
= 0;
1622 LIST_HEAD(fail_head
);
1623 struct pci_dev_resource
*fail_res
;
1625 unsigned long type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
|
1626 IORESOURCE_PREFETCH
;
1629 __pci_bus_size_bridges(parent
, &add_list
);
1630 __pci_bridge_assign_resources(bridge
, &add_list
, &fail_head
);
1631 BUG_ON(!list_empty(&add_list
));
1634 if (list_empty(&fail_head
))
1637 if (tried_times
>= 2) {
1638 /* still fail, don't need to try more */
1639 free_list(&fail_head
);
1643 printk(KERN_DEBUG
"PCI: No. %d try to assign unassigned res\n",
1647 * Try to release leaf bridge's resources that doesn't fit resource of
1648 * child device under that bridge
1650 list_for_each_entry(fail_res
, &fail_head
, list
)
1651 pci_bus_release_bridge_resources(fail_res
->dev
->bus
,
1652 fail_res
->flags
& type_mask
,
1655 /* restore size and flags */
1656 list_for_each_entry(fail_res
, &fail_head
, list
) {
1657 struct resource
*res
= fail_res
->res
;
1659 res
->start
= fail_res
->start
;
1660 res
->end
= fail_res
->end
;
1661 res
->flags
= fail_res
->flags
;
1662 if (fail_res
->dev
->subordinate
)
1665 free_list(&fail_head
);
1670 retval
= pci_reenable_device(bridge
);
1672 dev_err(&bridge
->dev
, "Error reenabling bridge (%d)\n", retval
);
1673 pci_set_master(bridge
);
1675 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources
);
1677 void pci_assign_unassigned_bus_resources(struct pci_bus
*bus
)
1679 struct pci_dev
*dev
;
1680 LIST_HEAD(add_list
); /* list of resources that
1681 want additional resources */
1683 down_read(&pci_bus_sem
);
1684 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1685 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1686 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1687 if (dev
->subordinate
)
1688 __pci_bus_size_bridges(dev
->subordinate
,
1690 up_read(&pci_bus_sem
);
1691 __pci_bus_assign_resources(bus
, &add_list
, NULL
);
1692 BUG_ON(!list_empty(&add_list
));