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[mirror_ubuntu-kernels.git] / drivers / pci / setup-bus.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support routines for initializing a PCI subsystem
4 *
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
9 *
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
15 */
16
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <linux/acpi.h>
26 #include "pci.h"
27
28 unsigned int pci_flags;
29
30 struct pci_dev_resource {
31 struct list_head list;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
36 resource_size_t add_size;
37 resource_size_t min_align;
38 unsigned long flags;
39 };
40
41 static void free_list(struct list_head *head)
42 {
43 struct pci_dev_resource *dev_res, *tmp;
44
45 list_for_each_entry_safe(dev_res, tmp, head, list) {
46 list_del(&dev_res->list);
47 kfree(dev_res);
48 }
49 }
50
51 /**
52 * add_to_list() - add a new resource tracker to the list
53 * @head: Head of the list
54 * @dev: device corresponding to which the resource
55 * belongs
56 * @res: The resource to be tracked
57 * @add_size: additional size to be optionally added
58 * to the resource
59 */
60 static int add_to_list(struct list_head *head,
61 struct pci_dev *dev, struct resource *res,
62 resource_size_t add_size, resource_size_t min_align)
63 {
64 struct pci_dev_resource *tmp;
65
66 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
67 if (!tmp)
68 return -ENOMEM;
69
70 tmp->res = res;
71 tmp->dev = dev;
72 tmp->start = res->start;
73 tmp->end = res->end;
74 tmp->flags = res->flags;
75 tmp->add_size = add_size;
76 tmp->min_align = min_align;
77
78 list_add(&tmp->list, head);
79
80 return 0;
81 }
82
83 static void remove_from_list(struct list_head *head,
84 struct resource *res)
85 {
86 struct pci_dev_resource *dev_res, *tmp;
87
88 list_for_each_entry_safe(dev_res, tmp, head, list) {
89 if (dev_res->res == res) {
90 list_del(&dev_res->list);
91 kfree(dev_res);
92 break;
93 }
94 }
95 }
96
97 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
98 struct resource *res)
99 {
100 struct pci_dev_resource *dev_res;
101
102 list_for_each_entry(dev_res, head, list) {
103 if (dev_res->res == res)
104 return dev_res;
105 }
106
107 return NULL;
108 }
109
110 static resource_size_t get_res_add_size(struct list_head *head,
111 struct resource *res)
112 {
113 struct pci_dev_resource *dev_res;
114
115 dev_res = res_to_dev_res(head, res);
116 return dev_res ? dev_res->add_size : 0;
117 }
118
119 static resource_size_t get_res_add_align(struct list_head *head,
120 struct resource *res)
121 {
122 struct pci_dev_resource *dev_res;
123
124 dev_res = res_to_dev_res(head, res);
125 return dev_res ? dev_res->min_align : 0;
126 }
127
128
129 /* Sort resources by alignment */
130 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
131 {
132 int i;
133
134 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
135 struct resource *r;
136 struct pci_dev_resource *dev_res, *tmp;
137 resource_size_t r_align;
138 struct list_head *n;
139
140 r = &dev->resource[i];
141
142 if (r->flags & IORESOURCE_PCI_FIXED)
143 continue;
144
145 if (!(r->flags) || r->parent)
146 continue;
147
148 r_align = pci_resource_alignment(dev, r);
149 if (!r_align) {
150 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
151 i, r);
152 continue;
153 }
154
155 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
156 if (!tmp)
157 panic("pdev_sort_resources(): kmalloc() failed!\n");
158 tmp->res = r;
159 tmp->dev = dev;
160
161 /* fallback is smallest one or list is empty*/
162 n = head;
163 list_for_each_entry(dev_res, head, list) {
164 resource_size_t align;
165
166 align = pci_resource_alignment(dev_res->dev,
167 dev_res->res);
168
169 if (r_align > align) {
170 n = &dev_res->list;
171 break;
172 }
173 }
174 /* Insert it just before n*/
175 list_add_tail(&tmp->list, n);
176 }
177 }
178
179 static void __dev_sort_resources(struct pci_dev *dev,
180 struct list_head *head)
181 {
182 u16 class = dev->class >> 8;
183
184 /* Don't touch classless devices or host bridges or ioapics. */
185 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
186 return;
187
188 /* Don't touch ioapic devices already enabled by firmware */
189 if (class == PCI_CLASS_SYSTEM_PIC) {
190 u16 command;
191 pci_read_config_word(dev, PCI_COMMAND, &command);
192 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
193 return;
194 }
195
196 pdev_sort_resources(dev, head);
197 }
198
199 static inline void reset_resource(struct resource *res)
200 {
201 res->start = 0;
202 res->end = 0;
203 res->flags = 0;
204 }
205
206 /**
207 * reassign_resources_sorted() - satisfy any additional resource requests
208 *
209 * @realloc_head : head of the list tracking requests requiring additional
210 * resources
211 * @head : head of the list tracking requests with allocated
212 * resources
213 *
214 * Walk through each element of the realloc_head and try to procure
215 * additional resources for the element, provided the element
216 * is in the head list.
217 */
218 static void reassign_resources_sorted(struct list_head *realloc_head,
219 struct list_head *head)
220 {
221 struct resource *res;
222 struct pci_dev_resource *add_res, *tmp;
223 struct pci_dev_resource *dev_res;
224 resource_size_t add_size, align;
225 int idx;
226
227 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
228 bool found_match = false;
229
230 res = add_res->res;
231 /* skip resource that has been reset */
232 if (!res->flags)
233 goto out;
234
235 /* skip this resource if not found in head list */
236 list_for_each_entry(dev_res, head, list) {
237 if (dev_res->res == res) {
238 found_match = true;
239 break;
240 }
241 }
242 if (!found_match)/* just skip */
243 continue;
244
245 idx = res - &add_res->dev->resource[0];
246 add_size = add_res->add_size;
247 align = add_res->min_align;
248 if (!resource_size(res)) {
249 res->start = align;
250 res->end = res->start + add_size - 1;
251 if (pci_assign_resource(add_res->dev, idx))
252 reset_resource(res);
253 } else {
254 res->flags |= add_res->flags &
255 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
256 if (pci_reassign_resource(add_res->dev, idx,
257 add_size, align))
258 pci_printk(KERN_DEBUG, add_res->dev,
259 "failed to add %llx res[%d]=%pR\n",
260 (unsigned long long)add_size,
261 idx, res);
262 }
263 out:
264 list_del(&add_res->list);
265 kfree(add_res);
266 }
267 }
268
269 /**
270 * assign_requested_resources_sorted() - satisfy resource requests
271 *
272 * @head : head of the list tracking requests for resources
273 * @fail_head : head of the list tracking requests that could
274 * not be allocated
275 *
276 * Satisfy resource requests of each element in the list. Add
277 * requests that could not satisfied to the failed_list.
278 */
279 static void assign_requested_resources_sorted(struct list_head *head,
280 struct list_head *fail_head)
281 {
282 struct resource *res;
283 struct pci_dev_resource *dev_res;
284 int idx;
285
286 list_for_each_entry(dev_res, head, list) {
287 res = dev_res->res;
288 idx = res - &dev_res->dev->resource[0];
289 if (resource_size(res) &&
290 pci_assign_resource(dev_res->dev, idx)) {
291 if (fail_head) {
292 /*
293 * if the failed res is for ROM BAR, and it will
294 * be enabled later, don't add it to the list
295 */
296 if (!((idx == PCI_ROM_RESOURCE) &&
297 (!(res->flags & IORESOURCE_ROM_ENABLE))))
298 add_to_list(fail_head,
299 dev_res->dev, res,
300 0 /* don't care */,
301 0 /* don't care */);
302 }
303 reset_resource(res);
304 }
305 }
306 }
307
308 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
309 {
310 struct pci_dev_resource *fail_res;
311 unsigned long mask = 0;
312
313 /* check failed type */
314 list_for_each_entry(fail_res, fail_head, list)
315 mask |= fail_res->flags;
316
317 /*
318 * one pref failed resource will set IORESOURCE_MEM,
319 * as we can allocate pref in non-pref range.
320 * Will release all assigned non-pref sibling resources
321 * according to that bit.
322 */
323 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
324 }
325
326 static bool pci_need_to_release(unsigned long mask, struct resource *res)
327 {
328 if (res->flags & IORESOURCE_IO)
329 return !!(mask & IORESOURCE_IO);
330
331 /* check pref at first */
332 if (res->flags & IORESOURCE_PREFETCH) {
333 if (mask & IORESOURCE_PREFETCH)
334 return true;
335 /* count pref if its parent is non-pref */
336 else if ((mask & IORESOURCE_MEM) &&
337 !(res->parent->flags & IORESOURCE_PREFETCH))
338 return true;
339 else
340 return false;
341 }
342
343 if (res->flags & IORESOURCE_MEM)
344 return !!(mask & IORESOURCE_MEM);
345
346 return false; /* should not get here */
347 }
348
349 static void __assign_resources_sorted(struct list_head *head,
350 struct list_head *realloc_head,
351 struct list_head *fail_head)
352 {
353 /*
354 * Should not assign requested resources at first.
355 * they could be adjacent, so later reassign can not reallocate
356 * them one by one in parent resource window.
357 * Try to assign requested + add_size at beginning
358 * if could do that, could get out early.
359 * if could not do that, we still try to assign requested at first,
360 * then try to reassign add_size for some resources.
361 *
362 * Separate three resource type checking if we need to release
363 * assigned resource after requested + add_size try.
364 * 1. if there is io port assign fail, will release assigned
365 * io port.
366 * 2. if there is pref mmio assign fail, release assigned
367 * pref mmio.
368 * if assigned pref mmio's parent is non-pref mmio and there
369 * is non-pref mmio assign fail, will release that assigned
370 * pref mmio.
371 * 3. if there is non-pref mmio assign fail or pref mmio
372 * assigned fail, will release assigned non-pref mmio.
373 */
374 LIST_HEAD(save_head);
375 LIST_HEAD(local_fail_head);
376 struct pci_dev_resource *save_res;
377 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
378 unsigned long fail_type;
379 resource_size_t add_align, align;
380
381 /* Check if optional add_size is there */
382 if (!realloc_head || list_empty(realloc_head))
383 goto requested_and_reassign;
384
385 /* Save original start, end, flags etc at first */
386 list_for_each_entry(dev_res, head, list) {
387 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
388 free_list(&save_head);
389 goto requested_and_reassign;
390 }
391 }
392
393 /* Update res in head list with add_size in realloc_head list */
394 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
395 dev_res->res->end += get_res_add_size(realloc_head,
396 dev_res->res);
397
398 /*
399 * There are two kinds of additional resources in the list:
400 * 1. bridge resource -- IORESOURCE_STARTALIGN
401 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
402 * Here just fix the additional alignment for bridge
403 */
404 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
405 continue;
406
407 add_align = get_res_add_align(realloc_head, dev_res->res);
408
409 /*
410 * The "head" list is sorted by the alignment to make sure
411 * resources with bigger alignment will be assigned first.
412 * After we change the alignment of a dev_res in "head" list,
413 * we need to reorder the list by alignment to make it
414 * consistent.
415 */
416 if (add_align > dev_res->res->start) {
417 resource_size_t r_size = resource_size(dev_res->res);
418
419 dev_res->res->start = add_align;
420 dev_res->res->end = add_align + r_size - 1;
421
422 list_for_each_entry(dev_res2, head, list) {
423 align = pci_resource_alignment(dev_res2->dev,
424 dev_res2->res);
425 if (add_align > align) {
426 list_move_tail(&dev_res->list,
427 &dev_res2->list);
428 break;
429 }
430 }
431 }
432
433 }
434
435 /* Try updated head list with add_size added */
436 assign_requested_resources_sorted(head, &local_fail_head);
437
438 /* all assigned with add_size ? */
439 if (list_empty(&local_fail_head)) {
440 /* Remove head list from realloc_head list */
441 list_for_each_entry(dev_res, head, list)
442 remove_from_list(realloc_head, dev_res->res);
443 free_list(&save_head);
444 free_list(head);
445 return;
446 }
447
448 /* check failed type */
449 fail_type = pci_fail_res_type_mask(&local_fail_head);
450 /* remove not need to be released assigned res from head list etc */
451 list_for_each_entry_safe(dev_res, tmp_res, head, list)
452 if (dev_res->res->parent &&
453 !pci_need_to_release(fail_type, dev_res->res)) {
454 /* remove it from realloc_head list */
455 remove_from_list(realloc_head, dev_res->res);
456 remove_from_list(&save_head, dev_res->res);
457 list_del(&dev_res->list);
458 kfree(dev_res);
459 }
460
461 free_list(&local_fail_head);
462 /* Release assigned resource */
463 list_for_each_entry(dev_res, head, list)
464 if (dev_res->res->parent)
465 release_resource(dev_res->res);
466 /* Restore start/end/flags from saved list */
467 list_for_each_entry(save_res, &save_head, list) {
468 struct resource *res = save_res->res;
469
470 res->start = save_res->start;
471 res->end = save_res->end;
472 res->flags = save_res->flags;
473 }
474 free_list(&save_head);
475
476 requested_and_reassign:
477 /* Satisfy the must-have resource requests */
478 assign_requested_resources_sorted(head, fail_head);
479
480 /* Try to satisfy any additional optional resource
481 requests */
482 if (realloc_head)
483 reassign_resources_sorted(realloc_head, head);
484 free_list(head);
485 }
486
487 static void pdev_assign_resources_sorted(struct pci_dev *dev,
488 struct list_head *add_head,
489 struct list_head *fail_head)
490 {
491 LIST_HEAD(head);
492
493 __dev_sort_resources(dev, &head);
494 __assign_resources_sorted(&head, add_head, fail_head);
495
496 }
497
498 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
499 struct list_head *realloc_head,
500 struct list_head *fail_head)
501 {
502 struct pci_dev *dev;
503 LIST_HEAD(head);
504
505 list_for_each_entry(dev, &bus->devices, bus_list)
506 __dev_sort_resources(dev, &head);
507
508 __assign_resources_sorted(&head, realloc_head, fail_head);
509 }
510
511 void pci_setup_cardbus(struct pci_bus *bus)
512 {
513 struct pci_dev *bridge = bus->self;
514 struct resource *res;
515 struct pci_bus_region region;
516
517 pci_info(bridge, "CardBus bridge to %pR\n",
518 &bus->busn_res);
519
520 res = bus->resource[0];
521 pcibios_resource_to_bus(bridge->bus, &region, res);
522 if (res->flags & IORESOURCE_IO) {
523 /*
524 * The IO resource is allocated a range twice as large as it
525 * would normally need. This allows us to set both IO regs.
526 */
527 pci_info(bridge, " bridge window %pR\n", res);
528 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
529 region.start);
530 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
531 region.end);
532 }
533
534 res = bus->resource[1];
535 pcibios_resource_to_bus(bridge->bus, &region, res);
536 if (res->flags & IORESOURCE_IO) {
537 pci_info(bridge, " bridge window %pR\n", res);
538 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
539 region.start);
540 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
541 region.end);
542 }
543
544 res = bus->resource[2];
545 pcibios_resource_to_bus(bridge->bus, &region, res);
546 if (res->flags & IORESOURCE_MEM) {
547 pci_info(bridge, " bridge window %pR\n", res);
548 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
549 region.start);
550 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
551 region.end);
552 }
553
554 res = bus->resource[3];
555 pcibios_resource_to_bus(bridge->bus, &region, res);
556 if (res->flags & IORESOURCE_MEM) {
557 pci_info(bridge, " bridge window %pR\n", res);
558 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
559 region.start);
560 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
561 region.end);
562 }
563 }
564 EXPORT_SYMBOL(pci_setup_cardbus);
565
566 /* Initialize bridges with base/limit values we have collected.
567 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
568 requires that if there is no I/O ports or memory behind the
569 bridge, corresponding range must be turned off by writing base
570 value greater than limit to the bridge's base/limit registers.
571
572 Note: care must be taken when updating I/O base/limit registers
573 of bridges which support 32-bit I/O. This update requires two
574 config space writes, so it's quite possible that an I/O window of
575 the bridge will have some undesirable address (e.g. 0) after the
576 first write. Ditto 64-bit prefetchable MMIO. */
577 static void pci_setup_bridge_io(struct pci_dev *bridge)
578 {
579 struct resource *res;
580 struct pci_bus_region region;
581 unsigned long io_mask;
582 u8 io_base_lo, io_limit_lo;
583 u16 l;
584 u32 io_upper16;
585
586 io_mask = PCI_IO_RANGE_MASK;
587 if (bridge->io_window_1k)
588 io_mask = PCI_IO_1K_RANGE_MASK;
589
590 /* Set up the top and bottom of the PCI I/O segment for this bus. */
591 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
592 pcibios_resource_to_bus(bridge->bus, &region, res);
593 if (res->flags & IORESOURCE_IO) {
594 pci_read_config_word(bridge, PCI_IO_BASE, &l);
595 io_base_lo = (region.start >> 8) & io_mask;
596 io_limit_lo = (region.end >> 8) & io_mask;
597 l = ((u16) io_limit_lo << 8) | io_base_lo;
598 /* Set up upper 16 bits of I/O base/limit. */
599 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
600 pci_info(bridge, " bridge window %pR\n", res);
601 } else {
602 /* Clear upper 16 bits of I/O base/limit. */
603 io_upper16 = 0;
604 l = 0x00f0;
605 }
606 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
607 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
608 /* Update lower 16 bits of I/O base/limit. */
609 pci_write_config_word(bridge, PCI_IO_BASE, l);
610 /* Update upper 16 bits of I/O base/limit. */
611 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
612 }
613
614 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
615 {
616 struct resource *res;
617 struct pci_bus_region region;
618 u32 l;
619
620 /* Set up the top and bottom of the PCI Memory segment for this bus. */
621 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
622 pcibios_resource_to_bus(bridge->bus, &region, res);
623 if (res->flags & IORESOURCE_MEM) {
624 l = (region.start >> 16) & 0xfff0;
625 l |= region.end & 0xfff00000;
626 pci_info(bridge, " bridge window %pR\n", res);
627 } else {
628 l = 0x0000fff0;
629 }
630 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
631 }
632
633 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
634 {
635 struct resource *res;
636 struct pci_bus_region region;
637 u32 l, bu, lu;
638
639 /* Clear out the upper 32 bits of PREF limit.
640 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
641 disables PREF range, which is ok. */
642 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
643
644 /* Set up PREF base/limit. */
645 bu = lu = 0;
646 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
647 pcibios_resource_to_bus(bridge->bus, &region, res);
648 if (res->flags & IORESOURCE_PREFETCH) {
649 l = (region.start >> 16) & 0xfff0;
650 l |= region.end & 0xfff00000;
651 if (res->flags & IORESOURCE_MEM_64) {
652 bu = upper_32_bits(region.start);
653 lu = upper_32_bits(region.end);
654 }
655 pci_info(bridge, " bridge window %pR\n", res);
656 } else {
657 l = 0x0000fff0;
658 }
659 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
660
661 /* Set the upper 32 bits of PREF base & limit. */
662 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
663 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
664 }
665
666 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
667 {
668 struct pci_dev *bridge = bus->self;
669
670 pci_info(bridge, "PCI bridge to %pR\n",
671 &bus->busn_res);
672
673 if (type & IORESOURCE_IO)
674 pci_setup_bridge_io(bridge);
675
676 if (type & IORESOURCE_MEM)
677 pci_setup_bridge_mmio(bridge);
678
679 if (type & IORESOURCE_PREFETCH)
680 pci_setup_bridge_mmio_pref(bridge);
681
682 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
683 }
684
685 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
686 {
687 }
688
689 void pci_setup_bridge(struct pci_bus *bus)
690 {
691 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
692 IORESOURCE_PREFETCH;
693
694 pcibios_setup_bridge(bus, type);
695 __pci_setup_bridge(bus, type);
696 }
697
698
699 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
700 {
701 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
702 return 0;
703
704 if (pci_claim_resource(bridge, i) == 0)
705 return 0; /* claimed the window */
706
707 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
708 return 0;
709
710 if (!pci_bus_clip_resource(bridge, i))
711 return -EINVAL; /* clipping didn't change anything */
712
713 switch (i - PCI_BRIDGE_RESOURCES) {
714 case 0:
715 pci_setup_bridge_io(bridge);
716 break;
717 case 1:
718 pci_setup_bridge_mmio(bridge);
719 break;
720 case 2:
721 pci_setup_bridge_mmio_pref(bridge);
722 break;
723 default:
724 return -EINVAL;
725 }
726
727 if (pci_claim_resource(bridge, i) == 0)
728 return 0; /* claimed a smaller window */
729
730 return -EINVAL;
731 }
732
733 /* Check whether the bridge supports optional I/O and
734 prefetchable memory ranges. If not, the respective
735 base/limit registers must be read-only and read as 0. */
736 static void pci_bridge_check_ranges(struct pci_bus *bus)
737 {
738 u16 io;
739 u32 pmem;
740 struct pci_dev *bridge = bus->self;
741 struct resource *b_res;
742
743 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
744 b_res[1].flags |= IORESOURCE_MEM;
745
746 pci_read_config_word(bridge, PCI_IO_BASE, &io);
747 if (!io) {
748 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
749 pci_read_config_word(bridge, PCI_IO_BASE, &io);
750 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
751 }
752 if (io)
753 b_res[0].flags |= IORESOURCE_IO;
754
755 /* DECchip 21050 pass 2 errata: the bridge may miss an address
756 disconnect boundary by one PCI data phase.
757 Workaround: do not use prefetching on this device. */
758 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
759 return;
760
761 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
762 if (!pmem) {
763 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
764 0xffe0fff0);
765 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
766 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
767 }
768 if (pmem) {
769 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
770 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
771 PCI_PREF_RANGE_TYPE_64) {
772 b_res[2].flags |= IORESOURCE_MEM_64;
773 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
774 }
775 }
776
777 /* double check if bridge does support 64 bit pref */
778 if (b_res[2].flags & IORESOURCE_MEM_64) {
779 u32 mem_base_hi, tmp;
780 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
781 &mem_base_hi);
782 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
783 0xffffffff);
784 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
785 if (!tmp)
786 b_res[2].flags &= ~IORESOURCE_MEM_64;
787 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
788 mem_base_hi);
789 }
790 }
791
792 /* Helper function for sizing routines: find first available
793 bus resource of a given type. Note: we intentionally skip
794 the bus resources which have already been assigned (that is,
795 have non-NULL parent resource). */
796 static struct resource *find_free_bus_resource(struct pci_bus *bus,
797 unsigned long type_mask, unsigned long type)
798 {
799 int i;
800 struct resource *r;
801
802 pci_bus_for_each_resource(bus, r, i) {
803 if (r == &ioport_resource || r == &iomem_resource)
804 continue;
805 if (r && (r->flags & type_mask) == type && !r->parent)
806 return r;
807 }
808 return NULL;
809 }
810
811 static resource_size_t calculate_iosize(resource_size_t size,
812 resource_size_t min_size,
813 resource_size_t size1,
814 resource_size_t add_size,
815 resource_size_t children_add_size,
816 resource_size_t old_size,
817 resource_size_t align)
818 {
819 if (size < min_size)
820 size = min_size;
821 if (old_size == 1)
822 old_size = 0;
823 /* To be fixed in 2.5: we should have sort of HAVE_ISA
824 flag in the struct pci_bus. */
825 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
826 size = (size & 0xff) + ((size & ~0xffUL) << 2);
827 #endif
828 size = size + size1;
829 if (size < old_size)
830 size = old_size;
831
832 size = ALIGN(max(size, add_size) + children_add_size, align);
833 return size;
834 }
835
836 static resource_size_t calculate_memsize(resource_size_t size,
837 resource_size_t min_size,
838 resource_size_t add_size,
839 resource_size_t children_add_size,
840 resource_size_t old_size,
841 resource_size_t align)
842 {
843 if (size < min_size)
844 size = min_size;
845 if (old_size == 1)
846 old_size = 0;
847 if (size < old_size)
848 size = old_size;
849
850 size = ALIGN(max(size, add_size) + children_add_size, align);
851 return size;
852 }
853
854 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
855 unsigned long type)
856 {
857 return 1;
858 }
859
860 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
861 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
862 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
863
864 static resource_size_t window_alignment(struct pci_bus *bus,
865 unsigned long type)
866 {
867 resource_size_t align = 1, arch_align;
868
869 if (type & IORESOURCE_MEM)
870 align = PCI_P2P_DEFAULT_MEM_ALIGN;
871 else if (type & IORESOURCE_IO) {
872 /*
873 * Per spec, I/O windows are 4K-aligned, but some
874 * bridges have an extension to support 1K alignment.
875 */
876 if (bus->self->io_window_1k)
877 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
878 else
879 align = PCI_P2P_DEFAULT_IO_ALIGN;
880 }
881
882 arch_align = pcibios_window_alignment(bus, type);
883 return max(align, arch_align);
884 }
885
886 /**
887 * pbus_size_io() - size the io window of a given bus
888 *
889 * @bus : the bus
890 * @min_size : the minimum io window that must to be allocated
891 * @add_size : additional optional io window
892 * @realloc_head : track the additional io window on this list
893 *
894 * Sizing the IO windows of the PCI-PCI bridge is trivial,
895 * since these windows have 1K or 4K granularity and the IO ranges
896 * of non-bridge PCI devices are limited to 256 bytes.
897 * We must be careful with the ISA aliasing though.
898 */
899 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
900 resource_size_t add_size, struct list_head *realloc_head)
901 {
902 struct pci_dev *dev;
903 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
904 IORESOURCE_IO);
905 resource_size_t size = 0, size0 = 0, size1 = 0;
906 resource_size_t children_add_size = 0;
907 resource_size_t min_align, align;
908
909 if (!b_res)
910 return;
911
912 min_align = window_alignment(bus, IORESOURCE_IO);
913 list_for_each_entry(dev, &bus->devices, bus_list) {
914 int i;
915
916 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
917 struct resource *r = &dev->resource[i];
918 unsigned long r_size;
919
920 if (r->parent || !(r->flags & IORESOURCE_IO))
921 continue;
922 r_size = resource_size(r);
923
924 if (r_size < 0x400)
925 /* Might be re-aligned for ISA */
926 size += r_size;
927 else
928 size1 += r_size;
929
930 align = pci_resource_alignment(dev, r);
931 if (align > min_align)
932 min_align = align;
933
934 if (realloc_head)
935 children_add_size += get_res_add_size(realloc_head, r);
936 }
937 }
938
939 size0 = calculate_iosize(size, min_size, size1, 0, 0,
940 resource_size(b_res), min_align);
941 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
942 calculate_iosize(size, min_size, size1, add_size, children_add_size,
943 resource_size(b_res), min_align);
944 if (!size0 && !size1) {
945 if (b_res->start || b_res->end)
946 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
947 b_res, &bus->busn_res);
948 b_res->flags = 0;
949 return;
950 }
951
952 b_res->start = min_align;
953 b_res->end = b_res->start + size0 - 1;
954 b_res->flags |= IORESOURCE_STARTALIGN;
955 if (size1 > size0 && realloc_head) {
956 add_to_list(realloc_head, bus->self, b_res, size1-size0,
957 min_align);
958 pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n",
959 b_res, &bus->busn_res,
960 (unsigned long long)size1-size0);
961 }
962 }
963
964 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
965 int max_order)
966 {
967 resource_size_t align = 0;
968 resource_size_t min_align = 0;
969 int order;
970
971 for (order = 0; order <= max_order; order++) {
972 resource_size_t align1 = 1;
973
974 align1 <<= (order + 20);
975
976 if (!align)
977 min_align = align1;
978 else if (ALIGN(align + min_align, min_align) < align1)
979 min_align = align1 >> 1;
980 align += aligns[order];
981 }
982
983 return min_align;
984 }
985
986 /**
987 * pbus_size_mem() - size the memory window of a given bus
988 *
989 * @bus : the bus
990 * @mask: mask the resource flag, then compare it with type
991 * @type: the type of free resource from bridge
992 * @type2: second match type
993 * @type3: third match type
994 * @min_size : the minimum memory window that must to be allocated
995 * @add_size : additional optional memory window
996 * @realloc_head : track the additional memory window on this list
997 *
998 * Calculate the size of the bus and minimal alignment which
999 * guarantees that all child resources fit in this size.
1000 *
1001 * Returns -ENOSPC if there's no available bus resource of the desired type.
1002 * Otherwise, sets the bus resource start/end to indicate the required
1003 * size, adds things to realloc_head (if supplied), and returns 0.
1004 */
1005 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1006 unsigned long type, unsigned long type2,
1007 unsigned long type3,
1008 resource_size_t min_size, resource_size_t add_size,
1009 struct list_head *realloc_head)
1010 {
1011 struct pci_dev *dev;
1012 resource_size_t min_align, align, size, size0, size1;
1013 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
1014 int order, max_order;
1015 struct resource *b_res = find_free_bus_resource(bus,
1016 mask | IORESOURCE_PREFETCH, type);
1017 resource_size_t children_add_size = 0;
1018 resource_size_t children_add_align = 0;
1019 resource_size_t add_align = 0;
1020
1021 if (!b_res)
1022 return -ENOSPC;
1023
1024 memset(aligns, 0, sizeof(aligns));
1025 max_order = 0;
1026 size = 0;
1027
1028 list_for_each_entry(dev, &bus->devices, bus_list) {
1029 int i;
1030
1031 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1032 struct resource *r = &dev->resource[i];
1033 resource_size_t r_size;
1034
1035 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1036 ((r->flags & mask) != type &&
1037 (r->flags & mask) != type2 &&
1038 (r->flags & mask) != type3))
1039 continue;
1040 r_size = resource_size(r);
1041 #ifdef CONFIG_PCI_IOV
1042 /* put SRIOV requested res to the optional list */
1043 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1044 i <= PCI_IOV_RESOURCE_END) {
1045 add_align = max(pci_resource_alignment(dev, r), add_align);
1046 r->end = r->start - 1;
1047 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1048 children_add_size += r_size;
1049 continue;
1050 }
1051 #endif
1052 /*
1053 * aligns[0] is for 1MB (since bridge memory
1054 * windows are always at least 1MB aligned), so
1055 * keep "order" from being negative for smaller
1056 * resources.
1057 */
1058 align = pci_resource_alignment(dev, r);
1059 order = __ffs(align) - 20;
1060 if (order < 0)
1061 order = 0;
1062 if (order >= ARRAY_SIZE(aligns)) {
1063 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1064 i, r, (unsigned long long) align);
1065 r->flags = 0;
1066 continue;
1067 }
1068 size += max(r_size, align);
1069 /* Exclude ranges with size > align from
1070 calculation of the alignment. */
1071 if (r_size <= align)
1072 aligns[order] += align;
1073 if (order > max_order)
1074 max_order = order;
1075
1076 if (realloc_head) {
1077 children_add_size += get_res_add_size(realloc_head, r);
1078 children_add_align = get_res_add_align(realloc_head, r);
1079 add_align = max(add_align, children_add_align);
1080 }
1081 }
1082 }
1083
1084 min_align = calculate_mem_align(aligns, max_order);
1085 min_align = max(min_align, window_alignment(bus, b_res->flags));
1086 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1087 add_align = max(min_align, add_align);
1088 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1089 calculate_memsize(size, min_size, add_size, children_add_size,
1090 resource_size(b_res), add_align);
1091 if (!size0 && !size1) {
1092 if (b_res->start || b_res->end)
1093 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1094 b_res, &bus->busn_res);
1095 b_res->flags = 0;
1096 return 0;
1097 }
1098 b_res->start = min_align;
1099 b_res->end = size0 + min_align - 1;
1100 b_res->flags |= IORESOURCE_STARTALIGN;
1101 if (size1 > size0 && realloc_head) {
1102 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1103 pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1104 b_res, &bus->busn_res,
1105 (unsigned long long) (size1 - size0),
1106 (unsigned long long) add_align);
1107 }
1108 return 0;
1109 }
1110
1111 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1112 {
1113 if (res->flags & IORESOURCE_IO)
1114 return pci_cardbus_io_size;
1115 if (res->flags & IORESOURCE_MEM)
1116 return pci_cardbus_mem_size;
1117 return 0;
1118 }
1119
1120 static void pci_bus_size_cardbus(struct pci_bus *bus,
1121 struct list_head *realloc_head)
1122 {
1123 struct pci_dev *bridge = bus->self;
1124 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1125 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1126 u16 ctrl;
1127
1128 if (b_res[0].parent)
1129 goto handle_b_res_1;
1130 /*
1131 * Reserve some resources for CardBus. We reserve
1132 * a fixed amount of bus space for CardBus bridges.
1133 */
1134 b_res[0].start = pci_cardbus_io_size;
1135 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1136 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1137 if (realloc_head) {
1138 b_res[0].end -= pci_cardbus_io_size;
1139 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1140 pci_cardbus_io_size);
1141 }
1142
1143 handle_b_res_1:
1144 if (b_res[1].parent)
1145 goto handle_b_res_2;
1146 b_res[1].start = pci_cardbus_io_size;
1147 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1148 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1149 if (realloc_head) {
1150 b_res[1].end -= pci_cardbus_io_size;
1151 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1152 pci_cardbus_io_size);
1153 }
1154
1155 handle_b_res_2:
1156 /* MEM1 must not be pref mmio */
1157 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1158 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1159 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1160 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1161 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1162 }
1163
1164 /*
1165 * Check whether prefetchable memory is supported
1166 * by this bridge.
1167 */
1168 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1169 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1170 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1171 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1172 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1173 }
1174
1175 if (b_res[2].parent)
1176 goto handle_b_res_3;
1177 /*
1178 * If we have prefetchable memory support, allocate
1179 * two regions. Otherwise, allocate one region of
1180 * twice the size.
1181 */
1182 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1183 b_res[2].start = pci_cardbus_mem_size;
1184 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1185 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1186 IORESOURCE_STARTALIGN;
1187 if (realloc_head) {
1188 b_res[2].end -= pci_cardbus_mem_size;
1189 add_to_list(realloc_head, bridge, b_res+2,
1190 pci_cardbus_mem_size, pci_cardbus_mem_size);
1191 }
1192
1193 /* reduce that to half */
1194 b_res_3_size = pci_cardbus_mem_size;
1195 }
1196
1197 handle_b_res_3:
1198 if (b_res[3].parent)
1199 goto handle_done;
1200 b_res[3].start = pci_cardbus_mem_size;
1201 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1202 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1203 if (realloc_head) {
1204 b_res[3].end -= b_res_3_size;
1205 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1206 pci_cardbus_mem_size);
1207 }
1208
1209 handle_done:
1210 ;
1211 }
1212
1213 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1214 {
1215 struct pci_dev *dev;
1216 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1217 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1218 struct resource *b_res;
1219 int ret;
1220
1221 list_for_each_entry(dev, &bus->devices, bus_list) {
1222 struct pci_bus *b = dev->subordinate;
1223 if (!b)
1224 continue;
1225
1226 switch (dev->class >> 8) {
1227 case PCI_CLASS_BRIDGE_CARDBUS:
1228 pci_bus_size_cardbus(b, realloc_head);
1229 break;
1230
1231 case PCI_CLASS_BRIDGE_PCI:
1232 default:
1233 __pci_bus_size_bridges(b, realloc_head);
1234 break;
1235 }
1236 }
1237
1238 /* The root bus? */
1239 if (pci_is_root_bus(bus))
1240 return;
1241
1242 switch (bus->self->class >> 8) {
1243 case PCI_CLASS_BRIDGE_CARDBUS:
1244 /* don't size cardbuses yet. */
1245 break;
1246
1247 case PCI_CLASS_BRIDGE_PCI:
1248 pci_bridge_check_ranges(bus);
1249 if (bus->self->is_hotplug_bridge) {
1250 additional_io_size = pci_hotplug_io_size;
1251 additional_mem_size = pci_hotplug_mem_size;
1252 }
1253 /* Fall through */
1254 default:
1255 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1256 additional_io_size, realloc_head);
1257
1258 /*
1259 * If there's a 64-bit prefetchable MMIO window, compute
1260 * the size required to put all 64-bit prefetchable
1261 * resources in it.
1262 */
1263 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1264 mask = IORESOURCE_MEM;
1265 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1266 if (b_res[2].flags & IORESOURCE_MEM_64) {
1267 prefmask |= IORESOURCE_MEM_64;
1268 ret = pbus_size_mem(bus, prefmask, prefmask,
1269 prefmask, prefmask,
1270 realloc_head ? 0 : additional_mem_size,
1271 additional_mem_size, realloc_head);
1272
1273 /*
1274 * If successful, all non-prefetchable resources
1275 * and any 32-bit prefetchable resources will go in
1276 * the non-prefetchable window.
1277 */
1278 if (ret == 0) {
1279 mask = prefmask;
1280 type2 = prefmask & ~IORESOURCE_MEM_64;
1281 type3 = prefmask & ~IORESOURCE_PREFETCH;
1282 }
1283 }
1284
1285 /*
1286 * If there is no 64-bit prefetchable window, compute the
1287 * size required to put all prefetchable resources in the
1288 * 32-bit prefetchable window (if there is one).
1289 */
1290 if (!type2) {
1291 prefmask &= ~IORESOURCE_MEM_64;
1292 ret = pbus_size_mem(bus, prefmask, prefmask,
1293 prefmask, prefmask,
1294 realloc_head ? 0 : additional_mem_size,
1295 additional_mem_size, realloc_head);
1296
1297 /*
1298 * If successful, only non-prefetchable resources
1299 * will go in the non-prefetchable window.
1300 */
1301 if (ret == 0)
1302 mask = prefmask;
1303 else
1304 additional_mem_size += additional_mem_size;
1305
1306 type2 = type3 = IORESOURCE_MEM;
1307 }
1308
1309 /*
1310 * Compute the size required to put everything else in the
1311 * non-prefetchable window. This includes:
1312 *
1313 * - all non-prefetchable resources
1314 * - 32-bit prefetchable resources if there's a 64-bit
1315 * prefetchable window or no prefetchable window at all
1316 * - 64-bit prefetchable resources if there's no
1317 * prefetchable window at all
1318 *
1319 * Note that the strategy in __pci_assign_resource() must
1320 * match that used here. Specifically, we cannot put a
1321 * 32-bit prefetchable resource in a 64-bit prefetchable
1322 * window.
1323 */
1324 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1325 realloc_head ? 0 : additional_mem_size,
1326 additional_mem_size, realloc_head);
1327 break;
1328 }
1329 }
1330
1331 void pci_bus_size_bridges(struct pci_bus *bus)
1332 {
1333 __pci_bus_size_bridges(bus, NULL);
1334 }
1335 EXPORT_SYMBOL(pci_bus_size_bridges);
1336
1337 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1338 {
1339 int i;
1340 struct resource *parent_r;
1341 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1342 IORESOURCE_PREFETCH;
1343
1344 pci_bus_for_each_resource(b, parent_r, i) {
1345 if (!parent_r)
1346 continue;
1347
1348 if ((r->flags & mask) == (parent_r->flags & mask) &&
1349 resource_contains(parent_r, r))
1350 request_resource(parent_r, r);
1351 }
1352 }
1353
1354 /*
1355 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1356 * are skipped by pbus_assign_resources_sorted().
1357 */
1358 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1359 {
1360 int i;
1361
1362 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1363 struct pci_bus *b;
1364 struct resource *r = &dev->resource[i];
1365
1366 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1367 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1368 continue;
1369
1370 b = dev->bus;
1371 while (b && !r->parent) {
1372 assign_fixed_resource_on_bus(b, r);
1373 b = b->parent;
1374 }
1375 }
1376 }
1377
1378 void __pci_bus_assign_resources(const struct pci_bus *bus,
1379 struct list_head *realloc_head,
1380 struct list_head *fail_head)
1381 {
1382 struct pci_bus *b;
1383 struct pci_dev *dev;
1384
1385 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1386
1387 list_for_each_entry(dev, &bus->devices, bus_list) {
1388 pdev_assign_fixed_resources(dev);
1389
1390 b = dev->subordinate;
1391 if (!b)
1392 continue;
1393
1394 __pci_bus_assign_resources(b, realloc_head, fail_head);
1395
1396 switch (dev->class >> 8) {
1397 case PCI_CLASS_BRIDGE_PCI:
1398 if (!pci_is_enabled(dev))
1399 pci_setup_bridge(b);
1400 break;
1401
1402 case PCI_CLASS_BRIDGE_CARDBUS:
1403 pci_setup_cardbus(b);
1404 break;
1405
1406 default:
1407 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1408 pci_domain_nr(b), b->number);
1409 break;
1410 }
1411 }
1412 }
1413
1414 void pci_bus_assign_resources(const struct pci_bus *bus)
1415 {
1416 __pci_bus_assign_resources(bus, NULL, NULL);
1417 }
1418 EXPORT_SYMBOL(pci_bus_assign_resources);
1419
1420 static void pci_claim_device_resources(struct pci_dev *dev)
1421 {
1422 int i;
1423
1424 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1425 struct resource *r = &dev->resource[i];
1426
1427 if (!r->flags || r->parent)
1428 continue;
1429
1430 pci_claim_resource(dev, i);
1431 }
1432 }
1433
1434 static void pci_claim_bridge_resources(struct pci_dev *dev)
1435 {
1436 int i;
1437
1438 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1439 struct resource *r = &dev->resource[i];
1440
1441 if (!r->flags || r->parent)
1442 continue;
1443
1444 pci_claim_bridge_resource(dev, i);
1445 }
1446 }
1447
1448 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1449 {
1450 struct pci_dev *dev;
1451 struct pci_bus *child;
1452
1453 list_for_each_entry(dev, &b->devices, bus_list) {
1454 pci_claim_device_resources(dev);
1455
1456 child = dev->subordinate;
1457 if (child)
1458 pci_bus_allocate_dev_resources(child);
1459 }
1460 }
1461
1462 static void pci_bus_allocate_resources(struct pci_bus *b)
1463 {
1464 struct pci_bus *child;
1465
1466 /*
1467 * Carry out a depth-first search on the PCI bus
1468 * tree to allocate bridge apertures. Read the
1469 * programmed bridge bases and recursively claim
1470 * the respective bridge resources.
1471 */
1472 if (b->self) {
1473 pci_read_bridge_bases(b);
1474 pci_claim_bridge_resources(b->self);
1475 }
1476
1477 list_for_each_entry(child, &b->children, node)
1478 pci_bus_allocate_resources(child);
1479 }
1480
1481 void pci_bus_claim_resources(struct pci_bus *b)
1482 {
1483 pci_bus_allocate_resources(b);
1484 pci_bus_allocate_dev_resources(b);
1485 }
1486 EXPORT_SYMBOL(pci_bus_claim_resources);
1487
1488 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1489 struct list_head *add_head,
1490 struct list_head *fail_head)
1491 {
1492 struct pci_bus *b;
1493
1494 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1495 add_head, fail_head);
1496
1497 b = bridge->subordinate;
1498 if (!b)
1499 return;
1500
1501 __pci_bus_assign_resources(b, add_head, fail_head);
1502
1503 switch (bridge->class >> 8) {
1504 case PCI_CLASS_BRIDGE_PCI:
1505 pci_setup_bridge(b);
1506 break;
1507
1508 case PCI_CLASS_BRIDGE_CARDBUS:
1509 pci_setup_cardbus(b);
1510 break;
1511
1512 default:
1513 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1514 pci_domain_nr(b), b->number);
1515 break;
1516 }
1517 }
1518
1519 #define PCI_RES_TYPE_MASK \
1520 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1521 IORESOURCE_MEM_64)
1522
1523 static void pci_bridge_release_resources(struct pci_bus *bus,
1524 unsigned long type)
1525 {
1526 struct pci_dev *dev = bus->self;
1527 struct resource *r;
1528 unsigned old_flags = 0;
1529 struct resource *b_res;
1530 int idx = 1;
1531
1532 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1533
1534 /*
1535 * 1. if there is io port assign fail, will release bridge
1536 * io port.
1537 * 2. if there is non pref mmio assign fail, release bridge
1538 * nonpref mmio.
1539 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1540 * is 64bit, release bridge pref mmio.
1541 * 4. if there is pref mmio assign fail, and bridge pref is
1542 * 32bit mmio, release bridge pref mmio
1543 * 5. if there is pref mmio assign fail, and bridge pref is not
1544 * assigned, release bridge nonpref mmio.
1545 */
1546 if (type & IORESOURCE_IO)
1547 idx = 0;
1548 else if (!(type & IORESOURCE_PREFETCH))
1549 idx = 1;
1550 else if ((type & IORESOURCE_MEM_64) &&
1551 (b_res[2].flags & IORESOURCE_MEM_64))
1552 idx = 2;
1553 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1554 (b_res[2].flags & IORESOURCE_PREFETCH))
1555 idx = 2;
1556 else
1557 idx = 1;
1558
1559 r = &b_res[idx];
1560
1561 if (!r->parent)
1562 return;
1563
1564 /*
1565 * if there are children under that, we should release them
1566 * all
1567 */
1568 release_child_resources(r);
1569 if (!release_resource(r)) {
1570 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1571 pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n",
1572 PCI_BRIDGE_RESOURCES + idx, r);
1573 /* keep the old size */
1574 r->end = resource_size(r) - 1;
1575 r->start = 0;
1576 r->flags = 0;
1577
1578 /* avoiding touch the one without PREF */
1579 if (type & IORESOURCE_PREFETCH)
1580 type = IORESOURCE_PREFETCH;
1581 __pci_setup_bridge(bus, type);
1582 /* for next child res under same bridge */
1583 r->flags = old_flags;
1584 }
1585 }
1586
1587 enum release_type {
1588 leaf_only,
1589 whole_subtree,
1590 };
1591 /*
1592 * try to release pci bridge resources that is from leaf bridge,
1593 * so we can allocate big new one later
1594 */
1595 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1596 unsigned long type,
1597 enum release_type rel_type)
1598 {
1599 struct pci_dev *dev;
1600 bool is_leaf_bridge = true;
1601
1602 list_for_each_entry(dev, &bus->devices, bus_list) {
1603 struct pci_bus *b = dev->subordinate;
1604 if (!b)
1605 continue;
1606
1607 is_leaf_bridge = false;
1608
1609 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1610 continue;
1611
1612 if (rel_type == whole_subtree)
1613 pci_bus_release_bridge_resources(b, type,
1614 whole_subtree);
1615 }
1616
1617 if (pci_is_root_bus(bus))
1618 return;
1619
1620 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1621 return;
1622
1623 if ((rel_type == whole_subtree) || is_leaf_bridge)
1624 pci_bridge_release_resources(bus, type);
1625 }
1626
1627 static void pci_bus_dump_res(struct pci_bus *bus)
1628 {
1629 struct resource *res;
1630 int i;
1631
1632 pci_bus_for_each_resource(bus, res, i) {
1633 if (!res || !res->end || !res->flags)
1634 continue;
1635
1636 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1637 }
1638 }
1639
1640 static void pci_bus_dump_resources(struct pci_bus *bus)
1641 {
1642 struct pci_bus *b;
1643 struct pci_dev *dev;
1644
1645
1646 pci_bus_dump_res(bus);
1647
1648 list_for_each_entry(dev, &bus->devices, bus_list) {
1649 b = dev->subordinate;
1650 if (!b)
1651 continue;
1652
1653 pci_bus_dump_resources(b);
1654 }
1655 }
1656
1657 static int pci_bus_get_depth(struct pci_bus *bus)
1658 {
1659 int depth = 0;
1660 struct pci_bus *child_bus;
1661
1662 list_for_each_entry(child_bus, &bus->children, node) {
1663 int ret;
1664
1665 ret = pci_bus_get_depth(child_bus);
1666 if (ret + 1 > depth)
1667 depth = ret + 1;
1668 }
1669
1670 return depth;
1671 }
1672
1673 /*
1674 * -1: undefined, will auto detect later
1675 * 0: disabled by user
1676 * 1: disabled by auto detect
1677 * 2: enabled by user
1678 * 3: enabled by auto detect
1679 */
1680 enum enable_type {
1681 undefined = -1,
1682 user_disabled,
1683 auto_disabled,
1684 user_enabled,
1685 auto_enabled,
1686 };
1687
1688 static enum enable_type pci_realloc_enable = undefined;
1689 void __init pci_realloc_get_opt(char *str)
1690 {
1691 if (!strncmp(str, "off", 3))
1692 pci_realloc_enable = user_disabled;
1693 else if (!strncmp(str, "on", 2))
1694 pci_realloc_enable = user_enabled;
1695 }
1696 static bool pci_realloc_enabled(enum enable_type enable)
1697 {
1698 return enable >= user_enabled;
1699 }
1700
1701 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1702 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1703 {
1704 int i;
1705 bool *unassigned = data;
1706
1707 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1708 struct resource *r = &dev->resource[i];
1709 struct pci_bus_region region;
1710
1711 /* Not assigned or rejected by kernel? */
1712 if (!r->flags)
1713 continue;
1714
1715 pcibios_resource_to_bus(dev->bus, &region, r);
1716 if (!region.start) {
1717 *unassigned = true;
1718 return 1; /* return early from pci_walk_bus() */
1719 }
1720 }
1721
1722 return 0;
1723 }
1724
1725 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1726 enum enable_type enable_local)
1727 {
1728 bool unassigned = false;
1729
1730 if (enable_local != undefined)
1731 return enable_local;
1732
1733 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1734 if (unassigned)
1735 return auto_enabled;
1736
1737 return enable_local;
1738 }
1739 #else
1740 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1741 enum enable_type enable_local)
1742 {
1743 return enable_local;
1744 }
1745 #endif
1746
1747 /*
1748 * first try will not touch pci bridge res
1749 * second and later try will clear small leaf bridge res
1750 * will stop till to the max depth if can not find good one
1751 */
1752 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1753 {
1754 LIST_HEAD(realloc_head); /* list of resources that
1755 want additional resources */
1756 struct list_head *add_list = NULL;
1757 int tried_times = 0;
1758 enum release_type rel_type = leaf_only;
1759 LIST_HEAD(fail_head);
1760 struct pci_dev_resource *fail_res;
1761 int pci_try_num = 1;
1762 enum enable_type enable_local;
1763
1764 /* don't realloc if asked to do so */
1765 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1766 if (pci_realloc_enabled(enable_local)) {
1767 int max_depth = pci_bus_get_depth(bus);
1768
1769 pci_try_num = max_depth + 1;
1770 dev_printk(KERN_DEBUG, &bus->dev,
1771 "max bus depth: %d pci_try_num: %d\n",
1772 max_depth, pci_try_num);
1773 }
1774
1775 again:
1776 /*
1777 * last try will use add_list, otherwise will try good to have as
1778 * must have, so can realloc parent bridge resource
1779 */
1780 if (tried_times + 1 == pci_try_num)
1781 add_list = &realloc_head;
1782 /* Depth first, calculate sizes and alignments of all
1783 subordinate buses. */
1784 __pci_bus_size_bridges(bus, add_list);
1785
1786 /* Depth last, allocate resources and update the hardware. */
1787 __pci_bus_assign_resources(bus, add_list, &fail_head);
1788 if (add_list)
1789 BUG_ON(!list_empty(add_list));
1790 tried_times++;
1791
1792 /* any device complain? */
1793 if (list_empty(&fail_head))
1794 goto dump;
1795
1796 if (tried_times >= pci_try_num) {
1797 if (enable_local == undefined)
1798 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1799 else if (enable_local == auto_enabled)
1800 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1801
1802 free_list(&fail_head);
1803 goto dump;
1804 }
1805
1806 dev_printk(KERN_DEBUG, &bus->dev,
1807 "No. %d try to assign unassigned res\n", tried_times + 1);
1808
1809 /* third times and later will not check if it is leaf */
1810 if ((tried_times + 1) > 2)
1811 rel_type = whole_subtree;
1812
1813 /*
1814 * Try to release leaf bridge's resources that doesn't fit resource of
1815 * child device under that bridge
1816 */
1817 list_for_each_entry(fail_res, &fail_head, list)
1818 pci_bus_release_bridge_resources(fail_res->dev->bus,
1819 fail_res->flags & PCI_RES_TYPE_MASK,
1820 rel_type);
1821
1822 /* restore size and flags */
1823 list_for_each_entry(fail_res, &fail_head, list) {
1824 struct resource *res = fail_res->res;
1825
1826 res->start = fail_res->start;
1827 res->end = fail_res->end;
1828 res->flags = fail_res->flags;
1829 if (fail_res->dev->subordinate)
1830 res->flags = 0;
1831 }
1832 free_list(&fail_head);
1833
1834 goto again;
1835
1836 dump:
1837 /* dump the resource on buses */
1838 pci_bus_dump_resources(bus);
1839 }
1840
1841 void __init pci_assign_unassigned_resources(void)
1842 {
1843 struct pci_bus *root_bus;
1844
1845 list_for_each_entry(root_bus, &pci_root_buses, node) {
1846 pci_assign_unassigned_root_bus_resources(root_bus);
1847
1848 /* Make sure the root bridge has a companion ACPI device: */
1849 if (ACPI_HANDLE(root_bus->bridge))
1850 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1851 }
1852 }
1853
1854 static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1855 struct list_head *add_list, resource_size_t available)
1856 {
1857 struct pci_dev_resource *dev_res;
1858
1859 if (res->parent)
1860 return;
1861
1862 if (resource_size(res) >= available)
1863 return;
1864
1865 dev_res = res_to_dev_res(add_list, res);
1866 if (!dev_res)
1867 return;
1868
1869 /* Is there room to extend the window? */
1870 if (available - resource_size(res) <= dev_res->add_size)
1871 return;
1872
1873 dev_res->add_size = available - resource_size(res);
1874 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1875 &dev_res->add_size);
1876 }
1877
1878 static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1879 struct list_head *add_list, resource_size_t available_io,
1880 resource_size_t available_mmio, resource_size_t available_mmio_pref)
1881 {
1882 resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1883 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1884 struct resource *io_res, *mmio_res, *mmio_pref_res;
1885 struct pci_dev *dev, *bridge = bus->self;
1886
1887 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1888 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1889 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1890
1891 /*
1892 * Update additional resource list (add_list) to fill all the
1893 * extra resource space available for this port except the space
1894 * calculated in __pci_bus_size_bridges() which covers all the
1895 * devices currently connected to the port and below.
1896 */
1897 extend_bridge_window(bridge, io_res, add_list, available_io);
1898 extend_bridge_window(bridge, mmio_res, add_list, available_mmio);
1899 extend_bridge_window(bridge, mmio_pref_res, add_list,
1900 available_mmio_pref);
1901
1902 /*
1903 * Calculate the total amount of extra resource space we can
1904 * pass to bridges below this one. This is basically the
1905 * extra space reduced by the minimal required space for the
1906 * non-hotplug bridges.
1907 */
1908 remaining_io = available_io;
1909 remaining_mmio = available_mmio;
1910 remaining_mmio_pref = available_mmio_pref;
1911
1912 /*
1913 * Calculate how many hotplug bridges and normal bridges there
1914 * are on this bus. We will distribute the additional available
1915 * resources between hotplug bridges.
1916 */
1917 for_each_pci_bridge(dev, bus) {
1918 if (dev->is_hotplug_bridge)
1919 hotplug_bridges++;
1920 else
1921 normal_bridges++;
1922 }
1923
1924 for_each_pci_bridge(dev, bus) {
1925 const struct resource *res;
1926
1927 if (dev->is_hotplug_bridge)
1928 continue;
1929
1930 /*
1931 * Reduce the available resource space by what the
1932 * bridge and devices below it occupy.
1933 */
1934 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1935 if (!res->parent && available_io > resource_size(res))
1936 remaining_io -= resource_size(res);
1937
1938 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1939 if (!res->parent && available_mmio > resource_size(res))
1940 remaining_mmio -= resource_size(res);
1941
1942 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1943 if (!res->parent && available_mmio_pref > resource_size(res))
1944 remaining_mmio_pref -= resource_size(res);
1945 }
1946
1947 /*
1948 * There is only one bridge on the bus so it gets all available
1949 * resources which it can then distribute to the possible
1950 * hotplug bridges below.
1951 */
1952 if (hotplug_bridges + normal_bridges == 1) {
1953 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1954 if (dev->subordinate) {
1955 pci_bus_distribute_available_resources(dev->subordinate,
1956 add_list, available_io, available_mmio,
1957 available_mmio_pref);
1958 }
1959 return;
1960 }
1961
1962 /*
1963 * Go over devices on this bus and distribute the remaining
1964 * resource space between hotplug bridges.
1965 */
1966 for_each_pci_bridge(dev, bus) {
1967 resource_size_t align, io, mmio, mmio_pref;
1968 struct pci_bus *b;
1969
1970 b = dev->subordinate;
1971 if (!b || !dev->is_hotplug_bridge)
1972 continue;
1973
1974 /*
1975 * Distribute available extra resources equally between
1976 * hotplug-capable downstream ports taking alignment into
1977 * account.
1978 *
1979 * Here hotplug_bridges is always != 0.
1980 */
1981 align = pci_resource_alignment(bridge, io_res);
1982 io = div64_ul(available_io, hotplug_bridges);
1983 io = min(ALIGN(io, align), remaining_io);
1984 remaining_io -= io;
1985
1986 align = pci_resource_alignment(bridge, mmio_res);
1987 mmio = div64_ul(available_mmio, hotplug_bridges);
1988 mmio = min(ALIGN(mmio, align), remaining_mmio);
1989 remaining_mmio -= mmio;
1990
1991 align = pci_resource_alignment(bridge, mmio_pref_res);
1992 mmio_pref = div64_ul(available_mmio_pref, hotplug_bridges);
1993 mmio_pref = min(ALIGN(mmio_pref, align), remaining_mmio_pref);
1994 remaining_mmio_pref -= mmio_pref;
1995
1996 pci_bus_distribute_available_resources(b, add_list, io, mmio,
1997 mmio_pref);
1998 }
1999 }
2000
2001 static void
2002 pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2003 struct list_head *add_list)
2004 {
2005 resource_size_t available_io, available_mmio, available_mmio_pref;
2006 const struct resource *res;
2007
2008 if (!bridge->is_hotplug_bridge)
2009 return;
2010
2011 /* Take the initial extra resources from the hotplug port */
2012 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
2013 available_io = resource_size(res);
2014 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
2015 available_mmio = resource_size(res);
2016 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
2017 available_mmio_pref = resource_size(res);
2018
2019 pci_bus_distribute_available_resources(bridge->subordinate,
2020 add_list, available_io, available_mmio, available_mmio_pref);
2021 }
2022
2023 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2024 {
2025 struct pci_bus *parent = bridge->subordinate;
2026 LIST_HEAD(add_list); /* list of resources that
2027 want additional resources */
2028 int tried_times = 0;
2029 LIST_HEAD(fail_head);
2030 struct pci_dev_resource *fail_res;
2031 int retval;
2032
2033 again:
2034 __pci_bus_size_bridges(parent, &add_list);
2035
2036 /*
2037 * Distribute remaining resources (if any) equally between
2038 * hotplug bridges below. This makes it possible to extend the
2039 * hierarchy later without running out of resources.
2040 */
2041 pci_bridge_distribute_available_resources(bridge, &add_list);
2042
2043 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2044 BUG_ON(!list_empty(&add_list));
2045 tried_times++;
2046
2047 if (list_empty(&fail_head))
2048 goto enable_all;
2049
2050 if (tried_times >= 2) {
2051 /* still fail, don't need to try more */
2052 free_list(&fail_head);
2053 goto enable_all;
2054 }
2055
2056 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2057 tried_times + 1);
2058
2059 /*
2060 * Try to release leaf bridge's resources that doesn't fit resource of
2061 * child device under that bridge
2062 */
2063 list_for_each_entry(fail_res, &fail_head, list)
2064 pci_bus_release_bridge_resources(fail_res->dev->bus,
2065 fail_res->flags & PCI_RES_TYPE_MASK,
2066 whole_subtree);
2067
2068 /* restore size and flags */
2069 list_for_each_entry(fail_res, &fail_head, list) {
2070 struct resource *res = fail_res->res;
2071
2072 res->start = fail_res->start;
2073 res->end = fail_res->end;
2074 res->flags = fail_res->flags;
2075 if (fail_res->dev->subordinate)
2076 res->flags = 0;
2077 }
2078 free_list(&fail_head);
2079
2080 goto again;
2081
2082 enable_all:
2083 retval = pci_reenable_device(bridge);
2084 if (retval)
2085 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2086 pci_set_master(bridge);
2087 }
2088 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2089
2090 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2091 {
2092 struct pci_dev_resource *dev_res;
2093 struct pci_dev *next;
2094 LIST_HEAD(saved);
2095 LIST_HEAD(added);
2096 LIST_HEAD(failed);
2097 unsigned int i;
2098 int ret;
2099
2100 /* Walk to the root hub, releasing bridge BARs when possible */
2101 next = bridge;
2102 do {
2103 bridge = next;
2104 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2105 i++) {
2106 struct resource *res = &bridge->resource[i];
2107
2108 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2109 continue;
2110
2111 /* Ignore BARs which are still in use */
2112 if (res->child)
2113 continue;
2114
2115 ret = add_to_list(&saved, bridge, res, 0, 0);
2116 if (ret)
2117 goto cleanup;
2118
2119 pci_info(bridge, "BAR %d: releasing %pR\n",
2120 i, res);
2121
2122 if (res->parent)
2123 release_resource(res);
2124 res->start = 0;
2125 res->end = 0;
2126 break;
2127 }
2128 if (i == PCI_BRIDGE_RESOURCE_END)
2129 break;
2130
2131 next = bridge->bus ? bridge->bus->self : NULL;
2132 } while (next);
2133
2134 if (list_empty(&saved))
2135 return -ENOENT;
2136
2137 __pci_bus_size_bridges(bridge->subordinate, &added);
2138 __pci_bridge_assign_resources(bridge, &added, &failed);
2139 BUG_ON(!list_empty(&added));
2140
2141 if (!list_empty(&failed)) {
2142 ret = -ENOSPC;
2143 goto cleanup;
2144 }
2145
2146 list_for_each_entry(dev_res, &saved, list) {
2147 /* Skip the bridge we just assigned resources for. */
2148 if (bridge == dev_res->dev)
2149 continue;
2150
2151 bridge = dev_res->dev;
2152 pci_setup_bridge(bridge->subordinate);
2153 }
2154
2155 free_list(&saved);
2156 return 0;
2157
2158 cleanup:
2159 /* restore size and flags */
2160 list_for_each_entry(dev_res, &failed, list) {
2161 struct resource *res = dev_res->res;
2162
2163 res->start = dev_res->start;
2164 res->end = dev_res->end;
2165 res->flags = dev_res->flags;
2166 }
2167 free_list(&failed);
2168
2169 /* Revert to the old configuration */
2170 list_for_each_entry(dev_res, &saved, list) {
2171 struct resource *res = dev_res->res;
2172
2173 bridge = dev_res->dev;
2174 i = res - bridge->resource;
2175
2176 res->start = dev_res->start;
2177 res->end = dev_res->end;
2178 res->flags = dev_res->flags;
2179
2180 pci_claim_resource(bridge, i);
2181 pci_setup_bridge(bridge->subordinate);
2182 }
2183 free_list(&saved);
2184
2185 return ret;
2186 }
2187
2188 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2189 {
2190 struct pci_dev *dev;
2191 LIST_HEAD(add_list); /* list of resources that
2192 want additional resources */
2193
2194 down_read(&pci_bus_sem);
2195 for_each_pci_bridge(dev, bus)
2196 if (pci_has_subordinate(dev))
2197 __pci_bus_size_bridges(dev->subordinate, &add_list);
2198 up_read(&pci_bus_sem);
2199 __pci_bus_assign_resources(bus, &add_list, NULL);
2200 BUG_ON(!list_empty(&add_list));
2201 }
2202 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
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