drivers/pcmcia/m32r_cfc.c

   1 /*
   2  *  drivers/pcmcia/m32r_cfc.c
   3  *
   4  *  Device driver for the CFC functionality of M32R.
   5  *
   6  *  Copyright (c) 2001, 2002, 2003, 2004
   7  *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/fcntl.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/errno.h>
  18 #include <linux/timer.h>
  19 #include <linux/slab.h>
  20 #include <linux/ioport.h>
  21 #include <linux/delay.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/bitops.h>
  26 #include <asm/irq.h>
  27 #include <asm/io.h>
  28 #include <asm/system.h>
  29
  30 #include <pcmcia/cs_types.h>
  31 #include <pcmcia/ss.h>
  32 #include <pcmcia/cs.h>
  33
  34 #undef MAX_IO_WIN       /* FIXME */
  35 #define MAX_IO_WIN 1
  36 #undef MAX_WIN          /* FIXME */
  37 #define MAX_WIN 1
  38
  39 #include "m32r_cfc.h"
  40
  41 /* Poll status interval -- 0 means default to interrupt */
  42 static int poll_interval = 0;
  43
  44 typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
  45
  46 typedef struct pcc_socket {
  47         u_short                 type, flags;
  48         struct pcmcia_socket    socket;
  49         unsigned int            number;
  50         unsigned int            ioaddr;
  51         u_long                  mapaddr;
  52         u_long                  base;   /* PCC register base */
  53         u_char                  cs_irq1, cs_irq2, intr;
  54         pccard_io_map           io_map[MAX_IO_WIN];
  55         pccard_mem_map          mem_map[MAX_WIN];
  56         u_char                  io_win;
  57         u_char                  mem_win;
  58         pcc_as_t                current_space;
  59         u_char                  last_iodbex;
  60 #ifdef CONFIG_PROC_FS
  61         struct proc_dir_entry *proc;
  62 #endif
  63 } pcc_socket_t;
  64
  65 static int pcc_sockets = 0;
  66 static pcc_socket_t socket[M32R_MAX_PCC] = {
  67         { 0, }, /* ... */
  68 };
  69
  70 /*====================================================================*/
  71
  72 static unsigned int pcc_get(u_short, unsigned int);
  73 static void pcc_set(u_short, unsigned int , unsigned int );
  74
  75 static DEFINE_SPINLOCK(pcc_lock);
  76
  77 #if !defined(CONFIG_PLAT_USRV)
  78 static inline u_long pcc_port2addr(unsigned long port, int size) {
  79         u_long addr = 0;
  80         u_long odd;
  81
  82         if (size == 1) {        /* byte access */
  83                 odd = (port&1) << 11;
  84                 port -= port & 1;
  85                 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
  86         } else if (size == 2)
  87                 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
  88
  89         return addr;
  90 }
  91 #else   /* CONFIG_PLAT_USRV */
  92 static inline u_long pcc_port2addr(unsigned long port, int size) {
  93         u_long odd;
  94         u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
  95
  96         if (size == 1) {        /* byte access */
  97                 odd = port & 1;
  98                 port -= odd;
  99                 odd <<= 11;
 100                 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
 101         } else if (size == 2)   /* word access */
 102                 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
 103
 104         return addr;
 105 }
 106 #endif  /* CONFIG_PLAT_USRV */
 107
 108 void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
 109         size_t nmemb, int flag)
 110 {
 111         u_long addr;
 112         unsigned char *bp = (unsigned char *)buf;
 113         unsigned long flags;
 114
 115         pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
 116                  "size=%u, nmemb=%d, flag=%d\n",
 117                   sock, port, buf, size, nmemb, flag);
 118
 119         addr = pcc_port2addr(port, 1);
 120         if (!addr) {
 121                 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
 122                 return;
 123         }
 124         pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
 125
 126         spin_lock_irqsave(&pcc_lock, flags);
 127         /* read Byte */
 128         while (nmemb--)
 129                 *bp++ = readb(addr);
 130         spin_unlock_irqrestore(&pcc_lock, flags);
 131 }
 132
 133 void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
 134         size_t nmemb, int flag)
 135 {
 136         u_long addr;
 137         unsigned short *bp = (unsigned short *)buf;
 138         unsigned long flags;
 139
 140         pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
 141                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 142                  sock, port, buf, size, nmemb, flag);
 143
 144         if (size != 2)
 145                 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
 146                         port);
 147         if (size == 9)
 148                 printk("m32r_cfc: ioread_word :insw \n");
 149
 150         addr = pcc_port2addr(port, 2);
 151         if (!addr) {
 152                 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
 153                 return;
 154         }
 155         pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
 156
 157         spin_lock_irqsave(&pcc_lock, flags);
 158         /* read Word */
 159         while (nmemb--)
 160                 *bp++ = readw(addr);
 161         spin_unlock_irqrestore(&pcc_lock, flags);
 162 }
 163
 164 void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
 165         size_t nmemb, int flag)
 166 {
 167         u_long addr;
 168         unsigned char *bp = (unsigned char *)buf;
 169         unsigned long flags;
 170
 171         pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
 172                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 173                  sock, port, buf, size, nmemb, flag);
 174
 175         /* write Byte */
 176         addr = pcc_port2addr(port, 1);
 177         if (!addr) {
 178                 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
 179                 return;
 180         }
 181         pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
 182
 183         spin_lock_irqsave(&pcc_lock, flags);
 184         while (nmemb--)
 185                 writeb(*bp++, addr);
 186         spin_unlock_irqrestore(&pcc_lock, flags);
 187 }
 188
 189 void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
 190         size_t nmemb, int flag)
 191 {
 192         u_long addr;
 193         unsigned short *bp = (unsigned short *)buf;
 194         unsigned long flags;
 195
 196         pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
 197                  "buf=%p, size=%u, nmemb=%d, flag=%d\n",
 198                  sock, port, buf, size, nmemb, flag);
 199
 200         if(size != 2)
 201                 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
 202                         size, port);
 203         if(size == 9)
 204                 printk("m32r_cfc: iowrite_word :outsw \n");
 205
 206         addr = pcc_port2addr(port, 2);
 207         if (!addr) {
 208                 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
 209                 return;
 210         }
 211 #if 1
 212         if (addr & 1) {
 213                 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
 214                         addr);
 215                 return;
 216         }
 217 #endif
 218         pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
 219
 220         spin_lock_irqsave(&pcc_lock, flags);
 221         while (nmemb--)
 222                 writew(*bp++, addr);
 223         spin_unlock_irqrestore(&pcc_lock, flags);
 224 }
 225
 226 /*====================================================================*/
 227
 228 #define IS_REGISTERED           0x2000
 229 #define IS_ALIVE                0x8000
 230
 231 typedef struct pcc_t {
 232         char                    *name;
 233         u_short                 flags;
 234 } pcc_t;
 235
 236 static pcc_t pcc[] = {
 237 #if !defined(CONFIG_PLAT_USRV)
 238         { "m32r_cfc", 0 }, { "", 0 },
 239 #else   /* CONFIG_PLAT_USRV */
 240         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
 241         { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
 242 #endif  /* CONFIG_PLAT_USRV */
 243 };
 244
 245 static irqreturn_t pcc_interrupt(int, void *);
 246
 247 /*====================================================================*/
 248
 249 static struct timer_list poll_timer;
 250
 251 static unsigned int pcc_get(u_short sock, unsigned int reg)
 252 {
 253         unsigned int val = inw(reg);
 254         pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
 255         return val;
 256 }
 257
 258
 259 static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
 260 {
 261         outw(data, reg);
 262         pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
 263 }
 264
 265 /*======================================================================
 266
 267         See if a card is present, powered up, in IO mode, and already
 268         bound to a (non PC Card) Linux driver.  We leave these alone.
 269
 270         We make an exception for cards that seem to be serial devices.
 271
 272 ======================================================================*/
 273
 274 static int __init is_alive(u_short sock)
 275 {
 276         unsigned int stat;
 277
 278         pr_debug("m32r_cfc: is_alive:\n");
 279
 280         printk("CF: ");
 281         stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
 282         if (!stat)
 283                 printk("No ");
 284         printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
 285         pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
 286
 287         return 0;
 288 }
 289
 290 static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
 291                            unsigned int ioaddr)
 292 {
 293         pcc_socket_t *t = &socket[pcc_sockets];
 294
 295         pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
 296                  "mapaddr=%#lx, ioaddr=%08x\n",
 297                  base, irq, mapaddr, ioaddr);
 298
 299         /* add sockets */
 300         t->ioaddr = ioaddr;
 301         t->mapaddr = mapaddr;
 302 #if !defined(CONFIG_PLAT_USRV)
 303         t->base = 0;
 304         t->flags = 0;
 305         t->cs_irq1 = irq;               // insert irq
 306         t->cs_irq2 = irq + 1;           // eject irq
 307 #else   /* CONFIG_PLAT_USRV */
 308         t->base = base;
 309         t->flags = 0;
 310         t->cs_irq1 = 0;                 // insert irq
 311         t->cs_irq2 = 0;                 // eject irq
 312 #endif  /* CONFIG_PLAT_USRV */
 313
 314         if (is_alive(pcc_sockets))
 315                 t->flags |= IS_ALIVE;
 316
 317         /* add pcc */
 318 #if !defined(CONFIG_PLAT_USRV)
 319         request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
 320 #else   /* CONFIG_PLAT_USRV */
 321         {
 322                 unsigned int reg_base;
 323
 324                 reg_base = (unsigned int)PLD_CFRSTCR;
 325                 reg_base |= pcc_sockets << 8;
 326                 request_region(reg_base, 0x20, "m32r_cfc");
 327         }
 328 #endif  /* CONFIG_PLAT_USRV */
 329         printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
 330         printk("pcc at 0x%08lx\n", t->base);
 331
 332         /* Update socket interrupt information, capabilities */
 333         t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
 334         t->socket.map_size = M32R_PCC_MAPSIZE;
 335         t->socket.io_offset = ioaddr;   /* use for io access offset */
 336         t->socket.irq_mask = 0;
 337 #if !defined(CONFIG_PLAT_USRV)
 338         t->socket.pci_irq = PLD_IRQ_CFIREQ ;    /* card interrupt */
 339 #else   /* CONFIG_PLAT_USRV */
 340         t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
 341 #endif  /* CONFIG_PLAT_USRV */
 342
 343 #ifndef CONFIG_PLAT_USRV
 344         /* insert interrupt */
 345         request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 346 #ifndef CONFIG_PLAT_MAPPI3
 347         /* eject interrupt */
 348         request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
 349 #endif
 350         pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n");
 351         pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
 352 #endif  /* CONFIG_PLAT_USRV */
 353 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 354         pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
 355 #endif
 356         pcc_sockets++;
 357
 358         return;
 359 }
 360
 361
 362 /*====================================================================*/
 363
 364 static irqreturn_t pcc_interrupt(int irq, void *dev)
 365 {
 366         int i;
 367         u_int events = 0;
 368         int handled = 0;
 369
 370         pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev);
 371         for (i = 0; i < pcc_sockets; i++) {
 372                 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
 373                         continue;
 374
 375                 handled = 1;
 376                 pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
 377                         i, irq);
 378                 events |= SS_DETECT;    /* insert or eject */
 379                 if (events)
 380                         pcmcia_parse_events(&socket[i].socket, events);
 381         }
 382         pr_debug("m32r_cfc: pcc_interrupt: done\n");
 383
 384         return IRQ_RETVAL(handled);
 385 } /* pcc_interrupt */
 386
 387 static void pcc_interrupt_wrapper(u_long data)
 388 {
 389         pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n");
 390         pcc_interrupt(0, NULL);
 391         init_timer(&poll_timer);
 392         poll_timer.expires = jiffies + poll_interval;
 393         add_timer(&poll_timer);
 394 }
 395
 396 /*====================================================================*/
 397
 398 static int _pcc_get_status(u_short sock, u_int *value)
 399 {
 400         u_int status;
 401
 402         pr_debug("m32r_cfc: _pcc_get_status:\n");
 403         status = pcc_get(sock, (unsigned int)PLD_CFSTS);
 404         *value = (status) ? SS_DETECT : 0;
 405         pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
 406
 407 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
 408         if ( status ) {
 409                 /* enable CF power */
 410                 status = inw((unsigned int)PLD_CPCR);
 411                 if (!(status & PLD_CPCR_CF)) {
 412                         pr_debug("m32r_cfc: _pcc_get_status: "
 413                                  "power on (CPCR=0x%08x)\n", status);
 414                         status |= PLD_CPCR_CF;
 415                         outw(status, (unsigned int)PLD_CPCR);
 416                         udelay(100);
 417                 }
 418                 *value |= SS_POWERON;
 419
 420                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
 421                 udelay(100);
 422
 423                 *value |= SS_READY;             /* always ready */
 424                 *value |= SS_3VCARD;
 425         } else {
 426                 /* disable CF power */
 427                 status = inw((unsigned int)PLD_CPCR);
 428                 status &= ~PLD_CPCR_CF;
 429                 outw(status, (unsigned int)PLD_CPCR);
 430                 udelay(100);
 431                 pr_debug("m32r_cfc: _pcc_get_status: "
 432                          "power off (CPCR=0x%08x)\n", status);
 433         }
 434 #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 435         if ( status ) {
 436                 status = pcc_get(sock, (unsigned int)PLD_CPCR);
 437                 if (status == 0) { /* power off */
 438                         pcc_set(sock, (unsigned int)PLD_CPCR, 1);
 439                         pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
 440                         udelay(50);
 441                 }
 442                 *value |= SS_POWERON;
 443
 444                 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
 445                 udelay(50);
 446                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
 447                 udelay(25); /* for IDE reset */
 448                 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
 449                 mdelay(2);  /* for IDE reset */
 450
 451                 *value |= SS_READY;
 452                 *value |= SS_3VCARD;
 453         } else {
 454                 /* disable CF power */
 455                 pcc_set(sock, (unsigned int)PLD_CPCR, 0);
 456                 udelay(100);
 457                 pr_debug("m32r_cfc: _pcc_get_status: "
 458                          "power off (CPCR=0x%08x)\n", status);
 459         }
 460 #else
 461 #error no platform configuration
 462 #endif
 463         pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
 464                  sock, *value);
 465         return 0;
 466 } /* _get_status */
 467
 468 /*====================================================================*/
 469
 470 static int _pcc_set_socket(u_short sock, socket_state_t *state)
 471 {
 472         pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
 473                   "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
 474                   state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
 475
 476 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 477         if (state->Vcc) {
 478                 if ((state->Vcc != 50) && (state->Vcc != 33))
 479                         return -EINVAL;
 480                 /* accept 5V and 3.3V */
 481         }
 482 #endif
 483         if (state->flags & SS_RESET) {
 484                 pr_debug(":RESET\n");
 485                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
 486         }else{
 487                 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
 488         }
 489         if (state->flags & SS_OUTPUT_ENA){
 490                 pr_debug(":OUTPUT_ENA\n");
 491                 /* bit clear */
 492                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
 493         } else {
 494                 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
 495         }
 496
 497         if(state->flags & SS_IOCARD){
 498                 pr_debug(":IOCARD");
 499         }
 500         if (state->flags & SS_PWR_AUTO) {
 501                 pr_debug(":PWR_AUTO");
 502         }
 503         if (state->csc_mask & SS_DETECT)
 504                 pr_debug(":csc-SS_DETECT");
 505         if (state->flags & SS_IOCARD) {
 506                 if (state->csc_mask & SS_STSCHG)
 507                         pr_debug(":STSCHG");
 508         } else {
 509                 if (state->csc_mask & SS_BATDEAD)
 510                         pr_debug(":BATDEAD");
 511                 if (state->csc_mask & SS_BATWARN)
 512                         pr_debug(":BATWARN");
 513                 if (state->csc_mask & SS_READY)
 514                         pr_debug(":READY");
 515         }
 516         pr_debug("\n");
 517         return 0;
 518 } /* _set_socket */
 519
 520 /*====================================================================*/
 521
 522 static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
 523 {
 524         u_char map;
 525
 526         pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
 527                   "%#llx-%#llx)\n", sock, io->map, io->flags,
 528                   io->speed, (unsigned long long)io->start,
 529                   (unsigned long long)io->stop);
 530         map = io->map;
 531
 532         return 0;
 533 } /* _set_io_map */
 534
 535 /*====================================================================*/
 536
 537 static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
 538 {
 539
 540         u_char map = mem->map;
 541         u_long addr;
 542         pcc_socket_t *t = &socket[sock];
 543
 544         pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
 545                  "%#llx, %#x)\n", sock, map, mem->flags,
 546                  mem->speed, (unsigned long long)mem->static_start,
 547                  mem->card_start);
 548
 549         /*
 550          * sanity check
 551          */
 552         if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
 553                 return -EINVAL;
 554         }
 555
 556         /*
 557          * de-activate
 558          */
 559         if ((mem->flags & MAP_ACTIVE) == 0) {
 560                 t->current_space = as_none;
 561                 return 0;
 562         }
 563
 564         /*
 565          * Set mode
 566          */
 567         if (mem->flags & MAP_ATTRIB) {
 568                 t->current_space = as_attr;
 569         } else {
 570                 t->current_space = as_comm;
 571         }
 572
 573         /*
 574          * Set address
 575          */
 576         addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
 577         mem->static_start = addr + mem->card_start;
 578
 579         return 0;
 580
 581 } /* _set_mem_map */
 582
 583 #if 0 /* driver model ordering issue */
 584 /*======================================================================
 585
 586         Routines for accessing socket information and register dumps via
 587         /proc/bus/pccard/...
 588
 589 ======================================================================*/
 590
 591 static ssize_t show_info(struct class_device *class_dev, char *buf)
 592 {
 593         pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
 594                 socket.dev);
 595
 596         return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
 597                 pcc[s->type].name, s->base);
 598 }
 599
 600 static ssize_t show_exca(struct class_device *class_dev, char *buf)
 601 {
 602         /* FIXME */
 603
 604         return 0;
 605 }
 606
 607 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
 608 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
 609 #endif
 610
 611 /*====================================================================*/
 612
 613 /* this is horribly ugly... proper locking needs to be done here at
 614  * some time... */
 615 #define LOCKED(x) do {                                  \
 616         int retval;                                     \
 617         unsigned long flags;                            \
 618         spin_lock_irqsave(&pcc_lock, flags);            \
 619         retval = x;                                     \
 620         spin_unlock_irqrestore(&pcc_lock, flags);       \
 621         return retval;                                  \
 622 } while (0)
 623
 624
 625 static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
 626 {
 627         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 628
 629         if (socket[sock].flags & IS_ALIVE) {
 630                 dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock);
 631                 *value = 0;
 632                 return -EINVAL;
 633         }
 634         dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock);
 635         LOCKED(_pcc_get_status(sock, value));
 636 }
 637
 638 static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
 639 {
 640         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 641
 642         if (socket[sock].flags & IS_ALIVE) {
 643                 dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock);
 644                 return -EINVAL;
 645         }
 646         dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock);
 647         LOCKED(_pcc_set_socket(sock, state));
 648 }
 649
 650 static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
 651 {
 652         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 653
 654         if (socket[sock].flags & IS_ALIVE) {
 655                 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock);
 656                 return -EINVAL;
 657         }
 658         dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock);
 659         LOCKED(_pcc_set_io_map(sock, io));
 660 }
 661
 662 static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
 663 {
 664         unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
 665
 666         if (socket[sock].flags & IS_ALIVE) {
 667                 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
 668                 return -EINVAL;
 669         }
 670         dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock);
 671         LOCKED(_pcc_set_mem_map(sock, mem));
 672 }
 673
 674 static int pcc_init(struct pcmcia_socket *s)
 675 {
 676         dev_dbg(&s->dev, "pcc_init()\n");
 677         return 0;
 678 }
 679
 680 static struct pccard_operations pcc_operations = {
 681         .init                   = pcc_init,
 682         .get_status             = pcc_get_status,
 683         .set_socket             = pcc_set_socket,
 684         .set_io_map             = pcc_set_io_map,
 685         .set_mem_map            = pcc_set_mem_map,
 686 };
 687
 688 static int cfc_drv_pcmcia_suspend(struct platform_device *dev,
 689                                      pm_message_t state)
 690 {
 691         return pcmcia_socket_dev_suspend(&dev->dev);
 692 }
 693
 694 static int cfc_drv_pcmcia_resume(struct platform_device *dev)
 695 {
 696         return pcmcia_socket_dev_resume(&dev->dev);
 697 }
 698 /*====================================================================*/
 699
 700 static struct platform_driver pcc_driver = {
 701         .driver = {
 702                 .name           = "cfc",
 703                 .owner          = THIS_MODULE,
 704         },
 705         .suspend        = cfc_drv_pcmcia_suspend,
 706         .resume         = cfc_drv_pcmcia_resume,
 707 };
 708
 709 static struct platform_device pcc_device = {
 710         .name = "cfc",
 711         .id = 0,
 712 };
 713
 714 /*====================================================================*/
 715
 716 static int __init init_m32r_pcc(void)
 717 {
 718         int i, ret;
 719
 720         ret = platform_driver_register(&pcc_driver);
 721         if (ret)
 722                 return ret;
 723
 724         ret = platform_device_register(&pcc_device);
 725         if (ret){
 726                 platform_driver_unregister(&pcc_driver);
 727                 return ret;
 728         }
 729
 730 #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
 731         pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
 732         pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
 733 #endif
 734
 735         pcc_sockets = 0;
 736
 737 #if !defined(CONFIG_PLAT_USRV)
 738         add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
 739                        CFC_IOPORT_BASE);
 740 #else   /* CONFIG_PLAT_USRV */
 741         {
 742                 ulong base, mapaddr;
 743                 unsigned int ioaddr;
 744
 745                 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
 746                         base = (ulong)PLD_CFRSTCR;
 747                         base = base | (i << 8);
 748                         ioaddr = (i + 1) << 12;
 749                         mapaddr = CFC_ATTR_MAPBASE | (i << 20);
 750                         add_pcc_socket(base, 0, mapaddr, ioaddr);
 751                 }
 752         }
 753 #endif  /* CONFIG_PLAT_USRV */
 754
 755         if (pcc_sockets == 0) {
 756                 printk("socket is not found.\n");
 757                 platform_device_unregister(&pcc_device);
 758                 platform_driver_unregister(&pcc_driver);
 759                 return -ENODEV;
 760         }
 761
 762         /* Set up interrupt handler(s) */
 763
 764         for (i = 0 ; i < pcc_sockets ; i++) {
 765                 socket[i].socket.dev.parent = &pcc_device.dev;
 766                 socket[i].socket.ops = &pcc_operations;
 767                 socket[i].socket.resource_ops = &pccard_static_ops;
 768                 socket[i].socket.owner = THIS_MODULE;
 769                 socket[i].number = i;
 770                 ret = pcmcia_register_socket(&socket[i].socket);
 771                 if (!ret)
 772                         socket[i].flags |= IS_REGISTERED;
 773
 774 #if 0   /* driver model ordering issue */
 775                 class_device_create_file(&socket[i].socket.dev,
 776                                          &class_device_attr_info);
 777                 class_device_create_file(&socket[i].socket.dev,
 778                                          &class_device_attr_exca);
 779 #endif
 780         }
 781
 782         /* Finally, schedule a polling interrupt */
 783         if (poll_interval != 0) {
 784                 poll_timer.function = pcc_interrupt_wrapper;
 785                 poll_timer.data = 0;
 786                 init_timer(&poll_timer);
 787                 poll_timer.expires = jiffies + poll_interval;
 788                 add_timer(&poll_timer);
 789         }
 790
 791         return 0;
 792 } /* init_m32r_pcc */
 793
 794 static void __exit exit_m32r_pcc(void)
 795 {
 796         int i;
 797
 798         for (i = 0; i < pcc_sockets; i++)
 799                 if (socket[i].flags & IS_REGISTERED)
 800                         pcmcia_unregister_socket(&socket[i].socket);
 801
 802         platform_device_unregister(&pcc_device);
 803         if (poll_interval != 0)
 804                 del_timer_sync(&poll_timer);
 805
 806         platform_driver_unregister(&pcc_driver);
 807 } /* exit_m32r_pcc */
 808
 809 module_init(init_m32r_pcc);
 810 module_exit(exit_m32r_pcc);
 811 MODULE_LICENSE("Dual MPL/GPL");
 812 /*====================================================================*/