drivers/perf/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 #
   3 # Performance Monitor Drivers
   4 #
   5
   6 menu "Performance monitor support"
   7         depends on PERF_EVENTS
   8
   9 config ARM_CCI_PMU
  10         tristate "ARM CCI PMU driver"
  11         depends on (ARM && CPU_V7) || ARM64
  12         select ARM_CCI
  13         help
  14           Support for PMU events monitoring on the ARM CCI (Cache Coherent
  15           Interconnect) family of products.
  16
  17           If compiled as a module, it will be called arm-cci.
  18
  19 config ARM_CCI400_PMU
  20         bool "support CCI-400"
  21         default y
  22         depends on ARM_CCI_PMU
  23         select ARM_CCI400_COMMON
  24         help
  25           CCI-400 provides 4 independent event counters counting events related
  26           to the connected slave/master interfaces, plus a cycle counter.
  27
  28 config ARM_CCI5xx_PMU
  29         bool "support CCI-500/CCI-550"
  30         default y
  31         depends on ARM_CCI_PMU
  32         help
  33           CCI-500/CCI-550 both provide 8 independent event counters, which can
  34           count events pertaining to the slave/master interfaces as well as the
  35           internal events to the CCI.
  36
  37 config ARM_CCN
  38         tristate "ARM CCN driver support"
  39         depends on ARM || ARM64
  40         help
  41           PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
  42           interconnect.
  43
  44 config ARM_PMU
  45         depends on ARM || ARM64
  46         bool "ARM PMU framework"
  47         default y
  48         help
  49           Say y if you want to use CPU performance monitors on ARM-based
  50           systems.
  51
  52 config ARM_PMU_ACPI
  53         depends on ARM_PMU && ACPI
  54         def_bool y
  55
  56 config ARM_SMMU_V3_PMU
  57          tristate "ARM SMMUv3 Performance Monitors Extension"
  58          depends on ARM64 && ACPI && ARM_SMMU_V3
  59            help
  60            Provides support for the ARM SMMUv3 Performance Monitor Counter
  61            Groups (PMCG), which provide monitoring of transactions passing
  62            through the SMMU and allow the resulting information to be filtered
  63            based on the Stream ID of the corresponding master.
  64
  65 config ARM_DSU_PMU
  66         tristate "ARM DynamIQ Shared Unit (DSU) PMU"
  67         depends on ARM64
  68           help
  69           Provides support for performance monitor unit in ARM DynamIQ Shared
  70           Unit (DSU). The DSU integrates one or more cores with an L3 memory
  71           system, control logic. The PMU allows counting various events related
  72           to DSU.
  73
  74 config HISI_PMU
  75        bool "HiSilicon SoC PMU"
  76        depends on ARM64 && ACPI
  77        help
  78          Support for HiSilicon SoC uncore performance monitoring
  79          unit (PMU), such as: L3C, HHA and DDRC.
  80
  81 config QCOM_L2_PMU
  82         bool "Qualcomm Technologies L2-cache PMU"
  83         depends on ARCH_QCOM && ARM64 && ACPI
  84           help
  85           Provides support for the L2 cache performance monitor unit (PMU)
  86           in Qualcomm Technologies processors.
  87           Adds the L2 cache PMU into the perf events subsystem for
  88           monitoring L2 cache events.
  89
  90 config QCOM_L3_PMU
  91         bool "Qualcomm Technologies L3-cache PMU"
  92         depends on ARCH_QCOM && ARM64 && ACPI
  93         select QCOM_IRQ_COMBINER
  94         help
  95            Provides support for the L3 cache performance monitor unit (PMU)
  96            in Qualcomm Technologies processors.
  97            Adds the L3 cache PMU into the perf events subsystem for
  98            monitoring L3 cache events.
  99
 100 config THUNDERX2_PMU
 101         tristate "Cavium ThunderX2 SoC PMU UNCORE"
 102         depends on ARCH_THUNDER2 && ARM64 && ACPI && NUMA
 103         default m
 104         help
 105            Provides support for ThunderX2 UNCORE events.
 106            The SoC has PMU support in its L3 cache controller (L3C) and
 107            in the DDR4 Memory Controller (DMC).
 108
 109 config XGENE_PMU
 110         depends on ARCH_XGENE
 111         bool "APM X-Gene SoC PMU"
 112         default n
 113         help
 114           Say y if you want to use APM X-Gene SoC performance monitors.
 115
 116 config ARM_SPE_PMU
 117         tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
 118         depends on ARM64
 119         help
 120           Enable perf support for the ARMv8.2 Statistical Profiling
 121           Extension, which provides periodic sampling of operations in
 122           the CPU pipeline and reports this via the perf AUX interface.
 123
 124 endmenu