1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM DynamIQ Shared Unit (DSU) PMU driver
5 * Copyright (C) ARM Limited, 2017.
7 * Based on ARM CCI-PMU, ARMv8 PMU-v3 drivers.
10 #define PMUNAME "arm_dsu"
11 #define DRVNAME PMUNAME "_pmu"
12 #define pr_fmt(fmt) DRVNAME ": " fmt
14 #include <linux/acpi.h>
15 #include <linux/bitmap.h>
16 #include <linux/bitops.h>
17 #include <linux/bug.h>
18 #include <linux/cpumask.h>
19 #include <linux/device.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of_device.h>
24 #include <linux/perf_event.h>
25 #include <linux/platform_device.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
31 #include <asm/arm_dsu_pmu.h>
32 #include <asm/local64.h>
35 #define DSU_PMU_EVT_CYCLES 0x11
36 #define DSU_PMU_EVT_CHAIN 0x1e
38 #define DSU_PMU_MAX_COMMON_EVENTS 0x40
40 #define DSU_PMU_MAX_HW_CNTRS 32
41 #define DSU_PMU_HW_COUNTER_MASK (DSU_PMU_MAX_HW_CNTRS - 1)
43 #define CLUSTERPMCR_E BIT(0)
44 #define CLUSTERPMCR_P BIT(1)
45 #define CLUSTERPMCR_C BIT(2)
46 #define CLUSTERPMCR_N_SHIFT 11
47 #define CLUSTERPMCR_N_MASK 0x1f
48 #define CLUSTERPMCR_IDCODE_SHIFT 16
49 #define CLUSTERPMCR_IDCODE_MASK 0xff
50 #define CLUSTERPMCR_IMP_SHIFT 24
51 #define CLUSTERPMCR_IMP_MASK 0xff
52 #define CLUSTERPMCR_RES_MASK 0x7e8
53 #define CLUSTERPMCR_RES_VAL 0x40
55 #define DSU_ACTIVE_CPU_MASK 0x0
56 #define DSU_ASSOCIATED_CPU_MASK 0x1
59 * We use the index of the counters as they appear in the counter
60 * bit maps in the PMU registers (e.g CLUSTERPMSELR).
65 * Cycle counter - Bit 31
67 #define DSU_PMU_IDX_CYCLE_COUNTER 31
69 /* All event counters are 32bit, with a 64bit Cycle counter */
70 #define DSU_PMU_COUNTER_WIDTH(idx) \
71 (((idx) == DSU_PMU_IDX_CYCLE_COUNTER) ? 64 : 32)
73 #define DSU_PMU_COUNTER_MASK(idx) \
74 GENMASK_ULL((DSU_PMU_COUNTER_WIDTH((idx)) - 1), 0)
76 #define DSU_EXT_ATTR(_name, _func, _config) \
77 (&((struct dev_ext_attribute[]) { \
79 .attr = __ATTR(_name, 0444, _func, NULL), \
80 .var = (void *)_config \
84 #define DSU_EVENT_ATTR(_name, _config) \
85 DSU_EXT_ATTR(_name, dsu_pmu_sysfs_event_show, (unsigned long)_config)
87 #define DSU_FORMAT_ATTR(_name, _config) \
88 DSU_EXT_ATTR(_name, dsu_pmu_sysfs_format_show, (char *)_config)
90 #define DSU_CPUMASK_ATTR(_name, _config) \
91 DSU_EXT_ATTR(_name, dsu_pmu_cpumask_show, (unsigned long)_config)
93 struct dsu_hw_events
{
94 DECLARE_BITMAP(used_mask
, DSU_PMU_MAX_HW_CNTRS
);
95 struct perf_event
*events
[DSU_PMU_MAX_HW_CNTRS
];
99 * struct dsu_pmu - DSU PMU descriptor
101 * @pmu_lock : Protects accesses to DSU PMU register from normal vs
102 * interrupt handler contexts.
103 * @hw_events : Holds the event counter state.
104 * @associated_cpus : CPUs attached to the DSU.
105 * @active_cpu : CPU to which the PMU is bound for accesses.
106 * @cpuhp_node : Node for CPU hotplug notifier link.
107 * @num_counters : Number of event counters implemented by the PMU,
108 * excluding the cycle counter.
109 * @irq : Interrupt line for counter overflow.
110 * @cpmceid_bitmap : Bitmap for the availability of architected common
111 * events (event_code < 0x40).
116 raw_spinlock_t pmu_lock
;
117 struct dsu_hw_events hw_events
;
118 cpumask_t associated_cpus
;
119 cpumask_t active_cpu
;
120 struct hlist_node cpuhp_node
;
123 DECLARE_BITMAP(cpmceid_bitmap
, DSU_PMU_MAX_COMMON_EVENTS
);
126 static unsigned long dsu_pmu_cpuhp_state
;
128 static inline struct dsu_pmu
*to_dsu_pmu(struct pmu
*pmu
)
130 return container_of(pmu
, struct dsu_pmu
, pmu
);
133 static ssize_t
dsu_pmu_sysfs_event_show(struct device
*dev
,
134 struct device_attribute
*attr
,
137 struct dev_ext_attribute
*eattr
= container_of(attr
,
138 struct dev_ext_attribute
, attr
);
139 return sysfs_emit(buf
, "event=0x%lx\n", (unsigned long)eattr
->var
);
142 static ssize_t
dsu_pmu_sysfs_format_show(struct device
*dev
,
143 struct device_attribute
*attr
,
146 struct dev_ext_attribute
*eattr
= container_of(attr
,
147 struct dev_ext_attribute
, attr
);
148 return sysfs_emit(buf
, "%s\n", (char *)eattr
->var
);
151 static ssize_t
dsu_pmu_cpumask_show(struct device
*dev
,
152 struct device_attribute
*attr
,
155 struct pmu
*pmu
= dev_get_drvdata(dev
);
156 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(pmu
);
157 struct dev_ext_attribute
*eattr
= container_of(attr
,
158 struct dev_ext_attribute
, attr
);
159 unsigned long mask_id
= (unsigned long)eattr
->var
;
160 const cpumask_t
*cpumask
;
163 case DSU_ACTIVE_CPU_MASK
:
164 cpumask
= &dsu_pmu
->active_cpu
;
166 case DSU_ASSOCIATED_CPU_MASK
:
167 cpumask
= &dsu_pmu
->associated_cpus
;
172 return cpumap_print_to_pagebuf(true, buf
, cpumask
);
175 static struct attribute
*dsu_pmu_format_attrs
[] = {
176 DSU_FORMAT_ATTR(event
, "config:0-31"),
180 static const struct attribute_group dsu_pmu_format_attr_group
= {
182 .attrs
= dsu_pmu_format_attrs
,
185 static struct attribute
*dsu_pmu_event_attrs
[] = {
186 DSU_EVENT_ATTR(cycles
, 0x11),
187 DSU_EVENT_ATTR(bus_access
, 0x19),
188 DSU_EVENT_ATTR(memory_error
, 0x1a),
189 DSU_EVENT_ATTR(bus_cycles
, 0x1d),
190 DSU_EVENT_ATTR(l3d_cache_allocate
, 0x29),
191 DSU_EVENT_ATTR(l3d_cache_refill
, 0x2a),
192 DSU_EVENT_ATTR(l3d_cache
, 0x2b),
193 DSU_EVENT_ATTR(l3d_cache_wb
, 0x2c),
198 dsu_pmu_event_attr_is_visible(struct kobject
*kobj
, struct attribute
*attr
,
201 struct pmu
*pmu
= dev_get_drvdata(kobj_to_dev(kobj
));
202 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(pmu
);
203 struct dev_ext_attribute
*eattr
= container_of(attr
,
204 struct dev_ext_attribute
, attr
.attr
);
205 unsigned long evt
= (unsigned long)eattr
->var
;
207 return test_bit(evt
, dsu_pmu
->cpmceid_bitmap
) ? attr
->mode
: 0;
210 static const struct attribute_group dsu_pmu_events_attr_group
= {
212 .attrs
= dsu_pmu_event_attrs
,
213 .is_visible
= dsu_pmu_event_attr_is_visible
,
216 static struct attribute
*dsu_pmu_cpumask_attrs
[] = {
217 DSU_CPUMASK_ATTR(cpumask
, DSU_ACTIVE_CPU_MASK
),
218 DSU_CPUMASK_ATTR(associated_cpus
, DSU_ASSOCIATED_CPU_MASK
),
222 static const struct attribute_group dsu_pmu_cpumask_attr_group
= {
223 .attrs
= dsu_pmu_cpumask_attrs
,
226 static const struct attribute_group
*dsu_pmu_attr_groups
[] = {
227 &dsu_pmu_cpumask_attr_group
,
228 &dsu_pmu_events_attr_group
,
229 &dsu_pmu_format_attr_group
,
233 static int dsu_pmu_get_online_cpu_any_but(struct dsu_pmu
*dsu_pmu
, int cpu
)
235 struct cpumask online_supported
;
237 cpumask_and(&online_supported
,
238 &dsu_pmu
->associated_cpus
, cpu_online_mask
);
239 return cpumask_any_but(&online_supported
, cpu
);
242 static inline bool dsu_pmu_counter_valid(struct dsu_pmu
*dsu_pmu
, u32 idx
)
244 return (idx
< dsu_pmu
->num_counters
) ||
245 (idx
== DSU_PMU_IDX_CYCLE_COUNTER
);
248 static inline u64
dsu_pmu_read_counter(struct perf_event
*event
)
252 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
253 int idx
= event
->hw
.idx
;
255 if (WARN_ON(!cpumask_test_cpu(smp_processor_id(),
256 &dsu_pmu
->associated_cpus
)))
259 if (!dsu_pmu_counter_valid(dsu_pmu
, idx
)) {
260 dev_err(event
->pmu
->dev
,
261 "Trying reading invalid counter %d\n", idx
);
265 raw_spin_lock_irqsave(&dsu_pmu
->pmu_lock
, flags
);
266 if (idx
== DSU_PMU_IDX_CYCLE_COUNTER
)
267 val
= __dsu_pmu_read_pmccntr();
269 val
= __dsu_pmu_read_counter(idx
);
270 raw_spin_unlock_irqrestore(&dsu_pmu
->pmu_lock
, flags
);
275 static void dsu_pmu_write_counter(struct perf_event
*event
, u64 val
)
278 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
279 int idx
= event
->hw
.idx
;
281 if (WARN_ON(!cpumask_test_cpu(smp_processor_id(),
282 &dsu_pmu
->associated_cpus
)))
285 if (!dsu_pmu_counter_valid(dsu_pmu
, idx
)) {
286 dev_err(event
->pmu
->dev
,
287 "writing to invalid counter %d\n", idx
);
291 raw_spin_lock_irqsave(&dsu_pmu
->pmu_lock
, flags
);
292 if (idx
== DSU_PMU_IDX_CYCLE_COUNTER
)
293 __dsu_pmu_write_pmccntr(val
);
295 __dsu_pmu_write_counter(idx
, val
);
296 raw_spin_unlock_irqrestore(&dsu_pmu
->pmu_lock
, flags
);
299 static int dsu_pmu_get_event_idx(struct dsu_hw_events
*hw_events
,
300 struct perf_event
*event
)
303 unsigned long evtype
= event
->attr
.config
;
304 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
305 unsigned long *used_mask
= hw_events
->used_mask
;
307 if (evtype
== DSU_PMU_EVT_CYCLES
) {
308 if (test_and_set_bit(DSU_PMU_IDX_CYCLE_COUNTER
, used_mask
))
310 return DSU_PMU_IDX_CYCLE_COUNTER
;
313 idx
= find_first_zero_bit(used_mask
, dsu_pmu
->num_counters
);
314 if (idx
>= dsu_pmu
->num_counters
)
316 set_bit(idx
, hw_events
->used_mask
);
320 static void dsu_pmu_enable_counter(struct dsu_pmu
*dsu_pmu
, int idx
)
322 __dsu_pmu_counter_interrupt_enable(idx
);
323 __dsu_pmu_enable_counter(idx
);
326 static void dsu_pmu_disable_counter(struct dsu_pmu
*dsu_pmu
, int idx
)
328 __dsu_pmu_disable_counter(idx
);
329 __dsu_pmu_counter_interrupt_disable(idx
);
332 static inline void dsu_pmu_set_event(struct dsu_pmu
*dsu_pmu
,
333 struct perf_event
*event
)
335 int idx
= event
->hw
.idx
;
338 if (!dsu_pmu_counter_valid(dsu_pmu
, idx
)) {
339 dev_err(event
->pmu
->dev
,
340 "Trying to set invalid counter %d\n", idx
);
344 raw_spin_lock_irqsave(&dsu_pmu
->pmu_lock
, flags
);
345 __dsu_pmu_set_event(idx
, event
->hw
.config_base
);
346 raw_spin_unlock_irqrestore(&dsu_pmu
->pmu_lock
, flags
);
349 static void dsu_pmu_event_update(struct perf_event
*event
)
351 struct hw_perf_event
*hwc
= &event
->hw
;
352 u64 delta
, prev_count
, new_count
;
355 /* We may also be called from the irq handler */
356 prev_count
= local64_read(&hwc
->prev_count
);
357 new_count
= dsu_pmu_read_counter(event
);
358 } while (local64_cmpxchg(&hwc
->prev_count
, prev_count
, new_count
) !=
360 delta
= (new_count
- prev_count
) & DSU_PMU_COUNTER_MASK(hwc
->idx
);
361 local64_add(delta
, &event
->count
);
364 static void dsu_pmu_read(struct perf_event
*event
)
366 dsu_pmu_event_update(event
);
369 static inline u32
dsu_pmu_get_reset_overflow(void)
371 return __dsu_pmu_get_reset_overflow();
375 * dsu_pmu_set_event_period: Set the period for the counter.
377 * All DSU PMU event counters, except the cycle counter are 32bit
378 * counters. To handle cases of extreme interrupt latency, we program
379 * the counter with half of the max count for the counters.
381 static void dsu_pmu_set_event_period(struct perf_event
*event
)
383 int idx
= event
->hw
.idx
;
384 u64 val
= DSU_PMU_COUNTER_MASK(idx
) >> 1;
386 local64_set(&event
->hw
.prev_count
, val
);
387 dsu_pmu_write_counter(event
, val
);
390 static irqreturn_t
dsu_pmu_handle_irq(int irq_num
, void *dev
)
393 bool handled
= false;
394 struct dsu_pmu
*dsu_pmu
= dev
;
395 struct dsu_hw_events
*hw_events
= &dsu_pmu
->hw_events
;
396 unsigned long overflow
;
398 overflow
= dsu_pmu_get_reset_overflow();
402 for_each_set_bit(i
, &overflow
, DSU_PMU_MAX_HW_CNTRS
) {
403 struct perf_event
*event
= hw_events
->events
[i
];
407 dsu_pmu_event_update(event
);
408 dsu_pmu_set_event_period(event
);
412 return IRQ_RETVAL(handled
);
415 static void dsu_pmu_start(struct perf_event
*event
, int pmu_flags
)
417 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
419 /* We always reprogram the counter */
420 if (pmu_flags
& PERF_EF_RELOAD
)
421 WARN_ON(!(event
->hw
.state
& PERF_HES_UPTODATE
));
422 dsu_pmu_set_event_period(event
);
423 if (event
->hw
.idx
!= DSU_PMU_IDX_CYCLE_COUNTER
)
424 dsu_pmu_set_event(dsu_pmu
, event
);
426 dsu_pmu_enable_counter(dsu_pmu
, event
->hw
.idx
);
429 static void dsu_pmu_stop(struct perf_event
*event
, int pmu_flags
)
431 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
433 if (event
->hw
.state
& PERF_HES_STOPPED
)
435 dsu_pmu_disable_counter(dsu_pmu
, event
->hw
.idx
);
436 dsu_pmu_event_update(event
);
437 event
->hw
.state
|= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
440 static int dsu_pmu_add(struct perf_event
*event
, int flags
)
442 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
443 struct dsu_hw_events
*hw_events
= &dsu_pmu
->hw_events
;
444 struct hw_perf_event
*hwc
= &event
->hw
;
447 if (WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(),
448 &dsu_pmu
->associated_cpus
)))
451 idx
= dsu_pmu_get_event_idx(hw_events
, event
);
456 hw_events
->events
[idx
] = event
;
457 hwc
->state
= PERF_HES_STOPPED
| PERF_HES_UPTODATE
;
459 if (flags
& PERF_EF_START
)
460 dsu_pmu_start(event
, PERF_EF_RELOAD
);
462 perf_event_update_userpage(event
);
466 static void dsu_pmu_del(struct perf_event
*event
, int flags
)
468 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
469 struct dsu_hw_events
*hw_events
= &dsu_pmu
->hw_events
;
470 struct hw_perf_event
*hwc
= &event
->hw
;
473 dsu_pmu_stop(event
, PERF_EF_UPDATE
);
474 hw_events
->events
[idx
] = NULL
;
475 clear_bit(idx
, hw_events
->used_mask
);
476 perf_event_update_userpage(event
);
479 static void dsu_pmu_enable(struct pmu
*pmu
)
483 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(pmu
);
485 /* If no counters are added, skip enabling the PMU */
486 if (bitmap_empty(dsu_pmu
->hw_events
.used_mask
, DSU_PMU_MAX_HW_CNTRS
))
489 raw_spin_lock_irqsave(&dsu_pmu
->pmu_lock
, flags
);
490 pmcr
= __dsu_pmu_read_pmcr();
491 pmcr
|= CLUSTERPMCR_E
;
492 __dsu_pmu_write_pmcr(pmcr
);
493 raw_spin_unlock_irqrestore(&dsu_pmu
->pmu_lock
, flags
);
496 static void dsu_pmu_disable(struct pmu
*pmu
)
500 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(pmu
);
502 raw_spin_lock_irqsave(&dsu_pmu
->pmu_lock
, flags
);
503 pmcr
= __dsu_pmu_read_pmcr();
504 pmcr
&= ~CLUSTERPMCR_E
;
505 __dsu_pmu_write_pmcr(pmcr
);
506 raw_spin_unlock_irqrestore(&dsu_pmu
->pmu_lock
, flags
);
509 static bool dsu_pmu_validate_event(struct pmu
*pmu
,
510 struct dsu_hw_events
*hw_events
,
511 struct perf_event
*event
)
513 if (is_software_event(event
))
515 /* Reject groups spanning multiple HW PMUs. */
516 if (event
->pmu
!= pmu
)
518 return dsu_pmu_get_event_idx(hw_events
, event
) >= 0;
522 * Make sure the group of events can be scheduled at once
525 static bool dsu_pmu_validate_group(struct perf_event
*event
)
527 struct perf_event
*sibling
, *leader
= event
->group_leader
;
528 struct dsu_hw_events fake_hw
;
530 if (event
->group_leader
== event
)
533 memset(fake_hw
.used_mask
, 0, sizeof(fake_hw
.used_mask
));
534 if (!dsu_pmu_validate_event(event
->pmu
, &fake_hw
, leader
))
536 for_each_sibling_event(sibling
, leader
) {
537 if (!dsu_pmu_validate_event(event
->pmu
, &fake_hw
, sibling
))
540 return dsu_pmu_validate_event(event
->pmu
, &fake_hw
, event
);
543 static int dsu_pmu_event_init(struct perf_event
*event
)
545 struct dsu_pmu
*dsu_pmu
= to_dsu_pmu(event
->pmu
);
547 if (event
->attr
.type
!= event
->pmu
->type
)
550 /* We don't support sampling */
551 if (is_sampling_event(event
)) {
552 dev_dbg(dsu_pmu
->pmu
.dev
, "Can't support sampling events\n");
556 /* We cannot support task bound events */
557 if (event
->cpu
< 0 || event
->attach_state
& PERF_ATTACH_TASK
) {
558 dev_dbg(dsu_pmu
->pmu
.dev
, "Can't support per-task counters\n");
562 if (has_branch_stack(event
)) {
563 dev_dbg(dsu_pmu
->pmu
.dev
, "Can't support filtering\n");
567 if (!cpumask_test_cpu(event
->cpu
, &dsu_pmu
->associated_cpus
)) {
568 dev_dbg(dsu_pmu
->pmu
.dev
,
569 "Requested cpu is not associated with the DSU\n");
573 * Choose the current active CPU to read the events. We don't want
574 * to migrate the event contexts, irq handling etc to the requested
575 * CPU. As long as the requested CPU is within the same DSU, we
578 event
->cpu
= cpumask_first(&dsu_pmu
->active_cpu
);
579 if (event
->cpu
>= nr_cpu_ids
)
581 if (!dsu_pmu_validate_group(event
))
584 event
->hw
.config_base
= event
->attr
.config
;
588 static struct dsu_pmu
*dsu_pmu_alloc(struct platform_device
*pdev
)
590 struct dsu_pmu
*dsu_pmu
;
592 dsu_pmu
= devm_kzalloc(&pdev
->dev
, sizeof(*dsu_pmu
), GFP_KERNEL
);
594 return ERR_PTR(-ENOMEM
);
596 raw_spin_lock_init(&dsu_pmu
->pmu_lock
);
598 * Initialise the number of counters to -1, until we probe
599 * the real number on a connected CPU.
601 dsu_pmu
->num_counters
= -1;
606 * dsu_pmu_dt_get_cpus: Get the list of CPUs in the cluster
609 static int dsu_pmu_dt_get_cpus(struct device
*dev
, cpumask_t
*mask
)
612 struct device_node
*cpu_node
;
614 n
= of_count_phandle_with_args(dev
->of_node
, "cpus", NULL
);
618 cpu_node
= of_parse_phandle(dev
->of_node
, "cpus", i
);
621 cpu
= of_cpu_node_to_id(cpu_node
);
622 of_node_put(cpu_node
);
624 * We have to ignore the failures here and continue scanning
625 * the list to handle cases where the nr_cpus could be capped
626 * in the running kernel.
630 cpumask_set_cpu(cpu
, mask
);
636 * dsu_pmu_acpi_get_cpus: Get the list of CPUs in the cluster
639 static int dsu_pmu_acpi_get_cpus(struct device
*dev
, cpumask_t
*mask
)
645 * A dsu pmu node is inside a cluster parent node along with cpu nodes.
646 * We need to find out all cpus that have the same parent with this pmu.
648 for_each_possible_cpu(cpu
) {
649 struct acpi_device
*acpi_dev
;
650 struct device
*cpu_dev
= get_cpu_device(cpu
);
655 acpi_dev
= ACPI_COMPANION(cpu_dev
);
657 acpi_dev
->parent
== ACPI_COMPANION(dev
)->parent
)
658 cpumask_set_cpu(cpu
, mask
);
666 * dsu_pmu_probe_pmu: Probe the PMU details on a CPU in the cluster.
668 static void dsu_pmu_probe_pmu(struct dsu_pmu
*dsu_pmu
)
673 num_counters
= (__dsu_pmu_read_pmcr() >> CLUSTERPMCR_N_SHIFT
) &
675 /* We can only support up to 31 independent counters */
676 if (WARN_ON(num_counters
> 31))
678 dsu_pmu
->num_counters
= num_counters
;
679 if (!dsu_pmu
->num_counters
)
681 cpmceid
[0] = __dsu_pmu_read_pmceid(0);
682 cpmceid
[1] = __dsu_pmu_read_pmceid(1);
683 bitmap_from_arr32(dsu_pmu
->cpmceid_bitmap
, cpmceid
,
684 DSU_PMU_MAX_COMMON_EVENTS
);
687 static void dsu_pmu_set_active_cpu(int cpu
, struct dsu_pmu
*dsu_pmu
)
689 cpumask_set_cpu(cpu
, &dsu_pmu
->active_cpu
);
690 if (irq_set_affinity(dsu_pmu
->irq
, &dsu_pmu
->active_cpu
))
691 pr_warn("Failed to set irq affinity to %d\n", cpu
);
695 * dsu_pmu_init_pmu: Initialise the DSU PMU configurations if
696 * we haven't done it already.
698 static void dsu_pmu_init_pmu(struct dsu_pmu
*dsu_pmu
)
700 if (dsu_pmu
->num_counters
== -1)
701 dsu_pmu_probe_pmu(dsu_pmu
);
702 /* Reset the interrupt overflow mask */
703 dsu_pmu_get_reset_overflow();
706 static int dsu_pmu_device_probe(struct platform_device
*pdev
)
709 struct dsu_pmu
*dsu_pmu
;
710 struct fwnode_handle
*fwnode
= dev_fwnode(&pdev
->dev
);
712 static atomic_t pmu_idx
= ATOMIC_INIT(-1);
714 dsu_pmu
= dsu_pmu_alloc(pdev
);
716 return PTR_ERR(dsu_pmu
);
718 if (is_of_node(fwnode
))
719 rc
= dsu_pmu_dt_get_cpus(&pdev
->dev
, &dsu_pmu
->associated_cpus
);
720 else if (is_acpi_device_node(fwnode
))
721 rc
= dsu_pmu_acpi_get_cpus(&pdev
->dev
, &dsu_pmu
->associated_cpus
);
726 dev_warn(&pdev
->dev
, "Failed to parse the CPUs\n");
730 irq
= platform_get_irq(pdev
, 0);
734 name
= devm_kasprintf(&pdev
->dev
, GFP_KERNEL
, "%s_%d",
735 PMUNAME
, atomic_inc_return(&pmu_idx
));
738 rc
= devm_request_irq(&pdev
->dev
, irq
, dsu_pmu_handle_irq
,
739 IRQF_NOBALANCING
, name
, dsu_pmu
);
741 dev_warn(&pdev
->dev
, "Failed to request IRQ %d\n", irq
);
746 platform_set_drvdata(pdev
, dsu_pmu
);
747 rc
= cpuhp_state_add_instance(dsu_pmu_cpuhp_state
,
748 &dsu_pmu
->cpuhp_node
);
752 dsu_pmu
->pmu
= (struct pmu
) {
753 .task_ctx_nr
= perf_invalid_context
,
754 .module
= THIS_MODULE
,
755 .pmu_enable
= dsu_pmu_enable
,
756 .pmu_disable
= dsu_pmu_disable
,
757 .event_init
= dsu_pmu_event_init
,
760 .start
= dsu_pmu_start
,
761 .stop
= dsu_pmu_stop
,
762 .read
= dsu_pmu_read
,
764 .attr_groups
= dsu_pmu_attr_groups
,
765 .capabilities
= PERF_PMU_CAP_NO_EXCLUDE
,
768 rc
= perf_pmu_register(&dsu_pmu
->pmu
, name
, -1);
770 cpuhp_state_remove_instance(dsu_pmu_cpuhp_state
,
771 &dsu_pmu
->cpuhp_node
);
777 static int dsu_pmu_device_remove(struct platform_device
*pdev
)
779 struct dsu_pmu
*dsu_pmu
= platform_get_drvdata(pdev
);
781 perf_pmu_unregister(&dsu_pmu
->pmu
);
782 cpuhp_state_remove_instance(dsu_pmu_cpuhp_state
, &dsu_pmu
->cpuhp_node
);
787 static const struct of_device_id dsu_pmu_of_match
[] = {
788 { .compatible
= "arm,dsu-pmu", },
791 MODULE_DEVICE_TABLE(of
, dsu_pmu_of_match
);
794 static const struct acpi_device_id dsu_pmu_acpi_match
[] = {
798 MODULE_DEVICE_TABLE(acpi
, dsu_pmu_acpi_match
);
801 static struct platform_driver dsu_pmu_driver
= {
804 .of_match_table
= of_match_ptr(dsu_pmu_of_match
),
805 .acpi_match_table
= ACPI_PTR(dsu_pmu_acpi_match
),
806 .suppress_bind_attrs
= true,
808 .probe
= dsu_pmu_device_probe
,
809 .remove
= dsu_pmu_device_remove
,
812 static int dsu_pmu_cpu_online(unsigned int cpu
, struct hlist_node
*node
)
814 struct dsu_pmu
*dsu_pmu
= hlist_entry_safe(node
, struct dsu_pmu
,
817 if (!cpumask_test_cpu(cpu
, &dsu_pmu
->associated_cpus
))
820 /* If the PMU is already managed, there is nothing to do */
821 if (!cpumask_empty(&dsu_pmu
->active_cpu
))
824 dsu_pmu_init_pmu(dsu_pmu
);
825 dsu_pmu_set_active_cpu(cpu
, dsu_pmu
);
830 static int dsu_pmu_cpu_teardown(unsigned int cpu
, struct hlist_node
*node
)
833 struct dsu_pmu
*dsu_pmu
= hlist_entry_safe(node
, struct dsu_pmu
,
836 if (!cpumask_test_and_clear_cpu(cpu
, &dsu_pmu
->active_cpu
))
839 dst
= dsu_pmu_get_online_cpu_any_but(dsu_pmu
, cpu
);
840 /* If there are no active CPUs in the DSU, leave IRQ disabled */
841 if (dst
>= nr_cpu_ids
)
844 perf_pmu_migrate_context(&dsu_pmu
->pmu
, cpu
, dst
);
845 dsu_pmu_set_active_cpu(dst
, dsu_pmu
);
850 static int __init
dsu_pmu_init(void)
854 ret
= cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN
,
857 dsu_pmu_cpu_teardown
);
860 dsu_pmu_cpuhp_state
= ret
;
861 return platform_driver_register(&dsu_pmu_driver
);
864 static void __exit
dsu_pmu_exit(void)
866 platform_driver_unregister(&dsu_pmu_driver
);
867 cpuhp_remove_multi_state(dsu_pmu_cpuhp_state
);
870 module_init(dsu_pmu_init
);
871 module_exit(dsu_pmu_exit
);
873 MODULE_DESCRIPTION("Perf driver for ARM DynamIQ Shared Unit");
874 MODULE_AUTHOR("Suzuki K Poulose <suzuki.poulose@arm.com>");
875 MODULE_LICENSE("GPL v2");