1 // SPDX-License-Identifier: GPL-2.0-only
3 * Perf support for the Statistical Profiling Extension, introduced as
6 * Copyright (C) 2016 ARM Limited
8 * Author: Will Deacon <will.deacon@arm.com>
11 #define PMUNAME "arm_spe"
12 #define DRVNAME PMUNAME "_pmu"
13 #define pr_fmt(fmt) DRVNAME ": " fmt
15 #include <linux/bitops.h>
16 #include <linux/bug.h>
17 #include <linux/capability.h>
18 #include <linux/cpuhotplug.h>
19 #include <linux/cpumask.h>
20 #include <linux/device.h>
21 #include <linux/errno.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/perf_event.h>
30 #include <linux/perf/arm_pmu.h>
31 #include <linux/platform_device.h>
32 #include <linux/printk.h>
33 #include <linux/slab.h>
34 #include <linux/smp.h>
35 #include <linux/vmalloc.h>
37 #include <asm/barrier.h>
38 #include <asm/cpufeature.h>
40 #include <asm/sysreg.h>
42 #define ARM_SPE_BUF_PAD_BYTE 0
44 struct arm_spe_pmu_buf
{
52 struct platform_device
*pdev
;
53 cpumask_t supported_cpus
;
54 struct hlist_node hotplug_node
;
61 #define SPE_PMU_FEAT_FILT_EVT (1UL << 0)
62 #define SPE_PMU_FEAT_FILT_TYP (1UL << 1)
63 #define SPE_PMU_FEAT_FILT_LAT (1UL << 2)
64 #define SPE_PMU_FEAT_ARCH_INST (1UL << 3)
65 #define SPE_PMU_FEAT_LDS (1UL << 4)
66 #define SPE_PMU_FEAT_ERND (1UL << 5)
67 #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63)
72 struct perf_output_handle __percpu
*handle
;
75 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
77 /* Convert a free-running index from perf into an SPE buffer offset */
78 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
80 /* Keep track of our dynamic hotplug state */
81 static enum cpuhp_state arm_spe_pmu_online
;
83 enum arm_spe_pmu_buf_fault_action
{
84 SPE_PMU_BUF_FAULT_ACT_SPURIOUS
,
85 SPE_PMU_BUF_FAULT_ACT_FATAL
,
86 SPE_PMU_BUF_FAULT_ACT_OK
,
89 /* This sysfs gunk was really good fun to write. */
90 enum arm_spe_pmu_capabilities
{
91 SPE_PMU_CAP_ARCH_INST
= 0,
94 SPE_PMU_CAP_CNT_SZ
= SPE_PMU_CAP_FEAT_MAX
,
98 static int arm_spe_pmu_feat_caps
[SPE_PMU_CAP_FEAT_MAX
] = {
99 [SPE_PMU_CAP_ARCH_INST
] = SPE_PMU_FEAT_ARCH_INST
,
100 [SPE_PMU_CAP_ERND
] = SPE_PMU_FEAT_ERND
,
103 static u32
arm_spe_pmu_cap_get(struct arm_spe_pmu
*spe_pmu
, int cap
)
105 if (cap
< SPE_PMU_CAP_FEAT_MAX
)
106 return !!(spe_pmu
->features
& arm_spe_pmu_feat_caps
[cap
]);
109 case SPE_PMU_CAP_CNT_SZ
:
110 return spe_pmu
->counter_sz
;
111 case SPE_PMU_CAP_MIN_IVAL
:
112 return spe_pmu
->min_period
;
114 WARN(1, "unknown cap %d\n", cap
);
120 static ssize_t
arm_spe_pmu_cap_show(struct device
*dev
,
121 struct device_attribute
*attr
,
124 struct arm_spe_pmu
*spe_pmu
= dev_get_drvdata(dev
);
125 struct dev_ext_attribute
*ea
=
126 container_of(attr
, struct dev_ext_attribute
, attr
);
127 int cap
= (long)ea
->var
;
129 return sysfs_emit(buf
, "%u\n", arm_spe_pmu_cap_get(spe_pmu
, cap
));
132 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var) \
133 &((struct dev_ext_attribute[]) { \
134 { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var } \
137 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var) \
138 SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var)
140 static struct attribute
*arm_spe_pmu_cap_attr
[] = {
141 SPE_CAP_EXT_ATTR_ENTRY(arch_inst
, SPE_PMU_CAP_ARCH_INST
),
142 SPE_CAP_EXT_ATTR_ENTRY(ernd
, SPE_PMU_CAP_ERND
),
143 SPE_CAP_EXT_ATTR_ENTRY(count_size
, SPE_PMU_CAP_CNT_SZ
),
144 SPE_CAP_EXT_ATTR_ENTRY(min_interval
, SPE_PMU_CAP_MIN_IVAL
),
148 static const struct attribute_group arm_spe_pmu_cap_group
= {
150 .attrs
= arm_spe_pmu_cap_attr
,
154 #define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */
155 #define ATTR_CFG_FLD_ts_enable_LO 0
156 #define ATTR_CFG_FLD_ts_enable_HI 0
157 #define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */
158 #define ATTR_CFG_FLD_pa_enable_LO 1
159 #define ATTR_CFG_FLD_pa_enable_HI 1
160 #define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */
161 #define ATTR_CFG_FLD_pct_enable_LO 2
162 #define ATTR_CFG_FLD_pct_enable_HI 2
163 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */
164 #define ATTR_CFG_FLD_jitter_LO 16
165 #define ATTR_CFG_FLD_jitter_HI 16
166 #define ATTR_CFG_FLD_branch_filter_CFG config /* PMSFCR_EL1.B */
167 #define ATTR_CFG_FLD_branch_filter_LO 32
168 #define ATTR_CFG_FLD_branch_filter_HI 32
169 #define ATTR_CFG_FLD_load_filter_CFG config /* PMSFCR_EL1.LD */
170 #define ATTR_CFG_FLD_load_filter_LO 33
171 #define ATTR_CFG_FLD_load_filter_HI 33
172 #define ATTR_CFG_FLD_store_filter_CFG config /* PMSFCR_EL1.ST */
173 #define ATTR_CFG_FLD_store_filter_LO 34
174 #define ATTR_CFG_FLD_store_filter_HI 34
176 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */
177 #define ATTR_CFG_FLD_event_filter_LO 0
178 #define ATTR_CFG_FLD_event_filter_HI 63
180 #define ATTR_CFG_FLD_min_latency_CFG config2 /* PMSLATFR_EL1.MINLAT */
181 #define ATTR_CFG_FLD_min_latency_LO 0
182 #define ATTR_CFG_FLD_min_latency_HI 11
184 /* Why does everything I do descend into this? */
185 #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
186 (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
188 #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \
189 __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
191 #define GEN_PMU_FORMAT_ATTR(name) \
192 PMU_FORMAT_ATTR(name, \
193 _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG, \
194 ATTR_CFG_FLD_##name##_LO, \
195 ATTR_CFG_FLD_##name##_HI))
197 #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi) \
198 ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
200 #define ATTR_CFG_GET_FLD(attr, name) \
201 _ATTR_CFG_GET_FLD(attr, \
202 ATTR_CFG_FLD_##name##_CFG, \
203 ATTR_CFG_FLD_##name##_LO, \
204 ATTR_CFG_FLD_##name##_HI)
206 GEN_PMU_FORMAT_ATTR(ts_enable
);
207 GEN_PMU_FORMAT_ATTR(pa_enable
);
208 GEN_PMU_FORMAT_ATTR(pct_enable
);
209 GEN_PMU_FORMAT_ATTR(jitter
);
210 GEN_PMU_FORMAT_ATTR(branch_filter
);
211 GEN_PMU_FORMAT_ATTR(load_filter
);
212 GEN_PMU_FORMAT_ATTR(store_filter
);
213 GEN_PMU_FORMAT_ATTR(event_filter
);
214 GEN_PMU_FORMAT_ATTR(min_latency
);
216 static struct attribute
*arm_spe_pmu_formats_attr
[] = {
217 &format_attr_ts_enable
.attr
,
218 &format_attr_pa_enable
.attr
,
219 &format_attr_pct_enable
.attr
,
220 &format_attr_jitter
.attr
,
221 &format_attr_branch_filter
.attr
,
222 &format_attr_load_filter
.attr
,
223 &format_attr_store_filter
.attr
,
224 &format_attr_event_filter
.attr
,
225 &format_attr_min_latency
.attr
,
229 static const struct attribute_group arm_spe_pmu_format_group
= {
231 .attrs
= arm_spe_pmu_formats_attr
,
234 static ssize_t
cpumask_show(struct device
*dev
,
235 struct device_attribute
*attr
, char *buf
)
237 struct arm_spe_pmu
*spe_pmu
= dev_get_drvdata(dev
);
239 return cpumap_print_to_pagebuf(true, buf
, &spe_pmu
->supported_cpus
);
241 static DEVICE_ATTR_RO(cpumask
);
243 static struct attribute
*arm_spe_pmu_attrs
[] = {
244 &dev_attr_cpumask
.attr
,
248 static const struct attribute_group arm_spe_pmu_group
= {
249 .attrs
= arm_spe_pmu_attrs
,
252 static const struct attribute_group
*arm_spe_pmu_attr_groups
[] = {
254 &arm_spe_pmu_cap_group
,
255 &arm_spe_pmu_format_group
,
259 /* Convert between user ABI and register values */
260 static u64
arm_spe_event_to_pmscr(struct perf_event
*event
)
262 struct perf_event_attr
*attr
= &event
->attr
;
265 reg
|= ATTR_CFG_GET_FLD(attr
, ts_enable
) << SYS_PMSCR_EL1_TS_SHIFT
;
266 reg
|= ATTR_CFG_GET_FLD(attr
, pa_enable
) << SYS_PMSCR_EL1_PA_SHIFT
;
267 reg
|= ATTR_CFG_GET_FLD(attr
, pct_enable
) << SYS_PMSCR_EL1_PCT_SHIFT
;
269 if (!attr
->exclude_user
)
270 reg
|= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT
);
272 if (!attr
->exclude_kernel
)
273 reg
|= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT
);
275 if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR
) && perfmon_capable())
276 reg
|= BIT(SYS_PMSCR_EL1_CX_SHIFT
);
281 static void arm_spe_event_sanitise_period(struct perf_event
*event
)
283 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(event
->pmu
);
284 u64 period
= event
->hw
.sample_period
;
285 u64 max_period
= SYS_PMSIRR_EL1_INTERVAL_MASK
286 << SYS_PMSIRR_EL1_INTERVAL_SHIFT
;
288 if (period
< spe_pmu
->min_period
)
289 period
= spe_pmu
->min_period
;
290 else if (period
> max_period
)
293 period
&= max_period
;
295 event
->hw
.sample_period
= period
;
298 static u64
arm_spe_event_to_pmsirr(struct perf_event
*event
)
300 struct perf_event_attr
*attr
= &event
->attr
;
303 arm_spe_event_sanitise_period(event
);
305 reg
|= ATTR_CFG_GET_FLD(attr
, jitter
) << SYS_PMSIRR_EL1_RND_SHIFT
;
306 reg
|= event
->hw
.sample_period
;
311 static u64
arm_spe_event_to_pmsfcr(struct perf_event
*event
)
313 struct perf_event_attr
*attr
= &event
->attr
;
316 reg
|= ATTR_CFG_GET_FLD(attr
, load_filter
) << SYS_PMSFCR_EL1_LD_SHIFT
;
317 reg
|= ATTR_CFG_GET_FLD(attr
, store_filter
) << SYS_PMSFCR_EL1_ST_SHIFT
;
318 reg
|= ATTR_CFG_GET_FLD(attr
, branch_filter
) << SYS_PMSFCR_EL1_B_SHIFT
;
321 reg
|= BIT(SYS_PMSFCR_EL1_FT_SHIFT
);
323 if (ATTR_CFG_GET_FLD(attr
, event_filter
))
324 reg
|= BIT(SYS_PMSFCR_EL1_FE_SHIFT
);
326 if (ATTR_CFG_GET_FLD(attr
, min_latency
))
327 reg
|= BIT(SYS_PMSFCR_EL1_FL_SHIFT
);
332 static u64
arm_spe_event_to_pmsevfr(struct perf_event
*event
)
334 struct perf_event_attr
*attr
= &event
->attr
;
335 return ATTR_CFG_GET_FLD(attr
, event_filter
);
338 static u64
arm_spe_event_to_pmslatfr(struct perf_event
*event
)
340 struct perf_event_attr
*attr
= &event
->attr
;
341 return ATTR_CFG_GET_FLD(attr
, min_latency
)
342 << SYS_PMSLATFR_EL1_MINLAT_SHIFT
;
345 static void arm_spe_pmu_pad_buf(struct perf_output_handle
*handle
, int len
)
347 struct arm_spe_pmu_buf
*buf
= perf_get_aux(handle
);
348 u64 head
= PERF_IDX2OFF(handle
->head
, buf
);
350 memset(buf
->base
+ head
, ARM_SPE_BUF_PAD_BYTE
, len
);
352 perf_aux_output_skip(handle
, len
);
355 static u64
arm_spe_pmu_next_snapshot_off(struct perf_output_handle
*handle
)
357 struct arm_spe_pmu_buf
*buf
= perf_get_aux(handle
);
358 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(handle
->event
->pmu
);
359 u64 head
= PERF_IDX2OFF(handle
->head
, buf
);
360 u64 limit
= buf
->nr_pages
* PAGE_SIZE
;
363 * The trace format isn't parseable in reverse, so clamp
364 * the limit to half of the buffer size in snapshot mode
365 * so that the worst case is half a buffer of records, as
366 * opposed to a single record.
368 if (head
< limit
>> 1)
372 * If we're within max_record_sz of the limit, we must
373 * pad, move the head index and recompute the limit.
375 if (limit
- head
< spe_pmu
->max_record_sz
) {
376 arm_spe_pmu_pad_buf(handle
, limit
- head
);
377 handle
->head
= PERF_IDX2OFF(limit
, buf
);
378 limit
= ((buf
->nr_pages
* PAGE_SIZE
) >> 1) + handle
->head
;
384 static u64
__arm_spe_pmu_next_off(struct perf_output_handle
*handle
)
386 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(handle
->event
->pmu
);
387 struct arm_spe_pmu_buf
*buf
= perf_get_aux(handle
);
388 const u64 bufsize
= buf
->nr_pages
* PAGE_SIZE
;
390 u64 head
, tail
, wakeup
;
393 * The head can be misaligned for two reasons:
395 * 1. The hardware left PMBPTR pointing to the first byte after
396 * a record when generating a buffer management event.
398 * 2. We used perf_aux_output_skip to consume handle->size bytes
399 * and CIRC_SPACE was used to compute the size, which always
400 * leaves one entry free.
402 * Deal with this by padding to the next alignment boundary and
403 * moving the head index. If we run out of buffer space, we'll
404 * reduce handle->size to zero and end up reporting truncation.
406 head
= PERF_IDX2OFF(handle
->head
, buf
);
407 if (!IS_ALIGNED(head
, spe_pmu
->align
)) {
408 unsigned long delta
= roundup(head
, spe_pmu
->align
) - head
;
410 delta
= min(delta
, handle
->size
);
411 arm_spe_pmu_pad_buf(handle
, delta
);
412 head
= PERF_IDX2OFF(handle
->head
, buf
);
415 /* If we've run out of free space, then nothing more to do */
419 /* Compute the tail and wakeup indices now that we've aligned head */
420 tail
= PERF_IDX2OFF(handle
->head
+ handle
->size
, buf
);
421 wakeup
= PERF_IDX2OFF(handle
->wakeup
, buf
);
424 * Avoid clobbering unconsumed data. We know we have space, so
425 * if we see head == tail we know that the buffer is empty. If
426 * head > tail, then there's nothing to clobber prior to
430 limit
= round_down(tail
, PAGE_SIZE
);
433 * Wakeup may be arbitrarily far into the future. If it's not in
434 * the current generation, either we'll wrap before hitting it,
435 * or it's in the past and has been handled already.
437 * If there's a wakeup before we wrap, arrange to be woken up by
438 * the page boundary following it. Keep the tail boundary if
441 if (handle
->wakeup
< (handle
->head
+ handle
->size
) && head
<= wakeup
)
442 limit
= min(limit
, round_up(wakeup
, PAGE_SIZE
));
447 arm_spe_pmu_pad_buf(handle
, handle
->size
);
449 perf_aux_output_flag(handle
, PERF_AUX_FLAG_TRUNCATED
);
450 perf_aux_output_end(handle
, 0);
454 static u64
arm_spe_pmu_next_off(struct perf_output_handle
*handle
)
456 struct arm_spe_pmu_buf
*buf
= perf_get_aux(handle
);
457 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(handle
->event
->pmu
);
458 u64 limit
= __arm_spe_pmu_next_off(handle
);
459 u64 head
= PERF_IDX2OFF(handle
->head
, buf
);
462 * If the head has come too close to the end of the buffer,
463 * then pad to the end and recompute the limit.
465 if (limit
&& (limit
- head
< spe_pmu
->max_record_sz
)) {
466 arm_spe_pmu_pad_buf(handle
, limit
- head
);
467 limit
= __arm_spe_pmu_next_off(handle
);
473 static void arm_spe_perf_aux_output_begin(struct perf_output_handle
*handle
,
474 struct perf_event
*event
)
477 struct arm_spe_pmu_buf
*buf
;
479 /* Start a new aux session */
480 buf
= perf_aux_output_begin(handle
, event
);
482 event
->hw
.state
|= PERF_HES_STOPPED
;
484 * We still need to clear the limit pointer, since the
485 * profiler might only be disabled by virtue of a fault.
488 goto out_write_limit
;
491 limit
= buf
->snapshot
? arm_spe_pmu_next_snapshot_off(handle
)
492 : arm_spe_pmu_next_off(handle
);
494 limit
|= BIT(SYS_PMBLIMITR_EL1_E_SHIFT
);
496 limit
+= (u64
)buf
->base
;
497 base
= (u64
)buf
->base
+ PERF_IDX2OFF(handle
->head
, buf
);
498 write_sysreg_s(base
, SYS_PMBPTR_EL1
);
501 write_sysreg_s(limit
, SYS_PMBLIMITR_EL1
);
504 static void arm_spe_perf_aux_output_end(struct perf_output_handle
*handle
)
506 struct arm_spe_pmu_buf
*buf
= perf_get_aux(handle
);
509 offset
= read_sysreg_s(SYS_PMBPTR_EL1
) - (u64
)buf
->base
;
510 size
= offset
- PERF_IDX2OFF(handle
->head
, buf
);
513 handle
->head
= offset
;
515 perf_aux_output_end(handle
, size
);
518 static void arm_spe_pmu_disable_and_drain_local(void)
520 /* Disable profiling at EL0 and EL1 */
521 write_sysreg_s(0, SYS_PMSCR_EL1
);
524 /* Drain any buffered data */
528 /* Disable the profiling buffer */
529 write_sysreg_s(0, SYS_PMBLIMITR_EL1
);
534 static enum arm_spe_pmu_buf_fault_action
535 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle
*handle
)
539 enum arm_spe_pmu_buf_fault_action ret
;
542 * Ensure new profiling data is visible to the CPU and any external
543 * aborts have been resolved.
548 /* Ensure hardware updates to PMBPTR_EL1 are visible */
551 /* Service required? */
552 pmbsr
= read_sysreg_s(SYS_PMBSR_EL1
);
553 if (!(pmbsr
& BIT(SYS_PMBSR_EL1_S_SHIFT
)))
554 return SPE_PMU_BUF_FAULT_ACT_SPURIOUS
;
557 * If we've lost data, disable profiling and also set the PARTIAL
558 * flag to indicate that the last record is corrupted.
560 if (pmbsr
& BIT(SYS_PMBSR_EL1_DL_SHIFT
))
561 perf_aux_output_flag(handle
, PERF_AUX_FLAG_TRUNCATED
|
562 PERF_AUX_FLAG_PARTIAL
);
564 /* Report collisions to userspace so that it can up the period */
565 if (pmbsr
& BIT(SYS_PMBSR_EL1_COLL_SHIFT
))
566 perf_aux_output_flag(handle
, PERF_AUX_FLAG_COLLISION
);
568 /* We only expect buffer management events */
569 switch (pmbsr
& (SYS_PMBSR_EL1_EC_MASK
<< SYS_PMBSR_EL1_EC_SHIFT
)) {
570 case SYS_PMBSR_EL1_EC_BUF
:
573 case SYS_PMBSR_EL1_EC_FAULT_S1
:
574 case SYS_PMBSR_EL1_EC_FAULT_S2
:
575 err_str
= "Unexpected buffer fault";
578 err_str
= "Unknown error code";
582 /* Buffer management event */
584 (SYS_PMBSR_EL1_BUF_BSC_MASK
<< SYS_PMBSR_EL1_BUF_BSC_SHIFT
)) {
585 case SYS_PMBSR_EL1_BUF_BSC_FULL
:
586 ret
= SPE_PMU_BUF_FAULT_ACT_OK
;
589 err_str
= "Unknown buffer status code";
593 pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n",
594 err_str
, smp_processor_id(), pmbsr
,
595 read_sysreg_s(SYS_PMBPTR_EL1
),
596 read_sysreg_s(SYS_PMBLIMITR_EL1
));
597 ret
= SPE_PMU_BUF_FAULT_ACT_FATAL
;
600 arm_spe_perf_aux_output_end(handle
);
604 static irqreturn_t
arm_spe_pmu_irq_handler(int irq
, void *dev
)
606 struct perf_output_handle
*handle
= dev
;
607 struct perf_event
*event
= handle
->event
;
608 enum arm_spe_pmu_buf_fault_action act
;
610 if (!perf_get_aux(handle
))
613 act
= arm_spe_pmu_buf_get_fault_act(handle
);
614 if (act
== SPE_PMU_BUF_FAULT_ACT_SPURIOUS
)
618 * Ensure perf callbacks have completed, which may disable the
619 * profiling buffer in response to a TRUNCATION flag.
624 case SPE_PMU_BUF_FAULT_ACT_FATAL
:
626 * If a fatal exception occurred then leaving the profiling
627 * buffer enabled is a recipe waiting to happen. Since
628 * fatal faults don't always imply truncation, make sure
629 * that the profiling buffer is disabled explicitly before
630 * clearing the syndrome register.
632 arm_spe_pmu_disable_and_drain_local();
634 case SPE_PMU_BUF_FAULT_ACT_OK
:
636 * We handled the fault (the buffer was full), so resume
637 * profiling as long as we didn't detect truncation.
638 * PMBPTR might be misaligned, but we'll burn that bridge
641 if (!(handle
->aux_flags
& PERF_AUX_FLAG_TRUNCATED
)) {
642 arm_spe_perf_aux_output_begin(handle
, event
);
646 case SPE_PMU_BUF_FAULT_ACT_SPURIOUS
:
647 /* We've seen you before, but GCC has the memory of a sieve. */
651 /* The buffer pointers are now sane, so resume profiling. */
652 write_sysreg_s(0, SYS_PMBSR_EL1
);
656 static u64
arm_spe_pmsevfr_res0(u16 pmsver
)
659 case ID_AA64DFR0_PMSVER_8_2
:
660 return SYS_PMSEVFR_EL1_RES0_8_2
;
661 case ID_AA64DFR0_PMSVER_8_3
:
662 /* Return the highest version we support in default */
664 return SYS_PMSEVFR_EL1_RES0_8_3
;
669 static int arm_spe_pmu_event_init(struct perf_event
*event
)
672 struct perf_event_attr
*attr
= &event
->attr
;
673 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(event
->pmu
);
675 /* This is, of course, deeply driver-specific */
676 if (attr
->type
!= event
->pmu
->type
)
679 if (event
->cpu
>= 0 &&
680 !cpumask_test_cpu(event
->cpu
, &spe_pmu
->supported_cpus
))
683 if (arm_spe_event_to_pmsevfr(event
) & arm_spe_pmsevfr_res0(spe_pmu
->pmsver
))
686 if (attr
->exclude_idle
)
690 * Feedback-directed frequency throttling doesn't work when we
691 * have a buffer of samples. We'd need to manually count the
692 * samples in the buffer when it fills up and adjust the event
693 * count to reflect that. Instead, just force the user to specify
699 reg
= arm_spe_event_to_pmsfcr(event
);
700 if ((reg
& BIT(SYS_PMSFCR_EL1_FE_SHIFT
)) &&
701 !(spe_pmu
->features
& SPE_PMU_FEAT_FILT_EVT
))
704 if ((reg
& BIT(SYS_PMSFCR_EL1_FT_SHIFT
)) &&
705 !(spe_pmu
->features
& SPE_PMU_FEAT_FILT_TYP
))
708 if ((reg
& BIT(SYS_PMSFCR_EL1_FL_SHIFT
)) &&
709 !(spe_pmu
->features
& SPE_PMU_FEAT_FILT_LAT
))
712 reg
= arm_spe_event_to_pmscr(event
);
713 if (!perfmon_capable() &&
714 (reg
& (BIT(SYS_PMSCR_EL1_PA_SHIFT
) |
715 BIT(SYS_PMSCR_EL1_CX_SHIFT
) |
716 BIT(SYS_PMSCR_EL1_PCT_SHIFT
))))
722 static void arm_spe_pmu_start(struct perf_event
*event
, int flags
)
725 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(event
->pmu
);
726 struct hw_perf_event
*hwc
= &event
->hw
;
727 struct perf_output_handle
*handle
= this_cpu_ptr(spe_pmu
->handle
);
730 arm_spe_perf_aux_output_begin(handle
, event
);
734 reg
= arm_spe_event_to_pmsfcr(event
);
735 write_sysreg_s(reg
, SYS_PMSFCR_EL1
);
737 reg
= arm_spe_event_to_pmsevfr(event
);
738 write_sysreg_s(reg
, SYS_PMSEVFR_EL1
);
740 reg
= arm_spe_event_to_pmslatfr(event
);
741 write_sysreg_s(reg
, SYS_PMSLATFR_EL1
);
743 if (flags
& PERF_EF_RELOAD
) {
744 reg
= arm_spe_event_to_pmsirr(event
);
745 write_sysreg_s(reg
, SYS_PMSIRR_EL1
);
747 reg
= local64_read(&hwc
->period_left
);
748 write_sysreg_s(reg
, SYS_PMSICR_EL1
);
751 reg
= arm_spe_event_to_pmscr(event
);
753 write_sysreg_s(reg
, SYS_PMSCR_EL1
);
756 static void arm_spe_pmu_stop(struct perf_event
*event
, int flags
)
758 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(event
->pmu
);
759 struct hw_perf_event
*hwc
= &event
->hw
;
760 struct perf_output_handle
*handle
= this_cpu_ptr(spe_pmu
->handle
);
762 /* If we're already stopped, then nothing to do */
763 if (hwc
->state
& PERF_HES_STOPPED
)
766 /* Stop all trace generation */
767 arm_spe_pmu_disable_and_drain_local();
769 if (flags
& PERF_EF_UPDATE
) {
771 * If there's a fault pending then ensure we contain it
772 * to this buffer, since we might be on the context-switch
775 if (perf_get_aux(handle
)) {
776 enum arm_spe_pmu_buf_fault_action act
;
778 act
= arm_spe_pmu_buf_get_fault_act(handle
);
779 if (act
== SPE_PMU_BUF_FAULT_ACT_SPURIOUS
)
780 arm_spe_perf_aux_output_end(handle
);
782 write_sysreg_s(0, SYS_PMBSR_EL1
);
786 * This may also contain ECOUNT, but nobody else should
787 * be looking at period_left, since we forbid frequency
790 local64_set(&hwc
->period_left
, read_sysreg_s(SYS_PMSICR_EL1
));
791 hwc
->state
|= PERF_HES_UPTODATE
;
794 hwc
->state
|= PERF_HES_STOPPED
;
797 static int arm_spe_pmu_add(struct perf_event
*event
, int flags
)
800 struct arm_spe_pmu
*spe_pmu
= to_spe_pmu(event
->pmu
);
801 struct hw_perf_event
*hwc
= &event
->hw
;
802 int cpu
= event
->cpu
== -1 ? smp_processor_id() : event
->cpu
;
804 if (!cpumask_test_cpu(cpu
, &spe_pmu
->supported_cpus
))
807 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
809 if (flags
& PERF_EF_START
) {
810 arm_spe_pmu_start(event
, PERF_EF_RELOAD
);
811 if (hwc
->state
& PERF_HES_STOPPED
)
818 static void arm_spe_pmu_del(struct perf_event
*event
, int flags
)
820 arm_spe_pmu_stop(event
, PERF_EF_UPDATE
);
823 static void arm_spe_pmu_read(struct perf_event
*event
)
827 static void *arm_spe_pmu_setup_aux(struct perf_event
*event
, void **pages
,
828 int nr_pages
, bool snapshot
)
830 int i
, cpu
= event
->cpu
;
831 struct page
**pglist
;
832 struct arm_spe_pmu_buf
*buf
;
834 /* We need at least two pages for this to work. */
839 * We require an even number of pages for snapshot mode, so that
840 * we can effectively treat the buffer as consisting of two equal
841 * parts and give userspace a fighting chance of getting some
842 * useful data out of it.
844 if (snapshot
&& (nr_pages
& 1))
848 cpu
= raw_smp_processor_id();
850 buf
= kzalloc_node(sizeof(*buf
), GFP_KERNEL
, cpu_to_node(cpu
));
854 pglist
= kcalloc(nr_pages
, sizeof(*pglist
), GFP_KERNEL
);
858 for (i
= 0; i
< nr_pages
; ++i
)
859 pglist
[i
] = virt_to_page(pages
[i
]);
861 buf
->base
= vmap(pglist
, nr_pages
, VM_MAP
, PAGE_KERNEL
);
863 goto out_free_pglist
;
865 buf
->nr_pages
= nr_pages
;
866 buf
->snapshot
= snapshot
;
878 static void arm_spe_pmu_free_aux(void *aux
)
880 struct arm_spe_pmu_buf
*buf
= aux
;
886 /* Initialisation and teardown functions */
887 static int arm_spe_pmu_perf_init(struct arm_spe_pmu
*spe_pmu
)
889 static atomic_t pmu_idx
= ATOMIC_INIT(-1);
893 struct device
*dev
= &spe_pmu
->pdev
->dev
;
895 spe_pmu
->pmu
= (struct pmu
) {
896 .module
= THIS_MODULE
,
897 .capabilities
= PERF_PMU_CAP_EXCLUSIVE
| PERF_PMU_CAP_ITRACE
,
898 .attr_groups
= arm_spe_pmu_attr_groups
,
900 * We hitch a ride on the software context here, so that
901 * we can support per-task profiling (which is not possible
902 * with the invalid context as it doesn't get sched callbacks).
903 * This requires that userspace either uses a dummy event for
904 * perf_event_open, since the aux buffer is not setup until
905 * a subsequent mmap, or creates the profiling event in a
906 * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it
907 * once the buffer has been created.
909 .task_ctx_nr
= perf_sw_context
,
910 .event_init
= arm_spe_pmu_event_init
,
911 .add
= arm_spe_pmu_add
,
912 .del
= arm_spe_pmu_del
,
913 .start
= arm_spe_pmu_start
,
914 .stop
= arm_spe_pmu_stop
,
915 .read
= arm_spe_pmu_read
,
916 .setup_aux
= arm_spe_pmu_setup_aux
,
917 .free_aux
= arm_spe_pmu_free_aux
,
920 idx
= atomic_inc_return(&pmu_idx
);
921 name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s_%d", PMUNAME
, idx
);
923 dev_err(dev
, "failed to allocate name for pmu %d\n", idx
);
927 return perf_pmu_register(&spe_pmu
->pmu
, name
, -1);
930 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu
*spe_pmu
)
932 perf_pmu_unregister(&spe_pmu
->pmu
);
935 static void __arm_spe_pmu_dev_probe(void *info
)
939 struct arm_spe_pmu
*spe_pmu
= info
;
940 struct device
*dev
= &spe_pmu
->pdev
->dev
;
942 fld
= cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1
),
943 ID_AA64DFR0_PMSVER_SHIFT
);
946 "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n",
947 fld
, smp_processor_id());
950 spe_pmu
->pmsver
= (u16
)fld
;
952 /* Read PMBIDR first to determine whether or not we have access */
953 reg
= read_sysreg_s(SYS_PMBIDR_EL1
);
954 if (reg
& BIT(SYS_PMBIDR_EL1_P_SHIFT
)) {
956 "profiling buffer owned by higher exception level\n");
960 /* Minimum alignment. If it's out-of-range, then fail the probe */
961 fld
= reg
>> SYS_PMBIDR_EL1_ALIGN_SHIFT
& SYS_PMBIDR_EL1_ALIGN_MASK
;
962 spe_pmu
->align
= 1 << fld
;
963 if (spe_pmu
->align
> SZ_2K
) {
964 dev_err(dev
, "unsupported PMBIDR.Align [%d] on CPU %d\n",
965 fld
, smp_processor_id());
969 /* It's now safe to read PMSIDR and figure out what we've got */
970 reg
= read_sysreg_s(SYS_PMSIDR_EL1
);
971 if (reg
& BIT(SYS_PMSIDR_EL1_FE_SHIFT
))
972 spe_pmu
->features
|= SPE_PMU_FEAT_FILT_EVT
;
974 if (reg
& BIT(SYS_PMSIDR_EL1_FT_SHIFT
))
975 spe_pmu
->features
|= SPE_PMU_FEAT_FILT_TYP
;
977 if (reg
& BIT(SYS_PMSIDR_EL1_FL_SHIFT
))
978 spe_pmu
->features
|= SPE_PMU_FEAT_FILT_LAT
;
980 if (reg
& BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT
))
981 spe_pmu
->features
|= SPE_PMU_FEAT_ARCH_INST
;
983 if (reg
& BIT(SYS_PMSIDR_EL1_LDS_SHIFT
))
984 spe_pmu
->features
|= SPE_PMU_FEAT_LDS
;
986 if (reg
& BIT(SYS_PMSIDR_EL1_ERND_SHIFT
))
987 spe_pmu
->features
|= SPE_PMU_FEAT_ERND
;
989 /* This field has a spaced out encoding, so just use a look-up */
990 fld
= reg
>> SYS_PMSIDR_EL1_INTERVAL_SHIFT
& SYS_PMSIDR_EL1_INTERVAL_MASK
;
993 spe_pmu
->min_period
= 256;
996 spe_pmu
->min_period
= 512;
999 spe_pmu
->min_period
= 768;
1002 spe_pmu
->min_period
= 1024;
1005 spe_pmu
->min_period
= 1536;
1008 spe_pmu
->min_period
= 2048;
1011 spe_pmu
->min_period
= 3072;
1014 dev_warn(dev
, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
1018 spe_pmu
->min_period
= 4096;
1021 /* Maximum record size. If it's out-of-range, then fail the probe */
1022 fld
= reg
>> SYS_PMSIDR_EL1_MAXSIZE_SHIFT
& SYS_PMSIDR_EL1_MAXSIZE_MASK
;
1023 spe_pmu
->max_record_sz
= 1 << fld
;
1024 if (spe_pmu
->max_record_sz
> SZ_2K
|| spe_pmu
->max_record_sz
< 16) {
1025 dev_err(dev
, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
1026 fld
, smp_processor_id());
1030 fld
= reg
>> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT
& SYS_PMSIDR_EL1_COUNTSIZE_MASK
;
1033 dev_warn(dev
, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
1037 spe_pmu
->counter_sz
= 12;
1041 "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n",
1042 cpumask_pr_args(&spe_pmu
->supported_cpus
),
1043 spe_pmu
->max_record_sz
, spe_pmu
->align
, spe_pmu
->features
);
1045 spe_pmu
->features
|= SPE_PMU_FEAT_DEV_PROBED
;
1048 static void __arm_spe_pmu_reset_local(void)
1051 * This is probably overkill, as we have no idea where we're
1052 * draining any buffered data to...
1054 arm_spe_pmu_disable_and_drain_local();
1056 /* Reset the buffer base pointer */
1057 write_sysreg_s(0, SYS_PMBPTR_EL1
);
1060 /* Clear any pending management interrupts */
1061 write_sysreg_s(0, SYS_PMBSR_EL1
);
1065 static void __arm_spe_pmu_setup_one(void *info
)
1067 struct arm_spe_pmu
*spe_pmu
= info
;
1069 __arm_spe_pmu_reset_local();
1070 enable_percpu_irq(spe_pmu
->irq
, IRQ_TYPE_NONE
);
1073 static void __arm_spe_pmu_stop_one(void *info
)
1075 struct arm_spe_pmu
*spe_pmu
= info
;
1077 disable_percpu_irq(spe_pmu
->irq
);
1078 __arm_spe_pmu_reset_local();
1081 static int arm_spe_pmu_cpu_startup(unsigned int cpu
, struct hlist_node
*node
)
1083 struct arm_spe_pmu
*spe_pmu
;
1085 spe_pmu
= hlist_entry_safe(node
, struct arm_spe_pmu
, hotplug_node
);
1086 if (!cpumask_test_cpu(cpu
, &spe_pmu
->supported_cpus
))
1089 __arm_spe_pmu_setup_one(spe_pmu
);
1093 static int arm_spe_pmu_cpu_teardown(unsigned int cpu
, struct hlist_node
*node
)
1095 struct arm_spe_pmu
*spe_pmu
;
1097 spe_pmu
= hlist_entry_safe(node
, struct arm_spe_pmu
, hotplug_node
);
1098 if (!cpumask_test_cpu(cpu
, &spe_pmu
->supported_cpus
))
1101 __arm_spe_pmu_stop_one(spe_pmu
);
1105 static int arm_spe_pmu_dev_init(struct arm_spe_pmu
*spe_pmu
)
1108 cpumask_t
*mask
= &spe_pmu
->supported_cpus
;
1110 /* Make sure we probe the hardware on a relevant CPU */
1111 ret
= smp_call_function_any(mask
, __arm_spe_pmu_dev_probe
, spe_pmu
, 1);
1112 if (ret
|| !(spe_pmu
->features
& SPE_PMU_FEAT_DEV_PROBED
))
1115 /* Request our PPIs (note that the IRQ is still disabled) */
1116 ret
= request_percpu_irq(spe_pmu
->irq
, arm_spe_pmu_irq_handler
, DRVNAME
,
1122 * Register our hotplug notifier now so we don't miss any events.
1123 * This will enable the IRQ for any supported CPUs that are already
1126 ret
= cpuhp_state_add_instance(arm_spe_pmu_online
,
1127 &spe_pmu
->hotplug_node
);
1129 free_percpu_irq(spe_pmu
->irq
, spe_pmu
->handle
);
1134 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu
*spe_pmu
)
1136 cpuhp_state_remove_instance(arm_spe_pmu_online
, &spe_pmu
->hotplug_node
);
1137 free_percpu_irq(spe_pmu
->irq
, spe_pmu
->handle
);
1140 /* Driver and device probing */
1141 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu
*spe_pmu
)
1143 struct platform_device
*pdev
= spe_pmu
->pdev
;
1144 int irq
= platform_get_irq(pdev
, 0);
1149 if (!irq_is_percpu(irq
)) {
1150 dev_err(&pdev
->dev
, "expected PPI but got SPI (%d)\n", irq
);
1154 if (irq_get_percpu_devid_partition(irq
, &spe_pmu
->supported_cpus
)) {
1155 dev_err(&pdev
->dev
, "failed to get PPI partition (%d)\n", irq
);
1163 static const struct of_device_id arm_spe_pmu_of_match
[] = {
1164 { .compatible
= "arm,statistical-profiling-extension-v1", .data
= (void *)1 },
1167 MODULE_DEVICE_TABLE(of
, arm_spe_pmu_of_match
);
1169 static const struct platform_device_id arm_spe_match
[] = {
1170 { ARMV8_SPE_PDEV_NAME
, 0},
1173 MODULE_DEVICE_TABLE(platform
, arm_spe_match
);
1175 static int arm_spe_pmu_device_probe(struct platform_device
*pdev
)
1178 struct arm_spe_pmu
*spe_pmu
;
1179 struct device
*dev
= &pdev
->dev
;
1182 * If kernelspace is unmapped when running at EL0, then the SPE
1183 * buffer will fault and prematurely terminate the AUX session.
1185 if (arm64_kernel_unmapped_at_el0()) {
1186 dev_warn_once(dev
, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n");
1190 spe_pmu
= devm_kzalloc(dev
, sizeof(*spe_pmu
), GFP_KERNEL
);
1194 spe_pmu
->handle
= alloc_percpu(typeof(*spe_pmu
->handle
));
1195 if (!spe_pmu
->handle
)
1198 spe_pmu
->pdev
= pdev
;
1199 platform_set_drvdata(pdev
, spe_pmu
);
1201 ret
= arm_spe_pmu_irq_probe(spe_pmu
);
1203 goto out_free_handle
;
1205 ret
= arm_spe_pmu_dev_init(spe_pmu
);
1207 goto out_free_handle
;
1209 ret
= arm_spe_pmu_perf_init(spe_pmu
);
1211 goto out_teardown_dev
;
1216 arm_spe_pmu_dev_teardown(spe_pmu
);
1218 free_percpu(spe_pmu
->handle
);
1222 static int arm_spe_pmu_device_remove(struct platform_device
*pdev
)
1224 struct arm_spe_pmu
*spe_pmu
= platform_get_drvdata(pdev
);
1226 arm_spe_pmu_perf_destroy(spe_pmu
);
1227 arm_spe_pmu_dev_teardown(spe_pmu
);
1228 free_percpu(spe_pmu
->handle
);
1232 static struct platform_driver arm_spe_pmu_driver
= {
1233 .id_table
= arm_spe_match
,
1236 .of_match_table
= of_match_ptr(arm_spe_pmu_of_match
),
1237 .suppress_bind_attrs
= true,
1239 .probe
= arm_spe_pmu_device_probe
,
1240 .remove
= arm_spe_pmu_device_remove
,
1243 static int __init
arm_spe_pmu_init(void)
1247 ret
= cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN
, DRVNAME
,
1248 arm_spe_pmu_cpu_startup
,
1249 arm_spe_pmu_cpu_teardown
);
1252 arm_spe_pmu_online
= ret
;
1254 ret
= platform_driver_register(&arm_spe_pmu_driver
);
1256 cpuhp_remove_multi_state(arm_spe_pmu_online
);
1261 static void __exit
arm_spe_pmu_exit(void)
1263 platform_driver_unregister(&arm_spe_pmu_driver
);
1264 cpuhp_remove_multi_state(arm_spe_pmu_online
);
1267 module_init(arm_spe_pmu_init
);
1268 module_exit(arm_spe_pmu_exit
);
1270 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension");
1271 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1272 MODULE_LICENSE("GPL v2");