2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include "phy-qcom-ufs-i.h"
17 #define MAX_PROP_NAME 32
18 #define VDDA_PHY_MIN_UV 1000000
19 #define VDDA_PHY_MAX_UV 1000000
20 #define VDDA_PLL_MIN_UV 1800000
21 #define VDDA_PLL_MAX_UV 1800000
22 #define VDDP_REF_CLK_MIN_UV 1200000
23 #define VDDP_REF_CLK_MAX_UV 1200000
25 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy
*ufs_qcom_phy
,
26 struct ufs_qcom_phy_calibration
*tbl_A
,
28 struct ufs_qcom_phy_calibration
*tbl_B
,
29 int tbl_size_B
, bool is_rate_B
)
35 dev_err(ufs_qcom_phy
->dev
, "%s: tbl_A is NULL", __func__
);
40 for (i
= 0; i
< tbl_size_A
; i
++)
41 writel_relaxed(tbl_A
[i
].cfg_value
,
42 ufs_qcom_phy
->mmio
+ tbl_A
[i
].reg_offset
);
45 * In case we would like to work in rate B, we need
46 * to override a registers that were configured in rate A table
47 * with registers of rate B table.
52 dev_err(ufs_qcom_phy
->dev
, "%s: tbl_B is NULL",
58 for (i
= 0; i
< tbl_size_B
; i
++)
59 writel_relaxed(tbl_B
[i
].cfg_value
,
60 ufs_qcom_phy
->mmio
+ tbl_B
[i
].reg_offset
);
63 /* flush buffered writes */
69 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate
);
72 * This assumes the embedded phy structure inside generic_phy is of type
73 * struct ufs_qcom_phy. In order to function properly it's crucial
74 * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
75 * as the first inside generic_phy.
77 struct ufs_qcom_phy
*get_ufs_qcom_phy(struct phy
*generic_phy
)
79 return (struct ufs_qcom_phy
*)phy_get_drvdata(generic_phy
);
81 EXPORT_SYMBOL_GPL(get_ufs_qcom_phy
);
84 int ufs_qcom_phy_base_init(struct platform_device
*pdev
,
85 struct ufs_qcom_phy
*phy_common
)
87 struct device
*dev
= &pdev
->dev
;
91 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "phy_mem");
92 phy_common
->mmio
= devm_ioremap_resource(dev
, res
);
93 if (IS_ERR((void const *)phy_common
->mmio
)) {
94 err
= PTR_ERR((void const *)phy_common
->mmio
);
95 phy_common
->mmio
= NULL
;
96 dev_err(dev
, "%s: ioremap for phy_mem resource failed %d\n",
101 /* "dev_ref_clk_ctrl_mem" is optional resource */
102 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
103 "dev_ref_clk_ctrl_mem");
104 phy_common
->dev_ref_clk_ctrl_mmio
= devm_ioremap_resource(dev
, res
);
105 if (IS_ERR((void const *)phy_common
->dev_ref_clk_ctrl_mmio
))
106 phy_common
->dev_ref_clk_ctrl_mmio
= NULL
;
111 struct phy
*ufs_qcom_phy_generic_probe(struct platform_device
*pdev
,
112 struct ufs_qcom_phy
*common_cfg
,
113 const struct phy_ops
*ufs_qcom_phy_gen_ops
,
114 struct ufs_qcom_phy_specific_ops
*phy_spec_ops
)
117 struct device
*dev
= &pdev
->dev
;
118 struct phy
*generic_phy
= NULL
;
119 struct phy_provider
*phy_provider
;
121 err
= ufs_qcom_phy_base_init(pdev
, common_cfg
);
123 dev_err(dev
, "%s: phy base init failed %d\n", __func__
, err
);
127 phy_provider
= devm_of_phy_provider_register(dev
, of_phy_simple_xlate
);
128 if (IS_ERR(phy_provider
)) {
129 err
= PTR_ERR(phy_provider
);
130 dev_err(dev
, "%s: failed to register phy %d\n", __func__
, err
);
134 generic_phy
= devm_phy_create(dev
, NULL
, ufs_qcom_phy_gen_ops
);
135 if (IS_ERR(generic_phy
)) {
136 err
= PTR_ERR(generic_phy
);
137 dev_err(dev
, "%s: failed to create phy %d\n", __func__
, err
);
142 common_cfg
->phy_spec_ops
= phy_spec_ops
;
143 common_cfg
->dev
= dev
;
148 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe
);
150 static int __ufs_qcom_phy_clk_get(struct device
*dev
,
151 const char *name
, struct clk
**clk_out
, bool err_print
)
156 clk
= devm_clk_get(dev
, name
);
160 dev_err(dev
, "failed to get %s err %d", name
, err
);
168 static int ufs_qcom_phy_clk_get(struct device
*dev
,
169 const char *name
, struct clk
**clk_out
)
171 return __ufs_qcom_phy_clk_get(dev
, name
, clk_out
, true);
174 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy
*phy_common
)
178 if (of_device_is_compatible(phy_common
->dev
->of_node
,
179 "qcom,msm8996-ufs-phy-qmp-14nm"))
182 err
= ufs_qcom_phy_clk_get(phy_common
->dev
, "tx_iface_clk",
183 &phy_common
->tx_iface_clk
);
187 err
= ufs_qcom_phy_clk_get(phy_common
->dev
, "rx_iface_clk",
188 &phy_common
->rx_iface_clk
);
193 err
= ufs_qcom_phy_clk_get(phy_common
->dev
, "ref_clk_src",
194 &phy_common
->ref_clk_src
);
199 * "ref_clk_parent" is optional hence don't abort init if it's not
202 __ufs_qcom_phy_clk_get(phy_common
->dev
, "ref_clk_parent",
203 &phy_common
->ref_clk_parent
, false);
205 err
= ufs_qcom_phy_clk_get(phy_common
->dev
, "ref_clk",
206 &phy_common
->ref_clk
);
211 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks
);
213 static int __ufs_qcom_phy_init_vreg(struct device
*dev
,
214 struct ufs_qcom_phy_vreg
*vreg
, const char *name
, bool optional
)
218 char prop_name
[MAX_PROP_NAME
];
221 vreg
->reg
= devm_regulator_get(dev
, name
);
222 if (IS_ERR(vreg
->reg
)) {
223 err
= PTR_ERR(vreg
->reg
);
226 dev_err(dev
, "failed to get %s, %d\n", name
, err
);
231 snprintf(prop_name
, MAX_PROP_NAME
, "%s-max-microamp", name
);
232 err
= of_property_read_u32(dev
->of_node
,
233 prop_name
, &vreg
->max_uA
);
234 if (err
&& err
!= -EINVAL
) {
235 dev_err(dev
, "%s: failed to read %s\n",
236 __func__
, prop_name
);
238 } else if (err
== -EINVAL
|| !vreg
->max_uA
) {
239 if (regulator_count_voltages(vreg
->reg
) > 0) {
240 dev_err(dev
, "%s: %s is mandatory\n",
241 __func__
, prop_name
);
246 snprintf(prop_name
, MAX_PROP_NAME
, "%s-always-on", name
);
247 vreg
->is_always_on
= of_property_read_bool(dev
->of_node
,
251 if (!strcmp(name
, "vdda-pll")) {
252 vreg
->max_uV
= VDDA_PLL_MAX_UV
;
253 vreg
->min_uV
= VDDA_PLL_MIN_UV
;
254 } else if (!strcmp(name
, "vdda-phy")) {
255 vreg
->max_uV
= VDDA_PHY_MAX_UV
;
256 vreg
->min_uV
= VDDA_PHY_MIN_UV
;
257 } else if (!strcmp(name
, "vddp-ref-clk")) {
258 vreg
->max_uV
= VDDP_REF_CLK_MAX_UV
;
259 vreg
->min_uV
= VDDP_REF_CLK_MIN_UV
;
266 static int ufs_qcom_phy_init_vreg(struct device
*dev
,
267 struct ufs_qcom_phy_vreg
*vreg
, const char *name
)
269 return __ufs_qcom_phy_init_vreg(dev
, vreg
, name
, false);
272 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy
*phy_common
)
276 err
= ufs_qcom_phy_init_vreg(phy_common
->dev
, &phy_common
->vdda_pll
,
281 err
= ufs_qcom_phy_init_vreg(phy_common
->dev
, &phy_common
->vdda_phy
,
287 /* vddp-ref-clk-* properties are optional */
288 __ufs_qcom_phy_init_vreg(phy_common
->dev
, &phy_common
->vddp_ref_clk
,
289 "vddp-ref-clk", true);
293 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators
);
295 static int ufs_qcom_phy_cfg_vreg(struct device
*dev
,
296 struct ufs_qcom_phy_vreg
*vreg
, bool on
)
299 struct regulator
*reg
= vreg
->reg
;
300 const char *name
= vreg
->name
;
304 if (regulator_count_voltages(reg
) > 0) {
305 min_uV
= on
? vreg
->min_uV
: 0;
306 ret
= regulator_set_voltage(reg
, min_uV
, vreg
->max_uV
);
308 dev_err(dev
, "%s: %s set voltage failed, err=%d\n",
309 __func__
, name
, ret
);
312 uA_load
= on
? vreg
->max_uA
: 0;
313 ret
= regulator_set_load(reg
, uA_load
);
316 * regulator_set_load() returns new regulator
321 dev_err(dev
, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
322 __func__
, name
, uA_load
, ret
);
330 static int ufs_qcom_phy_enable_vreg(struct device
*dev
,
331 struct ufs_qcom_phy_vreg
*vreg
)
335 if (!vreg
|| vreg
->enabled
)
338 ret
= ufs_qcom_phy_cfg_vreg(dev
, vreg
, true);
340 dev_err(dev
, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
345 ret
= regulator_enable(vreg
->reg
);
347 dev_err(dev
, "%s: enable failed, err=%d\n",
352 vreg
->enabled
= true;
357 static int ufs_qcom_phy_enable_ref_clk(struct ufs_qcom_phy
*phy
)
361 if (phy
->is_ref_clk_enabled
)
365 * reference clock is propagated in a daisy-chained manner from
366 * source to phy, so ungate them at each stage.
368 ret
= clk_prepare_enable(phy
->ref_clk_src
);
370 dev_err(phy
->dev
, "%s: ref_clk_src enable failed %d\n",
376 * "ref_clk_parent" is optional clock hence make sure that clk reference
377 * is available before trying to enable the clock.
379 if (phy
->ref_clk_parent
) {
380 ret
= clk_prepare_enable(phy
->ref_clk_parent
);
382 dev_err(phy
->dev
, "%s: ref_clk_parent enable failed %d\n",
384 goto out_disable_src
;
388 ret
= clk_prepare_enable(phy
->ref_clk
);
390 dev_err(phy
->dev
, "%s: ref_clk enable failed %d\n",
392 goto out_disable_parent
;
395 phy
->is_ref_clk_enabled
= true;
399 if (phy
->ref_clk_parent
)
400 clk_disable_unprepare(phy
->ref_clk_parent
);
402 clk_disable_unprepare(phy
->ref_clk_src
);
407 static int ufs_qcom_phy_disable_vreg(struct device
*dev
,
408 struct ufs_qcom_phy_vreg
*vreg
)
412 if (!vreg
|| !vreg
->enabled
|| vreg
->is_always_on
)
415 ret
= regulator_disable(vreg
->reg
);
418 /* ignore errors on applying disable config */
419 ufs_qcom_phy_cfg_vreg(dev
, vreg
, false);
420 vreg
->enabled
= false;
422 dev_err(dev
, "%s: %s disable failed, err=%d\n",
423 __func__
, vreg
->name
, ret
);
429 static void ufs_qcom_phy_disable_ref_clk(struct ufs_qcom_phy
*phy
)
431 if (phy
->is_ref_clk_enabled
) {
432 clk_disable_unprepare(phy
->ref_clk
);
434 * "ref_clk_parent" is optional clock hence make sure that clk
435 * reference is available before trying to disable the clock.
437 if (phy
->ref_clk_parent
)
438 clk_disable_unprepare(phy
->ref_clk_parent
);
439 clk_disable_unprepare(phy
->ref_clk_src
);
440 phy
->is_ref_clk_enabled
= false;
444 #define UFS_REF_CLK_EN (1 << 5)
446 static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy
*generic_phy
, bool enable
)
448 struct ufs_qcom_phy
*phy
= get_ufs_qcom_phy(generic_phy
);
450 if (phy
->dev_ref_clk_ctrl_mmio
&&
451 (enable
^ phy
->is_dev_ref_clk_enabled
)) {
452 u32 temp
= readl_relaxed(phy
->dev_ref_clk_ctrl_mmio
);
455 temp
|= UFS_REF_CLK_EN
;
457 temp
&= ~UFS_REF_CLK_EN
;
460 * If we are here to disable this clock immediately after
461 * entering into hibern8, we need to make sure that device
462 * ref_clk is active atleast 1us after the hibern8 enter.
467 writel_relaxed(temp
, phy
->dev_ref_clk_ctrl_mmio
);
468 /* ensure that ref_clk is enabled/disabled before we return */
471 * If we call hibern8 exit after this, we need to make sure that
472 * device ref_clk is stable for atleast 1us before the hibern8
478 phy
->is_dev_ref_clk_enabled
= enable
;
482 void ufs_qcom_phy_enable_dev_ref_clk(struct phy
*generic_phy
)
484 ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy
, true);
486 EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk
);
488 void ufs_qcom_phy_disable_dev_ref_clk(struct phy
*generic_phy
)
490 ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy
, false);
492 EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk
);
494 /* Turn ON M-PHY RMMI interface clocks */
495 static int ufs_qcom_phy_enable_iface_clk(struct ufs_qcom_phy
*phy
)
499 if (phy
->is_iface_clk_enabled
)
502 ret
= clk_prepare_enable(phy
->tx_iface_clk
);
504 dev_err(phy
->dev
, "%s: tx_iface_clk enable failed %d\n",
508 ret
= clk_prepare_enable(phy
->rx_iface_clk
);
510 clk_disable_unprepare(phy
->tx_iface_clk
);
511 dev_err(phy
->dev
, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
515 phy
->is_iface_clk_enabled
= true;
521 /* Turn OFF M-PHY RMMI interface clocks */
522 void ufs_qcom_phy_disable_iface_clk(struct ufs_qcom_phy
*phy
)
524 if (phy
->is_iface_clk_enabled
) {
525 clk_disable_unprepare(phy
->tx_iface_clk
);
526 clk_disable_unprepare(phy
->rx_iface_clk
);
527 phy
->is_iface_clk_enabled
= false;
531 int ufs_qcom_phy_start_serdes(struct phy
*generic_phy
)
533 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
536 if (!ufs_qcom_phy
->phy_spec_ops
->start_serdes
) {
537 dev_err(ufs_qcom_phy
->dev
, "%s: start_serdes() callback is not supported\n",
541 ufs_qcom_phy
->phy_spec_ops
->start_serdes(ufs_qcom_phy
);
546 EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes
);
548 int ufs_qcom_phy_set_tx_lane_enable(struct phy
*generic_phy
, u32 tx_lanes
)
550 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
553 if (!ufs_qcom_phy
->phy_spec_ops
->set_tx_lane_enable
) {
554 dev_err(ufs_qcom_phy
->dev
, "%s: set_tx_lane_enable() callback is not supported\n",
558 ufs_qcom_phy
->phy_spec_ops
->set_tx_lane_enable(ufs_qcom_phy
,
564 EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable
);
566 void ufs_qcom_phy_save_controller_version(struct phy
*generic_phy
,
567 u8 major
, u16 minor
, u16 step
)
569 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
571 ufs_qcom_phy
->host_ctrl_rev_major
= major
;
572 ufs_qcom_phy
->host_ctrl_rev_minor
= minor
;
573 ufs_qcom_phy
->host_ctrl_rev_step
= step
;
575 EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version
);
577 int ufs_qcom_phy_calibrate_phy(struct phy
*generic_phy
, bool is_rate_B
)
579 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
582 if (!ufs_qcom_phy
->phy_spec_ops
->calibrate_phy
) {
583 dev_err(ufs_qcom_phy
->dev
, "%s: calibrate_phy() callback is not supported\n",
587 ret
= ufs_qcom_phy
->phy_spec_ops
->
588 calibrate_phy(ufs_qcom_phy
, is_rate_B
);
590 dev_err(ufs_qcom_phy
->dev
, "%s: calibrate_phy() failed %d\n",
596 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy
);
598 int ufs_qcom_phy_is_pcs_ready(struct phy
*generic_phy
)
600 struct ufs_qcom_phy
*ufs_qcom_phy
= get_ufs_qcom_phy(generic_phy
);
602 if (!ufs_qcom_phy
->phy_spec_ops
->is_physical_coding_sublayer_ready
) {
603 dev_err(ufs_qcom_phy
->dev
, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
608 return ufs_qcom_phy
->phy_spec_ops
->
609 is_physical_coding_sublayer_ready(ufs_qcom_phy
);
611 EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready
);
613 int ufs_qcom_phy_power_on(struct phy
*generic_phy
)
615 struct ufs_qcom_phy
*phy_common
= get_ufs_qcom_phy(generic_phy
);
616 struct device
*dev
= phy_common
->dev
;
619 if (phy_common
->is_powered_on
)
622 err
= ufs_qcom_phy_enable_vreg(dev
, &phy_common
->vdda_phy
);
624 dev_err(dev
, "%s enable vdda_phy failed, err=%d\n",
629 phy_common
->phy_spec_ops
->power_control(phy_common
, true);
631 /* vdda_pll also enables ref clock LDOs so enable it first */
632 err
= ufs_qcom_phy_enable_vreg(dev
, &phy_common
->vdda_pll
);
634 dev_err(dev
, "%s enable vdda_pll failed, err=%d\n",
636 goto out_disable_phy
;
639 err
= ufs_qcom_phy_enable_iface_clk(phy_common
);
641 dev_err(dev
, "%s enable phy iface clock failed, err=%d\n",
643 goto out_disable_pll
;
646 err
= ufs_qcom_phy_enable_ref_clk(phy_common
);
648 dev_err(dev
, "%s enable phy ref clock failed, err=%d\n",
650 goto out_disable_iface_clk
;
653 /* enable device PHY ref_clk pad rail */
654 if (phy_common
->vddp_ref_clk
.reg
) {
655 err
= ufs_qcom_phy_enable_vreg(dev
,
656 &phy_common
->vddp_ref_clk
);
658 dev_err(dev
, "%s enable vddp_ref_clk failed, err=%d\n",
660 goto out_disable_ref_clk
;
664 phy_common
->is_powered_on
= true;
668 ufs_qcom_phy_disable_ref_clk(phy_common
);
669 out_disable_iface_clk
:
670 ufs_qcom_phy_disable_iface_clk(phy_common
);
672 ufs_qcom_phy_disable_vreg(dev
, &phy_common
->vdda_pll
);
674 ufs_qcom_phy_disable_vreg(dev
, &phy_common
->vdda_phy
);
678 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on
);
680 int ufs_qcom_phy_power_off(struct phy
*generic_phy
)
682 struct ufs_qcom_phy
*phy_common
= get_ufs_qcom_phy(generic_phy
);
684 if (!phy_common
->is_powered_on
)
687 phy_common
->phy_spec_ops
->power_control(phy_common
, false);
689 if (phy_common
->vddp_ref_clk
.reg
)
690 ufs_qcom_phy_disable_vreg(phy_common
->dev
,
691 &phy_common
->vddp_ref_clk
);
692 ufs_qcom_phy_disable_ref_clk(phy_common
);
693 ufs_qcom_phy_disable_iface_clk(phy_common
);
695 ufs_qcom_phy_disable_vreg(phy_common
->dev
, &phy_common
->vdda_pll
);
696 ufs_qcom_phy_disable_vreg(phy_common
->dev
, &phy_common
->vdda_phy
);
697 phy_common
->is_powered_on
= false;
701 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off
);