drivers/phy/phy-qcom-ufs.c

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include "phy-qcom-ufs-i.h"
  16
  17 #define MAX_PROP_NAME              32
  18 #define VDDA_PHY_MIN_UV            1000000
  19 #define VDDA_PHY_MAX_UV            1000000
  20 #define VDDA_PLL_MIN_UV            1800000
  21 #define VDDA_PLL_MAX_UV            1800000
  22 #define VDDP_REF_CLK_MIN_UV        1200000
  23 #define VDDP_REF_CLK_MAX_UV        1200000
  24
  25 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  26                            struct ufs_qcom_phy_calibration *tbl_A,
  27                            int tbl_size_A,
  28                            struct ufs_qcom_phy_calibration *tbl_B,
  29                            int tbl_size_B, bool is_rate_B)
  30 {
  31         int i;
  32         int ret = 0;
  33
  34         if (!tbl_A) {
  35                 dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
  36                 ret = EINVAL;
  37                 goto out;
  38         }
  39
  40         for (i = 0; i < tbl_size_A; i++)
  41                 writel_relaxed(tbl_A[i].cfg_value,
  42                                ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
  43
  44         /*
  45          * In case we would like to work in rate B, we need
  46          * to override a registers that were configured in rate A table
  47          * with registers of rate B table.
  48          * table.
  49          */
  50         if (is_rate_B) {
  51                 if (!tbl_B) {
  52                         dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
  53                                 __func__);
  54                         ret = EINVAL;
  55                         goto out;
  56                 }
  57
  58                 for (i = 0; i < tbl_size_B; i++)
  59                         writel_relaxed(tbl_B[i].cfg_value,
  60                                 ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
  61         }
  62
  63         /* flush buffered writes */
  64         mb();
  65
  66 out:
  67         return ret;
  68 }
  69 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate);
  70
  71 /*
  72  * This assumes the embedded phy structure inside generic_phy is of type
  73  * struct ufs_qcom_phy. In order to function properly it's crucial
  74  * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
  75  * as the first inside generic_phy.
  76  */
  77 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
  78 {
  79         return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
  80 }
  81 EXPORT_SYMBOL_GPL(get_ufs_qcom_phy);
  82
  83 static
  84 int ufs_qcom_phy_base_init(struct platform_device *pdev,
  85                            struct ufs_qcom_phy *phy_common)
  86 {
  87         struct device *dev = &pdev->dev;
  88         struct resource *res;
  89         int err = 0;
  90
  91         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
  92         phy_common->mmio = devm_ioremap_resource(dev, res);
  93         if (IS_ERR((void const *)phy_common->mmio)) {
  94                 err = PTR_ERR((void const *)phy_common->mmio);
  95                 phy_common->mmio = NULL;
  96                 dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
  97                         __func__, err);
  98                 return err;
  99         }
 100
 101         /* "dev_ref_clk_ctrl_mem" is optional resource */
 102         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 103                                            "dev_ref_clk_ctrl_mem");
 104         phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
 105         if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio))
 106                 phy_common->dev_ref_clk_ctrl_mmio = NULL;
 107
 108         return 0;
 109 }
 110
 111 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
 112                                 struct ufs_qcom_phy *common_cfg,
 113                                 const struct phy_ops *ufs_qcom_phy_gen_ops,
 114                                 struct ufs_qcom_phy_specific_ops *phy_spec_ops)
 115 {
 116         int err;
 117         struct device *dev = &pdev->dev;
 118         struct phy *generic_phy = NULL;
 119         struct phy_provider *phy_provider;
 120
 121         err = ufs_qcom_phy_base_init(pdev, common_cfg);
 122         if (err) {
 123                 dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
 124                 goto out;
 125         }
 126
 127         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 128         if (IS_ERR(phy_provider)) {
 129                 err = PTR_ERR(phy_provider);
 130                 dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
 131                 goto out;
 132         }
 133
 134         generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
 135         if (IS_ERR(generic_phy)) {
 136                 err =  PTR_ERR(generic_phy);
 137                 dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
 138                 generic_phy = NULL;
 139                 goto out;
 140         }
 141
 142         common_cfg->phy_spec_ops = phy_spec_ops;
 143         common_cfg->dev = dev;
 144
 145 out:
 146         return generic_phy;
 147 }
 148 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
 149
 150 static int __ufs_qcom_phy_clk_get(struct device *dev,
 151                          const char *name, struct clk **clk_out, bool err_print)
 152 {
 153         struct clk *clk;
 154         int err = 0;
 155
 156         clk = devm_clk_get(dev, name);
 157         if (IS_ERR(clk)) {
 158                 err = PTR_ERR(clk);
 159                 if (err_print)
 160                         dev_err(dev, "failed to get %s err %d", name, err);
 161         } else {
 162                 *clk_out = clk;
 163         }
 164
 165         return err;
 166 }
 167
 168 static int ufs_qcom_phy_clk_get(struct device *dev,
 169                          const char *name, struct clk **clk_out)
 170 {
 171         return __ufs_qcom_phy_clk_get(dev, name, clk_out, true);
 172 }
 173
 174 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common)
 175 {
 176         int err;
 177
 178         if (of_device_is_compatible(phy_common->dev->of_node,
 179                                 "qcom,msm8996-ufs-phy-qmp-14nm"))
 180                 goto skip_txrx_clk;
 181
 182         err = ufs_qcom_phy_clk_get(phy_common->dev, "tx_iface_clk",
 183                                    &phy_common->tx_iface_clk);
 184         if (err)
 185                 goto out;
 186
 187         err = ufs_qcom_phy_clk_get(phy_common->dev, "rx_iface_clk",
 188                                    &phy_common->rx_iface_clk);
 189         if (err)
 190                 goto out;
 191
 192 skip_txrx_clk:
 193         err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_src",
 194                                    &phy_common->ref_clk_src);
 195         if (err)
 196                 goto out;
 197
 198         /*
 199          * "ref_clk_parent" is optional hence don't abort init if it's not
 200          * found.
 201          */
 202         __ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_parent",
 203                                    &phy_common->ref_clk_parent, false);
 204
 205         err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk",
 206                                    &phy_common->ref_clk);
 207
 208 out:
 209         return err;
 210 }
 211 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks);
 212
 213 static int __ufs_qcom_phy_init_vreg(struct device *dev,
 214                 struct ufs_qcom_phy_vreg *vreg, const char *name, bool optional)
 215 {
 216         int err = 0;
 217
 218         char prop_name[MAX_PROP_NAME];
 219
 220         vreg->name = name;
 221         vreg->reg = devm_regulator_get(dev, name);
 222         if (IS_ERR(vreg->reg)) {
 223                 err = PTR_ERR(vreg->reg);
 224                 vreg->reg = NULL;
 225                 if (!optional)
 226                         dev_err(dev, "failed to get %s, %d\n", name, err);
 227                 goto out;
 228         }
 229
 230         if (dev->of_node) {
 231                 snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
 232                 err = of_property_read_u32(dev->of_node,
 233                                         prop_name, &vreg->max_uA);
 234                 if (err && err != -EINVAL) {
 235                         dev_err(dev, "%s: failed to read %s\n",
 236                                         __func__, prop_name);
 237                         goto out;
 238                 } else if (err == -EINVAL || !vreg->max_uA) {
 239                         if (regulator_count_voltages(vreg->reg) > 0) {
 240                                 dev_err(dev, "%s: %s is mandatory\n",
 241                                                 __func__, prop_name);
 242                                 goto out;
 243                         }
 244                         err = 0;
 245                 }
 246                 snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name);
 247                 vreg->is_always_on = of_property_read_bool(dev->of_node,
 248                                                            prop_name);
 249         }
 250
 251         if (!strcmp(name, "vdda-pll")) {
 252                 vreg->max_uV = VDDA_PLL_MAX_UV;
 253                 vreg->min_uV = VDDA_PLL_MIN_UV;
 254         } else if (!strcmp(name, "vdda-phy")) {
 255                 vreg->max_uV = VDDA_PHY_MAX_UV;
 256                 vreg->min_uV = VDDA_PHY_MIN_UV;
 257         } else if (!strcmp(name, "vddp-ref-clk")) {
 258                 vreg->max_uV = VDDP_REF_CLK_MAX_UV;
 259                 vreg->min_uV = VDDP_REF_CLK_MIN_UV;
 260         }
 261
 262 out:
 263         return err;
 264 }
 265
 266 static int ufs_qcom_phy_init_vreg(struct device *dev,
 267                         struct ufs_qcom_phy_vreg *vreg, const char *name)
 268 {
 269         return __ufs_qcom_phy_init_vreg(dev, vreg, name, false);
 270 }
 271
 272 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common)
 273 {
 274         int err;
 275
 276         err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_pll,
 277                 "vdda-pll");
 278         if (err)
 279                 goto out;
 280
 281         err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_phy,
 282                 "vdda-phy");
 283
 284         if (err)
 285                 goto out;
 286
 287         /* vddp-ref-clk-* properties are optional */
 288         __ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vddp_ref_clk,
 289                                  "vddp-ref-clk", true);
 290 out:
 291         return err;
 292 }
 293 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators);
 294
 295 static int ufs_qcom_phy_cfg_vreg(struct device *dev,
 296                           struct ufs_qcom_phy_vreg *vreg, bool on)
 297 {
 298         int ret = 0;
 299         struct regulator *reg = vreg->reg;
 300         const char *name = vreg->name;
 301         int min_uV;
 302         int uA_load;
 303
 304         if (regulator_count_voltages(reg) > 0) {
 305                 min_uV = on ? vreg->min_uV : 0;
 306                 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
 307                 if (ret) {
 308                         dev_err(dev, "%s: %s set voltage failed, err=%d\n",
 309                                         __func__, name, ret);
 310                         goto out;
 311                 }
 312                 uA_load = on ? vreg->max_uA : 0;
 313                 ret = regulator_set_load(reg, uA_load);
 314                 if (ret >= 0) {
 315                         /*
 316                          * regulator_set_load() returns new regulator
 317                          * mode upon success.
 318                          */
 319                         ret = 0;
 320                 } else {
 321                         dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
 322                                         __func__, name, uA_load, ret);
 323                         goto out;
 324                 }
 325         }
 326 out:
 327         return ret;
 328 }
 329
 330 static int ufs_qcom_phy_enable_vreg(struct device *dev,
 331                              struct ufs_qcom_phy_vreg *vreg)
 332 {
 333         int ret = 0;
 334
 335         if (!vreg || vreg->enabled)
 336                 goto out;
 337
 338         ret = ufs_qcom_phy_cfg_vreg(dev, vreg, true);
 339         if (ret) {
 340                 dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
 341                         __func__, ret);
 342                 goto out;
 343         }
 344
 345         ret = regulator_enable(vreg->reg);
 346         if (ret) {
 347                 dev_err(dev, "%s: enable failed, err=%d\n",
 348                                 __func__, ret);
 349                 goto out;
 350         }
 351
 352         vreg->enabled = true;
 353 out:
 354         return ret;
 355 }
 356
 357 static int ufs_qcom_phy_enable_ref_clk(struct ufs_qcom_phy *phy)
 358 {
 359         int ret = 0;
 360
 361         if (phy->is_ref_clk_enabled)
 362                 goto out;
 363
 364         /*
 365          * reference clock is propagated in a daisy-chained manner from
 366          * source to phy, so ungate them at each stage.
 367          */
 368         ret = clk_prepare_enable(phy->ref_clk_src);
 369         if (ret) {
 370                 dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
 371                                 __func__, ret);
 372                 goto out;
 373         }
 374
 375         /*
 376          * "ref_clk_parent" is optional clock hence make sure that clk reference
 377          * is available before trying to enable the clock.
 378          */
 379         if (phy->ref_clk_parent) {
 380                 ret = clk_prepare_enable(phy->ref_clk_parent);
 381                 if (ret) {
 382                         dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
 383                                         __func__, ret);
 384                         goto out_disable_src;
 385                 }
 386         }
 387
 388         ret = clk_prepare_enable(phy->ref_clk);
 389         if (ret) {
 390                 dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
 391                                 __func__, ret);
 392                 goto out_disable_parent;
 393         }
 394
 395         phy->is_ref_clk_enabled = true;
 396         goto out;
 397
 398 out_disable_parent:
 399         if (phy->ref_clk_parent)
 400                 clk_disable_unprepare(phy->ref_clk_parent);
 401 out_disable_src:
 402         clk_disable_unprepare(phy->ref_clk_src);
 403 out:
 404         return ret;
 405 }
 406
 407 static int ufs_qcom_phy_disable_vreg(struct device *dev,
 408                               struct ufs_qcom_phy_vreg *vreg)
 409 {
 410         int ret = 0;
 411
 412         if (!vreg || !vreg->enabled || vreg->is_always_on)
 413                 goto out;
 414
 415         ret = regulator_disable(vreg->reg);
 416
 417         if (!ret) {
 418                 /* ignore errors on applying disable config */
 419                 ufs_qcom_phy_cfg_vreg(dev, vreg, false);
 420                 vreg->enabled = false;
 421         } else {
 422                 dev_err(dev, "%s: %s disable failed, err=%d\n",
 423                                 __func__, vreg->name, ret);
 424         }
 425 out:
 426         return ret;
 427 }
 428
 429 static void ufs_qcom_phy_disable_ref_clk(struct ufs_qcom_phy *phy)
 430 {
 431         if (phy->is_ref_clk_enabled) {
 432                 clk_disable_unprepare(phy->ref_clk);
 433                 /*
 434                  * "ref_clk_parent" is optional clock hence make sure that clk
 435                  * reference is available before trying to disable the clock.
 436                  */
 437                 if (phy->ref_clk_parent)
 438                         clk_disable_unprepare(phy->ref_clk_parent);
 439                 clk_disable_unprepare(phy->ref_clk_src);
 440                 phy->is_ref_clk_enabled = false;
 441         }
 442 }
 443
 444 #define UFS_REF_CLK_EN  (1 << 5)
 445
 446 static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy *generic_phy, bool enable)
 447 {
 448         struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
 449
 450         if (phy->dev_ref_clk_ctrl_mmio &&
 451             (enable ^ phy->is_dev_ref_clk_enabled)) {
 452                 u32 temp = readl_relaxed(phy->dev_ref_clk_ctrl_mmio);
 453
 454                 if (enable)
 455                         temp |= UFS_REF_CLK_EN;
 456                 else
 457                         temp &= ~UFS_REF_CLK_EN;
 458
 459                 /*
 460                  * If we are here to disable this clock immediately after
 461                  * entering into hibern8, we need to make sure that device
 462                  * ref_clk is active atleast 1us after the hibern8 enter.
 463                  */
 464                 if (!enable)
 465                         udelay(1);
 466
 467                 writel_relaxed(temp, phy->dev_ref_clk_ctrl_mmio);
 468                 /* ensure that ref_clk is enabled/disabled before we return */
 469                 wmb();
 470                 /*
 471                  * If we call hibern8 exit after this, we need to make sure that
 472                  * device ref_clk is stable for atleast 1us before the hibern8
 473                  * exit command.
 474                  */
 475                 if (enable)
 476                         udelay(1);
 477
 478                 phy->is_dev_ref_clk_enabled = enable;
 479         }
 480 }
 481
 482 void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy)
 483 {
 484         ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);
 485 }
 486 EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk);
 487
 488 void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)
 489 {
 490         ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);
 491 }
 492 EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk);
 493
 494 /* Turn ON M-PHY RMMI interface clocks */
 495 static int ufs_qcom_phy_enable_iface_clk(struct ufs_qcom_phy *phy)
 496 {
 497         int ret = 0;
 498
 499         if (phy->is_iface_clk_enabled)
 500                 goto out;
 501
 502         ret = clk_prepare_enable(phy->tx_iface_clk);
 503         if (ret) {
 504                 dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
 505                                 __func__, ret);
 506                 goto out;
 507         }
 508         ret = clk_prepare_enable(phy->rx_iface_clk);
 509         if (ret) {
 510                 clk_disable_unprepare(phy->tx_iface_clk);
 511                 dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
 512                                 __func__, ret);
 513                 goto out;
 514         }
 515         phy->is_iface_clk_enabled = true;
 516
 517 out:
 518         return ret;
 519 }
 520
 521 /* Turn OFF M-PHY RMMI interface clocks */
 522 void ufs_qcom_phy_disable_iface_clk(struct ufs_qcom_phy *phy)
 523 {
 524         if (phy->is_iface_clk_enabled) {
 525                 clk_disable_unprepare(phy->tx_iface_clk);
 526                 clk_disable_unprepare(phy->rx_iface_clk);
 527                 phy->is_iface_clk_enabled = false;
 528         }
 529 }
 530
 531 int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
 532 {
 533         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 534         int ret = 0;
 535
 536         if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
 537                 dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
 538                         __func__);
 539                 ret = -ENOTSUPP;
 540         } else {
 541                 ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
 542         }
 543
 544         return ret;
 545 }
 546 EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes);
 547
 548 int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
 549 {
 550         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 551         int ret = 0;
 552
 553         if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
 554                 dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
 555                         __func__);
 556                 ret = -ENOTSUPP;
 557         } else {
 558                 ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
 559                                                                tx_lanes);
 560         }
 561
 562         return ret;
 563 }
 564 EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
 565
 566 void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
 567                                           u8 major, u16 minor, u16 step)
 568 {
 569         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 570
 571         ufs_qcom_phy->host_ctrl_rev_major = major;
 572         ufs_qcom_phy->host_ctrl_rev_minor = minor;
 573         ufs_qcom_phy->host_ctrl_rev_step = step;
 574 }
 575 EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
 576
 577 int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)
 578 {
 579         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 580         int ret = 0;
 581
 582         if (!ufs_qcom_phy->phy_spec_ops->calibrate_phy) {
 583                 dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() callback is not supported\n",
 584                         __func__);
 585                 ret = -ENOTSUPP;
 586         } else {
 587                 ret = ufs_qcom_phy->phy_spec_ops->
 588                                 calibrate_phy(ufs_qcom_phy, is_rate_B);
 589                 if (ret)
 590                         dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n",
 591                                 __func__, ret);
 592         }
 593
 594         return ret;
 595 }
 596 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy);
 597
 598 int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy)
 599 {
 600         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 601
 602         if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
 603                 dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
 604                         __func__);
 605                 return -ENOTSUPP;
 606         }
 607
 608         return ufs_qcom_phy->phy_spec_ops->
 609                         is_physical_coding_sublayer_ready(ufs_qcom_phy);
 610 }
 611 EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready);
 612
 613 int ufs_qcom_phy_power_on(struct phy *generic_phy)
 614 {
 615         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 616         struct device *dev = phy_common->dev;
 617         int err;
 618
 619         if (phy_common->is_powered_on)
 620                 return 0;
 621
 622         err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_phy);
 623         if (err) {
 624                 dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
 625                         __func__, err);
 626                 goto out;
 627         }
 628
 629         phy_common->phy_spec_ops->power_control(phy_common, true);
 630
 631         /* vdda_pll also enables ref clock LDOs so enable it first */
 632         err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_pll);
 633         if (err) {
 634                 dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
 635                         __func__, err);
 636                 goto out_disable_phy;
 637         }
 638
 639         err = ufs_qcom_phy_enable_iface_clk(phy_common);
 640         if (err) {
 641                 dev_err(dev, "%s enable phy iface clock failed, err=%d\n",
 642                         __func__, err);
 643                 goto out_disable_pll;
 644         }
 645
 646         err = ufs_qcom_phy_enable_ref_clk(phy_common);
 647         if (err) {
 648                 dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
 649                         __func__, err);
 650                 goto out_disable_iface_clk;
 651         }
 652
 653         /* enable device PHY ref_clk pad rail */
 654         if (phy_common->vddp_ref_clk.reg) {
 655                 err = ufs_qcom_phy_enable_vreg(dev,
 656                                                &phy_common->vddp_ref_clk);
 657                 if (err) {
 658                         dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
 659                                 __func__, err);
 660                         goto out_disable_ref_clk;
 661                 }
 662         }
 663
 664         phy_common->is_powered_on = true;
 665         goto out;
 666
 667 out_disable_ref_clk:
 668         ufs_qcom_phy_disable_ref_clk(phy_common);
 669 out_disable_iface_clk:
 670         ufs_qcom_phy_disable_iface_clk(phy_common);
 671 out_disable_pll:
 672         ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_pll);
 673 out_disable_phy:
 674         ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_phy);
 675 out:
 676         return err;
 677 }
 678 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on);
 679
 680 int ufs_qcom_phy_power_off(struct phy *generic_phy)
 681 {
 682         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 683
 684         if (!phy_common->is_powered_on)
 685                 return 0;
 686
 687         phy_common->phy_spec_ops->power_control(phy_common, false);
 688
 689         if (phy_common->vddp_ref_clk.reg)
 690                 ufs_qcom_phy_disable_vreg(phy_common->dev,
 691                                           &phy_common->vddp_ref_clk);
 692         ufs_qcom_phy_disable_ref_clk(phy_common);
 693         ufs_qcom_phy_disable_iface_clk(phy_common);
 694
 695         ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_pll);
 696         ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_phy);
 697         phy_common->is_powered_on = false;
 698
 699         return 0;
 700 }
 701 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off);