drivers/phy/phy-rockchip-emmc.c

   1 /*
   2  * Rockchip emmc PHY driver
   3  *
   4  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
   5  * Copyright (C) 2016 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26
  27 /*
  28  * The higher 16-bit of this register is used for write protection
  29  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
  30  */
  31 #define HIWORD_UPDATE(val, mask, shift) \
  32                 ((val) << (shift) | (mask) << ((shift) + 16))
  33
  34 /* Register definition */
  35 #define GRF_EMMCPHY_CON0                0x0
  36 #define GRF_EMMCPHY_CON1                0x4
  37 #define GRF_EMMCPHY_CON2                0x8
  38 #define GRF_EMMCPHY_CON3                0xc
  39 #define GRF_EMMCPHY_CON4                0x10
  40 #define GRF_EMMCPHY_CON5                0x14
  41 #define GRF_EMMCPHY_CON6                0x18
  42 #define GRF_EMMCPHY_STATUS              0x20
  43
  44 #define PHYCTRL_PDB_MASK                0x1
  45 #define PHYCTRL_PDB_SHIFT               0x0
  46 #define PHYCTRL_PDB_PWR_ON              0x1
  47 #define PHYCTRL_PDB_PWR_OFF             0x0
  48 #define PHYCTRL_ENDLL_MASK              0x1
  49 #define PHYCTRL_ENDLL_SHIFT             0x1
  50 #define PHYCTRL_ENDLL_ENABLE            0x1
  51 #define PHYCTRL_ENDLL_DISABLE           0x0
  52 #define PHYCTRL_CALDONE_MASK            0x1
  53 #define PHYCTRL_CALDONE_SHIFT           0x6
  54 #define PHYCTRL_CALDONE_DONE            0x1
  55 #define PHYCTRL_CALDONE_GOING           0x0
  56 #define PHYCTRL_DLLRDY_MASK             0x1
  57 #define PHYCTRL_DLLRDY_SHIFT            0x5
  58 #define PHYCTRL_DLLRDY_DONE             0x1
  59 #define PHYCTRL_DLLRDY_GOING            0x0
  60 #define PHYCTRL_FREQSEL_200M            0x0
  61 #define PHYCTRL_FREQSEL_50M             0x1
  62 #define PHYCTRL_FREQSEL_100M            0x2
  63 #define PHYCTRL_FREQSEL_150M            0x3
  64 #define PHYCTRL_FREQSEL_MASK            0x3
  65 #define PHYCTRL_FREQSEL_SHIFT           0xc
  66 #define PHYCTRL_DR_MASK                 0x7
  67 #define PHYCTRL_DR_SHIFT                0x4
  68 #define PHYCTRL_DR_50OHM                0x0
  69 #define PHYCTRL_DR_33OHM                0x1
  70 #define PHYCTRL_DR_66OHM                0x2
  71 #define PHYCTRL_DR_100OHM               0x3
  72 #define PHYCTRL_DR_40OHM                0x4
  73 #define PHYCTRL_OTAPDLYENA              0x1
  74 #define PHYCTRL_OTAPDLYENA_MASK         0x1
  75 #define PHYCTRL_OTAPDLYENA_SHIFT        0xb
  76 #define PHYCTRL_OTAPDLYSEL_MASK         0xf
  77 #define PHYCTRL_OTAPDLYSEL_SHIFT        0x7
  78
  79 struct rockchip_emmc_phy {
  80         unsigned int    reg_offset;
  81         struct regmap   *reg_base;
  82         struct clk      *emmcclk;
  83 };
  84
  85 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
  86 {
  87         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
  88         unsigned int caldone;
  89         unsigned int dllrdy;
  90         unsigned int freqsel = PHYCTRL_FREQSEL_200M;
  91         unsigned long timeout;
  92
  93         if (rk_phy->emmcclk != NULL) {
  94                 unsigned long rate = clk_get_rate(rk_phy->emmcclk);
  95                 unsigned long ideal_rate;
  96                 unsigned long diff;
  97
  98                 switch (rate) {
  99                 case 0 ... 74999999:
 100                         ideal_rate = 50000000;
 101                         freqsel = PHYCTRL_FREQSEL_50M;
 102                         break;
 103                 case 75000000 ... 124999999:
 104                         ideal_rate = 100000000;
 105                         freqsel = PHYCTRL_FREQSEL_100M;
 106                         break;
 107                 case 125000000 ... 174999999:
 108                         ideal_rate = 150000000;
 109                         freqsel = PHYCTRL_FREQSEL_150M;
 110                         break;
 111                 default:
 112                         ideal_rate = 200000000;
 113                         break;
 114                 };
 115
 116                 diff = (rate > ideal_rate) ?
 117                         rate - ideal_rate : ideal_rate - rate;
 118
 119                 /*
 120                  * In order for tuning delays to be accurate we need to be
 121                  * pretty spot on for the DLL range, so warn if we're too
 122                  * far off.  Also warn if we're above the 200 MHz max.  Don't
 123                  * warn for really slow rates since we won't be tuning then.
 124                  */
 125                 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
 126                         dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
 127         }
 128
 129         /*
 130          * Keep phyctrl_pdb and phyctrl_endll low to allow
 131          * initialization of CALIO state M/C DFFs
 132          */
 133         regmap_write(rk_phy->reg_base,
 134                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 135                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
 136                                    PHYCTRL_PDB_MASK,
 137                                    PHYCTRL_PDB_SHIFT));
 138         regmap_write(rk_phy->reg_base,
 139                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 140                      HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
 141                                    PHYCTRL_ENDLL_MASK,
 142                                    PHYCTRL_ENDLL_SHIFT));
 143
 144         /* Already finish power_off above */
 145         if (on_off == PHYCTRL_PDB_PWR_OFF)
 146                 return 0;
 147
 148         /*
 149          * According to the user manual, calpad calibration
 150          * cycle takes more than 2us without the minimal recommended
 151          * value, so we may need a little margin here
 152          */
 153         udelay(3);
 154         regmap_write(rk_phy->reg_base,
 155                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 156                      HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
 157                                    PHYCTRL_PDB_MASK,
 158                                    PHYCTRL_PDB_SHIFT));
 159
 160         /*
 161          * According to the user manual, it asks driver to
 162          * wait 5us for calpad busy trimming
 163          */
 164         udelay(5);
 165         regmap_read(rk_phy->reg_base,
 166                     rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 167                     &caldone);
 168         caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
 169         if (caldone != PHYCTRL_CALDONE_DONE) {
 170                 pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
 171                 return -ETIMEDOUT;
 172         }
 173
 174         /* Set the frequency of the DLL operation */
 175         regmap_write(rk_phy->reg_base,
 176                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 177                      HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
 178                                    PHYCTRL_FREQSEL_SHIFT));
 179
 180         /* Turn on the DLL */
 181         regmap_write(rk_phy->reg_base,
 182                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 183                      HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
 184                                    PHYCTRL_ENDLL_MASK,
 185                                    PHYCTRL_ENDLL_SHIFT));
 186         /*
 187          * After enabling analog DLL circuits docs say that we need 10.2 us if
 188          * our source clock is at 50 MHz and that lock time scales linearly
 189          * with clock speed.  If we are powering on the PHY and the card clock
 190          * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
 191          * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
 192          * Hopefully we won't be running at 100 kHz, but we should still make
 193          * sure we wait long enough.
 194          */
 195         timeout = jiffies + msecs_to_jiffies(10);
 196         do {
 197                 udelay(1);
 198
 199                 regmap_read(rk_phy->reg_base,
 200                         rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
 201                         &dllrdy);
 202                 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
 203                 if (dllrdy == PHYCTRL_DLLRDY_DONE)
 204                         break;
 205         } while (!time_after(jiffies, timeout));
 206
 207         if (dllrdy != PHYCTRL_DLLRDY_DONE) {
 208                 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
 209                 return -ETIMEDOUT;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static int rockchip_emmc_phy_init(struct phy *phy)
 216 {
 217         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 218         int ret = 0;
 219
 220         /*
 221          * We purposely get the clock here and not in probe to avoid the
 222          * circular dependency problem.  We expect:
 223          * - PHY driver to probe
 224          * - SDHCI driver to start probe
 225          * - SDHCI driver to register it's clock
 226          * - SDHCI driver to get the PHY
 227          * - SDHCI driver to init the PHY
 228          *
 229          * The clock is optional, so upon any error we just set to NULL.
 230          *
 231          * NOTE: we don't do anything special for EPROBE_DEFER here.  Given the
 232          * above expected use case, EPROBE_DEFER isn't sensible to expect, so
 233          * it's just like any other error.
 234          */
 235         rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
 236         if (IS_ERR(rk_phy->emmcclk)) {
 237                 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
 238                 rk_phy->emmcclk = NULL;
 239         }
 240
 241         return ret;
 242 }
 243
 244 static int rockchip_emmc_phy_exit(struct phy *phy)
 245 {
 246         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 247
 248         clk_put(rk_phy->emmcclk);
 249
 250         return 0;
 251 }
 252
 253 static int rockchip_emmc_phy_power_off(struct phy *phy)
 254 {
 255         /* Power down emmc phy analog blocks */
 256         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
 257 }
 258
 259 static int rockchip_emmc_phy_power_on(struct phy *phy)
 260 {
 261         struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
 262
 263         /* Drive impedance: 50 Ohm */
 264         regmap_write(rk_phy->reg_base,
 265                      rk_phy->reg_offset + GRF_EMMCPHY_CON6,
 266                      HIWORD_UPDATE(PHYCTRL_DR_50OHM,
 267                                    PHYCTRL_DR_MASK,
 268                                    PHYCTRL_DR_SHIFT));
 269
 270         /* Output tap delay: enable */
 271         regmap_write(rk_phy->reg_base,
 272                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 273                      HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
 274                                    PHYCTRL_OTAPDLYENA_MASK,
 275                                    PHYCTRL_OTAPDLYENA_SHIFT));
 276
 277         /* Output tap delay */
 278         regmap_write(rk_phy->reg_base,
 279                      rk_phy->reg_offset + GRF_EMMCPHY_CON0,
 280                      HIWORD_UPDATE(4,
 281                                    PHYCTRL_OTAPDLYSEL_MASK,
 282                                    PHYCTRL_OTAPDLYSEL_SHIFT));
 283
 284         /* Power up emmc phy analog blocks */
 285         return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
 286 }
 287
 288 static const struct phy_ops ops = {
 289         .init           = rockchip_emmc_phy_init,
 290         .exit           = rockchip_emmc_phy_exit,
 291         .power_on       = rockchip_emmc_phy_power_on,
 292         .power_off      = rockchip_emmc_phy_power_off,
 293         .owner          = THIS_MODULE,
 294 };
 295
 296 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
 297 {
 298         struct device *dev = &pdev->dev;
 299         struct rockchip_emmc_phy *rk_phy;
 300         struct phy *generic_phy;
 301         struct phy_provider *phy_provider;
 302         struct regmap *grf;
 303         unsigned int reg_offset;
 304
 305         if (!dev->parent || !dev->parent->of_node)
 306                 return -ENODEV;
 307
 308         grf = syscon_node_to_regmap(dev->parent->of_node);
 309         if (IS_ERR(grf)) {
 310                 dev_err(dev, "Missing rockchip,grf property\n");
 311                 return PTR_ERR(grf);
 312         }
 313
 314         rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
 315         if (!rk_phy)
 316                 return -ENOMEM;
 317
 318         if (of_property_read_u32(dev->of_node, "reg", &reg_offset)) {
 319                 dev_err(dev, "missing reg property in node %s\n",
 320                         dev->of_node->name);
 321                 return -EINVAL;
 322         }
 323
 324         rk_phy->reg_offset = reg_offset;
 325         rk_phy->reg_base = grf;
 326
 327         generic_phy = devm_phy_create(dev, dev->of_node, &ops);
 328         if (IS_ERR(generic_phy)) {
 329                 dev_err(dev, "failed to create PHY\n");
 330                 return PTR_ERR(generic_phy);
 331         }
 332
 333         phy_set_drvdata(generic_phy, rk_phy);
 334         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 335
 336         return PTR_ERR_OR_ZERO(phy_provider);
 337 }
 338
 339 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
 340         { .compatible = "rockchip,rk3399-emmc-phy" },
 341         {}
 342 };
 343
 344 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
 345
 346 static struct platform_driver rockchip_emmc_driver = {
 347         .probe          = rockchip_emmc_phy_probe,
 348         .driver         = {
 349                 .name   = "rockchip-emmc-phy",
 350                 .of_match_table = rockchip_emmc_phy_dt_ids,
 351         },
 352 };
 353
 354 module_platform_driver(rockchip_emmc_driver);
 355
 356 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
 357 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
 358 MODULE_LICENSE("GPL v2");