drivers/phy/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/spinlock.h>
  32
  33 #define PLL_STATUS              0x00000004
  34 #define PLL_GO                  0x00000008
  35 #define PLL_CONFIGURATION1      0x0000000C
  36 #define PLL_CONFIGURATION2      0x00000010
  37 #define PLL_CONFIGURATION3      0x00000014
  38 #define PLL_CONFIGURATION4      0x00000020
  39
  40 #define PLL_REGM_MASK           0x001FFE00
  41 #define PLL_REGM_SHIFT          0x9
  42 #define PLL_REGM_F_MASK         0x0003FFFF
  43 #define PLL_REGM_F_SHIFT        0x0
  44 #define PLL_REGN_MASK           0x000001FE
  45 #define PLL_REGN_SHIFT          0x1
  46 #define PLL_SELFREQDCO_MASK     0x0000000E
  47 #define PLL_SELFREQDCO_SHIFT    0x1
  48 #define PLL_SD_MASK             0x0003FC00
  49 #define PLL_SD_SHIFT            10
  50 #define SET_PLL_GO              0x1
  51 #define PLL_LDOPWDN             BIT(15)
  52 #define PLL_TICOPWDN            BIT(16)
  53 #define PLL_LOCK                0x2
  54 #define PLL_IDLE                0x1
  55
  56 /*
  57  * This is an Empirical value that works, need to confirm the actual
  58  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  59  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
  60  */
  61 #define PLL_IDLE_TIME   100     /* in milliseconds */
  62 #define PLL_LOCK_TIME   100     /* in milliseconds */
  63
  64 struct pipe3_dpll_params {
  65         u16     m;
  66         u8      n;
  67         u8      freq:3;
  68         u8      sd;
  69         u32     mf;
  70 };
  71
  72 struct pipe3_dpll_map {
  73         unsigned long rate;
  74         struct pipe3_dpll_params params;
  75 };
  76
  77 struct ti_pipe3 {
  78         void __iomem            *pll_ctrl_base;
  79         struct device           *dev;
  80         struct device           *control_dev;
  81         struct clk              *wkupclk;
  82         struct clk              *sys_clk;
  83         struct clk              *refclk;
  84         struct clk              *div_clk;
  85         struct pipe3_dpll_map   *dpll_map;
  86         bool                    enabled;
  87         spinlock_t              lock;   /* serialize clock enable/disable */
  88         /* the below flag is needed specifically for SATA */
  89         bool                    refclk_enabled;
  90 };
  91
  92 static struct pipe3_dpll_map dpll_map_usb[] = {
  93         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
  94         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
  95         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
  96         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
  97         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
  98         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
  99         { },                                    /* Terminator */
 100 };
 101
 102 static struct pipe3_dpll_map dpll_map_sata[] = {
 103         {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
 104         {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
 105         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 106         {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
 107         {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
 108         {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
 109         { },                                    /* Terminator */
 110 };
 111
 112 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 113 {
 114         return __raw_readl(addr + offset);
 115 }
 116
 117 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 118         u32 data)
 119 {
 120         __raw_writel(data, addr + offset);
 121 }
 122
 123 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 124 {
 125         unsigned long rate;
 126         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 127
 128         rate = clk_get_rate(phy->sys_clk);
 129
 130         for (; dpll_map->rate; dpll_map++) {
 131                 if (rate == dpll_map->rate)
 132                         return &dpll_map->params;
 133         }
 134
 135         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 136
 137         return NULL;
 138 }
 139
 140 static int ti_pipe3_power_off(struct phy *x)
 141 {
 142         struct ti_pipe3 *phy = phy_get_drvdata(x);
 143
 144         omap_control_phy_power(phy->control_dev, 0);
 145
 146         return 0;
 147 }
 148
 149 static int ti_pipe3_power_on(struct phy *x)
 150 {
 151         struct ti_pipe3 *phy = phy_get_drvdata(x);
 152
 153         omap_control_phy_power(phy->control_dev, 1);
 154
 155         return 0;
 156 }
 157
 158 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 159 {
 160         u32             val;
 161         unsigned long   timeout;
 162
 163         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 164         do {
 165                 cpu_relax();
 166                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 167                 if (val & PLL_LOCK)
 168                         break;
 169         } while (!time_after(jiffies, timeout));
 170
 171         if (!(val & PLL_LOCK)) {
 172                 dev_err(phy->dev, "DPLL failed to lock\n");
 173                 return -EBUSY;
 174         }
 175
 176         return 0;
 177 }
 178
 179 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 180 {
 181         u32                     val;
 182         struct pipe3_dpll_params *dpll_params;
 183
 184         dpll_params = ti_pipe3_get_dpll_params(phy);
 185         if (!dpll_params)
 186                 return -EINVAL;
 187
 188         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 189         val &= ~PLL_REGN_MASK;
 190         val |= dpll_params->n << PLL_REGN_SHIFT;
 191         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 192
 193         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 194         val &= ~PLL_SELFREQDCO_MASK;
 195         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 196         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 197
 198         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 199         val &= ~PLL_REGM_MASK;
 200         val |= dpll_params->m << PLL_REGM_SHIFT;
 201         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 202
 203         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 204         val &= ~PLL_REGM_F_MASK;
 205         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 206         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 207
 208         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 209         val &= ~PLL_SD_MASK;
 210         val |= dpll_params->sd << PLL_SD_SHIFT;
 211         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 212
 213         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 214
 215         return ti_pipe3_dpll_wait_lock(phy);
 216 }
 217
 218 static int ti_pipe3_init(struct phy *x)
 219 {
 220         struct ti_pipe3 *phy = phy_get_drvdata(x);
 221         u32 val;
 222         int ret = 0;
 223
 224         /*
 225          * Set pcie_pcs register to 0x96 for proper functioning of phy
 226          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 227          * 18-1804.
 228          */
 229         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 230                 omap_control_pcie_pcs(phy->control_dev, 0x96);
 231                 return 0;
 232         }
 233
 234         /* Bring it out of IDLE if it is IDLE */
 235         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 236         if (val & PLL_IDLE) {
 237                 val &= ~PLL_IDLE;
 238                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 239                 ret = ti_pipe3_dpll_wait_lock(phy);
 240         }
 241
 242         /* Program the DPLL only if not locked */
 243         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 244         if (!(val & PLL_LOCK))
 245                 if (ti_pipe3_dpll_program(phy))
 246                         return -EINVAL;
 247
 248         return ret;
 249 }
 250
 251 static int ti_pipe3_exit(struct phy *x)
 252 {
 253         struct ti_pipe3 *phy = phy_get_drvdata(x);
 254         u32 val;
 255         unsigned long timeout;
 256
 257         /* SATA DPLL can't be powered down due to Errata i783 and PCIe
 258          * does not have internal DPLL
 259          */
 260         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
 261             of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
 262                 return 0;
 263
 264         /* Put DPLL in IDLE mode */
 265         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 266         val |= PLL_IDLE;
 267         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 268
 269         /* wait for LDO and Oscillator to power down */
 270         timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 271         do {
 272                 cpu_relax();
 273                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 274                 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 275                         break;
 276         } while (!time_after(jiffies, timeout));
 277
 278         if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 279                 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 280                         val);
 281                 return -EBUSY;
 282         }
 283
 284         return 0;
 285 }
 286 static struct phy_ops ops = {
 287         .init           = ti_pipe3_init,
 288         .exit           = ti_pipe3_exit,
 289         .power_on       = ti_pipe3_power_on,
 290         .power_off      = ti_pipe3_power_off,
 291         .owner          = THIS_MODULE,
 292 };
 293
 294 #ifdef CONFIG_OF
 295 static const struct of_device_id ti_pipe3_id_table[];
 296 #endif
 297
 298 static int ti_pipe3_probe(struct platform_device *pdev)
 299 {
 300         struct ti_pipe3 *phy;
 301         struct phy *generic_phy;
 302         struct phy_provider *phy_provider;
 303         struct resource *res;
 304         struct device_node *node = pdev->dev.of_node;
 305         struct device_node *control_node;
 306         struct platform_device *control_pdev;
 307         const struct of_device_id *match;
 308         struct clk *clk;
 309
 310         phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 311         if (!phy)
 312                 return -ENOMEM;
 313
 314         phy->dev                = &pdev->dev;
 315         spin_lock_init(&phy->lock);
 316
 317         if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 318                 match = of_match_device(of_match_ptr(ti_pipe3_id_table),
 319                                         &pdev->dev);
 320                 if (!match)
 321                         return -EINVAL;
 322
 323                 phy->dpll_map = (struct pipe3_dpll_map *)match->data;
 324                 if (!phy->dpll_map) {
 325                         dev_err(&pdev->dev, "no DPLL data\n");
 326                         return -EINVAL;
 327                 }
 328
 329                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 330                                                    "pll_ctrl");
 331                 phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 332                 if (IS_ERR(phy->pll_ctrl_base))
 333                         return PTR_ERR(phy->pll_ctrl_base);
 334
 335                 phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
 336                 if (IS_ERR(phy->sys_clk)) {
 337                         dev_err(&pdev->dev, "unable to get sysclk\n");
 338                         return -EINVAL;
 339                 }
 340         }
 341
 342         phy->refclk = devm_clk_get(phy->dev, "refclk");
 343         if (IS_ERR(phy->refclk)) {
 344                 dev_err(&pdev->dev, "unable to get refclk\n");
 345                 /* older DTBs have missing refclk in SATA PHY
 346                  * so don't bail out in case of SATA PHY.
 347                  */
 348                 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
 349                         return PTR_ERR(phy->refclk);
 350         }
 351
 352         if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 353                 phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
 354                 if (IS_ERR(phy->wkupclk)) {
 355                         dev_err(&pdev->dev, "unable to get wkupclk\n");
 356                         return PTR_ERR(phy->wkupclk);
 357                 }
 358         } else {
 359                 phy->wkupclk = ERR_PTR(-ENODEV);
 360         }
 361
 362         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 363
 364                 clk = devm_clk_get(phy->dev, "dpll_ref");
 365                 if (IS_ERR(clk)) {
 366                         dev_err(&pdev->dev, "unable to get dpll ref clk\n");
 367                         return PTR_ERR(clk);
 368                 }
 369                 clk_set_rate(clk, 1500000000);
 370
 371                 clk = devm_clk_get(phy->dev, "dpll_ref_m2");
 372                 if (IS_ERR(clk)) {
 373                         dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
 374                         return PTR_ERR(clk);
 375                 }
 376                 clk_set_rate(clk, 100000000);
 377
 378                 clk = devm_clk_get(phy->dev, "phy-div");
 379                 if (IS_ERR(clk)) {
 380                         dev_err(&pdev->dev, "unable to get phy-div clk\n");
 381                         return PTR_ERR(clk);
 382                 }
 383                 clk_set_rate(clk, 100000000);
 384
 385                 phy->div_clk = devm_clk_get(phy->dev, "div-clk");
 386                 if (IS_ERR(phy->div_clk)) {
 387                         dev_err(&pdev->dev, "unable to get div-clk\n");
 388                         return PTR_ERR(phy->div_clk);
 389                 }
 390         } else {
 391                 phy->div_clk = ERR_PTR(-ENODEV);
 392         }
 393
 394         control_node = of_parse_phandle(node, "ctrl-module", 0);
 395         if (!control_node) {
 396                 dev_err(&pdev->dev, "Failed to get control device phandle\n");
 397                 return -EINVAL;
 398         }
 399
 400         control_pdev = of_find_device_by_node(control_node);
 401         if (!control_pdev) {
 402                 dev_err(&pdev->dev, "Failed to get control device\n");
 403                 return -EINVAL;
 404         }
 405
 406         phy->control_dev = &control_pdev->dev;
 407
 408         omap_control_phy_power(phy->control_dev, 0);
 409
 410         platform_set_drvdata(pdev, phy);
 411         pm_runtime_enable(phy->dev);
 412
 413         generic_phy = devm_phy_create(phy->dev, NULL, &ops);
 414         if (IS_ERR(generic_phy))
 415                 return PTR_ERR(generic_phy);
 416
 417         phy_set_drvdata(generic_phy, phy);
 418         phy_provider = devm_of_phy_provider_register(phy->dev,
 419                         of_phy_simple_xlate);
 420         if (IS_ERR(phy_provider))
 421                 return PTR_ERR(phy_provider);
 422
 423         pm_runtime_get(&pdev->dev);
 424
 425         return 0;
 426 }
 427
 428 static int ti_pipe3_remove(struct platform_device *pdev)
 429 {
 430         if (!pm_runtime_suspended(&pdev->dev))
 431                 pm_runtime_put(&pdev->dev);
 432         pm_runtime_disable(&pdev->dev);
 433
 434         return 0;
 435 }
 436
 437 #ifdef CONFIG_PM
 438 static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
 439 {
 440         if (!IS_ERR(phy->refclk) && !phy->refclk_enabled) {
 441                 int ret;
 442
 443                 ret = clk_prepare_enable(phy->refclk);
 444                 if (ret) {
 445                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 446                         return ret;
 447                 }
 448                 phy->refclk_enabled = true;
 449         }
 450
 451         return 0;
 452 }
 453
 454 static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy)
 455 {
 456         if (!IS_ERR(phy->refclk))
 457                 clk_disable_unprepare(phy->refclk);
 458
 459         phy->refclk_enabled = false;
 460 }
 461
 462 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
 463 {
 464         int ret = 0;
 465         unsigned long flags;
 466
 467         spin_lock_irqsave(&phy->lock, flags);
 468         if (phy->enabled)
 469                 goto err1;
 470
 471         ret = ti_pipe3_enable_refclk(phy);
 472         if (ret)
 473                 goto err1;
 474
 475         if (!IS_ERR(phy->wkupclk)) {
 476                 ret = clk_prepare_enable(phy->wkupclk);
 477                 if (ret) {
 478                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 479                         goto err2;
 480                 }
 481         }
 482
 483         if (!IS_ERR(phy->div_clk)) {
 484                 ret = clk_prepare_enable(phy->div_clk);
 485                 if (ret) {
 486                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 487                         goto err3;
 488                 }
 489         }
 490
 491         phy->enabled = true;
 492         spin_unlock_irqrestore(&phy->lock, flags);
 493         return 0;
 494
 495 err3:
 496         if (!IS_ERR(phy->wkupclk))
 497                 clk_disable_unprepare(phy->wkupclk);
 498
 499 err2:
 500         if (!IS_ERR(phy->refclk))
 501                 clk_disable_unprepare(phy->refclk);
 502
 503         ti_pipe3_disable_refclk(phy);
 504 err1:
 505         spin_unlock_irqrestore(&phy->lock, flags);
 506         return ret;
 507 }
 508
 509 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 510 {
 511         unsigned long flags;
 512
 513         spin_lock_irqsave(&phy->lock, flags);
 514         if (!phy->enabled) {
 515                 spin_unlock_irqrestore(&phy->lock, flags);
 516                 return;
 517         }
 518
 519         if (!IS_ERR(phy->wkupclk))
 520                 clk_disable_unprepare(phy->wkupclk);
 521         /* Don't disable refclk for SATA PHY due to Errata i783 */
 522         if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
 523                 ti_pipe3_disable_refclk(phy);
 524         if (!IS_ERR(phy->div_clk))
 525                 clk_disable_unprepare(phy->div_clk);
 526         phy->enabled = false;
 527         spin_unlock_irqrestore(&phy->lock, flags);
 528 }
 529
 530 static int ti_pipe3_runtime_suspend(struct device *dev)
 531 {
 532         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 533
 534         ti_pipe3_disable_clocks(phy);
 535         return 0;
 536 }
 537
 538 static int ti_pipe3_runtime_resume(struct device *dev)
 539 {
 540         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 541         int ret = 0;
 542
 543         ret = ti_pipe3_enable_clocks(phy);
 544         return ret;
 545 }
 546
 547 static int ti_pipe3_suspend(struct device *dev)
 548 {
 549         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 550
 551         ti_pipe3_disable_clocks(phy);
 552         return 0;
 553 }
 554
 555 static int ti_pipe3_resume(struct device *dev)
 556 {
 557         struct ti_pipe3 *phy = dev_get_drvdata(dev);
 558         int ret;
 559
 560         ret = ti_pipe3_enable_clocks(phy);
 561         if (ret)
 562                 return ret;
 563
 564         pm_runtime_disable(dev);
 565         pm_runtime_set_active(dev);
 566         pm_runtime_enable(dev);
 567         return 0;
 568 }
 569 #endif
 570
 571 static const struct dev_pm_ops ti_pipe3_pm_ops = {
 572         SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
 573                            ti_pipe3_runtime_resume, NULL)
 574         SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume)
 575 };
 576
 577 #ifdef CONFIG_OF
 578 static const struct of_device_id ti_pipe3_id_table[] = {
 579         {
 580                 .compatible = "ti,phy-usb3",
 581                 .data = dpll_map_usb,
 582         },
 583         {
 584                 .compatible = "ti,omap-usb3",
 585                 .data = dpll_map_usb,
 586         },
 587         {
 588                 .compatible = "ti,phy-pipe3-sata",
 589                 .data = dpll_map_sata,
 590         },
 591         {
 592                 .compatible = "ti,phy-pipe3-pcie",
 593         },
 594         {}
 595 };
 596 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 597 #endif
 598
 599 static struct platform_driver ti_pipe3_driver = {
 600         .probe          = ti_pipe3_probe,
 601         .remove         = ti_pipe3_remove,
 602         .driver         = {
 603                 .name   = "ti-pipe3",
 604                 .pm     = &ti_pipe3_pm_ops,
 605                 .of_match_table = of_match_ptr(ti_pipe3_id_table),
 606         },
 607 };
 608
 609 module_platform_driver(ti_pipe3_driver);
 610
 611 MODULE_ALIAS("platform: ti_pipe3");
 612 MODULE_AUTHOR("Texas Instruments Inc.");
 613 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 614 MODULE_LICENSE("GPL v2");