2 * phy-ti-pipe3 - PIPE3 PHY driver.
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * Author: Kishon Vijay Abraham I <kishon@ti.com>
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/phy/phy.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/delay.h>
29 #include <linux/phy/omap_control_phy.h>
30 #include <linux/of_platform.h>
32 #define PLL_STATUS 0x00000004
33 #define PLL_GO 0x00000008
34 #define PLL_CONFIGURATION1 0x0000000C
35 #define PLL_CONFIGURATION2 0x00000010
36 #define PLL_CONFIGURATION3 0x00000014
37 #define PLL_CONFIGURATION4 0x00000020
39 #define PLL_REGM_MASK 0x001FFE00
40 #define PLL_REGM_SHIFT 0x9
41 #define PLL_REGM_F_MASK 0x0003FFFF
42 #define PLL_REGM_F_SHIFT 0x0
43 #define PLL_REGN_MASK 0x000001FE
44 #define PLL_REGN_SHIFT 0x1
45 #define PLL_SELFREQDCO_MASK 0x0000000E
46 #define PLL_SELFREQDCO_SHIFT 0x1
47 #define PLL_SD_MASK 0x0003FC00
48 #define PLL_SD_SHIFT 10
49 #define SET_PLL_GO 0x1
50 #define PLL_LDOPWDN BIT(15)
51 #define PLL_TICOPWDN BIT(16)
56 * This is an Empirical value that works, need to confirm the actual
57 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
58 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
60 #define PLL_IDLE_TIME 100 /* in milliseconds */
61 #define PLL_LOCK_TIME 100 /* in milliseconds */
63 struct pipe3_dpll_params
{
71 struct pipe3_dpll_map
{
73 struct pipe3_dpll_params params
;
77 void __iomem
*pll_ctrl_base
;
79 struct device
*control_dev
;
84 struct pipe3_dpll_map
*dpll_map
;
88 static struct pipe3_dpll_map dpll_map_usb
[] = {
89 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
90 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
91 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
92 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
93 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
94 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
98 static struct pipe3_dpll_map dpll_map_sata
[] = {
99 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
100 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
101 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
102 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
103 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
104 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
105 { }, /* Terminator */
108 static inline u32
ti_pipe3_readl(void __iomem
*addr
, unsigned offset
)
110 return __raw_readl(addr
+ offset
);
113 static inline void ti_pipe3_writel(void __iomem
*addr
, unsigned offset
,
116 __raw_writel(data
, addr
+ offset
);
119 static struct pipe3_dpll_params
*ti_pipe3_get_dpll_params(struct ti_pipe3
*phy
)
122 struct pipe3_dpll_map
*dpll_map
= phy
->dpll_map
;
124 rate
= clk_get_rate(phy
->sys_clk
);
126 for (; dpll_map
->rate
; dpll_map
++) {
127 if (rate
== dpll_map
->rate
)
128 return &dpll_map
->params
;
131 dev_err(phy
->dev
, "No DPLL configuration for %lu Hz SYS CLK\n", rate
);
136 static int ti_pipe3_power_off(struct phy
*x
)
138 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
140 omap_control_phy_power(phy
->control_dev
, 0);
145 static int ti_pipe3_power_on(struct phy
*x
)
147 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
149 omap_control_phy_power(phy
->control_dev
, 1);
154 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3
*phy
)
157 unsigned long timeout
;
159 timeout
= jiffies
+ msecs_to_jiffies(PLL_LOCK_TIME
);
162 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
165 } while (!time_after(jiffies
, timeout
));
167 if (!(val
& PLL_LOCK
)) {
168 dev_err(phy
->dev
, "DPLL failed to lock\n");
175 static int ti_pipe3_dpll_program(struct ti_pipe3
*phy
)
178 struct pipe3_dpll_params
*dpll_params
;
180 dpll_params
= ti_pipe3_get_dpll_params(phy
);
184 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
);
185 val
&= ~PLL_REGN_MASK
;
186 val
|= dpll_params
->n
<< PLL_REGN_SHIFT
;
187 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
, val
);
189 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
190 val
&= ~PLL_SELFREQDCO_MASK
;
191 val
|= dpll_params
->freq
<< PLL_SELFREQDCO_SHIFT
;
192 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
194 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
);
195 val
&= ~PLL_REGM_MASK
;
196 val
|= dpll_params
->m
<< PLL_REGM_SHIFT
;
197 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION1
, val
);
199 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION4
);
200 val
&= ~PLL_REGM_F_MASK
;
201 val
|= dpll_params
->mf
<< PLL_REGM_F_SHIFT
;
202 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION4
, val
);
204 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION3
);
206 val
|= dpll_params
->sd
<< PLL_SD_SHIFT
;
207 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION3
, val
);
209 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_GO
, SET_PLL_GO
);
211 return ti_pipe3_dpll_wait_lock(phy
);
214 static int ti_pipe3_init(struct phy
*x
)
216 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
220 if (of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-pcie")) {
221 omap_control_pcie_pcs(phy
->control_dev
, phy
->id
, 0xF1);
225 /* Bring it out of IDLE if it is IDLE */
226 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
227 if (val
& PLL_IDLE
) {
229 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
230 ret
= ti_pipe3_dpll_wait_lock(phy
);
233 /* Program the DPLL only if not locked */
234 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
235 if (!(val
& PLL_LOCK
))
236 if (ti_pipe3_dpll_program(phy
))
242 static int ti_pipe3_exit(struct phy
*x
)
244 struct ti_pipe3
*phy
= phy_get_drvdata(x
);
246 unsigned long timeout
;
248 /* SATA DPLL can't be powered down due to Errata i783 and PCIe
249 * does not have internal DPLL
251 if (of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-sata") ||
252 of_device_is_compatible(phy
->dev
->of_node
, "ti,phy-pipe3-pcie"))
255 /* Put DPLL in IDLE mode */
256 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
);
258 ti_pipe3_writel(phy
->pll_ctrl_base
, PLL_CONFIGURATION2
, val
);
260 /* wait for LDO and Oscillator to power down */
261 timeout
= jiffies
+ msecs_to_jiffies(PLL_IDLE_TIME
);
264 val
= ti_pipe3_readl(phy
->pll_ctrl_base
, PLL_STATUS
);
265 if ((val
& PLL_TICOPWDN
) && (val
& PLL_LDOPWDN
))
267 } while (!time_after(jiffies
, timeout
));
269 if (!(val
& PLL_TICOPWDN
) || !(val
& PLL_LDOPWDN
)) {
270 dev_err(phy
->dev
, "Failed to power down: PLL_STATUS 0x%x\n",
277 static struct phy_ops ops
= {
278 .init
= ti_pipe3_init
,
279 .exit
= ti_pipe3_exit
,
280 .power_on
= ti_pipe3_power_on
,
281 .power_off
= ti_pipe3_power_off
,
282 .owner
= THIS_MODULE
,
286 static const struct of_device_id ti_pipe3_id_table
[];
289 static int ti_pipe3_probe(struct platform_device
*pdev
)
291 struct ti_pipe3
*phy
;
292 struct phy
*generic_phy
;
293 struct phy_provider
*phy_provider
;
294 struct resource
*res
;
295 struct device_node
*node
= pdev
->dev
.of_node
;
296 struct device_node
*control_node
;
297 struct platform_device
*control_pdev
;
298 const struct of_device_id
*match
;
301 phy
= devm_kzalloc(&pdev
->dev
, sizeof(*phy
), GFP_KERNEL
);
305 phy
->dev
= &pdev
->dev
;
307 if (!of_device_is_compatible(node
, "ti,phy-pipe3-pcie")) {
308 match
= of_match_device(of_match_ptr(ti_pipe3_id_table
),
313 phy
->dpll_map
= (struct pipe3_dpll_map
*)match
->data
;
314 if (!phy
->dpll_map
) {
315 dev_err(&pdev
->dev
, "no DPLL data\n");
319 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
321 phy
->pll_ctrl_base
= devm_ioremap_resource(&pdev
->dev
, res
);
322 if (IS_ERR(phy
->pll_ctrl_base
))
323 return PTR_ERR(phy
->pll_ctrl_base
);
325 phy
->sys_clk
= devm_clk_get(phy
->dev
, "sysclk");
326 if (IS_ERR(phy
->sys_clk
)) {
327 dev_err(&pdev
->dev
, "unable to get sysclk\n");
332 if (!of_device_is_compatible(node
, "ti,phy-pipe3-sata")) {
333 phy
->wkupclk
= devm_clk_get(phy
->dev
, "wkupclk");
334 if (IS_ERR(phy
->wkupclk
)) {
335 dev_err(&pdev
->dev
, "unable to get wkupclk\n");
336 return PTR_ERR(phy
->wkupclk
);
339 phy
->refclk
= devm_clk_get(phy
->dev
, "refclk");
340 if (IS_ERR(phy
->refclk
)) {
341 dev_err(&pdev
->dev
, "unable to get refclk\n");
342 return PTR_ERR(phy
->refclk
);
345 phy
->wkupclk
= ERR_PTR(-ENODEV
);
346 phy
->refclk
= ERR_PTR(-ENODEV
);
349 if (of_device_is_compatible(node
, "ti,phy-pipe3-pcie")) {
350 if (of_property_read_u8(node
, "id", &phy
->id
) < 0)
353 clk
= devm_clk_get(phy
->dev
, "dpll_ref");
355 dev_err(&pdev
->dev
, "unable to get dpll ref clk\n");
358 clk_set_rate(clk
, 1500000000);
360 clk
= devm_clk_get(phy
->dev
, "dpll_ref_m2");
362 dev_err(&pdev
->dev
, "unable to get dpll ref m2 clk\n");
365 clk_set_rate(clk
, 100000000);
367 clk
= devm_clk_get(phy
->dev
, "phy-div");
369 dev_err(&pdev
->dev
, "unable to get phy-div clk\n");
372 clk_set_rate(clk
, 100000000);
374 phy
->div_clk
= devm_clk_get(phy
->dev
, "div-clk");
375 if (IS_ERR(phy
->div_clk
)) {
376 dev_err(&pdev
->dev
, "unable to get div-clk\n");
377 return PTR_ERR(phy
->div_clk
);
380 phy
->div_clk
= ERR_PTR(-ENODEV
);
383 control_node
= of_parse_phandle(node
, "ctrl-module", 0);
385 dev_err(&pdev
->dev
, "Failed to get control device phandle\n");
389 control_pdev
= of_find_device_by_node(control_node
);
391 dev_err(&pdev
->dev
, "Failed to get control device\n");
395 phy
->control_dev
= &control_pdev
->dev
;
397 omap_control_phy_power(phy
->control_dev
, 0);
399 platform_set_drvdata(pdev
, phy
);
400 pm_runtime_enable(phy
->dev
);
402 generic_phy
= devm_phy_create(phy
->dev
, NULL
, &ops
, NULL
);
403 if (IS_ERR(generic_phy
))
404 return PTR_ERR(generic_phy
);
406 phy_set_drvdata(generic_phy
, phy
);
407 phy_provider
= devm_of_phy_provider_register(phy
->dev
,
408 of_phy_simple_xlate
);
409 if (IS_ERR(phy_provider
))
410 return PTR_ERR(phy_provider
);
412 pm_runtime_get(&pdev
->dev
);
417 static int ti_pipe3_remove(struct platform_device
*pdev
)
419 if (!pm_runtime_suspended(&pdev
->dev
))
420 pm_runtime_put(&pdev
->dev
);
421 pm_runtime_disable(&pdev
->dev
);
426 #ifdef CONFIG_PM_RUNTIME
428 static int ti_pipe3_runtime_suspend(struct device
*dev
)
430 struct ti_pipe3
*phy
= dev_get_drvdata(dev
);
432 if (!IS_ERR(phy
->wkupclk
))
433 clk_disable_unprepare(phy
->wkupclk
);
434 if (!IS_ERR(phy
->refclk
))
435 clk_disable_unprepare(phy
->refclk
);
436 if (!IS_ERR(phy
->div_clk
))
437 clk_disable_unprepare(phy
->div_clk
);
442 static int ti_pipe3_runtime_resume(struct device
*dev
)
445 struct ti_pipe3
*phy
= dev_get_drvdata(dev
);
447 if (!IS_ERR(phy
->refclk
)) {
448 ret
= clk_prepare_enable(phy
->refclk
);
450 dev_err(phy
->dev
, "Failed to enable refclk %d\n", ret
);
455 if (!IS_ERR(phy
->wkupclk
)) {
456 ret
= clk_prepare_enable(phy
->wkupclk
);
458 dev_err(phy
->dev
, "Failed to enable wkupclk %d\n", ret
);
463 if (!IS_ERR(phy
->div_clk
)) {
464 ret
= clk_prepare_enable(phy
->div_clk
);
466 dev_err(phy
->dev
, "Failed to enable div_clk %d\n", ret
);
473 if (!IS_ERR(phy
->wkupclk
))
474 clk_disable_unprepare(phy
->wkupclk
);
477 if (!IS_ERR(phy
->refclk
))
478 clk_disable_unprepare(phy
->refclk
);
484 static const struct dev_pm_ops ti_pipe3_pm_ops
= {
485 SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend
,
486 ti_pipe3_runtime_resume
, NULL
)
489 #define DEV_PM_OPS (&ti_pipe3_pm_ops)
491 #define DEV_PM_OPS NULL
495 static const struct of_device_id ti_pipe3_id_table
[] = {
497 .compatible
= "ti,phy-usb3",
498 .data
= dpll_map_usb
,
501 .compatible
= "ti,omap-usb3",
502 .data
= dpll_map_usb
,
505 .compatible
= "ti,phy-pipe3-sata",
506 .data
= dpll_map_sata
,
509 .compatible
= "ti,phy-pipe3-pcie",
513 MODULE_DEVICE_TABLE(of
, ti_pipe3_id_table
);
516 static struct platform_driver ti_pipe3_driver
= {
517 .probe
= ti_pipe3_probe
,
518 .remove
= ti_pipe3_remove
,
522 .of_match_table
= of_match_ptr(ti_pipe3_id_table
),
526 module_platform_driver(ti_pipe3_driver
);
528 MODULE_ALIAS("platform: ti_pipe3");
529 MODULE_AUTHOR("Texas Instruments Inc.");
530 MODULE_DESCRIPTION("TI PIPE3 phy driver");
531 MODULE_LICENSE("GPL v2");