drivers/phy/qualcomm/phy-qcom-ufs.c

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include "phy-qcom-ufs-i.h"
  16
  17 #define MAX_PROP_NAME              32
  18 #define VDDA_PHY_MIN_UV            1000000
  19 #define VDDA_PHY_MAX_UV            1000000
  20 #define VDDA_PLL_MIN_UV            1800000
  21 #define VDDA_PLL_MAX_UV            1800000
  22 #define VDDP_REF_CLK_MIN_UV        1200000
  23 #define VDDP_REF_CLK_MAX_UV        1200000
  24
  25 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  26                            struct ufs_qcom_phy_calibration *tbl_A,
  27                            int tbl_size_A,
  28                            struct ufs_qcom_phy_calibration *tbl_B,
  29                            int tbl_size_B, bool is_rate_B)
  30 {
  31         int i;
  32         int ret = 0;
  33
  34         if (!tbl_A) {
  35                 dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
  36                 ret = EINVAL;
  37                 goto out;
  38         }
  39
  40         for (i = 0; i < tbl_size_A; i++)
  41                 writel_relaxed(tbl_A[i].cfg_value,
  42                                ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
  43
  44         /*
  45          * In case we would like to work in rate B, we need
  46          * to override a registers that were configured in rate A table
  47          * with registers of rate B table.
  48          * table.
  49          */
  50         if (is_rate_B) {
  51                 if (!tbl_B) {
  52                         dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
  53                                 __func__);
  54                         ret = EINVAL;
  55                         goto out;
  56                 }
  57
  58                 for (i = 0; i < tbl_size_B; i++)
  59                         writel_relaxed(tbl_B[i].cfg_value,
  60                                 ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
  61         }
  62
  63         /* flush buffered writes */
  64         mb();
  65
  66 out:
  67         return ret;
  68 }
  69 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate);
  70
  71 /*
  72  * This assumes the embedded phy structure inside generic_phy is of type
  73  * struct ufs_qcom_phy. In order to function properly it's crucial
  74  * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
  75  * as the first inside generic_phy.
  76  */
  77 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
  78 {
  79         return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
  80 }
  81 EXPORT_SYMBOL_GPL(get_ufs_qcom_phy);
  82
  83 static
  84 int ufs_qcom_phy_base_init(struct platform_device *pdev,
  85                            struct ufs_qcom_phy *phy_common)
  86 {
  87         struct device *dev = &pdev->dev;
  88         struct resource *res;
  89         int err = 0;
  90
  91         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
  92         phy_common->mmio = devm_ioremap_resource(dev, res);
  93         if (IS_ERR((void const *)phy_common->mmio)) {
  94                 err = PTR_ERR((void const *)phy_common->mmio);
  95                 phy_common->mmio = NULL;
  96                 dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
  97                         __func__, err);
  98                 return err;
  99         }
 100
 101         /* "dev_ref_clk_ctrl_mem" is optional resource */
 102         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 103                                            "dev_ref_clk_ctrl_mem");
 104         phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
 105         if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio))
 106                 phy_common->dev_ref_clk_ctrl_mmio = NULL;
 107
 108         return 0;
 109 }
 110
 111 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
 112                                 struct ufs_qcom_phy *common_cfg,
 113                                 const struct phy_ops *ufs_qcom_phy_gen_ops,
 114                                 struct ufs_qcom_phy_specific_ops *phy_spec_ops)
 115 {
 116         int err;
 117         struct device *dev = &pdev->dev;
 118         struct phy *generic_phy = NULL;
 119         struct phy_provider *phy_provider;
 120
 121         err = ufs_qcom_phy_base_init(pdev, common_cfg);
 122         if (err) {
 123                 dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
 124                 goto out;
 125         }
 126
 127         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 128         if (IS_ERR(phy_provider)) {
 129                 err = PTR_ERR(phy_provider);
 130                 dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
 131                 goto out;
 132         }
 133
 134         generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
 135         if (IS_ERR(generic_phy)) {
 136                 err =  PTR_ERR(generic_phy);
 137                 dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
 138                 generic_phy = NULL;
 139                 goto out;
 140         }
 141
 142         common_cfg->phy_spec_ops = phy_spec_ops;
 143         common_cfg->dev = dev;
 144
 145 out:
 146         return generic_phy;
 147 }
 148 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
 149
 150 static int ufs_qcom_phy_get_reset(struct ufs_qcom_phy *phy_common)
 151 {
 152         struct reset_control *reset;
 153
 154         if (phy_common->ufs_reset)
 155                 return 0;
 156
 157         reset = devm_reset_control_get_exclusive_by_index(phy_common->dev, 0);
 158         if (IS_ERR(reset))
 159                 return PTR_ERR(reset);
 160
 161         phy_common->ufs_reset = reset;
 162         return 0;
 163 }
 164
 165 static int __ufs_qcom_phy_clk_get(struct device *dev,
 166                          const char *name, struct clk **clk_out, bool err_print)
 167 {
 168         struct clk *clk;
 169         int err = 0;
 170
 171         clk = devm_clk_get(dev, name);
 172         if (IS_ERR(clk)) {
 173                 err = PTR_ERR(clk);
 174                 if (err_print)
 175                         dev_err(dev, "failed to get %s err %d", name, err);
 176         } else {
 177                 *clk_out = clk;
 178         }
 179
 180         return err;
 181 }
 182
 183 static int ufs_qcom_phy_clk_get(struct device *dev,
 184                          const char *name, struct clk **clk_out)
 185 {
 186         return __ufs_qcom_phy_clk_get(dev, name, clk_out, true);
 187 }
 188
 189 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common)
 190 {
 191         int err;
 192
 193         if (of_device_is_compatible(phy_common->dev->of_node,
 194                                 "qcom,msm8996-ufs-phy-qmp-14nm"))
 195                 goto skip_txrx_clk;
 196
 197         err = ufs_qcom_phy_clk_get(phy_common->dev, "tx_iface_clk",
 198                                    &phy_common->tx_iface_clk);
 199         if (err)
 200                 goto out;
 201
 202         err = ufs_qcom_phy_clk_get(phy_common->dev, "rx_iface_clk",
 203                                    &phy_common->rx_iface_clk);
 204         if (err)
 205                 goto out;
 206
 207 skip_txrx_clk:
 208         err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_src",
 209                                    &phy_common->ref_clk_src);
 210         if (err)
 211                 goto out;
 212
 213         /*
 214          * "ref_clk_parent" is optional hence don't abort init if it's not
 215          * found.
 216          */
 217         __ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk_parent",
 218                                    &phy_common->ref_clk_parent, false);
 219
 220         err = ufs_qcom_phy_clk_get(phy_common->dev, "ref_clk",
 221                                    &phy_common->ref_clk);
 222
 223 out:
 224         return err;
 225 }
 226 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks);
 227
 228 static int ufs_qcom_phy_init_vreg(struct device *dev,
 229                                   struct ufs_qcom_phy_vreg *vreg,
 230                                   const char *name)
 231 {
 232         int err = 0;
 233
 234         char prop_name[MAX_PROP_NAME];
 235
 236         vreg->name = name;
 237         vreg->reg = devm_regulator_get(dev, name);
 238         if (IS_ERR(vreg->reg)) {
 239                 err = PTR_ERR(vreg->reg);
 240                 dev_err(dev, "failed to get %s, %d\n", name, err);
 241                 goto out;
 242         }
 243
 244         if (dev->of_node) {
 245                 snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
 246                 err = of_property_read_u32(dev->of_node,
 247                                         prop_name, &vreg->max_uA);
 248                 if (err && err != -EINVAL) {
 249                         dev_err(dev, "%s: failed to read %s\n",
 250                                         __func__, prop_name);
 251                         goto out;
 252                 } else if (err == -EINVAL || !vreg->max_uA) {
 253                         if (regulator_count_voltages(vreg->reg) > 0) {
 254                                 dev_err(dev, "%s: %s is mandatory\n",
 255                                                 __func__, prop_name);
 256                                 goto out;
 257                         }
 258                         err = 0;
 259                 }
 260         }
 261
 262         if (!strcmp(name, "vdda-pll")) {
 263                 vreg->max_uV = VDDA_PLL_MAX_UV;
 264                 vreg->min_uV = VDDA_PLL_MIN_UV;
 265         } else if (!strcmp(name, "vdda-phy")) {
 266                 vreg->max_uV = VDDA_PHY_MAX_UV;
 267                 vreg->min_uV = VDDA_PHY_MIN_UV;
 268         } else if (!strcmp(name, "vddp-ref-clk")) {
 269                 vreg->max_uV = VDDP_REF_CLK_MAX_UV;
 270                 vreg->min_uV = VDDP_REF_CLK_MIN_UV;
 271         }
 272
 273 out:
 274         return err;
 275 }
 276
 277 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common)
 278 {
 279         int err;
 280
 281         err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_pll,
 282                 "vdda-pll");
 283         if (err)
 284                 goto out;
 285
 286         err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vdda_phy,
 287                 "vdda-phy");
 288
 289         if (err)
 290                 goto out;
 291
 292         err = ufs_qcom_phy_init_vreg(phy_common->dev, &phy_common->vddp_ref_clk,
 293                                      "vddp-ref-clk");
 294
 295 out:
 296         return err;
 297 }
 298 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators);
 299
 300 static int ufs_qcom_phy_cfg_vreg(struct device *dev,
 301                           struct ufs_qcom_phy_vreg *vreg, bool on)
 302 {
 303         int ret = 0;
 304         struct regulator *reg = vreg->reg;
 305         const char *name = vreg->name;
 306         int min_uV;
 307         int uA_load;
 308
 309         if (regulator_count_voltages(reg) > 0) {
 310                 min_uV = on ? vreg->min_uV : 0;
 311                 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
 312                 if (ret) {
 313                         dev_err(dev, "%s: %s set voltage failed, err=%d\n",
 314                                         __func__, name, ret);
 315                         goto out;
 316                 }
 317                 uA_load = on ? vreg->max_uA : 0;
 318                 ret = regulator_set_load(reg, uA_load);
 319                 if (ret >= 0) {
 320                         /*
 321                          * regulator_set_load() returns new regulator
 322                          * mode upon success.
 323                          */
 324                         ret = 0;
 325                 } else {
 326                         dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
 327                                         __func__, name, uA_load, ret);
 328                         goto out;
 329                 }
 330         }
 331 out:
 332         return ret;
 333 }
 334
 335 static int ufs_qcom_phy_enable_vreg(struct device *dev,
 336                              struct ufs_qcom_phy_vreg *vreg)
 337 {
 338         int ret = 0;
 339
 340         if (!vreg || vreg->enabled)
 341                 goto out;
 342
 343         ret = ufs_qcom_phy_cfg_vreg(dev, vreg, true);
 344         if (ret) {
 345                 dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
 346                         __func__, ret);
 347                 goto out;
 348         }
 349
 350         ret = regulator_enable(vreg->reg);
 351         if (ret) {
 352                 dev_err(dev, "%s: enable failed, err=%d\n",
 353                                 __func__, ret);
 354                 goto out;
 355         }
 356
 357         vreg->enabled = true;
 358 out:
 359         return ret;
 360 }
 361
 362 static int ufs_qcom_phy_enable_ref_clk(struct ufs_qcom_phy *phy)
 363 {
 364         int ret = 0;
 365
 366         if (phy->is_ref_clk_enabled)
 367                 goto out;
 368
 369         /*
 370          * reference clock is propagated in a daisy-chained manner from
 371          * source to phy, so ungate them at each stage.
 372          */
 373         ret = clk_prepare_enable(phy->ref_clk_src);
 374         if (ret) {
 375                 dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
 376                                 __func__, ret);
 377                 goto out;
 378         }
 379
 380         /*
 381          * "ref_clk_parent" is optional clock hence make sure that clk reference
 382          * is available before trying to enable the clock.
 383          */
 384         if (phy->ref_clk_parent) {
 385                 ret = clk_prepare_enable(phy->ref_clk_parent);
 386                 if (ret) {
 387                         dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
 388                                         __func__, ret);
 389                         goto out_disable_src;
 390                 }
 391         }
 392
 393         ret = clk_prepare_enable(phy->ref_clk);
 394         if (ret) {
 395                 dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
 396                                 __func__, ret);
 397                 goto out_disable_parent;
 398         }
 399
 400         phy->is_ref_clk_enabled = true;
 401         goto out;
 402
 403 out_disable_parent:
 404         if (phy->ref_clk_parent)
 405                 clk_disable_unprepare(phy->ref_clk_parent);
 406 out_disable_src:
 407         clk_disable_unprepare(phy->ref_clk_src);
 408 out:
 409         return ret;
 410 }
 411
 412 static int ufs_qcom_phy_disable_vreg(struct device *dev,
 413                               struct ufs_qcom_phy_vreg *vreg)
 414 {
 415         int ret = 0;
 416
 417         if (!vreg || !vreg->enabled)
 418                 goto out;
 419
 420         ret = regulator_disable(vreg->reg);
 421
 422         if (!ret) {
 423                 /* ignore errors on applying disable config */
 424                 ufs_qcom_phy_cfg_vreg(dev, vreg, false);
 425                 vreg->enabled = false;
 426         } else {
 427                 dev_err(dev, "%s: %s disable failed, err=%d\n",
 428                                 __func__, vreg->name, ret);
 429         }
 430 out:
 431         return ret;
 432 }
 433
 434 static void ufs_qcom_phy_disable_ref_clk(struct ufs_qcom_phy *phy)
 435 {
 436         if (phy->is_ref_clk_enabled) {
 437                 clk_disable_unprepare(phy->ref_clk);
 438                 /*
 439                  * "ref_clk_parent" is optional clock hence make sure that clk
 440                  * reference is available before trying to disable the clock.
 441                  */
 442                 if (phy->ref_clk_parent)
 443                         clk_disable_unprepare(phy->ref_clk_parent);
 444                 clk_disable_unprepare(phy->ref_clk_src);
 445                 phy->is_ref_clk_enabled = false;
 446         }
 447 }
 448
 449 /* Turn ON M-PHY RMMI interface clocks */
 450 static int ufs_qcom_phy_enable_iface_clk(struct ufs_qcom_phy *phy)
 451 {
 452         int ret = 0;
 453
 454         if (phy->is_iface_clk_enabled)
 455                 goto out;
 456
 457         ret = clk_prepare_enable(phy->tx_iface_clk);
 458         if (ret) {
 459                 dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
 460                                 __func__, ret);
 461                 goto out;
 462         }
 463         ret = clk_prepare_enable(phy->rx_iface_clk);
 464         if (ret) {
 465                 clk_disable_unprepare(phy->tx_iface_clk);
 466                 dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
 467                                 __func__, ret);
 468                 goto out;
 469         }
 470         phy->is_iface_clk_enabled = true;
 471
 472 out:
 473         return ret;
 474 }
 475
 476 /* Turn OFF M-PHY RMMI interface clocks */
 477 static void ufs_qcom_phy_disable_iface_clk(struct ufs_qcom_phy *phy)
 478 {
 479         if (phy->is_iface_clk_enabled) {
 480                 clk_disable_unprepare(phy->tx_iface_clk);
 481                 clk_disable_unprepare(phy->rx_iface_clk);
 482                 phy->is_iface_clk_enabled = false;
 483         }
 484 }
 485
 486 static int ufs_qcom_phy_start_serdes(struct ufs_qcom_phy *ufs_qcom_phy)
 487 {
 488         int ret = 0;
 489
 490         if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
 491                 dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
 492                         __func__);
 493                 ret = -ENOTSUPP;
 494         } else {
 495                 ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
 496         }
 497
 498         return ret;
 499 }
 500
 501 int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
 502 {
 503         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 504         int ret = 0;
 505
 506         if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
 507                 dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
 508                         __func__);
 509                 ret = -ENOTSUPP;
 510         } else {
 511                 ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
 512                                                                tx_lanes);
 513         }
 514
 515         return ret;
 516 }
 517 EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
 518
 519 void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
 520                                           u8 major, u16 minor, u16 step)
 521 {
 522         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 523
 524         ufs_qcom_phy->host_ctrl_rev_major = major;
 525         ufs_qcom_phy->host_ctrl_rev_minor = minor;
 526         ufs_qcom_phy->host_ctrl_rev_step = step;
 527 }
 528 EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
 529
 530 static int ufs_qcom_phy_is_pcs_ready(struct ufs_qcom_phy *ufs_qcom_phy)
 531 {
 532         if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
 533                 dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
 534                         __func__);
 535                 return -ENOTSUPP;
 536         }
 537
 538         return ufs_qcom_phy->phy_spec_ops->
 539                         is_physical_coding_sublayer_ready(ufs_qcom_phy);
 540 }
 541
 542 int ufs_qcom_phy_power_on(struct phy *generic_phy)
 543 {
 544         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 545         struct device *dev = phy_common->dev;
 546         bool is_rate_B = false;
 547         int err;
 548
 549         err = ufs_qcom_phy_get_reset(phy_common);
 550         if (err)
 551                 return err;
 552
 553         err = reset_control_assert(phy_common->ufs_reset);
 554         if (err)
 555                 return err;
 556
 557         if (phy_common->mode == PHY_MODE_UFS_HS_B)
 558                 is_rate_B = true;
 559
 560         err = phy_common->phy_spec_ops->calibrate(phy_common, is_rate_B);
 561         if (err)
 562                 return err;
 563
 564         err = reset_control_deassert(phy_common->ufs_reset);
 565         if (err) {
 566                 dev_err(dev, "Failed to assert UFS PHY reset");
 567                 return err;
 568         }
 569
 570         err = ufs_qcom_phy_start_serdes(phy_common);
 571         if (err)
 572                 return err;
 573
 574         err = ufs_qcom_phy_is_pcs_ready(phy_common);
 575         if (err)
 576                 return err;
 577
 578         err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_phy);
 579         if (err) {
 580                 dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
 581                         __func__, err);
 582                 goto out;
 583         }
 584
 585         phy_common->phy_spec_ops->power_control(phy_common, true);
 586
 587         /* vdda_pll also enables ref clock LDOs so enable it first */
 588         err = ufs_qcom_phy_enable_vreg(dev, &phy_common->vdda_pll);
 589         if (err) {
 590                 dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
 591                         __func__, err);
 592                 goto out_disable_phy;
 593         }
 594
 595         err = ufs_qcom_phy_enable_iface_clk(phy_common);
 596         if (err) {
 597                 dev_err(dev, "%s enable phy iface clock failed, err=%d\n",
 598                         __func__, err);
 599                 goto out_disable_pll;
 600         }
 601
 602         err = ufs_qcom_phy_enable_ref_clk(phy_common);
 603         if (err) {
 604                 dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
 605                         __func__, err);
 606                 goto out_disable_iface_clk;
 607         }
 608
 609         /* enable device PHY ref_clk pad rail */
 610         if (phy_common->vddp_ref_clk.reg) {
 611                 err = ufs_qcom_phy_enable_vreg(dev,
 612                                                &phy_common->vddp_ref_clk);
 613                 if (err) {
 614                         dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
 615                                 __func__, err);
 616                         goto out_disable_ref_clk;
 617                 }
 618         }
 619
 620         goto out;
 621
 622 out_disable_ref_clk:
 623         ufs_qcom_phy_disable_ref_clk(phy_common);
 624 out_disable_iface_clk:
 625         ufs_qcom_phy_disable_iface_clk(phy_common);
 626 out_disable_pll:
 627         ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_pll);
 628 out_disable_phy:
 629         ufs_qcom_phy_disable_vreg(dev, &phy_common->vdda_phy);
 630 out:
 631         return err;
 632 }
 633 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on);
 634
 635 int ufs_qcom_phy_power_off(struct phy *generic_phy)
 636 {
 637         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 638
 639         phy_common->phy_spec_ops->power_control(phy_common, false);
 640
 641         if (phy_common->vddp_ref_clk.reg)
 642                 ufs_qcom_phy_disable_vreg(phy_common->dev,
 643                                           &phy_common->vddp_ref_clk);
 644         ufs_qcom_phy_disable_ref_clk(phy_common);
 645         ufs_qcom_phy_disable_iface_clk(phy_common);
 646
 647         ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_pll);
 648         ufs_qcom_phy_disable_vreg(phy_common->dev, &phy_common->vdda_phy);
 649         reset_control_assert(phy_common->ufs_reset);
 650         return 0;
 651 }
 652 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off);
 653
 654 MODULE_AUTHOR("Yaniv Gardi <ygardi@codeaurora.org>");
 655 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
 656 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY");
 657 MODULE_LICENSE("GPL v2");