2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Chris Zhong <zyw@rock-chips.com>
4 * Kever Yang <kever.yang@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock
16 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has
17 * 3 working modes: USB3 only mode, DP only mode, and USB3+DP mode.
18 * At USB3 only mode, both PLL clocks need to be initialized, this allows the
19 * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB
21 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes
22 * are all used for DP.
24 * This driver gets extcon cable state and property, then decides which mode to
28 * EXTCON_USB or EXTCON_USB_HOST state is true, and
29 * EXTCON_PROP_USB_SS property is true.
30 * EXTCON_DISP_DP state is false.
33 * EXTCON_DISP_DP state is true, and
34 * EXTCON_PROP_USB_SS property is false.
35 * If EXTCON_USB_HOST state is true, it is DP + USB2 mode, since the USB2 phy
36 * is a separate phy, so this case is still DP only mode.
39 * EXTCON_USB_HOST and EXTCON_DISP_DP are both true, and
40 * EXTCON_PROP_USB_SS property is true.
42 * This Type-C PHY driver supports normal and flip orientation. The orientation
43 * is reported by the EXTCON_PROP_USB_TYPEC_POLARITY property: true is flip
44 * orientation, false is normal orientation.
48 #include <linux/clk.h>
49 #include <linux/clk-provider.h>
50 #include <linux/delay.h>
51 #include <linux/extcon.h>
53 #include <linux/iopoll.h>
54 #include <linux/kernel.h>
55 #include <linux/module.h>
56 #include <linux/mutex.h>
58 #include <linux/of_address.h>
59 #include <linux/of_platform.h>
60 #include <linux/platform_device.h>
61 #include <linux/regmap.h>
62 #include <linux/reset.h>
64 #include <linux/mfd/syscon.h>
65 #include <linux/phy/phy.h>
67 #define CMN_SSM_BANDGAP (0x21 << 2)
68 #define CMN_SSM_BIAS (0x22 << 2)
69 #define CMN_PLLSM0_PLLEN (0x29 << 2)
70 #define CMN_PLLSM0_PLLPRE (0x2a << 2)
71 #define CMN_PLLSM0_PLLVREF (0x2b << 2)
72 #define CMN_PLLSM0_PLLLOCK (0x2c << 2)
73 #define CMN_PLLSM1_PLLEN (0x31 << 2)
74 #define CMN_PLLSM1_PLLPRE (0x32 << 2)
75 #define CMN_PLLSM1_PLLVREF (0x33 << 2)
76 #define CMN_PLLSM1_PLLLOCK (0x34 << 2)
77 #define CMN_PLLSM1_USER_DEF_CTRL (0x37 << 2)
78 #define CMN_ICAL_OVRD (0xc1 << 2)
79 #define CMN_PLL0_VCOCAL_OVRD (0x83 << 2)
80 #define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
81 #define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
82 #define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2)
83 #define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2)
84 #define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2)
85 #define CMN_PLL0_INTDIV (0x94 << 2)
86 #define CMN_PLL0_FRACDIV (0x95 << 2)
87 #define CMN_PLL0_HIGH_THR (0x96 << 2)
88 #define CMN_PLL0_DSM_DIAG (0x97 << 2)
89 #define CMN_PLL0_SS_CTRL1 (0x98 << 2)
90 #define CMN_PLL0_SS_CTRL2 (0x99 << 2)
91 #define CMN_PLL1_VCOCAL_START (0xa1 << 2)
92 #define CMN_PLL1_VCOCAL_OVRD (0xa3 << 2)
93 #define CMN_PLL1_VCOCAL_INIT (0xa4 << 2)
94 #define CMN_PLL1_VCOCAL_ITER (0xa5 << 2)
95 #define CMN_PLL1_LOCK_REFCNT_START (0xb0 << 2)
96 #define CMN_PLL1_LOCK_PLLCNT_START (0xb2 << 2)
97 #define CMN_PLL1_LOCK_PLLCNT_THR (0xb3 << 2)
98 #define CMN_PLL1_INTDIV (0xb4 << 2)
99 #define CMN_PLL1_FRACDIV (0xb5 << 2)
100 #define CMN_PLL1_HIGH_THR (0xb6 << 2)
101 #define CMN_PLL1_DSM_DIAG (0xb7 << 2)
102 #define CMN_PLL1_SS_CTRL1 (0xb8 << 2)
103 #define CMN_PLL1_SS_CTRL2 (0xb9 << 2)
104 #define CMN_RXCAL_OVRD (0xd1 << 2)
105 #define CMN_TXPUCAL_CTRL (0xe0 << 2)
106 #define CMN_TXPUCAL_OVRD (0xe1 << 2)
107 #define CMN_TXPDCAL_OVRD (0xf1 << 2)
108 #define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2)
109 #define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2)
110 #define CMN_DIAG_PLL0_OVRD (0x1c2 << 2)
111 #define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2)
112 #define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2)
113 #define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2)
114 #define CMN_DIAG_PLL1_FBH_OVRD (0x1d0 << 2)
115 #define CMN_DIAG_PLL1_FBL_OVRD (0x1d1 << 2)
116 #define CMN_DIAG_PLL1_OVRD (0x1d2 << 2)
117 #define CMN_DIAG_PLL1_V2I_TUNE (0x1d5 << 2)
118 #define CMN_DIAG_PLL1_CP_TUNE (0x1d6 << 2)
119 #define CMN_DIAG_PLL1_LF_PROG (0x1d7 << 2)
120 #define CMN_DIAG_PLL1_PTATIS_TUNE1 (0x1d8 << 2)
121 #define CMN_DIAG_PLL1_PTATIS_TUNE2 (0x1d9 << 2)
122 #define CMN_DIAG_PLL1_INCLK_CTRL (0x1da << 2)
123 #define CMN_DIAG_HSCLK_SEL (0x1e0 << 2)
125 #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2)
126 #define XCVR_PSM_CAL_TMR(n) ((0x4002 | ((n) << 9)) << 2)
127 #define XCVR_PSM_A0IN_TMR(n) ((0x4003 | ((n) << 9)) << 2)
128 #define TX_TXCC_CAL_SCLR_MULT(n) ((0x4047 | ((n) << 9)) << 2)
129 #define TX_TXCC_CPOST_MULT_00(n) ((0x404c | ((n) << 9)) << 2)
130 #define TX_TXCC_CPOST_MULT_01(n) ((0x404d | ((n) << 9)) << 2)
131 #define TX_TXCC_CPOST_MULT_10(n) ((0x404e | ((n) << 9)) << 2)
132 #define TX_TXCC_CPOST_MULT_11(n) ((0x404f | ((n) << 9)) << 2)
133 #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2)
134 #define TX_TXCC_MGNFS_MULT_001(n) ((0x4051 | ((n) << 9)) << 2)
135 #define TX_TXCC_MGNFS_MULT_010(n) ((0x4052 | ((n) << 9)) << 2)
136 #define TX_TXCC_MGNFS_MULT_011(n) ((0x4053 | ((n) << 9)) << 2)
137 #define TX_TXCC_MGNFS_MULT_100(n) ((0x4054 | ((n) << 9)) << 2)
138 #define TX_TXCC_MGNFS_MULT_101(n) ((0x4055 | ((n) << 9)) << 2)
139 #define TX_TXCC_MGNFS_MULT_110(n) ((0x4056 | ((n) << 9)) << 2)
140 #define TX_TXCC_MGNFS_MULT_111(n) ((0x4057 | ((n) << 9)) << 2)
141 #define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2)
142 #define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2)
143 #define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2)
144 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2)
145 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2)
146 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2)
147 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2)
148 #define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2)
149 #define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2)
150 #define TX_RCVDET_ST_TMR(n) ((0x4123 | ((n) << 9)) << 2)
151 #define TX_DIAG_TX_DRV(n) ((0x41e1 | ((n) << 9)) << 2)
152 #define TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 << 2)
153 #define TX_ANA_CTRL_REG_1 (0x5020 << 2)
154 #define TX_ANA_CTRL_REG_2 (0x5021 << 2)
155 #define TXDA_COEFF_CALC_CTRL (0x5022 << 2)
156 #define TX_DIG_CTRL_REG_2 (0x5024 << 2)
157 #define TXDA_CYA_AUXDA_CYA (0x5025 << 2)
158 #define TX_ANA_CTRL_REG_3 (0x5026 << 2)
159 #define TX_ANA_CTRL_REG_4 (0x5027 << 2)
160 #define TX_ANA_CTRL_REG_5 (0x5029 << 2)
162 #define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2)
163 #define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2)
164 #define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2)
165 #define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2)
166 #define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2)
167 #define RX_PSC_RDY(n) ((0x8007 | ((n) << 9)) << 2)
168 #define RX_IQPI_ILL_CAL_OVRD (0x8023 << 2)
169 #define RX_EPI_ILL_CAL_OVRD (0x8033 << 2)
170 #define RX_SDCAL0_OVRD (0x8041 << 2)
171 #define RX_SDCAL1_OVRD (0x8049 << 2)
172 #define RX_SLC_INIT (0x806d << 2)
173 #define RX_SLC_RUN (0x806e << 2)
174 #define RX_CDRLF_CNFG2 (0x8081 << 2)
175 #define RX_SIGDET_HL_FILT_TMR(n) ((0x8090 | ((n) << 9)) << 2)
176 #define RX_SLC_IOP0_OVRD (0x8101 << 2)
177 #define RX_SLC_IOP1_OVRD (0x8105 << 2)
178 #define RX_SLC_QOP0_OVRD (0x8109 << 2)
179 #define RX_SLC_QOP1_OVRD (0x810d << 2)
180 #define RX_SLC_EOP0_OVRD (0x8111 << 2)
181 #define RX_SLC_EOP1_OVRD (0x8115 << 2)
182 #define RX_SLC_ION0_OVRD (0x8119 << 2)
183 #define RX_SLC_ION1_OVRD (0x811d << 2)
184 #define RX_SLC_QON0_OVRD (0x8121 << 2)
185 #define RX_SLC_QON1_OVRD (0x8125 << 2)
186 #define RX_SLC_EON0_OVRD (0x8129 << 2)
187 #define RX_SLC_EON1_OVRD (0x812d << 2)
188 #define RX_SLC_IEP0_OVRD (0x8131 << 2)
189 #define RX_SLC_IEP1_OVRD (0x8135 << 2)
190 #define RX_SLC_QEP0_OVRD (0x8139 << 2)
191 #define RX_SLC_QEP1_OVRD (0x813d << 2)
192 #define RX_SLC_EEP0_OVRD (0x8141 << 2)
193 #define RX_SLC_EEP1_OVRD (0x8145 << 2)
194 #define RX_SLC_IEN0_OVRD (0x8149 << 2)
195 #define RX_SLC_IEN1_OVRD (0x814d << 2)
196 #define RX_SLC_QEN0_OVRD (0x8151 << 2)
197 #define RX_SLC_QEN1_OVRD (0x8155 << 2)
198 #define RX_SLC_EEN0_OVRD (0x8159 << 2)
199 #define RX_SLC_EEN1_OVRD (0x815d << 2)
200 #define RX_REE_CTRL_DATA_MASK(n) ((0x81bb | ((n) << 9)) << 2)
201 #define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2)
202 #define RX_DIAG_SC2C_DELAY (0x81e1 << 2)
204 #define PMA_LANE_CFG (0xc000 << 2)
205 #define PIPE_CMN_CTRL1 (0xc001 << 2)
206 #define PIPE_CMN_CTRL2 (0xc002 << 2)
207 #define PIPE_COM_LOCK_CFG1 (0xc003 << 2)
208 #define PIPE_COM_LOCK_CFG2 (0xc004 << 2)
209 #define PIPE_RCV_DET_INH (0xc005 << 2)
210 #define DP_MODE_CTL (0xc008 << 2)
211 #define DP_CLK_CTL (0xc009 << 2)
212 #define STS (0xc00F << 2)
213 #define PHY_ISO_CMN_CTRL (0xc010 << 2)
214 #define PHY_DP_TX_CTL (0xc408 << 2)
215 #define PMA_CMN_CTRL1 (0xc800 << 2)
216 #define PHY_PMA_ISO_CMN_CTRL (0xc810 << 2)
217 #define PHY_ISOLATION_CTRL (0xc81f << 2)
218 #define PHY_PMA_ISO_XCVR_CTRL(n) ((0xcc11 | ((n) << 6)) << 2)
219 #define PHY_PMA_ISO_LINK_MODE(n) ((0xcc12 | ((n) << 6)) << 2)
220 #define PHY_PMA_ISO_PWRST_CTRL(n) ((0xcc13 | ((n) << 6)) << 2)
221 #define PHY_PMA_ISO_TX_DATA_LO(n) ((0xcc14 | ((n) << 6)) << 2)
222 #define PHY_PMA_ISO_TX_DATA_HI(n) ((0xcc15 | ((n) << 6)) << 2)
223 #define PHY_PMA_ISO_RX_DATA_LO(n) ((0xcc16 | ((n) << 6)) << 2)
224 #define PHY_PMA_ISO_RX_DATA_HI(n) ((0xcc17 | ((n) << 6)) << 2)
225 #define TX_BIST_CTRL(n) ((0x4140 | ((n) << 9)) << 2)
226 #define TX_BIST_UDDWR(n) ((0x4141 | ((n) << 9)) << 2)
229 * Selects which PLL clock will be driven on the analog high speed
230 * clock 0: PLL 0 div 1
231 * clock 1: PLL 1 div 2
233 #define CLK_PLL_CONFIG 0X30
234 #define CLK_PLL_MASK 0x33
236 #define CMN_READY BIT(0)
238 #define DP_PLL_CLOCK_ENABLE BIT(2)
239 #define DP_PLL_ENABLE BIT(0)
240 #define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
241 #define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
242 #define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
244 #define DP_MODE_A0 BIT(4)
245 #define DP_MODE_A2 BIT(6)
246 #define DP_MODE_ENTER_A0 0xc101
247 #define DP_MODE_ENTER_A2 0xc104
249 #define PHY_MODE_SET_TIMEOUT 100000
251 #define PIN_ASSIGN_C_E 0x51d9
252 #define PIN_ASSIGN_D_F 0x5100
254 #define MODE_DISCONNECT 0
255 #define MODE_UFP_USB BIT(0)
256 #define MODE_DFP_USB BIT(1)
257 #define MODE_DFP_DP BIT(2)
265 struct rockchip_usb3phy_port_cfg
{
266 struct usb3phy_reg typec_conn_dir
;
267 struct usb3phy_reg usb3tousb2_en
;
268 struct usb3phy_reg external_psm
;
269 struct usb3phy_reg pipe_status
;
272 struct rockchip_typec_phy
{
275 struct extcon_dev
*extcon
;
276 struct regmap
*grf_regs
;
277 struct clk
*clk_core
;
279 struct reset_control
*uphy_rst
;
280 struct reset_control
*pipe_rst
;
281 struct reset_control
*tcphy_rst
;
282 struct rockchip_usb3phy_port_cfg port_cfgs
;
283 /* mutex to protect access to individual PHYs */
295 struct phy_reg usb3_pll_cfg
[] = {
296 { 0xf0, CMN_PLL0_VCOCAL_INIT
},
297 { 0x18, CMN_PLL0_VCOCAL_ITER
},
298 { 0xd0, CMN_PLL0_INTDIV
},
299 { 0x4a4a, CMN_PLL0_FRACDIV
},
300 { 0x34, CMN_PLL0_HIGH_THR
},
301 { 0x1ee, CMN_PLL0_SS_CTRL1
},
302 { 0x7f03, CMN_PLL0_SS_CTRL2
},
303 { 0x20, CMN_PLL0_DSM_DIAG
},
304 { 0, CMN_DIAG_PLL0_OVRD
},
305 { 0, CMN_DIAG_PLL0_FBH_OVRD
},
306 { 0, CMN_DIAG_PLL0_FBL_OVRD
},
307 { 0x7, CMN_DIAG_PLL0_V2I_TUNE
},
308 { 0x45, CMN_DIAG_PLL0_CP_TUNE
},
309 { 0x8, CMN_DIAG_PLL0_LF_PROG
},
312 struct phy_reg dp_pll_cfg
[] = {
313 { 0xf0, CMN_PLL1_VCOCAL_INIT
},
314 { 0x18, CMN_PLL1_VCOCAL_ITER
},
315 { 0x30b9, CMN_PLL1_VCOCAL_START
},
316 { 0x21c, CMN_PLL1_INTDIV
},
317 { 0, CMN_PLL1_FRACDIV
},
318 { 0x5, CMN_PLL1_HIGH_THR
},
319 { 0x35, CMN_PLL1_SS_CTRL1
},
320 { 0x7f1e, CMN_PLL1_SS_CTRL2
},
321 { 0x20, CMN_PLL1_DSM_DIAG
},
322 { 0, CMN_PLLSM1_USER_DEF_CTRL
},
323 { 0, CMN_DIAG_PLL1_OVRD
},
324 { 0, CMN_DIAG_PLL1_FBH_OVRD
},
325 { 0, CMN_DIAG_PLL1_FBL_OVRD
},
326 { 0x6, CMN_DIAG_PLL1_V2I_TUNE
},
327 { 0x45, CMN_DIAG_PLL1_CP_TUNE
},
328 { 0x8, CMN_DIAG_PLL1_LF_PROG
},
329 { 0x100, CMN_DIAG_PLL1_PTATIS_TUNE1
},
330 { 0x7, CMN_DIAG_PLL1_PTATIS_TUNE2
},
331 { 0x4, CMN_DIAG_PLL1_INCLK_CTRL
},
334 static void tcphy_cfg_24m(struct rockchip_typec_phy
*tcphy
)
339 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
340 * cmn_psm_clk_dig_div = 2, set the clk division to 2
342 writel(0x830, tcphy
->base
+ PMA_CMN_CTRL1
);
343 for (i
= 0; i
< 4; i
++) {
345 * The following PHY configuration assumes a 24 MHz reference
348 writel(0x90, tcphy
->base
+ XCVR_DIAG_LANE_FCM_EN_MGN(i
));
349 writel(0x960, tcphy
->base
+ TX_RCVDET_EN_TMR(i
));
350 writel(0x30, tcphy
->base
+ TX_RCVDET_ST_TMR(i
));
353 rdata
= readl(tcphy
->base
+ CMN_DIAG_HSCLK_SEL
);
354 rdata
&= ~CLK_PLL_MASK
;
355 rdata
|= CLK_PLL_CONFIG
;
356 writel(rdata
, tcphy
->base
+ CMN_DIAG_HSCLK_SEL
);
359 static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy
*tcphy
)
363 /* load the configuration of PLL0 */
364 for (i
= 0; i
< ARRAY_SIZE(usb3_pll_cfg
); i
++)
365 writel(usb3_pll_cfg
[i
].value
,
366 tcphy
->base
+ usb3_pll_cfg
[i
].addr
);
369 static void tcphy_cfg_dp_pll(struct rockchip_typec_phy
*tcphy
)
373 /* set the default mode to RBR */
374 writel(DP_PLL_CLOCK_ENABLE
| DP_PLL_ENABLE
| DP_PLL_DATA_RATE_RBR
,
375 tcphy
->base
+ DP_CLK_CTL
);
377 /* load the configuration of PLL1 */
378 for (i
= 0; i
< ARRAY_SIZE(dp_pll_cfg
); i
++)
379 writel(dp_pll_cfg
[i
].value
, tcphy
->base
+ dp_pll_cfg
[i
].addr
);
382 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy
*tcphy
, u32 lane
)
384 writel(0x7799, tcphy
->base
+ TX_PSC_A0(lane
));
385 writel(0x7798, tcphy
->base
+ TX_PSC_A1(lane
));
386 writel(0x5098, tcphy
->base
+ TX_PSC_A2(lane
));
387 writel(0x5098, tcphy
->base
+ TX_PSC_A3(lane
));
388 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_000(lane
));
389 writel(0xbf, tcphy
->base
+ XCVR_DIAG_BIDI_CTRL(lane
));
392 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy
*tcphy
, u32 lane
)
394 writel(0xa6fd, tcphy
->base
+ RX_PSC_A0(lane
));
395 writel(0xa6fd, tcphy
->base
+ RX_PSC_A1(lane
));
396 writel(0xa410, tcphy
->base
+ RX_PSC_A2(lane
));
397 writel(0x2410, tcphy
->base
+ RX_PSC_A3(lane
));
398 writel(0x23ff, tcphy
->base
+ RX_PSC_CAL(lane
));
399 writel(0x13, tcphy
->base
+ RX_SIGDET_HL_FILT_TMR(lane
));
400 writel(0x03e7, tcphy
->base
+ RX_REE_CTRL_DATA_MASK(lane
));
401 writel(0x1004, tcphy
->base
+ RX_DIAG_SIGDET_TUNE(lane
));
402 writel(0x2010, tcphy
->base
+ RX_PSC_RDY(lane
));
403 writel(0xfb, tcphy
->base
+ XCVR_DIAG_BIDI_CTRL(lane
));
406 static void tcphy_dp_cfg_lane(struct rockchip_typec_phy
*tcphy
, u32 lane
)
410 writel(0xbefc, tcphy
->base
+ XCVR_PSM_RCTRL(lane
));
411 writel(0x6799, tcphy
->base
+ TX_PSC_A0(lane
));
412 writel(0x6798, tcphy
->base
+ TX_PSC_A1(lane
));
413 writel(0x98, tcphy
->base
+ TX_PSC_A2(lane
));
414 writel(0x98, tcphy
->base
+ TX_PSC_A3(lane
));
416 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_000(lane
));
417 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_001(lane
));
418 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_010(lane
));
419 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_011(lane
));
420 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_100(lane
));
421 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_101(lane
));
422 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_110(lane
));
423 writel(0, tcphy
->base
+ TX_TXCC_MGNFS_MULT_111(lane
));
424 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_10(lane
));
425 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_01(lane
));
426 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_00(lane
));
427 writel(0, tcphy
->base
+ TX_TXCC_CPOST_MULT_11(lane
));
429 writel(0x128, tcphy
->base
+ TX_TXCC_CAL_SCLR_MULT(lane
));
430 writel(0x400, tcphy
->base
+ TX_DIAG_TX_DRV(lane
));
432 rdata
= readl(tcphy
->base
+ XCVR_DIAG_PLLDRC_CTRL(lane
));
433 rdata
= (rdata
& 0x8fff) | 0x6000;
434 writel(rdata
, tcphy
->base
+ XCVR_DIAG_PLLDRC_CTRL(lane
));
437 static inline int property_enable(struct rockchip_typec_phy
*tcphy
,
438 const struct usb3phy_reg
*reg
, bool en
)
440 u32 mask
= 1 << reg
->write_enable
;
441 u32 val
= en
<< reg
->enable_bit
;
443 return regmap_write(tcphy
->grf_regs
, reg
->offset
, val
| mask
);
446 static void tcphy_dp_aux_set_flip(struct rockchip_typec_phy
*tcphy
)
448 u16 tx_ana_ctrl_reg_1
;
451 * Select the polarity of the xcvr:
452 * 1, Reverses the polarity (If TYPEC, Pulls ups aux_p and pull
454 * 0, Normal polarity (if TYPEC, pulls up aux_m and pulls down
457 tx_ana_ctrl_reg_1
= readl(tcphy
->base
+ TX_ANA_CTRL_REG_1
);
459 tx_ana_ctrl_reg_1
|= BIT(12);
461 tx_ana_ctrl_reg_1
&= ~BIT(12);
462 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
465 static void tcphy_dp_aux_calibration(struct rockchip_typec_phy
*tcphy
)
467 u16 tx_ana_ctrl_reg_1
;
468 u16 rdata
, rdata2
, val
;
470 /* disable txda_cal_latch_en for rewrite the calibration values */
471 tx_ana_ctrl_reg_1
= readl(tcphy
->base
+ TX_ANA_CTRL_REG_1
);
472 tx_ana_ctrl_reg_1
&= ~BIT(13);
473 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
476 * read a resistor calibration code from CMN_TXPUCAL_CTRL[6:0] and
477 * write it to TX_DIG_CTRL_REG_2[6:0], and delay 1ms to make sure it
480 rdata
= readl(tcphy
->base
+ TX_DIG_CTRL_REG_2
);
481 rdata
= rdata
& 0xffc0;
483 rdata2
= readl(tcphy
->base
+ CMN_TXPUCAL_CTRL
);
484 rdata2
= rdata2
& 0x3f;
486 val
= rdata
| rdata2
;
487 writel(val
, tcphy
->base
+ TX_DIG_CTRL_REG_2
);
488 usleep_range(1000, 1050);
491 * Enable signal for latch that sample and holds calibration values.
492 * Activate this signal for 1 clock cycle to sample new calibration
495 tx_ana_ctrl_reg_1
|= BIT(13);
496 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
497 usleep_range(150, 200);
499 /* set TX Voltage Level and TX Deemphasis to 0 */
500 writel(0, tcphy
->base
+ PHY_DP_TX_CTL
);
501 /* re-enable decap */
502 writel(0x100, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
503 writel(0x300, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
504 tx_ana_ctrl_reg_1
|= BIT(3);
505 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
506 tx_ana_ctrl_reg_1
|= BIT(4);
507 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
509 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_5
);
512 * Programs txda_drv_ldo_prog[15:0], Sets driver LDO
513 * voltage 16'h1001 for DP-AUX-TX and RX
515 writel(0x1001, tcphy
->base
+ TX_ANA_CTRL_REG_4
);
517 /* re-enables Bandgap reference for LDO */
518 tx_ana_ctrl_reg_1
|= BIT(7);
519 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
520 tx_ana_ctrl_reg_1
|= BIT(8);
521 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
524 * re-enables the transmitter pre-driver, driver data selection MUX,
525 * and receiver detect circuits.
527 writel(0x301, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
528 writel(0x303, tcphy
->base
+ TX_ANA_CTRL_REG_2
);
531 * Do some magic undocumented stuff, some of which appears to
532 * undo the "re-enables Bandgap reference for LDO" above.
534 tx_ana_ctrl_reg_1
|= BIT(15);
535 tx_ana_ctrl_reg_1
&= ~BIT(8);
536 tx_ana_ctrl_reg_1
&= ~BIT(7);
537 tx_ana_ctrl_reg_1
|= BIT(6);
538 tx_ana_ctrl_reg_1
|= BIT(5);
539 writel(tx_ana_ctrl_reg_1
, tcphy
->base
+ TX_ANA_CTRL_REG_1
);
541 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_3
);
542 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_4
);
543 writel(0, tcphy
->base
+ TX_ANA_CTRL_REG_5
);
546 * Controls low_power_swing_en, don't set the voltage swing of the
547 * driver to 400mv. The values below are peak to peak (differential)
550 writel(0, tcphy
->base
+ TXDA_COEFF_CALC_CTRL
);
551 writel(0, tcphy
->base
+ TXDA_CYA_AUXDA_CYA
);
553 /* Controls tx_high_z_tm_en */
554 val
= readl(tcphy
->base
+ TX_DIG_CTRL_REG_2
);
556 writel(val
, tcphy
->base
+ TX_DIG_CTRL_REG_2
);
559 static int tcphy_phy_init(struct rockchip_typec_phy
*tcphy
, u8 mode
)
561 struct rockchip_usb3phy_port_cfg
*cfg
= &tcphy
->port_cfgs
;
565 ret
= clk_prepare_enable(tcphy
->clk_core
);
567 dev_err(tcphy
->dev
, "Failed to prepare_enable core clock\n");
571 ret
= clk_prepare_enable(tcphy
->clk_ref
);
573 dev_err(tcphy
->dev
, "Failed to prepare_enable ref clock\n");
577 reset_control_deassert(tcphy
->tcphy_rst
);
579 property_enable(tcphy
, &cfg
->typec_conn_dir
, tcphy
->flip
);
580 tcphy_dp_aux_set_flip(tcphy
);
582 tcphy_cfg_24m(tcphy
);
584 if (mode
== MODE_DFP_DP
) {
585 tcphy_cfg_dp_pll(tcphy
);
586 for (i
= 0; i
< 4; i
++)
587 tcphy_dp_cfg_lane(tcphy
, i
);
589 writel(PIN_ASSIGN_C_E
, tcphy
->base
+ PMA_LANE_CFG
);
591 tcphy_cfg_usb3_pll(tcphy
);
592 tcphy_cfg_dp_pll(tcphy
);
594 tcphy_tx_usb3_cfg_lane(tcphy
, 3);
595 tcphy_rx_usb3_cfg_lane(tcphy
, 2);
596 tcphy_dp_cfg_lane(tcphy
, 0);
597 tcphy_dp_cfg_lane(tcphy
, 1);
599 tcphy_tx_usb3_cfg_lane(tcphy
, 0);
600 tcphy_rx_usb3_cfg_lane(tcphy
, 1);
601 tcphy_dp_cfg_lane(tcphy
, 2);
602 tcphy_dp_cfg_lane(tcphy
, 3);
605 writel(PIN_ASSIGN_D_F
, tcphy
->base
+ PMA_LANE_CFG
);
608 writel(DP_MODE_ENTER_A2
, tcphy
->base
+ DP_MODE_CTL
);
610 reset_control_deassert(tcphy
->uphy_rst
);
612 ret
= readx_poll_timeout(readl
, tcphy
->base
+ PMA_CMN_CTRL1
,
613 val
, val
& CMN_READY
, 10,
614 PHY_MODE_SET_TIMEOUT
);
616 dev_err(tcphy
->dev
, "wait pma ready timeout\n");
621 reset_control_deassert(tcphy
->pipe_rst
);
626 reset_control_assert(tcphy
->uphy_rst
);
627 reset_control_assert(tcphy
->tcphy_rst
);
628 clk_disable_unprepare(tcphy
->clk_ref
);
630 clk_disable_unprepare(tcphy
->clk_core
);
634 static void tcphy_phy_deinit(struct rockchip_typec_phy
*tcphy
)
636 reset_control_assert(tcphy
->tcphy_rst
);
637 reset_control_assert(tcphy
->uphy_rst
);
638 reset_control_assert(tcphy
->pipe_rst
);
639 clk_disable_unprepare(tcphy
->clk_core
);
640 clk_disable_unprepare(tcphy
->clk_ref
);
643 static int tcphy_get_mode(struct rockchip_typec_phy
*tcphy
)
645 struct extcon_dev
*edev
= tcphy
->extcon
;
646 union extcon_property_value property
;
652 ufp
= extcon_get_state(edev
, EXTCON_USB
);
653 dp
= extcon_get_state(edev
, EXTCON_DISP_DP
);
656 id
= EXTCON_USB_HOST
;
665 ret
= extcon_get_property(edev
, id
, EXTCON_PROP_USB_SS
,
668 dev_err(tcphy
->dev
, "get superspeed property failed\n");
673 mode
|= MODE_DFP_USB
;
676 ret
= extcon_get_property(edev
, id
, EXTCON_PROP_USB_TYPEC_POLARITY
,
679 dev_err(tcphy
->dev
, "get polarity property failed\n");
683 tcphy
->flip
= property
.intval
? 1 : 0;
688 static int rockchip_usb3_phy_power_on(struct phy
*phy
)
690 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
691 struct rockchip_usb3phy_port_cfg
*cfg
= &tcphy
->port_cfgs
;
692 const struct usb3phy_reg
*reg
= &cfg
->pipe_status
;
693 int timeout
, new_mode
, ret
= 0;
696 mutex_lock(&tcphy
->lock
);
698 new_mode
= tcphy_get_mode(tcphy
);
704 /* DP-only mode; fall back to USB2 */
705 if (!(new_mode
& (MODE_DFP_USB
| MODE_UFP_USB
)))
708 if (tcphy
->mode
== new_mode
)
711 if (tcphy
->mode
== MODE_DISCONNECT
) {
712 ret
= tcphy_phy_init(tcphy
, new_mode
);
717 /* wait TCPHY for pipe ready */
718 for (timeout
= 0; timeout
< 100; timeout
++) {
719 regmap_read(tcphy
->grf_regs
, reg
->offset
, &val
);
720 if (!(val
& BIT(reg
->enable_bit
))) {
721 tcphy
->mode
|= new_mode
& (MODE_DFP_USB
| MODE_UFP_USB
);
724 usleep_range(10, 20);
727 if (tcphy
->mode
== MODE_DISCONNECT
)
728 tcphy_phy_deinit(tcphy
);
733 mutex_unlock(&tcphy
->lock
);
737 static int rockchip_usb3_phy_power_off(struct phy
*phy
)
739 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
741 mutex_lock(&tcphy
->lock
);
743 if (tcphy
->mode
== MODE_DISCONNECT
)
746 tcphy
->mode
&= ~(MODE_UFP_USB
| MODE_DFP_USB
);
747 if (tcphy
->mode
== MODE_DISCONNECT
)
748 tcphy_phy_deinit(tcphy
);
751 mutex_unlock(&tcphy
->lock
);
755 static const struct phy_ops rockchip_usb3_phy_ops
= {
756 .power_on
= rockchip_usb3_phy_power_on
,
757 .power_off
= rockchip_usb3_phy_power_off
,
758 .owner
= THIS_MODULE
,
761 static int rockchip_dp_phy_power_on(struct phy
*phy
)
763 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
764 int new_mode
, ret
= 0;
767 mutex_lock(&tcphy
->lock
);
769 new_mode
= tcphy_get_mode(tcphy
);
775 if (!(new_mode
& MODE_DFP_DP
)) {
780 if (tcphy
->mode
== new_mode
)
784 * If the PHY has been power on, but the mode is not DP only mode,
785 * re-init the PHY for setting all of 4 lanes to DP.
787 if (new_mode
== MODE_DFP_DP
&& tcphy
->mode
!= MODE_DISCONNECT
) {
788 tcphy_phy_deinit(tcphy
);
789 ret
= tcphy_phy_init(tcphy
, new_mode
);
790 } else if (tcphy
->mode
== MODE_DISCONNECT
) {
791 ret
= tcphy_phy_init(tcphy
, new_mode
);
796 ret
= readx_poll_timeout(readl
, tcphy
->base
+ DP_MODE_CTL
,
797 val
, val
& DP_MODE_A2
, 1000,
798 PHY_MODE_SET_TIMEOUT
);
800 dev_err(tcphy
->dev
, "failed to wait TCPHY enter A2\n");
801 goto power_on_finish
;
804 tcphy_dp_aux_calibration(tcphy
);
806 writel(DP_MODE_ENTER_A0
, tcphy
->base
+ DP_MODE_CTL
);
808 ret
= readx_poll_timeout(readl
, tcphy
->base
+ DP_MODE_CTL
,
809 val
, val
& DP_MODE_A0
, 1000,
810 PHY_MODE_SET_TIMEOUT
);
812 writel(DP_MODE_ENTER_A2
, tcphy
->base
+ DP_MODE_CTL
);
813 dev_err(tcphy
->dev
, "failed to wait TCPHY enter A0\n");
814 goto power_on_finish
;
817 tcphy
->mode
|= MODE_DFP_DP
;
820 if (tcphy
->mode
== MODE_DISCONNECT
)
821 tcphy_phy_deinit(tcphy
);
823 mutex_unlock(&tcphy
->lock
);
827 static int rockchip_dp_phy_power_off(struct phy
*phy
)
829 struct rockchip_typec_phy
*tcphy
= phy_get_drvdata(phy
);
831 mutex_lock(&tcphy
->lock
);
833 if (tcphy
->mode
== MODE_DISCONNECT
)
836 tcphy
->mode
&= ~MODE_DFP_DP
;
838 writel(DP_MODE_ENTER_A2
, tcphy
->base
+ DP_MODE_CTL
);
840 if (tcphy
->mode
== MODE_DISCONNECT
)
841 tcphy_phy_deinit(tcphy
);
844 mutex_unlock(&tcphy
->lock
);
848 static const struct phy_ops rockchip_dp_phy_ops
= {
849 .power_on
= rockchip_dp_phy_power_on
,
850 .power_off
= rockchip_dp_phy_power_off
,
851 .owner
= THIS_MODULE
,
854 static int tcphy_get_param(struct device
*dev
,
855 struct usb3phy_reg
*reg
,
861 ret
= of_property_read_u32_array(dev
->of_node
, name
, buffer
, 3);
863 dev_err(dev
, "Can not parse %s\n", name
);
867 reg
->offset
= buffer
[0];
868 reg
->enable_bit
= buffer
[1];
869 reg
->write_enable
= buffer
[2];
873 static int tcphy_parse_dt(struct rockchip_typec_phy
*tcphy
,
876 struct rockchip_usb3phy_port_cfg
*cfg
= &tcphy
->port_cfgs
;
879 ret
= tcphy_get_param(dev
, &cfg
->typec_conn_dir
,
880 "rockchip,typec-conn-dir");
884 ret
= tcphy_get_param(dev
, &cfg
->usb3tousb2_en
,
885 "rockchip,usb3tousb2-en");
889 ret
= tcphy_get_param(dev
, &cfg
->external_psm
,
890 "rockchip,external-psm");
894 ret
= tcphy_get_param(dev
, &cfg
->pipe_status
,
895 "rockchip,pipe-status");
899 tcphy
->grf_regs
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
901 if (IS_ERR(tcphy
->grf_regs
)) {
902 dev_err(dev
, "could not find grf dt node\n");
903 return PTR_ERR(tcphy
->grf_regs
);
906 tcphy
->clk_core
= devm_clk_get(dev
, "tcpdcore");
907 if (IS_ERR(tcphy
->clk_core
)) {
908 dev_err(dev
, "could not get uphy core clock\n");
909 return PTR_ERR(tcphy
->clk_core
);
912 tcphy
->clk_ref
= devm_clk_get(dev
, "tcpdphy-ref");
913 if (IS_ERR(tcphy
->clk_ref
)) {
914 dev_err(dev
, "could not get uphy ref clock\n");
915 return PTR_ERR(tcphy
->clk_ref
);
918 tcphy
->uphy_rst
= devm_reset_control_get(dev
, "uphy");
919 if (IS_ERR(tcphy
->uphy_rst
)) {
920 dev_err(dev
, "no uphy_rst reset control found\n");
921 return PTR_ERR(tcphy
->uphy_rst
);
924 tcphy
->pipe_rst
= devm_reset_control_get(dev
, "uphy-pipe");
925 if (IS_ERR(tcphy
->pipe_rst
)) {
926 dev_err(dev
, "no pipe_rst reset control found\n");
927 return PTR_ERR(tcphy
->pipe_rst
);
930 tcphy
->tcphy_rst
= devm_reset_control_get(dev
, "uphy-tcphy");
931 if (IS_ERR(tcphy
->tcphy_rst
)) {
932 dev_err(dev
, "no tcphy_rst reset control found\n");
933 return PTR_ERR(tcphy
->tcphy_rst
);
939 static void typec_phy_pre_init(struct rockchip_typec_phy
*tcphy
)
941 struct rockchip_usb3phy_port_cfg
*cfg
= &tcphy
->port_cfgs
;
943 reset_control_assert(tcphy
->tcphy_rst
);
944 reset_control_assert(tcphy
->uphy_rst
);
945 reset_control_assert(tcphy
->pipe_rst
);
947 /* select external psm clock */
948 property_enable(tcphy
, &cfg
->external_psm
, 1);
949 property_enable(tcphy
, &cfg
->usb3tousb2_en
, 0);
951 tcphy
->mode
= MODE_DISCONNECT
;
954 static int rockchip_typec_phy_probe(struct platform_device
*pdev
)
956 struct device
*dev
= &pdev
->dev
;
957 struct device_node
*np
= dev
->of_node
;
958 struct device_node
*child_np
;
959 struct rockchip_typec_phy
*tcphy
;
960 struct phy_provider
*phy_provider
;
961 struct resource
*res
;
964 tcphy
= devm_kzalloc(dev
, sizeof(*tcphy
), GFP_KERNEL
);
968 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
969 tcphy
->base
= devm_ioremap_resource(dev
, res
);
970 if (IS_ERR(tcphy
->base
))
971 return PTR_ERR(tcphy
->base
);
973 ret
= tcphy_parse_dt(tcphy
, dev
);
978 platform_set_drvdata(pdev
, tcphy
);
979 mutex_init(&tcphy
->lock
);
981 typec_phy_pre_init(tcphy
);
983 tcphy
->extcon
= extcon_get_edev_by_phandle(dev
, 0);
984 if (IS_ERR(tcphy
->extcon
)) {
985 if (PTR_ERR(tcphy
->extcon
) != -EPROBE_DEFER
)
986 dev_err(dev
, "Invalid or missing extcon\n");
987 return PTR_ERR(tcphy
->extcon
);
990 pm_runtime_enable(dev
);
992 for_each_available_child_of_node(np
, child_np
) {
995 if (!of_node_cmp(child_np
->name
, "dp-port"))
996 phy
= devm_phy_create(dev
, child_np
,
997 &rockchip_dp_phy_ops
);
998 else if (!of_node_cmp(child_np
->name
, "usb3-port"))
999 phy
= devm_phy_create(dev
, child_np
,
1000 &rockchip_usb3_phy_ops
);
1005 dev_err(dev
, "failed to create phy: %s\n",
1007 return PTR_ERR(phy
);
1010 phy_set_drvdata(phy
, tcphy
);
1013 phy_provider
= devm_of_phy_provider_register(dev
, of_phy_simple_xlate
);
1014 if (IS_ERR(phy_provider
)) {
1015 dev_err(dev
, "Failed to register phy provider\n");
1016 return PTR_ERR(phy_provider
);
1022 static int rockchip_typec_phy_remove(struct platform_device
*pdev
)
1024 pm_runtime_disable(&pdev
->dev
);
1029 static const struct of_device_id rockchip_typec_phy_dt_ids
[] = {
1030 { .compatible
= "rockchip,rk3399-typec-phy" },
1034 MODULE_DEVICE_TABLE(of
, rockchip_typec_phy_dt_ids
);
1036 static struct platform_driver rockchip_typec_phy_driver
= {
1037 .probe
= rockchip_typec_phy_probe
,
1038 .remove
= rockchip_typec_phy_remove
,
1040 .name
= "rockchip-typec-phy",
1041 .of_match_table
= rockchip_typec_phy_dt_ids
,
1045 module_platform_driver(rockchip_typec_phy_driver
);
1047 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1048 MODULE_AUTHOR("Kever Yang <kever.yang@rock-chips.com>");
1049 MODULE_DESCRIPTION("Rockchip USB TYPE-C PHY driver");
1050 MODULE_LICENSE("GPL v2");