drivers/phy/st/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STMicroelectronics STM32 USB PHY Controller driver
   4  *
   5  * Copyright (C) 2018 STMicroelectronics
   6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
   7  */
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/reset.h>
  18
  19 #define STM32_USBPHYC_PLL       0x0
  20 #define STM32_USBPHYC_MISC      0x8
  21 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
  22 #define STM32_USBPHYC_VERSION   0x3F4
  23
  24 /* STM32_USBPHYC_PLL bit fields */
  25 #define PLLNDIV                 GENMASK(6, 0)
  26 #define PLLFRACIN               GENMASK(25, 10)
  27 #define PLLEN                   BIT(26)
  28 #define PLLSTRB                 BIT(27)
  29 #define PLLSTRBYP               BIT(28)
  30 #define PLLFRACCTL              BIT(29)
  31 #define PLLDITHEN0              BIT(30)
  32 #define PLLDITHEN1              BIT(31)
  33
  34 /* STM32_USBPHYC_MISC bit fields */
  35 #define SWITHOST                BIT(0)
  36
  37 /* STM32_USBPHYC_MONITOR bit fields */
  38 #define STM32_USBPHYC_MON_OUT   GENMASK(3, 0)
  39 #define STM32_USBPHYC_MON_SEL   GENMASK(8, 4)
  40 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
  41 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
  42
  43 /* STM32_USBPHYC_VERSION bit fields */
  44 #define MINREV                  GENMASK(3, 0)
  45 #define MAJREV                  GENMASK(7, 4)
  46
  47 #define PLL_FVCO_MHZ            2880
  48 #define PLL_INFF_MIN_RATE_HZ    19200000
  49 #define PLL_INFF_MAX_RATE_HZ    38400000
  50 #define HZ_PER_MHZ              1000000L
  51
  52 struct pll_params {
  53         u8 ndiv;
  54         u16 frac;
  55 };
  56
  57 struct stm32_usbphyc_phy {
  58         struct phy *phy;
  59         struct stm32_usbphyc *usbphyc;
  60         u32 index;
  61         bool active;
  62 };
  63
  64 struct stm32_usbphyc {
  65         struct device *dev;
  66         void __iomem *base;
  67         struct clk *clk;
  68         struct reset_control *rst;
  69         struct stm32_usbphyc_phy **phys;
  70         int nphys;
  71         struct regulator *vdda1v1;
  72         struct regulator *vdda1v8;
  73         atomic_t n_pll_cons;
  74         struct clk_hw clk48_hw;
  75         int switch_setup;
  76 };
  77
  78 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
  79 {
  80         writel_relaxed(readl_relaxed(reg) | bits, reg);
  81 }
  82
  83 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
  84 {
  85         writel_relaxed(readl_relaxed(reg) & ~bits, reg);
  86 }
  87
  88 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
  89 {
  90         int ret;
  91
  92         ret = regulator_enable(usbphyc->vdda1v1);
  93         if (ret)
  94                 return ret;
  95
  96         ret = regulator_enable(usbphyc->vdda1v8);
  97         if (ret)
  98                 goto vdda1v1_disable;
  99
 100         return 0;
 101
 102 vdda1v1_disable:
 103         regulator_disable(usbphyc->vdda1v1);
 104
 105         return ret;
 106 }
 107
 108 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
 109 {
 110         int ret;
 111
 112         ret = regulator_disable(usbphyc->vdda1v8);
 113         if (ret)
 114                 return ret;
 115
 116         ret = regulator_disable(usbphyc->vdda1v1);
 117         if (ret)
 118                 return ret;
 119
 120         return 0;
 121 }
 122
 123 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
 124                                          struct pll_params *pll_params)
 125 {
 126         unsigned long long fvco, ndiv, frac;
 127
 128         /*    _
 129          *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
 130          *   | FVCO = 2880MHz
 131          *  <
 132          *   | NDIV = integer part of input bits to set the LDF
 133          *   |_FRACT = fractional part of input bits to set the LDF
 134          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
 135          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
 136          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
 137          */
 138         fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
 139
 140         ndiv = fvco;
 141         do_div(ndiv, (clk_rate * 2));
 142         pll_params->ndiv = (u8)ndiv;
 143
 144         frac = fvco * (1 << 16);
 145         do_div(frac, (clk_rate * 2));
 146         frac = frac - (ndiv * (1 << 16));
 147         pll_params->frac = (u16)frac;
 148 }
 149
 150 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
 151 {
 152         struct pll_params pll_params;
 153         u32 clk_rate = clk_get_rate(usbphyc->clk);
 154         u32 ndiv, frac;
 155         u32 usbphyc_pll;
 156
 157         if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
 158             (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
 159                 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
 160                         clk_rate);
 161                 return -EINVAL;
 162         }
 163
 164         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 165         ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
 166         frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
 167
 168         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
 169
 170         if (pll_params.frac)
 171                 usbphyc_pll |= PLLFRACCTL | frac;
 172
 173         writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 174
 175         dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
 176                 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
 177                 FIELD_GET(PLLFRACIN, usbphyc_pll));
 178
 179         return 0;
 180 }
 181
 182 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 183 {
 184         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 185         u32 pllen;
 186
 187         stm32_usbphyc_clr_bits(pll_reg, PLLEN);
 188
 189         /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
 190         if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
 191                 dev_err(usbphyc->dev, "PLL not reset\n");
 192
 193         return stm32_usbphyc_regulators_disable(usbphyc);
 194 }
 195
 196 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
 197 {
 198         /* Check if a phy port is still active or clk48 in use */
 199         if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
 200                 return 0;
 201
 202         return __stm32_usbphyc_pll_disable(usbphyc);
 203 }
 204
 205 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
 206 {
 207         void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
 208         bool pllen = readl_relaxed(pll_reg) & PLLEN;
 209         int ret;
 210
 211         /*
 212          * Check if a phy port or clk48 prepare has configured the pll
 213          * and ensure the PLL is enabled
 214          */
 215         if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
 216                 return 0;
 217
 218         if (pllen) {
 219                 /*
 220                  * PLL shouldn't be enabled without known consumer,
 221                  * disable it and reinit n_pll_cons
 222                  */
 223                 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
 224
 225                 ret = __stm32_usbphyc_pll_disable(usbphyc);
 226                 if (ret)
 227                         return ret;
 228         }
 229
 230         ret = stm32_usbphyc_regulators_enable(usbphyc);
 231         if (ret)
 232                 goto dec_n_pll_cons;
 233
 234         ret = stm32_usbphyc_pll_init(usbphyc);
 235         if (ret)
 236                 goto reg_disable;
 237
 238         stm32_usbphyc_set_bits(pll_reg, PLLEN);
 239
 240         return 0;
 241
 242 reg_disable:
 243         stm32_usbphyc_regulators_disable(usbphyc);
 244
 245 dec_n_pll_cons:
 246         atomic_dec(&usbphyc->n_pll_cons);
 247
 248         return ret;
 249 }
 250
 251 static int stm32_usbphyc_phy_init(struct phy *phy)
 252 {
 253         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 254         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 255         u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
 256         u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
 257                                 STM32_USBPHYC_MON_SEL_LOCKP);
 258         u32 monout;
 259         int ret;
 260
 261         ret = stm32_usbphyc_pll_enable(usbphyc);
 262         if (ret)
 263                 return ret;
 264
 265         /* Check that PLL Lock input to PHY is High */
 266         writel_relaxed(monsel, usbphyc->base + reg_mon);
 267         ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
 268                                          (monout & STM32_USBPHYC_MON_OUT_LOCKP),
 269                                          100, 1000);
 270         if (ret) {
 271                 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
 272                         (u32)(monout & STM32_USBPHYC_MON_OUT));
 273                 goto pll_disable;
 274         }
 275
 276         usbphyc_phy->active = true;
 277
 278         return 0;
 279
 280 pll_disable:
 281         return stm32_usbphyc_pll_disable(usbphyc);
 282 }
 283
 284 static int stm32_usbphyc_phy_exit(struct phy *phy)
 285 {
 286         struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
 287         struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
 288
 289         usbphyc_phy->active = false;
 290
 291         return stm32_usbphyc_pll_disable(usbphyc);
 292 }
 293
 294 static const struct phy_ops stm32_usbphyc_phy_ops = {
 295         .init = stm32_usbphyc_phy_init,
 296         .exit = stm32_usbphyc_phy_exit,
 297         .owner = THIS_MODULE,
 298 };
 299
 300 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
 301 {
 302         struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
 303
 304         return stm32_usbphyc_pll_enable(usbphyc);
 305 }
 306
 307 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
 308 {
 309         struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
 310
 311         stm32_usbphyc_pll_disable(usbphyc);
 312 }
 313
 314 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 315 {
 316         return 48000000;
 317 }
 318
 319 static const struct clk_ops usbphyc_clk48_ops = {
 320         .prepare = stm32_usbphyc_clk48_prepare,
 321         .unprepare = stm32_usbphyc_clk48_unprepare,
 322         .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
 323 };
 324
 325 static void stm32_usbphyc_clk48_unregister(void *data)
 326 {
 327         struct stm32_usbphyc *usbphyc = data;
 328
 329         of_clk_del_provider(usbphyc->dev->of_node);
 330         clk_hw_unregister(&usbphyc->clk48_hw);
 331 }
 332
 333 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
 334 {
 335         struct device_node *node = usbphyc->dev->of_node;
 336         struct clk_init_data init = { };
 337         int ret = 0;
 338
 339         init.name = "ck_usbo_48m";
 340         init.ops = &usbphyc_clk48_ops;
 341
 342         usbphyc->clk48_hw.init = &init;
 343
 344         ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
 345         if (ret)
 346                 return ret;
 347
 348         ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
 349         if (ret)
 350                 clk_hw_unregister(&usbphyc->clk48_hw);
 351
 352         return ret;
 353 }
 354
 355 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
 356                                        u32 utmi_switch)
 357 {
 358         if (!utmi_switch)
 359                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
 360                                        SWITHOST);
 361         else
 362                 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
 363                                        SWITHOST);
 364         usbphyc->switch_setup = utmi_switch;
 365 }
 366
 367 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
 368                                           struct of_phandle_args *args)
 369 {
 370         struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
 371         struct stm32_usbphyc_phy *usbphyc_phy = NULL;
 372         struct device_node *phynode = args->np;
 373         int port = 0;
 374
 375         for (port = 0; port < usbphyc->nphys; port++) {
 376                 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
 377                         usbphyc_phy = usbphyc->phys[port];
 378                         break;
 379                 }
 380         }
 381         if (!usbphyc_phy) {
 382                 dev_err(dev, "failed to find phy\n");
 383                 return ERR_PTR(-EINVAL);
 384         }
 385
 386         if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
 387             ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
 388                 dev_err(dev, "invalid number of cells for phy port%d\n",
 389                         usbphyc_phy->index);
 390                 return ERR_PTR(-EINVAL);
 391         }
 392
 393         /* Configure the UTMI switch for PHY port#2 */
 394         if (usbphyc_phy->index == 1) {
 395                 if (usbphyc->switch_setup < 0) {
 396                         stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
 397                 } else {
 398                         if (args->args[0] != usbphyc->switch_setup) {
 399                                 dev_err(dev, "phy port1 already used\n");
 400                                 return ERR_PTR(-EBUSY);
 401                         }
 402                 }
 403         }
 404
 405         return usbphyc_phy->phy;
 406 }
 407
 408 static int stm32_usbphyc_probe(struct platform_device *pdev)
 409 {
 410         struct stm32_usbphyc *usbphyc;
 411         struct device *dev = &pdev->dev;
 412         struct device_node *child, *np = dev->of_node;
 413         struct phy_provider *phy_provider;
 414         u32 pllen, version;
 415         int ret, port = 0;
 416
 417         usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
 418         if (!usbphyc)
 419                 return -ENOMEM;
 420         usbphyc->dev = dev;
 421         dev_set_drvdata(dev, usbphyc);
 422
 423         usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
 424         if (IS_ERR(usbphyc->base))
 425                 return PTR_ERR(usbphyc->base);
 426
 427         usbphyc->clk = devm_clk_get(dev, NULL);
 428         if (IS_ERR(usbphyc->clk))
 429                 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
 430
 431         ret = clk_prepare_enable(usbphyc->clk);
 432         if (ret) {
 433                 dev_err(dev, "clk enable failed: %d\n", ret);
 434                 return ret;
 435         }
 436
 437         usbphyc->rst = devm_reset_control_get(dev, NULL);
 438         if (!IS_ERR(usbphyc->rst)) {
 439                 reset_control_assert(usbphyc->rst);
 440                 udelay(2);
 441                 reset_control_deassert(usbphyc->rst);
 442         } else {
 443                 ret = PTR_ERR(usbphyc->rst);
 444                 if (ret == -EPROBE_DEFER)
 445                         goto clk_disable;
 446
 447                 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 448         }
 449
 450         /*
 451          * Wait for minimum width of powerdown pulse (ENABLE = Low):
 452          * we have to ensure the PLL is disabled before phys initialization.
 453          */
 454         if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
 455                                        pllen, !(pllen & PLLEN), 5, 50)) {
 456                 dev_warn(usbphyc->dev, "PLL not reset\n");
 457                 ret = -EPROBE_DEFER;
 458                 goto clk_disable;
 459         }
 460
 461         usbphyc->switch_setup = -EINVAL;
 462         usbphyc->nphys = of_get_child_count(np);
 463         usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
 464                                      sizeof(*usbphyc->phys), GFP_KERNEL);
 465         if (!usbphyc->phys) {
 466                 ret = -ENOMEM;
 467                 goto clk_disable;
 468         }
 469
 470         usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
 471         if (IS_ERR(usbphyc->vdda1v1)) {
 472                 ret = PTR_ERR(usbphyc->vdda1v1);
 473                 if (ret != -EPROBE_DEFER)
 474                         dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
 475                 goto clk_disable;
 476         }
 477
 478         usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
 479         if (IS_ERR(usbphyc->vdda1v8)) {
 480                 ret = PTR_ERR(usbphyc->vdda1v8);
 481                 if (ret != -EPROBE_DEFER)
 482                         dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
 483                 goto clk_disable;
 484         }
 485
 486         for_each_child_of_node(np, child) {
 487                 struct stm32_usbphyc_phy *usbphyc_phy;
 488                 struct phy *phy;
 489                 u32 index;
 490
 491                 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
 492                 if (IS_ERR(phy)) {
 493                         ret = PTR_ERR(phy);
 494                         if (ret != -EPROBE_DEFER)
 495                                 dev_err(dev, "failed to create phy%d: %d\n",
 496                                         port, ret);
 497                         goto put_child;
 498                 }
 499
 500                 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
 501                                            GFP_KERNEL);
 502                 if (!usbphyc_phy) {
 503                         ret = -ENOMEM;
 504                         goto put_child;
 505                 }
 506
 507                 ret = of_property_read_u32(child, "reg", &index);
 508                 if (ret || index > usbphyc->nphys) {
 509                         dev_err(&phy->dev, "invalid reg property: %d\n", ret);
 510                         goto put_child;
 511                 }
 512
 513                 usbphyc->phys[port] = usbphyc_phy;
 514                 phy_set_bus_width(phy, 8);
 515                 phy_set_drvdata(phy, usbphyc_phy);
 516
 517                 usbphyc->phys[port]->phy = phy;
 518                 usbphyc->phys[port]->usbphyc = usbphyc;
 519                 usbphyc->phys[port]->index = index;
 520                 usbphyc->phys[port]->active = false;
 521
 522                 port++;
 523         }
 524
 525         phy_provider = devm_of_phy_provider_register(dev,
 526                                                      stm32_usbphyc_of_xlate);
 527         if (IS_ERR(phy_provider)) {
 528                 ret = PTR_ERR(phy_provider);
 529                 dev_err(dev, "failed to register phy provider: %d\n", ret);
 530                 goto clk_disable;
 531         }
 532
 533         ret = stm32_usbphyc_clk48_register(usbphyc);
 534         if (ret) {
 535                 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
 536                 goto clk_disable;
 537         }
 538
 539         version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
 540         dev_info(dev, "registered rev:%lu.%lu\n",
 541                  FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
 542
 543         return 0;
 544
 545 put_child:
 546         of_node_put(child);
 547 clk_disable:
 548         clk_disable_unprepare(usbphyc->clk);
 549
 550         return ret;
 551 }
 552
 553 static int stm32_usbphyc_remove(struct platform_device *pdev)
 554 {
 555         struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
 556         int port;
 557
 558         /* Ensure PHYs are not active, to allow PLL disabling */
 559         for (port = 0; port < usbphyc->nphys; port++)
 560                 if (usbphyc->phys[port]->active)
 561                         stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
 562
 563         stm32_usbphyc_clk48_unregister(usbphyc);
 564
 565         clk_disable_unprepare(usbphyc->clk);
 566
 567         return 0;
 568 }
 569
 570 static const struct of_device_id stm32_usbphyc_of_match[] = {
 571         { .compatible = "st,stm32mp1-usbphyc", },
 572         { },
 573 };
 574 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
 575
 576 static struct platform_driver stm32_usbphyc_driver = {
 577         .probe = stm32_usbphyc_probe,
 578         .remove = stm32_usbphyc_remove,
 579         .driver = {
 580                 .of_match_table = stm32_usbphyc_of_match,
 581                 .name = "stm32-usbphyc",
 582         }
 583 };
 584 module_platform_driver(stm32_usbphyc_driver);
 585
 586 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
 587 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 588 MODULE_LICENSE("GPL v2");