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[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm281xx.c
1 /*
2 * Copyright (C) 2013-2017 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/init.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include "../core.h"
26 #include "../pinctrl-utils.h"
27
28 /* BCM281XX Pin Control Registers Definitions */
29
30 /* Function Select bits are the same for all pin control registers */
31 #define BCM281XX_PIN_REG_F_SEL_MASK 0x0700
32 #define BCM281XX_PIN_REG_F_SEL_SHIFT 8
33
34 /* Standard pin register */
35 #define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007
36 #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0
37 #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
38 #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3
39 #define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010
40 #define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4
41 #define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020
42 #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5
43 #define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040
44 #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6
45 #define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080
46 #define BCM281XX_STD_PIN_REG_HYST_SHIFT 7
47
48 /* I2C pin register */
49 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
50 #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2
51 #define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008
52 #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3
53 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
54 #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
55
56 /* HDMI pin register */
57 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
58 #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
59 #define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010
60 #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4
61
62 /**
63 * bcm281xx_pin_type - types of pin register
64 */
65 enum bcm281xx_pin_type {
66 BCM281XX_PIN_TYPE_UNKNOWN = 0,
67 BCM281XX_PIN_TYPE_STD,
68 BCM281XX_PIN_TYPE_I2C,
69 BCM281XX_PIN_TYPE_HDMI,
70 };
71
72 static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
73 static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
74 static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
75
76 /**
77 * bcm281xx_pin_function- define pin function
78 */
79 struct bcm281xx_pin_function {
80 const char *name;
81 const char * const *groups;
82 const unsigned ngroups;
83 };
84
85 /**
86 * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
87 * @reg_base - base of pinctrl registers
88 */
89 struct bcm281xx_pinctrl_data {
90 void __iomem *reg_base;
91
92 /* List of all pins */
93 const struct pinctrl_pin_desc *pins;
94 const unsigned npins;
95
96 const struct bcm281xx_pin_function *functions;
97 const unsigned nfunctions;
98
99 struct regmap *regmap;
100 };
101
102 /*
103 * Pin number definition. The order here must be the same as defined in the
104 * PADCTRLREG block in the RDB.
105 */
106 #define BCM281XX_PIN_ADCSYNC 0
107 #define BCM281XX_PIN_BAT_RM 1
108 #define BCM281XX_PIN_BSC1_SCL 2
109 #define BCM281XX_PIN_BSC1_SDA 3
110 #define BCM281XX_PIN_BSC2_SCL 4
111 #define BCM281XX_PIN_BSC2_SDA 5
112 #define BCM281XX_PIN_CLASSGPWR 6
113 #define BCM281XX_PIN_CLK_CX8 7
114 #define BCM281XX_PIN_CLKOUT_0 8
115 #define BCM281XX_PIN_CLKOUT_1 9
116 #define BCM281XX_PIN_CLKOUT_2 10
117 #define BCM281XX_PIN_CLKOUT_3 11
118 #define BCM281XX_PIN_CLKREQ_IN_0 12
119 #define BCM281XX_PIN_CLKREQ_IN_1 13
120 #define BCM281XX_PIN_CWS_SYS_REQ1 14
121 #define BCM281XX_PIN_CWS_SYS_REQ2 15
122 #define BCM281XX_PIN_CWS_SYS_REQ3 16
123 #define BCM281XX_PIN_DIGMIC1_CLK 17
124 #define BCM281XX_PIN_DIGMIC1_DQ 18
125 #define BCM281XX_PIN_DIGMIC2_CLK 19
126 #define BCM281XX_PIN_DIGMIC2_DQ 20
127 #define BCM281XX_PIN_GPEN13 21
128 #define BCM281XX_PIN_GPEN14 22
129 #define BCM281XX_PIN_GPEN15 23
130 #define BCM281XX_PIN_GPIO00 24
131 #define BCM281XX_PIN_GPIO01 25
132 #define BCM281XX_PIN_GPIO02 26
133 #define BCM281XX_PIN_GPIO03 27
134 #define BCM281XX_PIN_GPIO04 28
135 #define BCM281XX_PIN_GPIO05 29
136 #define BCM281XX_PIN_GPIO06 30
137 #define BCM281XX_PIN_GPIO07 31
138 #define BCM281XX_PIN_GPIO08 32
139 #define BCM281XX_PIN_GPIO09 33
140 #define BCM281XX_PIN_GPIO10 34
141 #define BCM281XX_PIN_GPIO11 35
142 #define BCM281XX_PIN_GPIO12 36
143 #define BCM281XX_PIN_GPIO13 37
144 #define BCM281XX_PIN_GPIO14 38
145 #define BCM281XX_PIN_GPS_PABLANK 39
146 #define BCM281XX_PIN_GPS_TMARK 40
147 #define BCM281XX_PIN_HDMI_SCL 41
148 #define BCM281XX_PIN_HDMI_SDA 42
149 #define BCM281XX_PIN_IC_DM 43
150 #define BCM281XX_PIN_IC_DP 44
151 #define BCM281XX_PIN_KP_COL_IP_0 45
152 #define BCM281XX_PIN_KP_COL_IP_1 46
153 #define BCM281XX_PIN_KP_COL_IP_2 47
154 #define BCM281XX_PIN_KP_COL_IP_3 48
155 #define BCM281XX_PIN_KP_ROW_OP_0 49
156 #define BCM281XX_PIN_KP_ROW_OP_1 50
157 #define BCM281XX_PIN_KP_ROW_OP_2 51
158 #define BCM281XX_PIN_KP_ROW_OP_3 52
159 #define BCM281XX_PIN_LCD_B_0 53
160 #define BCM281XX_PIN_LCD_B_1 54
161 #define BCM281XX_PIN_LCD_B_2 55
162 #define BCM281XX_PIN_LCD_B_3 56
163 #define BCM281XX_PIN_LCD_B_4 57
164 #define BCM281XX_PIN_LCD_B_5 58
165 #define BCM281XX_PIN_LCD_B_6 59
166 #define BCM281XX_PIN_LCD_B_7 60
167 #define BCM281XX_PIN_LCD_G_0 61
168 #define BCM281XX_PIN_LCD_G_1 62
169 #define BCM281XX_PIN_LCD_G_2 63
170 #define BCM281XX_PIN_LCD_G_3 64
171 #define BCM281XX_PIN_LCD_G_4 65
172 #define BCM281XX_PIN_LCD_G_5 66
173 #define BCM281XX_PIN_LCD_G_6 67
174 #define BCM281XX_PIN_LCD_G_7 68
175 #define BCM281XX_PIN_LCD_HSYNC 69
176 #define BCM281XX_PIN_LCD_OE 70
177 #define BCM281XX_PIN_LCD_PCLK 71
178 #define BCM281XX_PIN_LCD_R_0 72
179 #define BCM281XX_PIN_LCD_R_1 73
180 #define BCM281XX_PIN_LCD_R_2 74
181 #define BCM281XX_PIN_LCD_R_3 75
182 #define BCM281XX_PIN_LCD_R_4 76
183 #define BCM281XX_PIN_LCD_R_5 77
184 #define BCM281XX_PIN_LCD_R_6 78
185 #define BCM281XX_PIN_LCD_R_7 79
186 #define BCM281XX_PIN_LCD_VSYNC 80
187 #define BCM281XX_PIN_MDMGPIO0 81
188 #define BCM281XX_PIN_MDMGPIO1 82
189 #define BCM281XX_PIN_MDMGPIO2 83
190 #define BCM281XX_PIN_MDMGPIO3 84
191 #define BCM281XX_PIN_MDMGPIO4 85
192 #define BCM281XX_PIN_MDMGPIO5 86
193 #define BCM281XX_PIN_MDMGPIO6 87
194 #define BCM281XX_PIN_MDMGPIO7 88
195 #define BCM281XX_PIN_MDMGPIO8 89
196 #define BCM281XX_PIN_MPHI_DATA_0 90
197 #define BCM281XX_PIN_MPHI_DATA_1 91
198 #define BCM281XX_PIN_MPHI_DATA_2 92
199 #define BCM281XX_PIN_MPHI_DATA_3 93
200 #define BCM281XX_PIN_MPHI_DATA_4 94
201 #define BCM281XX_PIN_MPHI_DATA_5 95
202 #define BCM281XX_PIN_MPHI_DATA_6 96
203 #define BCM281XX_PIN_MPHI_DATA_7 97
204 #define BCM281XX_PIN_MPHI_DATA_8 98
205 #define BCM281XX_PIN_MPHI_DATA_9 99
206 #define BCM281XX_PIN_MPHI_DATA_10 100
207 #define BCM281XX_PIN_MPHI_DATA_11 101
208 #define BCM281XX_PIN_MPHI_DATA_12 102
209 #define BCM281XX_PIN_MPHI_DATA_13 103
210 #define BCM281XX_PIN_MPHI_DATA_14 104
211 #define BCM281XX_PIN_MPHI_DATA_15 105
212 #define BCM281XX_PIN_MPHI_HA0 106
213 #define BCM281XX_PIN_MPHI_HAT0 107
214 #define BCM281XX_PIN_MPHI_HAT1 108
215 #define BCM281XX_PIN_MPHI_HCE0_N 109
216 #define BCM281XX_PIN_MPHI_HCE1_N 110
217 #define BCM281XX_PIN_MPHI_HRD_N 111
218 #define BCM281XX_PIN_MPHI_HWR_N 112
219 #define BCM281XX_PIN_MPHI_RUN0 113
220 #define BCM281XX_PIN_MPHI_RUN1 114
221 #define BCM281XX_PIN_MTX_SCAN_CLK 115
222 #define BCM281XX_PIN_MTX_SCAN_DATA 116
223 #define BCM281XX_PIN_NAND_AD_0 117
224 #define BCM281XX_PIN_NAND_AD_1 118
225 #define BCM281XX_PIN_NAND_AD_2 119
226 #define BCM281XX_PIN_NAND_AD_3 120
227 #define BCM281XX_PIN_NAND_AD_4 121
228 #define BCM281XX_PIN_NAND_AD_5 122
229 #define BCM281XX_PIN_NAND_AD_6 123
230 #define BCM281XX_PIN_NAND_AD_7 124
231 #define BCM281XX_PIN_NAND_ALE 125
232 #define BCM281XX_PIN_NAND_CEN_0 126
233 #define BCM281XX_PIN_NAND_CEN_1 127
234 #define BCM281XX_PIN_NAND_CLE 128
235 #define BCM281XX_PIN_NAND_OEN 129
236 #define BCM281XX_PIN_NAND_RDY_0 130
237 #define BCM281XX_PIN_NAND_RDY_1 131
238 #define BCM281XX_PIN_NAND_WEN 132
239 #define BCM281XX_PIN_NAND_WP 133
240 #define BCM281XX_PIN_PC1 134
241 #define BCM281XX_PIN_PC2 135
242 #define BCM281XX_PIN_PMU_INT 136
243 #define BCM281XX_PIN_PMU_SCL 137
244 #define BCM281XX_PIN_PMU_SDA 138
245 #define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139
246 #define BCM281XX_PIN_RGMII_0_RX_CTL 140
247 #define BCM281XX_PIN_RGMII_0_RXC 141
248 #define BCM281XX_PIN_RGMII_0_RXD_0 142
249 #define BCM281XX_PIN_RGMII_0_RXD_1 143
250 #define BCM281XX_PIN_RGMII_0_RXD_2 144
251 #define BCM281XX_PIN_RGMII_0_RXD_3 145
252 #define BCM281XX_PIN_RGMII_0_TX_CTL 146
253 #define BCM281XX_PIN_RGMII_0_TXC 147
254 #define BCM281XX_PIN_RGMII_0_TXD_0 148
255 #define BCM281XX_PIN_RGMII_0_TXD_1 149
256 #define BCM281XX_PIN_RGMII_0_TXD_2 150
257 #define BCM281XX_PIN_RGMII_0_TXD_3 151
258 #define BCM281XX_PIN_RGMII_1_RX_CTL 152
259 #define BCM281XX_PIN_RGMII_1_RXC 153
260 #define BCM281XX_PIN_RGMII_1_RXD_0 154
261 #define BCM281XX_PIN_RGMII_1_RXD_1 155
262 #define BCM281XX_PIN_RGMII_1_RXD_2 156
263 #define BCM281XX_PIN_RGMII_1_RXD_3 157
264 #define BCM281XX_PIN_RGMII_1_TX_CTL 158
265 #define BCM281XX_PIN_RGMII_1_TXC 159
266 #define BCM281XX_PIN_RGMII_1_TXD_0 160
267 #define BCM281XX_PIN_RGMII_1_TXD_1 161
268 #define BCM281XX_PIN_RGMII_1_TXD_2 162
269 #define BCM281XX_PIN_RGMII_1_TXD_3 163
270 #define BCM281XX_PIN_RGMII_GPIO_0 164
271 #define BCM281XX_PIN_RGMII_GPIO_1 165
272 #define BCM281XX_PIN_RGMII_GPIO_2 166
273 #define BCM281XX_PIN_RGMII_GPIO_3 167
274 #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168
275 #define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169
276 #define BCM281XX_PIN_RXDATA3G0 170
277 #define BCM281XX_PIN_RXDATA3G1 171
278 #define BCM281XX_PIN_RXDATA3G2 172
279 #define BCM281XX_PIN_SDIO1_CLK 173
280 #define BCM281XX_PIN_SDIO1_CMD 174
281 #define BCM281XX_PIN_SDIO1_DATA_0 175
282 #define BCM281XX_PIN_SDIO1_DATA_1 176
283 #define BCM281XX_PIN_SDIO1_DATA_2 177
284 #define BCM281XX_PIN_SDIO1_DATA_3 178
285 #define BCM281XX_PIN_SDIO4_CLK 179
286 #define BCM281XX_PIN_SDIO4_CMD 180
287 #define BCM281XX_PIN_SDIO4_DATA_0 181
288 #define BCM281XX_PIN_SDIO4_DATA_1 182
289 #define BCM281XX_PIN_SDIO4_DATA_2 183
290 #define BCM281XX_PIN_SDIO4_DATA_3 184
291 #define BCM281XX_PIN_SIM_CLK 185
292 #define BCM281XX_PIN_SIM_DATA 186
293 #define BCM281XX_PIN_SIM_DET 187
294 #define BCM281XX_PIN_SIM_RESETN 188
295 #define BCM281XX_PIN_SIM2_CLK 189
296 #define BCM281XX_PIN_SIM2_DATA 190
297 #define BCM281XX_PIN_SIM2_DET 191
298 #define BCM281XX_PIN_SIM2_RESETN 192
299 #define BCM281XX_PIN_SRI_C 193
300 #define BCM281XX_PIN_SRI_D 194
301 #define BCM281XX_PIN_SRI_E 195
302 #define BCM281XX_PIN_SSP_EXTCLK 196
303 #define BCM281XX_PIN_SSP0_CLK 197
304 #define BCM281XX_PIN_SSP0_FS 198
305 #define BCM281XX_PIN_SSP0_RXD 199
306 #define BCM281XX_PIN_SSP0_TXD 200
307 #define BCM281XX_PIN_SSP2_CLK 201
308 #define BCM281XX_PIN_SSP2_FS_0 202
309 #define BCM281XX_PIN_SSP2_FS_1 203
310 #define BCM281XX_PIN_SSP2_FS_2 204
311 #define BCM281XX_PIN_SSP2_FS_3 205
312 #define BCM281XX_PIN_SSP2_RXD_0 206
313 #define BCM281XX_PIN_SSP2_RXD_1 207
314 #define BCM281XX_PIN_SSP2_TXD_0 208
315 #define BCM281XX_PIN_SSP2_TXD_1 209
316 #define BCM281XX_PIN_SSP3_CLK 210
317 #define BCM281XX_PIN_SSP3_FS 211
318 #define BCM281XX_PIN_SSP3_RXD 212
319 #define BCM281XX_PIN_SSP3_TXD 213
320 #define BCM281XX_PIN_SSP4_CLK 214
321 #define BCM281XX_PIN_SSP4_FS 215
322 #define BCM281XX_PIN_SSP4_RXD 216
323 #define BCM281XX_PIN_SSP4_TXD 217
324 #define BCM281XX_PIN_SSP5_CLK 218
325 #define BCM281XX_PIN_SSP5_FS 219
326 #define BCM281XX_PIN_SSP5_RXD 220
327 #define BCM281XX_PIN_SSP5_TXD 221
328 #define BCM281XX_PIN_SSP6_CLK 222
329 #define BCM281XX_PIN_SSP6_FS 223
330 #define BCM281XX_PIN_SSP6_RXD 224
331 #define BCM281XX_PIN_SSP6_TXD 225
332 #define BCM281XX_PIN_STAT_1 226
333 #define BCM281XX_PIN_STAT_2 227
334 #define BCM281XX_PIN_SYSCLKEN 228
335 #define BCM281XX_PIN_TRACECLK 229
336 #define BCM281XX_PIN_TRACEDT00 230
337 #define BCM281XX_PIN_TRACEDT01 231
338 #define BCM281XX_PIN_TRACEDT02 232
339 #define BCM281XX_PIN_TRACEDT03 233
340 #define BCM281XX_PIN_TRACEDT04 234
341 #define BCM281XX_PIN_TRACEDT05 235
342 #define BCM281XX_PIN_TRACEDT06 236
343 #define BCM281XX_PIN_TRACEDT07 237
344 #define BCM281XX_PIN_TRACEDT08 238
345 #define BCM281XX_PIN_TRACEDT09 239
346 #define BCM281XX_PIN_TRACEDT10 240
347 #define BCM281XX_PIN_TRACEDT11 241
348 #define BCM281XX_PIN_TRACEDT12 242
349 #define BCM281XX_PIN_TRACEDT13 243
350 #define BCM281XX_PIN_TRACEDT14 244
351 #define BCM281XX_PIN_TRACEDT15 245
352 #define BCM281XX_PIN_TXDATA3G0 246
353 #define BCM281XX_PIN_TXPWRIND 247
354 #define BCM281XX_PIN_UARTB1_UCTS 248
355 #define BCM281XX_PIN_UARTB1_URTS 249
356 #define BCM281XX_PIN_UARTB1_URXD 250
357 #define BCM281XX_PIN_UARTB1_UTXD 251
358 #define BCM281XX_PIN_UARTB2_URXD 252
359 #define BCM281XX_PIN_UARTB2_UTXD 253
360 #define BCM281XX_PIN_UARTB3_UCTS 254
361 #define BCM281XX_PIN_UARTB3_URTS 255
362 #define BCM281XX_PIN_UARTB3_URXD 256
363 #define BCM281XX_PIN_UARTB3_UTXD 257
364 #define BCM281XX_PIN_UARTB4_UCTS 258
365 #define BCM281XX_PIN_UARTB4_URTS 259
366 #define BCM281XX_PIN_UARTB4_URXD 260
367 #define BCM281XX_PIN_UARTB4_UTXD 261
368 #define BCM281XX_PIN_VC_CAM1_SCL 262
369 #define BCM281XX_PIN_VC_CAM1_SDA 263
370 #define BCM281XX_PIN_VC_CAM2_SCL 264
371 #define BCM281XX_PIN_VC_CAM2_SDA 265
372 #define BCM281XX_PIN_VC_CAM3_SCL 266
373 #define BCM281XX_PIN_VC_CAM3_SDA 267
374
375 #define BCM281XX_PIN_DESC(a, b, c) \
376 { .number = a, .name = b, .drv_data = &c##_pin }
377
378 /*
379 * Pin description definition. The order here must be the same as defined in
380 * the PADCTRLREG block in the RDB, since the pin number is used as an index
381 * into this array.
382 */
383 static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
384 BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
385 BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
386 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
387 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
388 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
389 BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
390 BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
391 BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
392 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
393 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
394 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
395 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
396 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
397 BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
398 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
399 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
400 BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
401 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
402 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
403 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
404 BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
405 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
406 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
407 BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
408 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
409 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
410 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
411 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
412 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
413 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
414 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
415 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
416 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
417 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
418 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
419 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
420 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
421 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
422 BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
423 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
424 BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
425 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
426 BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
427 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
428 BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
429 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
430 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
431 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
432 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
433 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
434 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
435 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
436 BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
437 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
438 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
439 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
440 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
441 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
442 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
443 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
444 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
445 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
446 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
447 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
448 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
449 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
450 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
451 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
452 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
453 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
454 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
455 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
456 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
457 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
458 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
459 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
460 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
461 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
462 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
463 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
464 BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
465 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
466 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
467 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
468 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
469 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
470 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
471 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
472 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
473 BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
474 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
475 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
476 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
477 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
478 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
479 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
480 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
481 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
482 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
483 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
484 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
485 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
486 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
487 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
488 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
489 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
490 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
491 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
492 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
493 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
494 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
495 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
496 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
497 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
498 BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
499 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
500 BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
501 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
502 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
503 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
504 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
505 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
506 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
507 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
508 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
509 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
510 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
511 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
512 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
513 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
514 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
515 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
516 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
517 BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
518 BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
519 BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
520 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
521 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
522 BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
523 BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
524 std),
525 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
526 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
527 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
528 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
529 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
530 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
531 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
532 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
533 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
534 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
535 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
536 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
537 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
538 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
539 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
540 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
541 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
542 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
543 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
544 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
545 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
546 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
547 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
548 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
549 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
550 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
551 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
552 BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
553 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
554 "rtxdata2g_txdata3g1", std),
555 BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
556 std),
557 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
558 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
559 BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
560 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
561 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
562 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
563 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
564 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
565 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
566 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
567 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
568 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
569 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
570 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
571 BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
572 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
573 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
574 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
575 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
576 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
577 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
578 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
579 BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
580 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
581 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
582 BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
583 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
584 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
585 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
586 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
587 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
588 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
589 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
590 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
591 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
592 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
593 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
594 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
595 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
596 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
597 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
598 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
599 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
600 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
601 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
602 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
603 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
604 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
605 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
606 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
607 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
608 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
609 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
610 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
611 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
612 BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
613 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
614 BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
615 BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
616 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
617 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
618 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
619 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
620 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
621 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
622 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
623 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
624 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
625 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
626 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
627 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
628 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
629 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
630 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
631 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
632 BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
633 BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
634 BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
635 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
636 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
637 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
638 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
639 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
640 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
641 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
642 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
643 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
644 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
645 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
646 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
647 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
648 BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
649 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
650 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
651 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
652 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
653 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
654 BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
655 };
656
657 static const char * const bcm281xx_alt_groups[] = {
658 "adcsync",
659 "bat_rm",
660 "bsc1_scl",
661 "bsc1_sda",
662 "bsc2_scl",
663 "bsc2_sda",
664 "classgpwr",
665 "clk_cx8",
666 "clkout_0",
667 "clkout_1",
668 "clkout_2",
669 "clkout_3",
670 "clkreq_in_0",
671 "clkreq_in_1",
672 "cws_sys_req1",
673 "cws_sys_req2",
674 "cws_sys_req3",
675 "digmic1_clk",
676 "digmic1_dq",
677 "digmic2_clk",
678 "digmic2_dq",
679 "gpen13",
680 "gpen14",
681 "gpen15",
682 "gpio00",
683 "gpio01",
684 "gpio02",
685 "gpio03",
686 "gpio04",
687 "gpio05",
688 "gpio06",
689 "gpio07",
690 "gpio08",
691 "gpio09",
692 "gpio10",
693 "gpio11",
694 "gpio12",
695 "gpio13",
696 "gpio14",
697 "gps_pablank",
698 "gps_tmark",
699 "hdmi_scl",
700 "hdmi_sda",
701 "ic_dm",
702 "ic_dp",
703 "kp_col_ip_0",
704 "kp_col_ip_1",
705 "kp_col_ip_2",
706 "kp_col_ip_3",
707 "kp_row_op_0",
708 "kp_row_op_1",
709 "kp_row_op_2",
710 "kp_row_op_3",
711 "lcd_b_0",
712 "lcd_b_1",
713 "lcd_b_2",
714 "lcd_b_3",
715 "lcd_b_4",
716 "lcd_b_5",
717 "lcd_b_6",
718 "lcd_b_7",
719 "lcd_g_0",
720 "lcd_g_1",
721 "lcd_g_2",
722 "lcd_g_3",
723 "lcd_g_4",
724 "lcd_g_5",
725 "lcd_g_6",
726 "lcd_g_7",
727 "lcd_hsync",
728 "lcd_oe",
729 "lcd_pclk",
730 "lcd_r_0",
731 "lcd_r_1",
732 "lcd_r_2",
733 "lcd_r_3",
734 "lcd_r_4",
735 "lcd_r_5",
736 "lcd_r_6",
737 "lcd_r_7",
738 "lcd_vsync",
739 "mdmgpio0",
740 "mdmgpio1",
741 "mdmgpio2",
742 "mdmgpio3",
743 "mdmgpio4",
744 "mdmgpio5",
745 "mdmgpio6",
746 "mdmgpio7",
747 "mdmgpio8",
748 "mphi_data_0",
749 "mphi_data_1",
750 "mphi_data_2",
751 "mphi_data_3",
752 "mphi_data_4",
753 "mphi_data_5",
754 "mphi_data_6",
755 "mphi_data_7",
756 "mphi_data_8",
757 "mphi_data_9",
758 "mphi_data_10",
759 "mphi_data_11",
760 "mphi_data_12",
761 "mphi_data_13",
762 "mphi_data_14",
763 "mphi_data_15",
764 "mphi_ha0",
765 "mphi_hat0",
766 "mphi_hat1",
767 "mphi_hce0_n",
768 "mphi_hce1_n",
769 "mphi_hrd_n",
770 "mphi_hwr_n",
771 "mphi_run0",
772 "mphi_run1",
773 "mtx_scan_clk",
774 "mtx_scan_data",
775 "nand_ad_0",
776 "nand_ad_1",
777 "nand_ad_2",
778 "nand_ad_3",
779 "nand_ad_4",
780 "nand_ad_5",
781 "nand_ad_6",
782 "nand_ad_7",
783 "nand_ale",
784 "nand_cen_0",
785 "nand_cen_1",
786 "nand_cle",
787 "nand_oen",
788 "nand_rdy_0",
789 "nand_rdy_1",
790 "nand_wen",
791 "nand_wp",
792 "pc1",
793 "pc2",
794 "pmu_int",
795 "pmu_scl",
796 "pmu_sda",
797 "rfst2g_mtsloten3g",
798 "rgmii_0_rx_ctl",
799 "rgmii_0_rxc",
800 "rgmii_0_rxd_0",
801 "rgmii_0_rxd_1",
802 "rgmii_0_rxd_2",
803 "rgmii_0_rxd_3",
804 "rgmii_0_tx_ctl",
805 "rgmii_0_txc",
806 "rgmii_0_txd_0",
807 "rgmii_0_txd_1",
808 "rgmii_0_txd_2",
809 "rgmii_0_txd_3",
810 "rgmii_1_rx_ctl",
811 "rgmii_1_rxc",
812 "rgmii_1_rxd_0",
813 "rgmii_1_rxd_1",
814 "rgmii_1_rxd_2",
815 "rgmii_1_rxd_3",
816 "rgmii_1_tx_ctl",
817 "rgmii_1_txc",
818 "rgmii_1_txd_0",
819 "rgmii_1_txd_1",
820 "rgmii_1_txd_2",
821 "rgmii_1_txd_3",
822 "rgmii_gpio_0",
823 "rgmii_gpio_1",
824 "rgmii_gpio_2",
825 "rgmii_gpio_3",
826 "rtxdata2g_txdata3g1",
827 "rtxen2g_txdata3g2",
828 "rxdata3g0",
829 "rxdata3g1",
830 "rxdata3g2",
831 "sdio1_clk",
832 "sdio1_cmd",
833 "sdio1_data_0",
834 "sdio1_data_1",
835 "sdio1_data_2",
836 "sdio1_data_3",
837 "sdio4_clk",
838 "sdio4_cmd",
839 "sdio4_data_0",
840 "sdio4_data_1",
841 "sdio4_data_2",
842 "sdio4_data_3",
843 "sim_clk",
844 "sim_data",
845 "sim_det",
846 "sim_resetn",
847 "sim2_clk",
848 "sim2_data",
849 "sim2_det",
850 "sim2_resetn",
851 "sri_c",
852 "sri_d",
853 "sri_e",
854 "ssp_extclk",
855 "ssp0_clk",
856 "ssp0_fs",
857 "ssp0_rxd",
858 "ssp0_txd",
859 "ssp2_clk",
860 "ssp2_fs_0",
861 "ssp2_fs_1",
862 "ssp2_fs_2",
863 "ssp2_fs_3",
864 "ssp2_rxd_0",
865 "ssp2_rxd_1",
866 "ssp2_txd_0",
867 "ssp2_txd_1",
868 "ssp3_clk",
869 "ssp3_fs",
870 "ssp3_rxd",
871 "ssp3_txd",
872 "ssp4_clk",
873 "ssp4_fs",
874 "ssp4_rxd",
875 "ssp4_txd",
876 "ssp5_clk",
877 "ssp5_fs",
878 "ssp5_rxd",
879 "ssp5_txd",
880 "ssp6_clk",
881 "ssp6_fs",
882 "ssp6_rxd",
883 "ssp6_txd",
884 "stat_1",
885 "stat_2",
886 "sysclken",
887 "traceclk",
888 "tracedt00",
889 "tracedt01",
890 "tracedt02",
891 "tracedt03",
892 "tracedt04",
893 "tracedt05",
894 "tracedt06",
895 "tracedt07",
896 "tracedt08",
897 "tracedt09",
898 "tracedt10",
899 "tracedt11",
900 "tracedt12",
901 "tracedt13",
902 "tracedt14",
903 "tracedt15",
904 "txdata3g0",
905 "txpwrind",
906 "uartb1_ucts",
907 "uartb1_urts",
908 "uartb1_urxd",
909 "uartb1_utxd",
910 "uartb2_urxd",
911 "uartb2_utxd",
912 "uartb3_ucts",
913 "uartb3_urts",
914 "uartb3_urxd",
915 "uartb3_utxd",
916 "uartb4_ucts",
917 "uartb4_urts",
918 "uartb4_urxd",
919 "uartb4_utxd",
920 "vc_cam1_scl",
921 "vc_cam1_sda",
922 "vc_cam2_scl",
923 "vc_cam2_sda",
924 "vc_cam3_scl",
925 "vc_cam3_sda",
926 };
927
928 /* Every pin can implement all ALT1-ALT4 functions */
929 #define BCM281XX_PIN_FUNCTION(fcn_name) \
930 { \
931 .name = #fcn_name, \
932 .groups = bcm281xx_alt_groups, \
933 .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \
934 }
935
936 static const struct bcm281xx_pin_function bcm281xx_functions[] = {
937 BCM281XX_PIN_FUNCTION(alt1),
938 BCM281XX_PIN_FUNCTION(alt2),
939 BCM281XX_PIN_FUNCTION(alt3),
940 BCM281XX_PIN_FUNCTION(alt4),
941 };
942
943 static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
944 .pins = bcm281xx_pinctrl_pins,
945 .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
946 .functions = bcm281xx_functions,
947 .nfunctions = ARRAY_SIZE(bcm281xx_functions),
948 };
949
950 static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
951 unsigned pin)
952 {
953 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
954
955 if (pin >= pdata->npins)
956 return BCM281XX_PIN_TYPE_UNKNOWN;
957
958 return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
959 }
960
961 #define BCM281XX_PIN_SHIFT(type, param) \
962 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
963
964 #define BCM281XX_PIN_MASK(type, param) \
965 (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
966
967 /*
968 * This helper function is used to build up the value and mask used to write to
969 * a pin register, but does not actually write to the register.
970 */
971 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
972 u32 param_val, u32 param_shift,
973 u32 param_mask)
974 {
975 *reg_val &= ~param_mask;
976 *reg_val |= (param_val << param_shift) & param_mask;
977 *reg_mask |= param_mask;
978 }
979
980 static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
981 .reg_bits = 32,
982 .reg_stride = 4,
983 .val_bits = 32,
984 .max_register = BCM281XX_PIN_VC_CAM3_SDA,
985 };
986
987 static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
988 {
989 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
990
991 return pdata->npins;
992 }
993
994 static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
995 unsigned group)
996 {
997 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
998
999 return pdata->pins[group].name;
1000 }
1001
1002 static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1003 unsigned group,
1004 const unsigned **pins,
1005 unsigned *num_pins)
1006 {
1007 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1008
1009 *pins = &pdata->pins[group].number;
1010 *num_pins = 1;
1011
1012 return 0;
1013 }
1014
1015 static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1016 struct seq_file *s,
1017 unsigned offset)
1018 {
1019 seq_printf(s, " %s", dev_name(pctldev->dev));
1020 }
1021
1022 static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
1023 .get_groups_count = bcm281xx_pinctrl_get_groups_count,
1024 .get_group_name = bcm281xx_pinctrl_get_group_name,
1025 .get_group_pins = bcm281xx_pinctrl_get_group_pins,
1026 .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
1027 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1028 .dt_free_map = pinctrl_utils_free_map,
1029 };
1030
1031 static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1032 {
1033 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1034
1035 return pdata->nfunctions;
1036 }
1037
1038 static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1039 unsigned function)
1040 {
1041 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1042
1043 return pdata->functions[function].name;
1044 }
1045
1046 static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1047 unsigned function,
1048 const char * const **groups,
1049 unsigned * const num_groups)
1050 {
1051 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1052
1053 *groups = pdata->functions[function].groups;
1054 *num_groups = pdata->functions[function].ngroups;
1055
1056 return 0;
1057 }
1058
1059 static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1060 unsigned function,
1061 unsigned group)
1062 {
1063 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1064 const struct bcm281xx_pin_function *f = &pdata->functions[function];
1065 u32 offset = 4 * pdata->pins[group].number;
1066 int rc = 0;
1067
1068 dev_dbg(pctldev->dev,
1069 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1070 __func__, f->name, function, pdata->pins[group].name,
1071 pdata->pins[group].number, offset);
1072
1073 rc = regmap_update_bits(pdata->regmap, offset,
1074 BCM281XX_PIN_REG_F_SEL_MASK,
1075 function << BCM281XX_PIN_REG_F_SEL_SHIFT);
1076 if (rc)
1077 dev_err(pctldev->dev,
1078 "Error updating register for pin %s (%d).\n",
1079 pdata->pins[group].name, pdata->pins[group].number);
1080
1081 return rc;
1082 }
1083
1084 static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1085 .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1086 .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1087 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1088 .set_mux = bcm281xx_pinmux_set,
1089 };
1090
1091 static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1092 unsigned pin,
1093 unsigned long *config)
1094 {
1095 return -ENOTSUPP;
1096 }
1097
1098
1099 /* Goes through the configs and update register val/mask */
1100 static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
1101 unsigned pin,
1102 unsigned long *configs,
1103 unsigned num_configs,
1104 u32 *val,
1105 u32 *mask)
1106 {
1107 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1108 int i;
1109 enum pin_config_param param;
1110 u32 arg;
1111
1112 for (i = 0; i < num_configs; i++) {
1113 param = pinconf_to_config_param(configs[i]);
1114 arg = pinconf_to_config_argument(configs[i]);
1115
1116 switch (param) {
1117 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1118 arg = (arg >= 1 ? 1 : 0);
1119 bcm281xx_pin_update(val, mask, arg,
1120 BCM281XX_PIN_SHIFT(STD, HYST),
1121 BCM281XX_PIN_MASK(STD, HYST));
1122 break;
1123 /*
1124 * The pin bias can only be one of pull-up, pull-down, or
1125 * disable. The user does not need to specify a value for the
1126 * property, and the default value from pinconf-generic is
1127 * ignored.
1128 */
1129 case PIN_CONFIG_BIAS_DISABLE:
1130 bcm281xx_pin_update(val, mask, 0,
1131 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1132 BCM281XX_PIN_MASK(STD, PULL_UP));
1133 bcm281xx_pin_update(val, mask, 0,
1134 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1135 BCM281XX_PIN_MASK(STD, PULL_DN));
1136 break;
1137
1138 case PIN_CONFIG_BIAS_PULL_UP:
1139 bcm281xx_pin_update(val, mask, 1,
1140 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1141 BCM281XX_PIN_MASK(STD, PULL_UP));
1142 bcm281xx_pin_update(val, mask, 0,
1143 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1144 BCM281XX_PIN_MASK(STD, PULL_DN));
1145 break;
1146
1147 case PIN_CONFIG_BIAS_PULL_DOWN:
1148 bcm281xx_pin_update(val, mask, 0,
1149 BCM281XX_PIN_SHIFT(STD, PULL_UP),
1150 BCM281XX_PIN_MASK(STD, PULL_UP));
1151 bcm281xx_pin_update(val, mask, 1,
1152 BCM281XX_PIN_SHIFT(STD, PULL_DN),
1153 BCM281XX_PIN_MASK(STD, PULL_DN));
1154 break;
1155
1156 case PIN_CONFIG_SLEW_RATE:
1157 arg = (arg >= 1 ? 1 : 0);
1158 bcm281xx_pin_update(val, mask, arg,
1159 BCM281XX_PIN_SHIFT(STD, SLEW),
1160 BCM281XX_PIN_MASK(STD, SLEW));
1161 break;
1162
1163 case PIN_CONFIG_INPUT_ENABLE:
1164 /* inversed since register is for input _disable_ */
1165 arg = (arg >= 1 ? 0 : 1);
1166 bcm281xx_pin_update(val, mask, arg,
1167 BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
1168 BCM281XX_PIN_MASK(STD, INPUT_DIS));
1169 break;
1170
1171 case PIN_CONFIG_DRIVE_STRENGTH:
1172 /* Valid range is 2-16 mA, even numbers only */
1173 if ((arg < 2) || (arg > 16) || (arg % 2)) {
1174 dev_err(pctldev->dev,
1175 "Invalid Drive Strength value (%d) for "
1176 "pin %s (%d). Valid values are "
1177 "(2..16) mA, even numbers only.\n",
1178 arg, pdata->pins[pin].name, pin);
1179 return -EINVAL;
1180 }
1181 bcm281xx_pin_update(val, mask, (arg/2)-1,
1182 BCM281XX_PIN_SHIFT(STD, DRV_STR),
1183 BCM281XX_PIN_MASK(STD, DRV_STR));
1184 break;
1185
1186 default:
1187 dev_err(pctldev->dev,
1188 "Unrecognized pin config %d for pin %s (%d).\n",
1189 param, pdata->pins[pin].name, pin);
1190 return -EINVAL;
1191
1192 } /* switch config */
1193 } /* for each config */
1194
1195 return 0;
1196 }
1197
1198 /*
1199 * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1200 * register with the following mapping:
1201 * 0b000: No pull-up
1202 * 0b001: 1200 Ohm
1203 * 0b010: 1800 Ohm
1204 * 0b011: 720 Ohm
1205 * 0b100: 2700 Ohm
1206 * 0b101: 831 Ohm
1207 * 0b110: 1080 Ohm
1208 * 0b111: 568 Ohm
1209 * This array maps pull-up strength in Ohms to register values (1+index).
1210 */
1211 static const u16 bcm281xx_pullup_map[] = {
1212 1200, 1800, 720, 2700, 831, 1080, 568
1213 };
1214
1215 /* Goes through the configs and update register val/mask */
1216 static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
1217 unsigned pin,
1218 unsigned long *configs,
1219 unsigned num_configs,
1220 u32 *val,
1221 u32 *mask)
1222 {
1223 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1224 int i, j;
1225 enum pin_config_param param;
1226 u32 arg;
1227
1228 for (i = 0; i < num_configs; i++) {
1229 param = pinconf_to_config_param(configs[i]);
1230 arg = pinconf_to_config_argument(configs[i]);
1231
1232 switch (param) {
1233 case PIN_CONFIG_BIAS_PULL_UP:
1234 for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
1235 if (bcm281xx_pullup_map[j] == arg)
1236 break;
1237
1238 if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
1239 dev_err(pctldev->dev,
1240 "Invalid pull-up value (%d) for pin %s "
1241 "(%d). Valid values are 568, 720, 831, "
1242 "1080, 1200, 1800, 2700 Ohms.\n",
1243 arg, pdata->pins[pin].name, pin);
1244 return -EINVAL;
1245 }
1246
1247 bcm281xx_pin_update(val, mask, j+1,
1248 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1249 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1250 break;
1251
1252 case PIN_CONFIG_BIAS_DISABLE:
1253 bcm281xx_pin_update(val, mask, 0,
1254 BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
1255 BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
1256 break;
1257
1258 case PIN_CONFIG_SLEW_RATE:
1259 arg = (arg >= 1 ? 1 : 0);
1260 bcm281xx_pin_update(val, mask, arg,
1261 BCM281XX_PIN_SHIFT(I2C, SLEW),
1262 BCM281XX_PIN_MASK(I2C, SLEW));
1263 break;
1264
1265 case PIN_CONFIG_INPUT_ENABLE:
1266 /* inversed since register is for input _disable_ */
1267 arg = (arg >= 1 ? 0 : 1);
1268 bcm281xx_pin_update(val, mask, arg,
1269 BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
1270 BCM281XX_PIN_MASK(I2C, INPUT_DIS));
1271 break;
1272
1273 default:
1274 dev_err(pctldev->dev,
1275 "Unrecognized pin config %d for pin %s (%d).\n",
1276 param, pdata->pins[pin].name, pin);
1277 return -EINVAL;
1278
1279 } /* switch config */
1280 } /* for each config */
1281
1282 return 0;
1283 }
1284
1285 /* Goes through the configs and update register val/mask */
1286 static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
1287 unsigned pin,
1288 unsigned long *configs,
1289 unsigned num_configs,
1290 u32 *val,
1291 u32 *mask)
1292 {
1293 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1294 int i;
1295 enum pin_config_param param;
1296 u32 arg;
1297
1298 for (i = 0; i < num_configs; i++) {
1299 param = pinconf_to_config_param(configs[i]);
1300 arg = pinconf_to_config_argument(configs[i]);
1301
1302 switch (param) {
1303 case PIN_CONFIG_SLEW_RATE:
1304 arg = (arg >= 1 ? 1 : 0);
1305 bcm281xx_pin_update(val, mask, arg,
1306 BCM281XX_PIN_SHIFT(HDMI, MODE),
1307 BCM281XX_PIN_MASK(HDMI, MODE));
1308 break;
1309
1310 case PIN_CONFIG_INPUT_ENABLE:
1311 /* inversed since register is for input _disable_ */
1312 arg = (arg >= 1 ? 0 : 1);
1313 bcm281xx_pin_update(val, mask, arg,
1314 BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
1315 BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
1316 break;
1317
1318 default:
1319 dev_err(pctldev->dev,
1320 "Unrecognized pin config %d for pin %s (%d).\n",
1321 param, pdata->pins[pin].name, pin);
1322 return -EINVAL;
1323
1324 } /* switch config */
1325 } /* for each config */
1326
1327 return 0;
1328 }
1329
1330 static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1331 unsigned pin,
1332 unsigned long *configs,
1333 unsigned num_configs)
1334 {
1335 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1336 enum bcm281xx_pin_type pin_type;
1337 u32 offset = 4 * pin;
1338 u32 cfg_val, cfg_mask;
1339 int rc;
1340
1341 cfg_val = 0;
1342 cfg_mask = 0;
1343 pin_type = pin_type_get(pctldev, pin);
1344
1345 /* Different pins have different configuration options */
1346 switch (pin_type) {
1347 case BCM281XX_PIN_TYPE_STD:
1348 rc = bcm281xx_std_pin_update(pctldev, pin, configs,
1349 num_configs, &cfg_val, &cfg_mask);
1350 break;
1351
1352 case BCM281XX_PIN_TYPE_I2C:
1353 rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
1354 num_configs, &cfg_val, &cfg_mask);
1355 break;
1356
1357 case BCM281XX_PIN_TYPE_HDMI:
1358 rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
1359 num_configs, &cfg_val, &cfg_mask);
1360 break;
1361
1362 default:
1363 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1364 pdata->pins[pin].name, pin);
1365 return -EINVAL;
1366
1367 } /* switch pin type */
1368
1369 if (rc)
1370 return rc;
1371
1372 dev_dbg(pctldev->dev,
1373 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1374 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1375
1376 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1377 if (rc) {
1378 dev_err(pctldev->dev,
1379 "Error updating register for pin %s (%d).\n",
1380 pdata->pins[pin].name, pin);
1381 return rc;
1382 }
1383
1384 return 0;
1385 }
1386
1387 static struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
1388 .pin_config_get = bcm281xx_pinctrl_pin_config_get,
1389 .pin_config_set = bcm281xx_pinctrl_pin_config_set,
1390 };
1391
1392 static struct pinctrl_desc bcm281xx_pinctrl_desc = {
1393 /* name, pins, npins members initialized in probe function */
1394 .pctlops = &bcm281xx_pinctrl_ops,
1395 .pmxops = &bcm281xx_pinctrl_pinmux_ops,
1396 .confops = &bcm281xx_pinctrl_pinconf_ops,
1397 .owner = THIS_MODULE,
1398 };
1399
1400 static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1401 {
1402 struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1403 struct resource *res;
1404 struct pinctrl_dev *pctl;
1405
1406 /* So far We can assume there is only 1 bank of registers */
1407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1408 pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
1409 if (IS_ERR(pdata->reg_base)) {
1410 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1411 return -ENODEV;
1412 }
1413
1414 /* Initialize the dynamic part of pinctrl_desc */
1415 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1416 &bcm281xx_pinctrl_regmap_config);
1417 if (IS_ERR(pdata->regmap)) {
1418 dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1419 return -ENODEV;
1420 }
1421
1422 bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
1423 bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
1424 bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
1425
1426 pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
1427 if (IS_ERR(pctl)) {
1428 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1429 return PTR_ERR(pctl);
1430 }
1431
1432 platform_set_drvdata(pdev, pdata);
1433
1434 return 0;
1435 }
1436
1437 static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
1438 { .compatible = "brcm,bcm11351-pinctrl", },
1439 { },
1440 };
1441
1442 static struct platform_driver bcm281xx_pinctrl_driver = {
1443 .driver = {
1444 .name = "bcm281xx-pinctrl",
1445 .of_match_table = bcm281xx_pinctrl_of_match,
1446 },
1447 };
1448 builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
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