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pinctrl-bcm2835: Fix cut-and-paste error in "pull" parsing
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
1 /*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/irqdesc.h>
31 #include <linux/irqdomain.h>
32 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/pinctrl/consumer.h>
37 #include <linux/pinctrl/machine.h>
38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/pinctrl/pinmux.h>
41 #include <linux/platform_device.h>
42 #include <linux/seq_file.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45 #include <linux/types.h>
46
47 #define MODULE_NAME "pinctrl-bcm2835"
48 #define BCM2835_NUM_GPIOS 54
49 #define BCM2835_NUM_BANKS 2
50
51 #define BCM2835_PIN_BITMAP_SZ \
52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53
54 /* GPIO register offsets */
55 #define GPFSEL0 0x0 /* Function Select */
56 #define GPSET0 0x1c /* Pin Output Set */
57 #define GPCLR0 0x28 /* Pin Output Clear */
58 #define GPLEV0 0x34 /* Pin Level */
59 #define GPEDS0 0x40 /* Pin Event Detect Status */
60 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
61 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
62 #define GPHEN0 0x64 /* Pin High Detect Enable */
63 #define GPLEN0 0x70 /* Pin Low Detect Enable */
64 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
65 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
66 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
67 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
68
69 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
70 #define FSEL_SHIFT(p) (((p) % 10) * 3)
71 #define GPIO_REG_OFFSET(p) ((p) / 32)
72 #define GPIO_REG_SHIFT(p) ((p) % 32)
73
74 enum bcm2835_pinconf_param {
75 /* argument: bcm2835_pinconf_pull */
76 BCM2835_PINCONF_PARAM_PULL,
77 };
78
79 enum bcm2835_pinconf_pull {
80 BCM2835_PINCONFIG_PULL_NONE,
81 BCM2835_PINCONFIG_PULL_DOWN,
82 BCM2835_PINCONFIG_PULL_UP,
83 };
84
85 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
86 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
87 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
88
89 struct bcm2835_gpio_irqdata {
90 struct bcm2835_pinctrl *pc;
91 int bank;
92 };
93
94 struct bcm2835_pinctrl {
95 struct device *dev;
96 void __iomem *base;
97 int irq[BCM2835_NUM_BANKS];
98
99 /* note: locking assumes each bank will have its own unsigned long */
100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
101 unsigned int irq_type[BCM2835_NUM_GPIOS];
102
103 struct pinctrl_dev *pctl_dev;
104 struct irq_domain *irq_domain;
105 struct gpio_chip gpio_chip;
106 struct pinctrl_gpio_range gpio_range;
107
108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
109 spinlock_t irq_lock[BCM2835_NUM_BANKS];
110 };
111
112 static struct lock_class_key gpio_lock_class;
113
114 /* pins are just named GPIO0..GPIO53 */
115 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
116 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
117 BCM2835_GPIO_PIN(0),
118 BCM2835_GPIO_PIN(1),
119 BCM2835_GPIO_PIN(2),
120 BCM2835_GPIO_PIN(3),
121 BCM2835_GPIO_PIN(4),
122 BCM2835_GPIO_PIN(5),
123 BCM2835_GPIO_PIN(6),
124 BCM2835_GPIO_PIN(7),
125 BCM2835_GPIO_PIN(8),
126 BCM2835_GPIO_PIN(9),
127 BCM2835_GPIO_PIN(10),
128 BCM2835_GPIO_PIN(11),
129 BCM2835_GPIO_PIN(12),
130 BCM2835_GPIO_PIN(13),
131 BCM2835_GPIO_PIN(14),
132 BCM2835_GPIO_PIN(15),
133 BCM2835_GPIO_PIN(16),
134 BCM2835_GPIO_PIN(17),
135 BCM2835_GPIO_PIN(18),
136 BCM2835_GPIO_PIN(19),
137 BCM2835_GPIO_PIN(20),
138 BCM2835_GPIO_PIN(21),
139 BCM2835_GPIO_PIN(22),
140 BCM2835_GPIO_PIN(23),
141 BCM2835_GPIO_PIN(24),
142 BCM2835_GPIO_PIN(25),
143 BCM2835_GPIO_PIN(26),
144 BCM2835_GPIO_PIN(27),
145 BCM2835_GPIO_PIN(28),
146 BCM2835_GPIO_PIN(29),
147 BCM2835_GPIO_PIN(30),
148 BCM2835_GPIO_PIN(31),
149 BCM2835_GPIO_PIN(32),
150 BCM2835_GPIO_PIN(33),
151 BCM2835_GPIO_PIN(34),
152 BCM2835_GPIO_PIN(35),
153 BCM2835_GPIO_PIN(36),
154 BCM2835_GPIO_PIN(37),
155 BCM2835_GPIO_PIN(38),
156 BCM2835_GPIO_PIN(39),
157 BCM2835_GPIO_PIN(40),
158 BCM2835_GPIO_PIN(41),
159 BCM2835_GPIO_PIN(42),
160 BCM2835_GPIO_PIN(43),
161 BCM2835_GPIO_PIN(44),
162 BCM2835_GPIO_PIN(45),
163 BCM2835_GPIO_PIN(46),
164 BCM2835_GPIO_PIN(47),
165 BCM2835_GPIO_PIN(48),
166 BCM2835_GPIO_PIN(49),
167 BCM2835_GPIO_PIN(50),
168 BCM2835_GPIO_PIN(51),
169 BCM2835_GPIO_PIN(52),
170 BCM2835_GPIO_PIN(53),
171 };
172
173 /* one pin per group */
174 static const char * const bcm2835_gpio_groups[] = {
175 "gpio0",
176 "gpio1",
177 "gpio2",
178 "gpio3",
179 "gpio4",
180 "gpio5",
181 "gpio6",
182 "gpio7",
183 "gpio8",
184 "gpio9",
185 "gpio10",
186 "gpio11",
187 "gpio12",
188 "gpio13",
189 "gpio14",
190 "gpio15",
191 "gpio16",
192 "gpio17",
193 "gpio18",
194 "gpio19",
195 "gpio20",
196 "gpio21",
197 "gpio22",
198 "gpio23",
199 "gpio24",
200 "gpio25",
201 "gpio26",
202 "gpio27",
203 "gpio28",
204 "gpio29",
205 "gpio30",
206 "gpio31",
207 "gpio32",
208 "gpio33",
209 "gpio34",
210 "gpio35",
211 "gpio36",
212 "gpio37",
213 "gpio38",
214 "gpio39",
215 "gpio40",
216 "gpio41",
217 "gpio42",
218 "gpio43",
219 "gpio44",
220 "gpio45",
221 "gpio46",
222 "gpio47",
223 "gpio48",
224 "gpio49",
225 "gpio50",
226 "gpio51",
227 "gpio52",
228 "gpio53",
229 };
230
231 enum bcm2835_fsel {
232 BCM2835_FSEL_GPIO_IN = 0,
233 BCM2835_FSEL_GPIO_OUT = 1,
234 BCM2835_FSEL_ALT0 = 4,
235 BCM2835_FSEL_ALT1 = 5,
236 BCM2835_FSEL_ALT2 = 6,
237 BCM2835_FSEL_ALT3 = 7,
238 BCM2835_FSEL_ALT4 = 3,
239 BCM2835_FSEL_ALT5 = 2,
240 BCM2835_FSEL_COUNT = 8,
241 BCM2835_FSEL_MASK = 0x7,
242 };
243
244 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
245 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
247 [BCM2835_FSEL_ALT0] = "alt0",
248 [BCM2835_FSEL_ALT1] = "alt1",
249 [BCM2835_FSEL_ALT2] = "alt2",
250 [BCM2835_FSEL_ALT3] = "alt3",
251 [BCM2835_FSEL_ALT4] = "alt4",
252 [BCM2835_FSEL_ALT5] = "alt5",
253 };
254
255 static const char * const irq_type_names[] = {
256 [IRQ_TYPE_NONE] = "none",
257 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
259 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
260 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
261 [IRQ_TYPE_LEVEL_LOW] = "level-low",
262 };
263
264 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
265 {
266 return readl(pc->base + reg);
267 }
268
269 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
270 u32 val)
271 {
272 writel(val, pc->base + reg);
273 }
274
275 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
276 unsigned bit)
277 {
278 reg += GPIO_REG_OFFSET(bit) * 4;
279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
280 }
281
282 /* note NOT a read/modify/write cycle */
283 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
284 unsigned reg, unsigned bit)
285 {
286 reg += GPIO_REG_OFFSET(bit) * 4;
287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
288 }
289
290 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
291 struct bcm2835_pinctrl *pc, unsigned pin)
292 {
293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
295
296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
297 bcm2835_functions[status]);
298
299 return status;
300 }
301
302 static inline void bcm2835_pinctrl_fsel_set(
303 struct bcm2835_pinctrl *pc, unsigned pin,
304 enum bcm2835_fsel fsel)
305 {
306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
308
309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
310 bcm2835_functions[cur]);
311
312 if (cur == fsel)
313 return;
314
315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
316 /* always transition through GPIO_IN */
317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
319
320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
323 }
324
325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
326 val |= fsel << FSEL_SHIFT(pin);
327
328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
329 bcm2835_functions[fsel]);
330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
331 }
332
333 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
334 {
335 return pinctrl_gpio_direction_input(chip->base + offset);
336 }
337
338 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
339 {
340 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
341
342 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
343 }
344
345 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
346 {
347 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
348
349 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
350 }
351
352 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
353 unsigned offset, int value)
354 {
355 bcm2835_gpio_set(chip, offset, value);
356 return pinctrl_gpio_direction_output(chip->base + offset);
357 }
358
359 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
360 {
361 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
362
363 return irq_linear_revmap(pc->irq_domain, offset);
364 }
365
366 static struct gpio_chip bcm2835_gpio_chip = {
367 .label = MODULE_NAME,
368 .owner = THIS_MODULE,
369 .request = gpiochip_generic_request,
370 .free = gpiochip_generic_free,
371 .direction_input = bcm2835_gpio_direction_input,
372 .direction_output = bcm2835_gpio_direction_output,
373 .get = bcm2835_gpio_get,
374 .set = bcm2835_gpio_set,
375 .to_irq = bcm2835_gpio_to_irq,
376 .base = -1,
377 .ngpio = BCM2835_NUM_GPIOS,
378 .can_sleep = false,
379 };
380
381 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
382 {
383 struct bcm2835_gpio_irqdata *irqdata = dev_id;
384 struct bcm2835_pinctrl *pc = irqdata->pc;
385 int bank = irqdata->bank;
386 unsigned long events;
387 unsigned offset;
388 unsigned gpio;
389 unsigned int type;
390
391 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
392 events &= pc->enabled_irq_map[bank];
393 for_each_set_bit(offset, &events, 32) {
394 gpio = (32 * bank) + offset;
395 type = pc->irq_type[gpio];
396
397 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
398 }
399 return events ? IRQ_HANDLED : IRQ_NONE;
400 }
401
402 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
403 unsigned reg, unsigned offset, bool enable)
404 {
405 u32 value;
406 reg += GPIO_REG_OFFSET(offset) * 4;
407 value = bcm2835_gpio_rd(pc, reg);
408 if (enable)
409 value |= BIT(GPIO_REG_SHIFT(offset));
410 else
411 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
412 bcm2835_gpio_wr(pc, reg, value);
413 }
414
415 /* fast path for IRQ handler */
416 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
417 unsigned offset, bool enable)
418 {
419 switch (pc->irq_type[offset]) {
420 case IRQ_TYPE_EDGE_RISING:
421 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
422 break;
423
424 case IRQ_TYPE_EDGE_FALLING:
425 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
426 break;
427
428 case IRQ_TYPE_EDGE_BOTH:
429 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
430 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
431 break;
432
433 case IRQ_TYPE_LEVEL_HIGH:
434 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
435 break;
436
437 case IRQ_TYPE_LEVEL_LOW:
438 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
439 break;
440 }
441 }
442
443 static void bcm2835_gpio_irq_enable(struct irq_data *data)
444 {
445 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
446 unsigned gpio = irqd_to_hwirq(data);
447 unsigned offset = GPIO_REG_SHIFT(gpio);
448 unsigned bank = GPIO_REG_OFFSET(gpio);
449 unsigned long flags;
450
451 spin_lock_irqsave(&pc->irq_lock[bank], flags);
452 set_bit(offset, &pc->enabled_irq_map[bank]);
453 bcm2835_gpio_irq_config(pc, gpio, true);
454 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
455 }
456
457 static void bcm2835_gpio_irq_disable(struct irq_data *data)
458 {
459 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
460 unsigned gpio = irqd_to_hwirq(data);
461 unsigned offset = GPIO_REG_SHIFT(gpio);
462 unsigned bank = GPIO_REG_OFFSET(gpio);
463 unsigned long flags;
464
465 spin_lock_irqsave(&pc->irq_lock[bank], flags);
466 bcm2835_gpio_irq_config(pc, gpio, false);
467 /* Clear events that were latched prior to clearing event sources */
468 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
469 clear_bit(offset, &pc->enabled_irq_map[bank]);
470 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
471 }
472
473 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
474 unsigned offset, unsigned int type)
475 {
476 switch (type) {
477 case IRQ_TYPE_NONE:
478 case IRQ_TYPE_EDGE_RISING:
479 case IRQ_TYPE_EDGE_FALLING:
480 case IRQ_TYPE_EDGE_BOTH:
481 case IRQ_TYPE_LEVEL_HIGH:
482 case IRQ_TYPE_LEVEL_LOW:
483 pc->irq_type[offset] = type;
484 break;
485
486 default:
487 return -EINVAL;
488 }
489 return 0;
490 }
491
492 /* slower path for reconfiguring IRQ type */
493 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
494 unsigned offset, unsigned int type)
495 {
496 switch (type) {
497 case IRQ_TYPE_NONE:
498 if (pc->irq_type[offset] != type) {
499 bcm2835_gpio_irq_config(pc, offset, false);
500 pc->irq_type[offset] = type;
501 }
502 break;
503
504 case IRQ_TYPE_EDGE_RISING:
505 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
506 /* RISING already enabled, disable FALLING */
507 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
508 bcm2835_gpio_irq_config(pc, offset, false);
509 pc->irq_type[offset] = type;
510 } else if (pc->irq_type[offset] != type) {
511 bcm2835_gpio_irq_config(pc, offset, false);
512 pc->irq_type[offset] = type;
513 bcm2835_gpio_irq_config(pc, offset, true);
514 }
515 break;
516
517 case IRQ_TYPE_EDGE_FALLING:
518 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
519 /* FALLING already enabled, disable RISING */
520 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
521 bcm2835_gpio_irq_config(pc, offset, false);
522 pc->irq_type[offset] = type;
523 } else if (pc->irq_type[offset] != type) {
524 bcm2835_gpio_irq_config(pc, offset, false);
525 pc->irq_type[offset] = type;
526 bcm2835_gpio_irq_config(pc, offset, true);
527 }
528 break;
529
530 case IRQ_TYPE_EDGE_BOTH:
531 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
532 /* RISING already enabled, enable FALLING too */
533 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
534 bcm2835_gpio_irq_config(pc, offset, true);
535 pc->irq_type[offset] = type;
536 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
537 /* FALLING already enabled, enable RISING too */
538 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
539 bcm2835_gpio_irq_config(pc, offset, true);
540 pc->irq_type[offset] = type;
541 } else if (pc->irq_type[offset] != type) {
542 bcm2835_gpio_irq_config(pc, offset, false);
543 pc->irq_type[offset] = type;
544 bcm2835_gpio_irq_config(pc, offset, true);
545 }
546 break;
547
548 case IRQ_TYPE_LEVEL_HIGH:
549 case IRQ_TYPE_LEVEL_LOW:
550 if (pc->irq_type[offset] != type) {
551 bcm2835_gpio_irq_config(pc, offset, false);
552 pc->irq_type[offset] = type;
553 bcm2835_gpio_irq_config(pc, offset, true);
554 }
555 break;
556
557 default:
558 return -EINVAL;
559 }
560 return 0;
561 }
562
563 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
564 {
565 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
566 unsigned gpio = irqd_to_hwirq(data);
567 unsigned offset = GPIO_REG_SHIFT(gpio);
568 unsigned bank = GPIO_REG_OFFSET(gpio);
569 unsigned long flags;
570 int ret;
571
572 spin_lock_irqsave(&pc->irq_lock[bank], flags);
573
574 if (test_bit(offset, &pc->enabled_irq_map[bank]))
575 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
576 else
577 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
578
579 if (type & IRQ_TYPE_EDGE_BOTH)
580 irq_set_handler_locked(data, handle_edge_irq);
581 else
582 irq_set_handler_locked(data, handle_level_irq);
583
584 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
585
586 return ret;
587 }
588
589 static void bcm2835_gpio_irq_ack(struct irq_data *data)
590 {
591 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
592 unsigned gpio = irqd_to_hwirq(data);
593
594 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
595 }
596
597 static struct irq_chip bcm2835_gpio_irq_chip = {
598 .name = MODULE_NAME,
599 .irq_enable = bcm2835_gpio_irq_enable,
600 .irq_disable = bcm2835_gpio_irq_disable,
601 .irq_set_type = bcm2835_gpio_irq_set_type,
602 .irq_ack = bcm2835_gpio_irq_ack,
603 .irq_mask = bcm2835_gpio_irq_disable,
604 .irq_unmask = bcm2835_gpio_irq_enable,
605 };
606
607 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
608 {
609 return ARRAY_SIZE(bcm2835_gpio_groups);
610 }
611
612 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
613 unsigned selector)
614 {
615 return bcm2835_gpio_groups[selector];
616 }
617
618 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
619 unsigned selector,
620 const unsigned **pins,
621 unsigned *num_pins)
622 {
623 *pins = &bcm2835_gpio_pins[selector].number;
624 *num_pins = 1;
625
626 return 0;
627 }
628
629 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
630 struct seq_file *s,
631 unsigned offset)
632 {
633 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
634 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
635 const char *fname = bcm2835_functions[fsel];
636 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
637 int irq = irq_find_mapping(pc->irq_domain, offset);
638
639 seq_printf(s, "function %s in %s; irq %d (%s)",
640 fname, value ? "hi" : "lo",
641 irq, irq_type_names[pc->irq_type[offset]]);
642 }
643
644 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
645 struct pinctrl_map *maps, unsigned num_maps)
646 {
647 int i;
648
649 for (i = 0; i < num_maps; i++)
650 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
651 kfree(maps[i].data.configs.configs);
652
653 kfree(maps);
654 }
655
656 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
657 struct device_node *np, u32 pin, u32 fnum,
658 struct pinctrl_map **maps)
659 {
660 struct pinctrl_map *map = *maps;
661
662 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
663 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
664 of_node_full_name(np), fnum);
665 return -EINVAL;
666 }
667
668 map->type = PIN_MAP_TYPE_MUX_GROUP;
669 map->data.mux.group = bcm2835_gpio_groups[pin];
670 map->data.mux.function = bcm2835_functions[fnum];
671 (*maps)++;
672
673 return 0;
674 }
675
676 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
677 struct device_node *np, u32 pin, u32 pull,
678 struct pinctrl_map **maps)
679 {
680 struct pinctrl_map *map = *maps;
681 unsigned long *configs;
682
683 if (pull > 2) {
684 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
685 of_node_full_name(np), pull);
686 return -EINVAL;
687 }
688
689 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
690 if (!configs)
691 return -ENOMEM;
692 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
693
694 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
695 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
696 map->data.configs.configs = configs;
697 map->data.configs.num_configs = 1;
698 (*maps)++;
699
700 return 0;
701 }
702
703 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
704 struct device_node *np,
705 struct pinctrl_map **map, unsigned *num_maps)
706 {
707 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
708 struct property *pins, *funcs, *pulls;
709 int num_pins, num_funcs, num_pulls, maps_per_pin;
710 struct pinctrl_map *maps, *cur_map;
711 int i, err;
712 u32 pin, func, pull;
713
714 pins = of_find_property(np, "brcm,pins", NULL);
715 if (!pins) {
716 dev_err(pc->dev, "%s: missing brcm,pins property\n",
717 of_node_full_name(np));
718 return -EINVAL;
719 }
720
721 funcs = of_find_property(np, "brcm,function", NULL);
722 pulls = of_find_property(np, "brcm,pull", NULL);
723
724 if (!funcs && !pulls) {
725 dev_err(pc->dev,
726 "%s: neither brcm,function nor brcm,pull specified\n",
727 of_node_full_name(np));
728 return -EINVAL;
729 }
730
731 num_pins = pins->length / 4;
732 num_funcs = funcs ? (funcs->length / 4) : 0;
733 num_pulls = pulls ? (pulls->length / 4) : 0;
734
735 if (num_funcs > 1 && num_funcs != num_pins) {
736 dev_err(pc->dev,
737 "%s: brcm,function must have 1 or %d entries\n",
738 of_node_full_name(np), num_pins);
739 return -EINVAL;
740 }
741
742 if (num_pulls > 1 && num_pulls != num_pins) {
743 dev_err(pc->dev,
744 "%s: brcm,pull must have 1 or %d entries\n",
745 of_node_full_name(np), num_pins);
746 return -EINVAL;
747 }
748
749 maps_per_pin = 0;
750 if (num_funcs)
751 maps_per_pin++;
752 if (num_pulls)
753 maps_per_pin++;
754 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
755 GFP_KERNEL);
756 if (!maps)
757 return -ENOMEM;
758
759 for (i = 0; i < num_pins; i++) {
760 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
761 if (err)
762 goto out;
763 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
764 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
765 of_node_full_name(np), pin);
766 err = -EINVAL;
767 goto out;
768 }
769
770 if (num_funcs) {
771 err = of_property_read_u32_index(np, "brcm,function",
772 (num_funcs > 1) ? i : 0, &func);
773 if (err)
774 goto out;
775 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
776 func, &cur_map);
777 if (err)
778 goto out;
779 }
780 if (num_pulls) {
781 err = of_property_read_u32_index(np, "brcm,pull",
782 (num_pulls > 1) ? i : 0, &pull);
783 if (err)
784 goto out;
785 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
786 pull, &cur_map);
787 if (err)
788 goto out;
789 }
790 }
791
792 *map = maps;
793 *num_maps = num_pins * maps_per_pin;
794
795 return 0;
796
797 out:
798 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
799 return err;
800 }
801
802 static const struct pinctrl_ops bcm2835_pctl_ops = {
803 .get_groups_count = bcm2835_pctl_get_groups_count,
804 .get_group_name = bcm2835_pctl_get_group_name,
805 .get_group_pins = bcm2835_pctl_get_group_pins,
806 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
807 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
808 .dt_free_map = bcm2835_pctl_dt_free_map,
809 };
810
811 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
812 {
813 return BCM2835_FSEL_COUNT;
814 }
815
816 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
817 unsigned selector)
818 {
819 return bcm2835_functions[selector];
820 }
821
822 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
823 unsigned selector,
824 const char * const **groups,
825 unsigned * const num_groups)
826 {
827 /* every pin can do every function */
828 *groups = bcm2835_gpio_groups;
829 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
830
831 return 0;
832 }
833
834 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
835 unsigned func_selector,
836 unsigned group_selector)
837 {
838 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
839
840 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
841
842 return 0;
843 }
844
845 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
846 struct pinctrl_gpio_range *range,
847 unsigned offset)
848 {
849 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
850
851 /* disable by setting to GPIO_IN */
852 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
853 }
854
855 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
856 struct pinctrl_gpio_range *range,
857 unsigned offset,
858 bool input)
859 {
860 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
861 enum bcm2835_fsel fsel = input ?
862 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
863
864 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
865
866 return 0;
867 }
868
869 static const struct pinmux_ops bcm2835_pmx_ops = {
870 .get_functions_count = bcm2835_pmx_get_functions_count,
871 .get_function_name = bcm2835_pmx_get_function_name,
872 .get_function_groups = bcm2835_pmx_get_function_groups,
873 .set_mux = bcm2835_pmx_set,
874 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
875 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
876 };
877
878 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
879 unsigned pin, unsigned long *config)
880 {
881 /* No way to read back config in HW */
882 return -ENOTSUPP;
883 }
884
885 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
886 unsigned pin, unsigned long *configs,
887 unsigned num_configs)
888 {
889 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
890 enum bcm2835_pinconf_param param;
891 u16 arg;
892 u32 off, bit;
893 int i;
894
895 for (i = 0; i < num_configs; i++) {
896 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
897 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
898
899 if (param != BCM2835_PINCONF_PARAM_PULL)
900 return -EINVAL;
901
902 off = GPIO_REG_OFFSET(pin);
903 bit = GPIO_REG_SHIFT(pin);
904
905 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
906 /*
907 * Docs say to wait 150 cycles, but not of what. We assume a
908 * 1 MHz clock here, which is pretty slow...
909 */
910 udelay(150);
911 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
912 udelay(150);
913 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
914 } /* for each config */
915
916 return 0;
917 }
918
919 static const struct pinconf_ops bcm2835_pinconf_ops = {
920 .pin_config_get = bcm2835_pinconf_get,
921 .pin_config_set = bcm2835_pinconf_set,
922 };
923
924 static struct pinctrl_desc bcm2835_pinctrl_desc = {
925 .name = MODULE_NAME,
926 .pins = bcm2835_gpio_pins,
927 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
928 .pctlops = &bcm2835_pctl_ops,
929 .pmxops = &bcm2835_pmx_ops,
930 .confops = &bcm2835_pinconf_ops,
931 .owner = THIS_MODULE,
932 };
933
934 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
935 .name = MODULE_NAME,
936 .npins = BCM2835_NUM_GPIOS,
937 };
938
939 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
940 {
941 struct device *dev = &pdev->dev;
942 struct device_node *np = dev->of_node;
943 struct bcm2835_pinctrl *pc;
944 struct resource iomem;
945 int err, i;
946 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
947 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
948
949 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
950 if (!pc)
951 return -ENOMEM;
952
953 platform_set_drvdata(pdev, pc);
954 pc->dev = dev;
955
956 err = of_address_to_resource(np, 0, &iomem);
957 if (err) {
958 dev_err(dev, "could not get IO memory\n");
959 return err;
960 }
961
962 pc->base = devm_ioremap_resource(dev, &iomem);
963 if (IS_ERR(pc->base))
964 return PTR_ERR(pc->base);
965
966 pc->gpio_chip = bcm2835_gpio_chip;
967 pc->gpio_chip.parent = dev;
968 pc->gpio_chip.of_node = np;
969
970 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
971 &irq_domain_simple_ops, NULL);
972 if (!pc->irq_domain) {
973 dev_err(dev, "could not create IRQ domain\n");
974 return -ENOMEM;
975 }
976
977 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
978 int irq = irq_create_mapping(pc->irq_domain, i);
979 irq_set_lockdep_class(irq, &gpio_lock_class);
980 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
981 handle_level_irq);
982 irq_set_chip_data(irq, pc);
983 }
984
985 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
986 unsigned long events;
987 unsigned offset;
988 int len;
989 char *name;
990
991 /* clear event detection flags */
992 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
993 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
994 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
995 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
996 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
997 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
998
999 /* clear all the events */
1000 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1001 for_each_set_bit(offset, &events, 32)
1002 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1003
1004 pc->irq[i] = irq_of_parse_and_map(np, i);
1005 pc->irq_data[i].pc = pc;
1006 pc->irq_data[i].bank = i;
1007 spin_lock_init(&pc->irq_lock[i]);
1008
1009 len = strlen(dev_name(pc->dev)) + 16;
1010 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1011 if (!name)
1012 return -ENOMEM;
1013 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1014
1015 err = devm_request_irq(dev, pc->irq[i],
1016 bcm2835_gpio_irq_handler, IRQF_SHARED,
1017 name, &pc->irq_data[i]);
1018 if (err) {
1019 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1020 return err;
1021 }
1022 }
1023
1024 err = gpiochip_add_data(&pc->gpio_chip, pc);
1025 if (err) {
1026 dev_err(dev, "could not add GPIO chip\n");
1027 return err;
1028 }
1029
1030 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
1031 if (IS_ERR(pc->pctl_dev)) {
1032 gpiochip_remove(&pc->gpio_chip);
1033 return PTR_ERR(pc->pctl_dev);
1034 }
1035
1036 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1037 pc->gpio_range.base = pc->gpio_chip.base;
1038 pc->gpio_range.gc = &pc->gpio_chip;
1039 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1040
1041 return 0;
1042 }
1043
1044 static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1045 {
1046 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1047
1048 pinctrl_unregister(pc->pctl_dev);
1049 gpiochip_remove(&pc->gpio_chip);
1050
1051 return 0;
1052 }
1053
1054 static const struct of_device_id bcm2835_pinctrl_match[] = {
1055 { .compatible = "brcm,bcm2835-gpio" },
1056 {}
1057 };
1058 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1059
1060 static struct platform_driver bcm2835_pinctrl_driver = {
1061 .probe = bcm2835_pinctrl_probe,
1062 .remove = bcm2835_pinctrl_remove,
1063 .driver = {
1064 .name = MODULE_NAME,
1065 .of_match_table = bcm2835_pinctrl_match,
1066 },
1067 };
1068 module_platform_driver(bcm2835_pinctrl_driver);
1069
1070 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1071 MODULE_DESCRIPTION("BCM2835 Pin control driver");
1072 MODULE_LICENSE("GPL");
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