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[mirror_ubuntu-focal-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
1 /*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/irqdesc.h>
30 #include <linux/init.h>
31 #include <linux/of_address.h>
32 #include <linux/of.h>
33 #include <linux/of_irq.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/machine.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinctrl.h>
38 #include <linux/pinctrl/pinmux.h>
39 #include <linux/platform_device.h>
40 #include <linux/seq_file.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
44
45 #define MODULE_NAME "pinctrl-bcm2835"
46 #define BCM2835_NUM_GPIOS 54
47 #define BCM2835_NUM_BANKS 2
48 #define BCM2835_NUM_IRQS 3
49
50 #define BCM2835_PIN_BITMAP_SZ \
51 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
52
53 /* GPIO register offsets */
54 #define GPFSEL0 0x0 /* Function Select */
55 #define GPSET0 0x1c /* Pin Output Set */
56 #define GPCLR0 0x28 /* Pin Output Clear */
57 #define GPLEV0 0x34 /* Pin Level */
58 #define GPEDS0 0x40 /* Pin Event Detect Status */
59 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
60 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
61 #define GPHEN0 0x64 /* Pin High Detect Enable */
62 #define GPLEN0 0x70 /* Pin Low Detect Enable */
63 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
64 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
65 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
66 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
67
68 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
69 #define FSEL_SHIFT(p) (((p) % 10) * 3)
70 #define GPIO_REG_OFFSET(p) ((p) / 32)
71 #define GPIO_REG_SHIFT(p) ((p) % 32)
72
73 enum bcm2835_pinconf_param {
74 /* argument: bcm2835_pinconf_pull */
75 BCM2835_PINCONF_PARAM_PULL,
76 };
77
78 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
79 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
80 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
81
82 struct bcm2835_pinctrl {
83 struct device *dev;
84 void __iomem *base;
85 int irq[BCM2835_NUM_IRQS];
86
87 /* note: locking assumes each bank will have its own unsigned long */
88 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
89 unsigned int irq_type[BCM2835_NUM_GPIOS];
90
91 struct pinctrl_dev *pctl_dev;
92 struct gpio_chip gpio_chip;
93 struct pinctrl_gpio_range gpio_range;
94
95 spinlock_t irq_lock[BCM2835_NUM_BANKS];
96 };
97
98 /* pins are just named GPIO0..GPIO53 */
99 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
100 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
101 BCM2835_GPIO_PIN(0),
102 BCM2835_GPIO_PIN(1),
103 BCM2835_GPIO_PIN(2),
104 BCM2835_GPIO_PIN(3),
105 BCM2835_GPIO_PIN(4),
106 BCM2835_GPIO_PIN(5),
107 BCM2835_GPIO_PIN(6),
108 BCM2835_GPIO_PIN(7),
109 BCM2835_GPIO_PIN(8),
110 BCM2835_GPIO_PIN(9),
111 BCM2835_GPIO_PIN(10),
112 BCM2835_GPIO_PIN(11),
113 BCM2835_GPIO_PIN(12),
114 BCM2835_GPIO_PIN(13),
115 BCM2835_GPIO_PIN(14),
116 BCM2835_GPIO_PIN(15),
117 BCM2835_GPIO_PIN(16),
118 BCM2835_GPIO_PIN(17),
119 BCM2835_GPIO_PIN(18),
120 BCM2835_GPIO_PIN(19),
121 BCM2835_GPIO_PIN(20),
122 BCM2835_GPIO_PIN(21),
123 BCM2835_GPIO_PIN(22),
124 BCM2835_GPIO_PIN(23),
125 BCM2835_GPIO_PIN(24),
126 BCM2835_GPIO_PIN(25),
127 BCM2835_GPIO_PIN(26),
128 BCM2835_GPIO_PIN(27),
129 BCM2835_GPIO_PIN(28),
130 BCM2835_GPIO_PIN(29),
131 BCM2835_GPIO_PIN(30),
132 BCM2835_GPIO_PIN(31),
133 BCM2835_GPIO_PIN(32),
134 BCM2835_GPIO_PIN(33),
135 BCM2835_GPIO_PIN(34),
136 BCM2835_GPIO_PIN(35),
137 BCM2835_GPIO_PIN(36),
138 BCM2835_GPIO_PIN(37),
139 BCM2835_GPIO_PIN(38),
140 BCM2835_GPIO_PIN(39),
141 BCM2835_GPIO_PIN(40),
142 BCM2835_GPIO_PIN(41),
143 BCM2835_GPIO_PIN(42),
144 BCM2835_GPIO_PIN(43),
145 BCM2835_GPIO_PIN(44),
146 BCM2835_GPIO_PIN(45),
147 BCM2835_GPIO_PIN(46),
148 BCM2835_GPIO_PIN(47),
149 BCM2835_GPIO_PIN(48),
150 BCM2835_GPIO_PIN(49),
151 BCM2835_GPIO_PIN(50),
152 BCM2835_GPIO_PIN(51),
153 BCM2835_GPIO_PIN(52),
154 BCM2835_GPIO_PIN(53),
155 };
156
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
159 "gpio0",
160 "gpio1",
161 "gpio2",
162 "gpio3",
163 "gpio4",
164 "gpio5",
165 "gpio6",
166 "gpio7",
167 "gpio8",
168 "gpio9",
169 "gpio10",
170 "gpio11",
171 "gpio12",
172 "gpio13",
173 "gpio14",
174 "gpio15",
175 "gpio16",
176 "gpio17",
177 "gpio18",
178 "gpio19",
179 "gpio20",
180 "gpio21",
181 "gpio22",
182 "gpio23",
183 "gpio24",
184 "gpio25",
185 "gpio26",
186 "gpio27",
187 "gpio28",
188 "gpio29",
189 "gpio30",
190 "gpio31",
191 "gpio32",
192 "gpio33",
193 "gpio34",
194 "gpio35",
195 "gpio36",
196 "gpio37",
197 "gpio38",
198 "gpio39",
199 "gpio40",
200 "gpio41",
201 "gpio42",
202 "gpio43",
203 "gpio44",
204 "gpio45",
205 "gpio46",
206 "gpio47",
207 "gpio48",
208 "gpio49",
209 "gpio50",
210 "gpio51",
211 "gpio52",
212 "gpio53",
213 };
214
215 enum bcm2835_fsel {
216 BCM2835_FSEL_GPIO_IN = 0,
217 BCM2835_FSEL_GPIO_OUT = 1,
218 BCM2835_FSEL_ALT0 = 4,
219 BCM2835_FSEL_ALT1 = 5,
220 BCM2835_FSEL_ALT2 = 6,
221 BCM2835_FSEL_ALT3 = 7,
222 BCM2835_FSEL_ALT4 = 3,
223 BCM2835_FSEL_ALT5 = 2,
224 BCM2835_FSEL_COUNT = 8,
225 BCM2835_FSEL_MASK = 0x7,
226 };
227
228 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
229 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
230 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
231 [BCM2835_FSEL_ALT0] = "alt0",
232 [BCM2835_FSEL_ALT1] = "alt1",
233 [BCM2835_FSEL_ALT2] = "alt2",
234 [BCM2835_FSEL_ALT3] = "alt3",
235 [BCM2835_FSEL_ALT4] = "alt4",
236 [BCM2835_FSEL_ALT5] = "alt5",
237 };
238
239 static const char * const irq_type_names[] = {
240 [IRQ_TYPE_NONE] = "none",
241 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
242 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
243 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
244 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
245 [IRQ_TYPE_LEVEL_LOW] = "level-low",
246 };
247
248 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
249 {
250 return readl(pc->base + reg);
251 }
252
253 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
254 u32 val)
255 {
256 writel(val, pc->base + reg);
257 }
258
259 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
260 unsigned bit)
261 {
262 reg += GPIO_REG_OFFSET(bit) * 4;
263 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
264 }
265
266 /* note NOT a read/modify/write cycle */
267 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
268 unsigned reg, unsigned bit)
269 {
270 reg += GPIO_REG_OFFSET(bit) * 4;
271 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
272 }
273
274 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
275 struct bcm2835_pinctrl *pc, unsigned pin)
276 {
277 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
278 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
279
280 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
281 bcm2835_functions[status]);
282
283 return status;
284 }
285
286 static inline void bcm2835_pinctrl_fsel_set(
287 struct bcm2835_pinctrl *pc, unsigned pin,
288 enum bcm2835_fsel fsel)
289 {
290 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
291 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
292
293 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
294 bcm2835_functions[cur]);
295
296 if (cur == fsel)
297 return;
298
299 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
300 /* always transition through GPIO_IN */
301 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
302 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
303
304 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
305 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
306 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
307 }
308
309 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
310 val |= fsel << FSEL_SHIFT(pin);
311
312 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
313 bcm2835_functions[fsel]);
314 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
315 }
316
317 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
318 {
319 return pinctrl_gpio_direction_input(chip->base + offset);
320 }
321
322 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
323 {
324 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
325
326 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
327 }
328
329 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
330 {
331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
332 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
333
334 /* Alternative function doesn't clearly provide a direction */
335 if (fsel > BCM2835_FSEL_GPIO_OUT)
336 return -EINVAL;
337
338 return (fsel == BCM2835_FSEL_GPIO_IN);
339 }
340
341 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
342 {
343 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
344
345 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
346 }
347
348 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
349 unsigned offset, int value)
350 {
351 bcm2835_gpio_set(chip, offset, value);
352 return pinctrl_gpio_direction_output(chip->base + offset);
353 }
354
355 static const struct gpio_chip bcm2835_gpio_chip = {
356 .label = MODULE_NAME,
357 .owner = THIS_MODULE,
358 .request = gpiochip_generic_request,
359 .free = gpiochip_generic_free,
360 .direction_input = bcm2835_gpio_direction_input,
361 .direction_output = bcm2835_gpio_direction_output,
362 .get_direction = bcm2835_gpio_get_direction,
363 .get = bcm2835_gpio_get,
364 .set = bcm2835_gpio_set,
365 .base = -1,
366 .ngpio = BCM2835_NUM_GPIOS,
367 .can_sleep = false,
368 };
369
370 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
371 unsigned int bank, u32 mask)
372 {
373 unsigned long events;
374 unsigned offset;
375 unsigned gpio;
376 unsigned int type;
377
378 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
379 events &= mask;
380 events &= pc->enabled_irq_map[bank];
381 for_each_set_bit(offset, &events, 32) {
382 gpio = (32 * bank) + offset;
383 /* FIXME: no clue why the code looks up the type here */
384 type = pc->irq_type[gpio];
385
386 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
387 gpio));
388 }
389 }
390
391 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
392 {
393 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
394 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
395 struct irq_chip *host_chip = irq_desc_get_chip(desc);
396 int irq = irq_desc_get_irq(desc);
397 int group;
398 int i;
399
400 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
401 if (pc->irq[i] == irq) {
402 group = i;
403 break;
404 }
405 }
406 /* This should not happen, every IRQ has a bank */
407 if (i == ARRAY_SIZE(pc->irq))
408 BUG();
409
410 chained_irq_enter(host_chip, desc);
411
412 switch (group) {
413 case 0: /* IRQ0 covers GPIOs 0-27 */
414 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
415 break;
416 case 1: /* IRQ1 covers GPIOs 28-45 */
417 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
418 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
419 break;
420 case 2: /* IRQ2 covers GPIOs 46-53 */
421 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
422 break;
423 }
424
425 chained_irq_exit(host_chip, desc);
426 }
427
428 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
429 unsigned reg, unsigned offset, bool enable)
430 {
431 u32 value;
432 reg += GPIO_REG_OFFSET(offset) * 4;
433 value = bcm2835_gpio_rd(pc, reg);
434 if (enable)
435 value |= BIT(GPIO_REG_SHIFT(offset));
436 else
437 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
438 bcm2835_gpio_wr(pc, reg, value);
439 }
440
441 /* fast path for IRQ handler */
442 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
443 unsigned offset, bool enable)
444 {
445 switch (pc->irq_type[offset]) {
446 case IRQ_TYPE_EDGE_RISING:
447 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
448 break;
449
450 case IRQ_TYPE_EDGE_FALLING:
451 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
452 break;
453
454 case IRQ_TYPE_EDGE_BOTH:
455 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
456 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
457 break;
458
459 case IRQ_TYPE_LEVEL_HIGH:
460 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
461 break;
462
463 case IRQ_TYPE_LEVEL_LOW:
464 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
465 break;
466 }
467 }
468
469 static void bcm2835_gpio_irq_enable(struct irq_data *data)
470 {
471 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
472 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
473 unsigned gpio = irqd_to_hwirq(data);
474 unsigned offset = GPIO_REG_SHIFT(gpio);
475 unsigned bank = GPIO_REG_OFFSET(gpio);
476 unsigned long flags;
477
478 spin_lock_irqsave(&pc->irq_lock[bank], flags);
479 set_bit(offset, &pc->enabled_irq_map[bank]);
480 bcm2835_gpio_irq_config(pc, gpio, true);
481 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
482 }
483
484 static void bcm2835_gpio_irq_disable(struct irq_data *data)
485 {
486 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
487 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
488 unsigned gpio = irqd_to_hwirq(data);
489 unsigned offset = GPIO_REG_SHIFT(gpio);
490 unsigned bank = GPIO_REG_OFFSET(gpio);
491 unsigned long flags;
492
493 spin_lock_irqsave(&pc->irq_lock[bank], flags);
494 bcm2835_gpio_irq_config(pc, gpio, false);
495 /* Clear events that were latched prior to clearing event sources */
496 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
497 clear_bit(offset, &pc->enabled_irq_map[bank]);
498 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
499 }
500
501 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
502 unsigned offset, unsigned int type)
503 {
504 switch (type) {
505 case IRQ_TYPE_NONE:
506 case IRQ_TYPE_EDGE_RISING:
507 case IRQ_TYPE_EDGE_FALLING:
508 case IRQ_TYPE_EDGE_BOTH:
509 case IRQ_TYPE_LEVEL_HIGH:
510 case IRQ_TYPE_LEVEL_LOW:
511 pc->irq_type[offset] = type;
512 break;
513
514 default:
515 return -EINVAL;
516 }
517 return 0;
518 }
519
520 /* slower path for reconfiguring IRQ type */
521 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
522 unsigned offset, unsigned int type)
523 {
524 switch (type) {
525 case IRQ_TYPE_NONE:
526 if (pc->irq_type[offset] != type) {
527 bcm2835_gpio_irq_config(pc, offset, false);
528 pc->irq_type[offset] = type;
529 }
530 break;
531
532 case IRQ_TYPE_EDGE_RISING:
533 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
534 /* RISING already enabled, disable FALLING */
535 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
536 bcm2835_gpio_irq_config(pc, offset, false);
537 pc->irq_type[offset] = type;
538 } else if (pc->irq_type[offset] != type) {
539 bcm2835_gpio_irq_config(pc, offset, false);
540 pc->irq_type[offset] = type;
541 bcm2835_gpio_irq_config(pc, offset, true);
542 }
543 break;
544
545 case IRQ_TYPE_EDGE_FALLING:
546 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
547 /* FALLING already enabled, disable RISING */
548 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
549 bcm2835_gpio_irq_config(pc, offset, false);
550 pc->irq_type[offset] = type;
551 } else if (pc->irq_type[offset] != type) {
552 bcm2835_gpio_irq_config(pc, offset, false);
553 pc->irq_type[offset] = type;
554 bcm2835_gpio_irq_config(pc, offset, true);
555 }
556 break;
557
558 case IRQ_TYPE_EDGE_BOTH:
559 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
560 /* RISING already enabled, enable FALLING too */
561 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
562 bcm2835_gpio_irq_config(pc, offset, true);
563 pc->irq_type[offset] = type;
564 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
565 /* FALLING already enabled, enable RISING too */
566 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
567 bcm2835_gpio_irq_config(pc, offset, true);
568 pc->irq_type[offset] = type;
569 } else if (pc->irq_type[offset] != type) {
570 bcm2835_gpio_irq_config(pc, offset, false);
571 pc->irq_type[offset] = type;
572 bcm2835_gpio_irq_config(pc, offset, true);
573 }
574 break;
575
576 case IRQ_TYPE_LEVEL_HIGH:
577 case IRQ_TYPE_LEVEL_LOW:
578 if (pc->irq_type[offset] != type) {
579 bcm2835_gpio_irq_config(pc, offset, false);
580 pc->irq_type[offset] = type;
581 bcm2835_gpio_irq_config(pc, offset, true);
582 }
583 break;
584
585 default:
586 return -EINVAL;
587 }
588 return 0;
589 }
590
591 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
592 {
593 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
594 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
595 unsigned gpio = irqd_to_hwirq(data);
596 unsigned offset = GPIO_REG_SHIFT(gpio);
597 unsigned bank = GPIO_REG_OFFSET(gpio);
598 unsigned long flags;
599 int ret;
600
601 spin_lock_irqsave(&pc->irq_lock[bank], flags);
602
603 if (test_bit(offset, &pc->enabled_irq_map[bank]))
604 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
605 else
606 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
607
608 if (type & IRQ_TYPE_EDGE_BOTH)
609 irq_set_handler_locked(data, handle_edge_irq);
610 else
611 irq_set_handler_locked(data, handle_level_irq);
612
613 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
614
615 return ret;
616 }
617
618 static void bcm2835_gpio_irq_ack(struct irq_data *data)
619 {
620 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
621 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
622 unsigned gpio = irqd_to_hwirq(data);
623
624 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
625 }
626
627 static struct irq_chip bcm2835_gpio_irq_chip = {
628 .name = MODULE_NAME,
629 .irq_enable = bcm2835_gpio_irq_enable,
630 .irq_disable = bcm2835_gpio_irq_disable,
631 .irq_set_type = bcm2835_gpio_irq_set_type,
632 .irq_ack = bcm2835_gpio_irq_ack,
633 .irq_mask = bcm2835_gpio_irq_disable,
634 .irq_unmask = bcm2835_gpio_irq_enable,
635 };
636
637 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
638 {
639 return ARRAY_SIZE(bcm2835_gpio_groups);
640 }
641
642 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
643 unsigned selector)
644 {
645 return bcm2835_gpio_groups[selector];
646 }
647
648 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
649 unsigned selector,
650 const unsigned **pins,
651 unsigned *num_pins)
652 {
653 *pins = &bcm2835_gpio_pins[selector].number;
654 *num_pins = 1;
655
656 return 0;
657 }
658
659 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
660 struct seq_file *s,
661 unsigned offset)
662 {
663 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
664 struct gpio_chip *chip = &pc->gpio_chip;
665 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
666 const char *fname = bcm2835_functions[fsel];
667 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
668 int irq = irq_find_mapping(chip->irqdomain, offset);
669
670 seq_printf(s, "function %s in %s; irq %d (%s)",
671 fname, value ? "hi" : "lo",
672 irq, irq_type_names[pc->irq_type[offset]]);
673 }
674
675 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
676 struct pinctrl_map *maps, unsigned num_maps)
677 {
678 int i;
679
680 for (i = 0; i < num_maps; i++)
681 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
682 kfree(maps[i].data.configs.configs);
683
684 kfree(maps);
685 }
686
687 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
688 struct device_node *np, u32 pin, u32 fnum,
689 struct pinctrl_map **maps)
690 {
691 struct pinctrl_map *map = *maps;
692
693 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
694 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
695 return -EINVAL;
696 }
697
698 map->type = PIN_MAP_TYPE_MUX_GROUP;
699 map->data.mux.group = bcm2835_gpio_groups[pin];
700 map->data.mux.function = bcm2835_functions[fnum];
701 (*maps)++;
702
703 return 0;
704 }
705
706 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
707 struct device_node *np, u32 pin, u32 pull,
708 struct pinctrl_map **maps)
709 {
710 struct pinctrl_map *map = *maps;
711 unsigned long *configs;
712
713 if (pull > 2) {
714 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
715 return -EINVAL;
716 }
717
718 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
719 if (!configs)
720 return -ENOMEM;
721 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
722
723 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
724 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
725 map->data.configs.configs = configs;
726 map->data.configs.num_configs = 1;
727 (*maps)++;
728
729 return 0;
730 }
731
732 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
733 struct device_node *np,
734 struct pinctrl_map **map, unsigned *num_maps)
735 {
736 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
737 struct property *pins, *funcs, *pulls;
738 int num_pins, num_funcs, num_pulls, maps_per_pin;
739 struct pinctrl_map *maps, *cur_map;
740 int i, err;
741 u32 pin, func, pull;
742
743 pins = of_find_property(np, "brcm,pins", NULL);
744 if (!pins) {
745 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
746 return -EINVAL;
747 }
748
749 funcs = of_find_property(np, "brcm,function", NULL);
750 pulls = of_find_property(np, "brcm,pull", NULL);
751
752 if (!funcs && !pulls) {
753 dev_err(pc->dev,
754 "%pOF: neither brcm,function nor brcm,pull specified\n",
755 np);
756 return -EINVAL;
757 }
758
759 num_pins = pins->length / 4;
760 num_funcs = funcs ? (funcs->length / 4) : 0;
761 num_pulls = pulls ? (pulls->length / 4) : 0;
762
763 if (num_funcs > 1 && num_funcs != num_pins) {
764 dev_err(pc->dev,
765 "%pOF: brcm,function must have 1 or %d entries\n",
766 np, num_pins);
767 return -EINVAL;
768 }
769
770 if (num_pulls > 1 && num_pulls != num_pins) {
771 dev_err(pc->dev,
772 "%pOF: brcm,pull must have 1 or %d entries\n",
773 np, num_pins);
774 return -EINVAL;
775 }
776
777 maps_per_pin = 0;
778 if (num_funcs)
779 maps_per_pin++;
780 if (num_pulls)
781 maps_per_pin++;
782 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
783 GFP_KERNEL);
784 if (!maps)
785 return -ENOMEM;
786
787 for (i = 0; i < num_pins; i++) {
788 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
789 if (err)
790 goto out;
791 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
792 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
793 np, pin);
794 err = -EINVAL;
795 goto out;
796 }
797
798 if (num_funcs) {
799 err = of_property_read_u32_index(np, "brcm,function",
800 (num_funcs > 1) ? i : 0, &func);
801 if (err)
802 goto out;
803 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
804 func, &cur_map);
805 if (err)
806 goto out;
807 }
808 if (num_pulls) {
809 err = of_property_read_u32_index(np, "brcm,pull",
810 (num_pulls > 1) ? i : 0, &pull);
811 if (err)
812 goto out;
813 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
814 pull, &cur_map);
815 if (err)
816 goto out;
817 }
818 }
819
820 *map = maps;
821 *num_maps = num_pins * maps_per_pin;
822
823 return 0;
824
825 out:
826 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
827 return err;
828 }
829
830 static const struct pinctrl_ops bcm2835_pctl_ops = {
831 .get_groups_count = bcm2835_pctl_get_groups_count,
832 .get_group_name = bcm2835_pctl_get_group_name,
833 .get_group_pins = bcm2835_pctl_get_group_pins,
834 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
835 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
836 .dt_free_map = bcm2835_pctl_dt_free_map,
837 };
838
839 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
840 unsigned offset)
841 {
842 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
843
844 /* disable by setting to GPIO_IN */
845 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
846 return 0;
847 }
848
849 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
850 {
851 return BCM2835_FSEL_COUNT;
852 }
853
854 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
855 unsigned selector)
856 {
857 return bcm2835_functions[selector];
858 }
859
860 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
861 unsigned selector,
862 const char * const **groups,
863 unsigned * const num_groups)
864 {
865 /* every pin can do every function */
866 *groups = bcm2835_gpio_groups;
867 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
868
869 return 0;
870 }
871
872 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
873 unsigned func_selector,
874 unsigned group_selector)
875 {
876 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
877
878 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
879
880 return 0;
881 }
882
883 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
884 struct pinctrl_gpio_range *range,
885 unsigned offset)
886 {
887 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
888
889 /* disable by setting to GPIO_IN */
890 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
891 }
892
893 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
894 struct pinctrl_gpio_range *range,
895 unsigned offset,
896 bool input)
897 {
898 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
899 enum bcm2835_fsel fsel = input ?
900 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
901
902 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
903
904 return 0;
905 }
906
907 static const struct pinmux_ops bcm2835_pmx_ops = {
908 .free = bcm2835_pmx_free,
909 .get_functions_count = bcm2835_pmx_get_functions_count,
910 .get_function_name = bcm2835_pmx_get_function_name,
911 .get_function_groups = bcm2835_pmx_get_function_groups,
912 .set_mux = bcm2835_pmx_set,
913 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
914 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
915 };
916
917 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
918 unsigned pin, unsigned long *config)
919 {
920 /* No way to read back config in HW */
921 return -ENOTSUPP;
922 }
923
924 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
925 unsigned pin, unsigned long *configs,
926 unsigned num_configs)
927 {
928 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
929 enum bcm2835_pinconf_param param;
930 u16 arg;
931 u32 off, bit;
932 int i;
933
934 for (i = 0; i < num_configs; i++) {
935 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
936 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
937
938 if (param != BCM2835_PINCONF_PARAM_PULL)
939 return -EINVAL;
940
941 off = GPIO_REG_OFFSET(pin);
942 bit = GPIO_REG_SHIFT(pin);
943
944 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
945 /*
946 * BCM2835 datasheet say to wait 150 cycles, but not of what.
947 * But the VideoCore firmware delay for this operation
948 * based nearly on the same amount of VPU cycles and this clock
949 * runs at 250 MHz.
950 */
951 udelay(1);
952 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
953 udelay(1);
954 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
955 } /* for each config */
956
957 return 0;
958 }
959
960 static const struct pinconf_ops bcm2835_pinconf_ops = {
961 .pin_config_get = bcm2835_pinconf_get,
962 .pin_config_set = bcm2835_pinconf_set,
963 };
964
965 static struct pinctrl_desc bcm2835_pinctrl_desc = {
966 .name = MODULE_NAME,
967 .pins = bcm2835_gpio_pins,
968 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
969 .pctlops = &bcm2835_pctl_ops,
970 .pmxops = &bcm2835_pmx_ops,
971 .confops = &bcm2835_pinconf_ops,
972 .owner = THIS_MODULE,
973 };
974
975 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
976 .name = MODULE_NAME,
977 .npins = BCM2835_NUM_GPIOS,
978 };
979
980 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
981 {
982 struct device *dev = &pdev->dev;
983 struct device_node *np = dev->of_node;
984 struct bcm2835_pinctrl *pc;
985 struct resource iomem;
986 int err, i;
987 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
988 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
989
990 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
991 if (!pc)
992 return -ENOMEM;
993
994 platform_set_drvdata(pdev, pc);
995 pc->dev = dev;
996
997 err = of_address_to_resource(np, 0, &iomem);
998 if (err) {
999 dev_err(dev, "could not get IO memory\n");
1000 return err;
1001 }
1002
1003 pc->base = devm_ioremap_resource(dev, &iomem);
1004 if (IS_ERR(pc->base))
1005 return PTR_ERR(pc->base);
1006
1007 pc->gpio_chip = bcm2835_gpio_chip;
1008 pc->gpio_chip.parent = dev;
1009 pc->gpio_chip.of_node = np;
1010
1011 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1012 unsigned long events;
1013 unsigned offset;
1014
1015 /* clear event detection flags */
1016 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1017 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1018 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1019 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1020 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1021 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1022
1023 /* clear all the events */
1024 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1025 for_each_set_bit(offset, &events, 32)
1026 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1027
1028 spin_lock_init(&pc->irq_lock[i]);
1029 }
1030
1031 err = gpiochip_add_data(&pc->gpio_chip, pc);
1032 if (err) {
1033 dev_err(dev, "could not add GPIO chip\n");
1034 return err;
1035 }
1036
1037 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1038 0, handle_level_irq, IRQ_TYPE_NONE);
1039 if (err) {
1040 dev_info(dev, "could not add irqchip\n");
1041 return err;
1042 }
1043
1044 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1045 pc->irq[i] = irq_of_parse_and_map(np, i);
1046
1047 if (pc->irq[i] == 0)
1048 continue;
1049
1050 /*
1051 * Use the same handler for all groups: this is necessary
1052 * since we use one gpiochip to cover all lines - the
1053 * irq handler then needs to figure out which group and
1054 * bank that was firing the IRQ and look up the per-group
1055 * and bank data.
1056 */
1057 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1058 &bcm2835_gpio_irq_chip,
1059 pc->irq[i],
1060 bcm2835_gpio_irq_handler);
1061 }
1062
1063 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1064 if (IS_ERR(pc->pctl_dev)) {
1065 gpiochip_remove(&pc->gpio_chip);
1066 return PTR_ERR(pc->pctl_dev);
1067 }
1068
1069 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1070 pc->gpio_range.base = pc->gpio_chip.base;
1071 pc->gpio_range.gc = &pc->gpio_chip;
1072 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1073
1074 return 0;
1075 }
1076
1077 static const struct of_device_id bcm2835_pinctrl_match[] = {
1078 { .compatible = "brcm,bcm2835-gpio" },
1079 {}
1080 };
1081
1082 static struct platform_driver bcm2835_pinctrl_driver = {
1083 .probe = bcm2835_pinctrl_probe,
1084 .driver = {
1085 .name = MODULE_NAME,
1086 .of_match_table = bcm2835_pinctrl_match,
1087 .suppress_bind_attrs = true,
1088 },
1089 };
1090 builtin_platform_driver(bcm2835_pinctrl_driver);
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