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pinctrl-bcm2835: Set base to 0 give expected gpio numbering
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
1 /*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/irqdesc.h>
31 #include <linux/init.h>
32 #include <linux/irqdomain.h>
33 #include <linux/of_address.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/pinctrl/consumer.h>
37 #include <linux/pinctrl/machine.h>
38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/pinctrl/pinmux.h>
41 #include <linux/platform_device.h>
42 #include <linux/seq_file.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45 #include <linux/types.h>
46
47 #define MODULE_NAME "pinctrl-bcm2835"
48 #define BCM2835_NUM_GPIOS 54
49 #define BCM2835_NUM_BANKS 2
50 #define BCM2835_NUM_IRQS 3
51
52 #define BCM2835_PIN_BITMAP_SZ \
53 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
54
55 /* GPIO register offsets */
56 #define GPFSEL0 0x0 /* Function Select */
57 #define GPSET0 0x1c /* Pin Output Set */
58 #define GPCLR0 0x28 /* Pin Output Clear */
59 #define GPLEV0 0x34 /* Pin Level */
60 #define GPEDS0 0x40 /* Pin Event Detect Status */
61 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
62 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
63 #define GPHEN0 0x64 /* Pin High Detect Enable */
64 #define GPLEN0 0x70 /* Pin Low Detect Enable */
65 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
66 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
67 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
68 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
69
70 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
71 #define FSEL_SHIFT(p) (((p) % 10) * 3)
72 #define GPIO_REG_OFFSET(p) ((p) / 32)
73 #define GPIO_REG_SHIFT(p) ((p) % 32)
74
75 enum bcm2835_pinconf_param {
76 /* argument: bcm2835_pinconf_pull */
77 BCM2835_PINCONF_PARAM_PULL,
78 };
79
80 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
81 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
82 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
83
84 struct bcm2835_gpio_irqdata {
85 struct bcm2835_pinctrl *pc;
86 int irqgroup;
87 };
88
89 struct bcm2835_pinctrl {
90 struct device *dev;
91 void __iomem *base;
92 int irq[BCM2835_NUM_IRQS];
93
94 /* note: locking assumes each bank will have its own unsigned long */
95 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
96 unsigned int irq_type[BCM2835_NUM_GPIOS];
97
98 struct pinctrl_dev *pctl_dev;
99 struct irq_domain *irq_domain;
100 struct gpio_chip gpio_chip;
101 struct pinctrl_gpio_range gpio_range;
102
103 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
104 spinlock_t irq_lock[BCM2835_NUM_BANKS];
105 };
106
107 static struct lock_class_key gpio_lock_class;
108
109 /* pins are just named GPIO0..GPIO53 */
110 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
111 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
112 BCM2835_GPIO_PIN(0),
113 BCM2835_GPIO_PIN(1),
114 BCM2835_GPIO_PIN(2),
115 BCM2835_GPIO_PIN(3),
116 BCM2835_GPIO_PIN(4),
117 BCM2835_GPIO_PIN(5),
118 BCM2835_GPIO_PIN(6),
119 BCM2835_GPIO_PIN(7),
120 BCM2835_GPIO_PIN(8),
121 BCM2835_GPIO_PIN(9),
122 BCM2835_GPIO_PIN(10),
123 BCM2835_GPIO_PIN(11),
124 BCM2835_GPIO_PIN(12),
125 BCM2835_GPIO_PIN(13),
126 BCM2835_GPIO_PIN(14),
127 BCM2835_GPIO_PIN(15),
128 BCM2835_GPIO_PIN(16),
129 BCM2835_GPIO_PIN(17),
130 BCM2835_GPIO_PIN(18),
131 BCM2835_GPIO_PIN(19),
132 BCM2835_GPIO_PIN(20),
133 BCM2835_GPIO_PIN(21),
134 BCM2835_GPIO_PIN(22),
135 BCM2835_GPIO_PIN(23),
136 BCM2835_GPIO_PIN(24),
137 BCM2835_GPIO_PIN(25),
138 BCM2835_GPIO_PIN(26),
139 BCM2835_GPIO_PIN(27),
140 BCM2835_GPIO_PIN(28),
141 BCM2835_GPIO_PIN(29),
142 BCM2835_GPIO_PIN(30),
143 BCM2835_GPIO_PIN(31),
144 BCM2835_GPIO_PIN(32),
145 BCM2835_GPIO_PIN(33),
146 BCM2835_GPIO_PIN(34),
147 BCM2835_GPIO_PIN(35),
148 BCM2835_GPIO_PIN(36),
149 BCM2835_GPIO_PIN(37),
150 BCM2835_GPIO_PIN(38),
151 BCM2835_GPIO_PIN(39),
152 BCM2835_GPIO_PIN(40),
153 BCM2835_GPIO_PIN(41),
154 BCM2835_GPIO_PIN(42),
155 BCM2835_GPIO_PIN(43),
156 BCM2835_GPIO_PIN(44),
157 BCM2835_GPIO_PIN(45),
158 BCM2835_GPIO_PIN(46),
159 BCM2835_GPIO_PIN(47),
160 BCM2835_GPIO_PIN(48),
161 BCM2835_GPIO_PIN(49),
162 BCM2835_GPIO_PIN(50),
163 BCM2835_GPIO_PIN(51),
164 BCM2835_GPIO_PIN(52),
165 BCM2835_GPIO_PIN(53),
166 };
167
168 /* one pin per group */
169 static const char * const bcm2835_gpio_groups[] = {
170 "gpio0",
171 "gpio1",
172 "gpio2",
173 "gpio3",
174 "gpio4",
175 "gpio5",
176 "gpio6",
177 "gpio7",
178 "gpio8",
179 "gpio9",
180 "gpio10",
181 "gpio11",
182 "gpio12",
183 "gpio13",
184 "gpio14",
185 "gpio15",
186 "gpio16",
187 "gpio17",
188 "gpio18",
189 "gpio19",
190 "gpio20",
191 "gpio21",
192 "gpio22",
193 "gpio23",
194 "gpio24",
195 "gpio25",
196 "gpio26",
197 "gpio27",
198 "gpio28",
199 "gpio29",
200 "gpio30",
201 "gpio31",
202 "gpio32",
203 "gpio33",
204 "gpio34",
205 "gpio35",
206 "gpio36",
207 "gpio37",
208 "gpio38",
209 "gpio39",
210 "gpio40",
211 "gpio41",
212 "gpio42",
213 "gpio43",
214 "gpio44",
215 "gpio45",
216 "gpio46",
217 "gpio47",
218 "gpio48",
219 "gpio49",
220 "gpio50",
221 "gpio51",
222 "gpio52",
223 "gpio53",
224 };
225
226 enum bcm2835_fsel {
227 BCM2835_FSEL_GPIO_IN = 0,
228 BCM2835_FSEL_GPIO_OUT = 1,
229 BCM2835_FSEL_ALT0 = 4,
230 BCM2835_FSEL_ALT1 = 5,
231 BCM2835_FSEL_ALT2 = 6,
232 BCM2835_FSEL_ALT3 = 7,
233 BCM2835_FSEL_ALT4 = 3,
234 BCM2835_FSEL_ALT5 = 2,
235 BCM2835_FSEL_COUNT = 8,
236 BCM2835_FSEL_MASK = 0x7,
237 };
238
239 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
240 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
241 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
242 [BCM2835_FSEL_ALT0] = "alt0",
243 [BCM2835_FSEL_ALT1] = "alt1",
244 [BCM2835_FSEL_ALT2] = "alt2",
245 [BCM2835_FSEL_ALT3] = "alt3",
246 [BCM2835_FSEL_ALT4] = "alt4",
247 [BCM2835_FSEL_ALT5] = "alt5",
248 };
249
250 static const char * const irq_type_names[] = {
251 [IRQ_TYPE_NONE] = "none",
252 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
253 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
254 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
255 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
256 [IRQ_TYPE_LEVEL_LOW] = "level-low",
257 };
258
259 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
260 {
261 return readl(pc->base + reg);
262 }
263
264 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
265 u32 val)
266 {
267 writel(val, pc->base + reg);
268 }
269
270 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
271 unsigned bit)
272 {
273 reg += GPIO_REG_OFFSET(bit) * 4;
274 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
275 }
276
277 /* note NOT a read/modify/write cycle */
278 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
279 unsigned reg, unsigned bit)
280 {
281 reg += GPIO_REG_OFFSET(bit) * 4;
282 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
283 }
284
285 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
286 struct bcm2835_pinctrl *pc, unsigned pin)
287 {
288 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
289 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
290
291 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
292 bcm2835_functions[status]);
293
294 return status;
295 }
296
297 static inline void bcm2835_pinctrl_fsel_set(
298 struct bcm2835_pinctrl *pc, unsigned pin,
299 enum bcm2835_fsel fsel)
300 {
301 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
302 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
303
304 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
305 bcm2835_functions[cur]);
306
307 if (cur == fsel)
308 return;
309
310 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
311 /* always transition through GPIO_IN */
312 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
313 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
314
315 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
316 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
317 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
318 }
319
320 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
321 val |= fsel << FSEL_SHIFT(pin);
322
323 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
324 bcm2835_functions[fsel]);
325 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
326 }
327
328 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
329 {
330 return pinctrl_gpio_direction_input(chip->base + offset);
331 }
332
333 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
334 {
335 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
336
337 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
338 }
339
340 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
341 {
342 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
343 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
344
345 /* Alternative function doesn't clearly provide a direction */
346 if (fsel > BCM2835_FSEL_GPIO_OUT)
347 return -EINVAL;
348
349 return (fsel == BCM2835_FSEL_GPIO_IN);
350 }
351
352 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
353 {
354 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
355
356 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
357 }
358
359 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
360 unsigned offset, int value)
361 {
362 bcm2835_gpio_set(chip, offset, value);
363 return pinctrl_gpio_direction_output(chip->base + offset);
364 }
365
366 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
367 {
368 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
369
370 return irq_linear_revmap(pc->irq_domain, offset);
371 }
372
373 static struct gpio_chip bcm2835_gpio_chip = {
374 .label = MODULE_NAME,
375 .owner = THIS_MODULE,
376 .request = gpiochip_generic_request,
377 .free = gpiochip_generic_free,
378 .direction_input = bcm2835_gpio_direction_input,
379 .direction_output = bcm2835_gpio_direction_output,
380 .get_direction = bcm2835_gpio_get_direction,
381 .get = bcm2835_gpio_get,
382 .set = bcm2835_gpio_set,
383 .to_irq = bcm2835_gpio_to_irq,
384 .base = 0,
385 .ngpio = BCM2835_NUM_GPIOS,
386 .can_sleep = false,
387 };
388
389 static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
390 unsigned int bank, u32 mask)
391 {
392 unsigned long events;
393 unsigned offset;
394 unsigned gpio;
395 unsigned int type;
396
397 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
398 events &= mask;
399 events &= pc->enabled_irq_map[bank];
400 for_each_set_bit(offset, &events, 32) {
401 gpio = (32 * bank) + offset;
402 type = pc->irq_type[gpio];
403
404 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
405 }
406
407 return (events != 0);
408 }
409
410 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
411 {
412 struct bcm2835_gpio_irqdata *irqdata = dev_id;
413 struct bcm2835_pinctrl *pc = irqdata->pc;
414 int handled = 0;
415
416 switch (irqdata->irqgroup) {
417 case 0: /* IRQ0 covers GPIOs 0-27 */
418 handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
419 break;
420 case 1: /* IRQ1 covers GPIOs 28-45 */
421 handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
422 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
423 break;
424 case 2: /* IRQ2 covers GPIOs 46-53 */
425 handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
426 break;
427 }
428
429 return handled ? IRQ_HANDLED : IRQ_NONE;
430 }
431
432 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
433 unsigned reg, unsigned offset, bool enable)
434 {
435 u32 value;
436 reg += GPIO_REG_OFFSET(offset) * 4;
437 value = bcm2835_gpio_rd(pc, reg);
438 if (enable)
439 value |= BIT(GPIO_REG_SHIFT(offset));
440 else
441 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
442 bcm2835_gpio_wr(pc, reg, value);
443 }
444
445 /* fast path for IRQ handler */
446 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
447 unsigned offset, bool enable)
448 {
449 switch (pc->irq_type[offset]) {
450 case IRQ_TYPE_EDGE_RISING:
451 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
452 break;
453
454 case IRQ_TYPE_EDGE_FALLING:
455 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
456 break;
457
458 case IRQ_TYPE_EDGE_BOTH:
459 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
460 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
461 break;
462
463 case IRQ_TYPE_LEVEL_HIGH:
464 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
465 break;
466
467 case IRQ_TYPE_LEVEL_LOW:
468 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
469 break;
470 }
471 }
472
473 static void bcm2835_gpio_irq_enable(struct irq_data *data)
474 {
475 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
476 unsigned gpio = irqd_to_hwirq(data);
477 unsigned offset = GPIO_REG_SHIFT(gpio);
478 unsigned bank = GPIO_REG_OFFSET(gpio);
479 unsigned long flags;
480
481 spin_lock_irqsave(&pc->irq_lock[bank], flags);
482 set_bit(offset, &pc->enabled_irq_map[bank]);
483 bcm2835_gpio_irq_config(pc, gpio, true);
484 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
485 }
486
487 static void bcm2835_gpio_irq_disable(struct irq_data *data)
488 {
489 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
490 unsigned gpio = irqd_to_hwirq(data);
491 unsigned offset = GPIO_REG_SHIFT(gpio);
492 unsigned bank = GPIO_REG_OFFSET(gpio);
493 unsigned long flags;
494
495 spin_lock_irqsave(&pc->irq_lock[bank], flags);
496 bcm2835_gpio_irq_config(pc, gpio, false);
497 /* Clear events that were latched prior to clearing event sources */
498 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
499 clear_bit(offset, &pc->enabled_irq_map[bank]);
500 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
501 }
502
503 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
504 unsigned offset, unsigned int type)
505 {
506 switch (type) {
507 case IRQ_TYPE_NONE:
508 case IRQ_TYPE_EDGE_RISING:
509 case IRQ_TYPE_EDGE_FALLING:
510 case IRQ_TYPE_EDGE_BOTH:
511 case IRQ_TYPE_LEVEL_HIGH:
512 case IRQ_TYPE_LEVEL_LOW:
513 pc->irq_type[offset] = type;
514 break;
515
516 default:
517 return -EINVAL;
518 }
519 return 0;
520 }
521
522 /* slower path for reconfiguring IRQ type */
523 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
524 unsigned offset, unsigned int type)
525 {
526 switch (type) {
527 case IRQ_TYPE_NONE:
528 if (pc->irq_type[offset] != type) {
529 bcm2835_gpio_irq_config(pc, offset, false);
530 pc->irq_type[offset] = type;
531 }
532 break;
533
534 case IRQ_TYPE_EDGE_RISING:
535 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
536 /* RISING already enabled, disable FALLING */
537 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
538 bcm2835_gpio_irq_config(pc, offset, false);
539 pc->irq_type[offset] = type;
540 } else if (pc->irq_type[offset] != type) {
541 bcm2835_gpio_irq_config(pc, offset, false);
542 pc->irq_type[offset] = type;
543 bcm2835_gpio_irq_config(pc, offset, true);
544 }
545 break;
546
547 case IRQ_TYPE_EDGE_FALLING:
548 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
549 /* FALLING already enabled, disable RISING */
550 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
551 bcm2835_gpio_irq_config(pc, offset, false);
552 pc->irq_type[offset] = type;
553 } else if (pc->irq_type[offset] != type) {
554 bcm2835_gpio_irq_config(pc, offset, false);
555 pc->irq_type[offset] = type;
556 bcm2835_gpio_irq_config(pc, offset, true);
557 }
558 break;
559
560 case IRQ_TYPE_EDGE_BOTH:
561 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
562 /* RISING already enabled, enable FALLING too */
563 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
564 bcm2835_gpio_irq_config(pc, offset, true);
565 pc->irq_type[offset] = type;
566 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
567 /* FALLING already enabled, enable RISING too */
568 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
569 bcm2835_gpio_irq_config(pc, offset, true);
570 pc->irq_type[offset] = type;
571 } else if (pc->irq_type[offset] != type) {
572 bcm2835_gpio_irq_config(pc, offset, false);
573 pc->irq_type[offset] = type;
574 bcm2835_gpio_irq_config(pc, offset, true);
575 }
576 break;
577
578 case IRQ_TYPE_LEVEL_HIGH:
579 case IRQ_TYPE_LEVEL_LOW:
580 if (pc->irq_type[offset] != type) {
581 bcm2835_gpio_irq_config(pc, offset, false);
582 pc->irq_type[offset] = type;
583 bcm2835_gpio_irq_config(pc, offset, true);
584 }
585 break;
586
587 default:
588 return -EINVAL;
589 }
590 return 0;
591 }
592
593 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
594 {
595 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
596 unsigned gpio = irqd_to_hwirq(data);
597 unsigned offset = GPIO_REG_SHIFT(gpio);
598 unsigned bank = GPIO_REG_OFFSET(gpio);
599 unsigned long flags;
600 int ret;
601
602 spin_lock_irqsave(&pc->irq_lock[bank], flags);
603
604 if (test_bit(offset, &pc->enabled_irq_map[bank]))
605 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
606 else
607 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
608
609 if (type & IRQ_TYPE_EDGE_BOTH)
610 irq_set_handler_locked(data, handle_edge_irq);
611 else
612 irq_set_handler_locked(data, handle_level_irq);
613
614 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
615
616 return ret;
617 }
618
619 static void bcm2835_gpio_irq_ack(struct irq_data *data)
620 {
621 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
622 unsigned gpio = irqd_to_hwirq(data);
623
624 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
625 }
626
627 static struct irq_chip bcm2835_gpio_irq_chip = {
628 .name = MODULE_NAME,
629 .irq_enable = bcm2835_gpio_irq_enable,
630 .irq_disable = bcm2835_gpio_irq_disable,
631 .irq_set_type = bcm2835_gpio_irq_set_type,
632 .irq_ack = bcm2835_gpio_irq_ack,
633 .irq_mask = bcm2835_gpio_irq_disable,
634 .irq_unmask = bcm2835_gpio_irq_enable,
635 };
636
637 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
638 {
639 return ARRAY_SIZE(bcm2835_gpio_groups);
640 }
641
642 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
643 unsigned selector)
644 {
645 return bcm2835_gpio_groups[selector];
646 }
647
648 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
649 unsigned selector,
650 const unsigned **pins,
651 unsigned *num_pins)
652 {
653 *pins = &bcm2835_gpio_pins[selector].number;
654 *num_pins = 1;
655
656 return 0;
657 }
658
659 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
660 struct seq_file *s,
661 unsigned offset)
662 {
663 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
664 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
665 const char *fname = bcm2835_functions[fsel];
666 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
667 int irq = irq_find_mapping(pc->irq_domain, offset);
668
669 seq_printf(s, "function %s in %s; irq %d (%s)",
670 fname, value ? "hi" : "lo",
671 irq, irq_type_names[pc->irq_type[offset]]);
672 }
673
674 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
675 struct pinctrl_map *maps, unsigned num_maps)
676 {
677 int i;
678
679 for (i = 0; i < num_maps; i++)
680 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
681 kfree(maps[i].data.configs.configs);
682
683 kfree(maps);
684 }
685
686 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
687 struct device_node *np, u32 pin, u32 fnum,
688 struct pinctrl_map **maps)
689 {
690 struct pinctrl_map *map = *maps;
691
692 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
693 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
694 of_node_full_name(np), fnum);
695 return -EINVAL;
696 }
697
698 map->type = PIN_MAP_TYPE_MUX_GROUP;
699 map->data.mux.group = bcm2835_gpio_groups[pin];
700 map->data.mux.function = bcm2835_functions[fnum];
701 (*maps)++;
702
703 return 0;
704 }
705
706 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
707 struct device_node *np, u32 pin, u32 pull,
708 struct pinctrl_map **maps)
709 {
710 struct pinctrl_map *map = *maps;
711 unsigned long *configs;
712
713 if (pull > 2) {
714 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
715 of_node_full_name(np), pull);
716 return -EINVAL;
717 }
718
719 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
720 if (!configs)
721 return -ENOMEM;
722 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
723
724 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
725 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
726 map->data.configs.configs = configs;
727 map->data.configs.num_configs = 1;
728 (*maps)++;
729
730 return 0;
731 }
732
733 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
734 struct device_node *np,
735 struct pinctrl_map **map, unsigned *num_maps)
736 {
737 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
738 struct property *pins, *funcs, *pulls;
739 int num_pins, num_funcs, num_pulls, maps_per_pin;
740 struct pinctrl_map *maps, *cur_map;
741 int i, err;
742 u32 pin, func, pull;
743
744 pins = of_find_property(np, "brcm,pins", NULL);
745 if (!pins) {
746 dev_err(pc->dev, "%s: missing brcm,pins property\n",
747 of_node_full_name(np));
748 return -EINVAL;
749 }
750
751 funcs = of_find_property(np, "brcm,function", NULL);
752 pulls = of_find_property(np, "brcm,pull", NULL);
753
754 if (!funcs && !pulls) {
755 dev_err(pc->dev,
756 "%s: neither brcm,function nor brcm,pull specified\n",
757 of_node_full_name(np));
758 return -EINVAL;
759 }
760
761 num_pins = pins->length / 4;
762 num_funcs = funcs ? (funcs->length / 4) : 0;
763 num_pulls = pulls ? (pulls->length / 4) : 0;
764
765 if (num_funcs > 1 && num_funcs != num_pins) {
766 dev_err(pc->dev,
767 "%s: brcm,function must have 1 or %d entries\n",
768 of_node_full_name(np), num_pins);
769 return -EINVAL;
770 }
771
772 if (num_pulls > 1 && num_pulls != num_pins) {
773 dev_err(pc->dev,
774 "%s: brcm,pull must have 1 or %d entries\n",
775 of_node_full_name(np), num_pins);
776 return -EINVAL;
777 }
778
779 maps_per_pin = 0;
780 if (num_funcs)
781 maps_per_pin++;
782 if (num_pulls)
783 maps_per_pin++;
784 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
785 GFP_KERNEL);
786 if (!maps)
787 return -ENOMEM;
788
789 for (i = 0; i < num_pins; i++) {
790 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
791 if (err)
792 goto out;
793 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
794 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
795 of_node_full_name(np), pin);
796 err = -EINVAL;
797 goto out;
798 }
799
800 if (num_funcs) {
801 err = of_property_read_u32_index(np, "brcm,function",
802 (num_funcs > 1) ? i : 0, &func);
803 if (err)
804 goto out;
805 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
806 func, &cur_map);
807 if (err)
808 goto out;
809 }
810 if (num_pulls) {
811 err = of_property_read_u32_index(np, "brcm,pull",
812 (num_pulls > 1) ? i : 0, &pull);
813 if (err)
814 goto out;
815 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
816 pull, &cur_map);
817 if (err)
818 goto out;
819 }
820 }
821
822 *map = maps;
823 *num_maps = num_pins * maps_per_pin;
824
825 return 0;
826
827 out:
828 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
829 return err;
830 }
831
832 static const struct pinctrl_ops bcm2835_pctl_ops = {
833 .get_groups_count = bcm2835_pctl_get_groups_count,
834 .get_group_name = bcm2835_pctl_get_group_name,
835 .get_group_pins = bcm2835_pctl_get_group_pins,
836 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
837 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
838 .dt_free_map = bcm2835_pctl_dt_free_map,
839 };
840
841 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
842 unsigned offset)
843 {
844 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
845
846 /* disable by setting to GPIO_IN */
847 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
848 return 0;
849 }
850
851 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
852 {
853 return BCM2835_FSEL_COUNT;
854 }
855
856 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
857 unsigned selector)
858 {
859 return bcm2835_functions[selector];
860 }
861
862 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
863 unsigned selector,
864 const char * const **groups,
865 unsigned * const num_groups)
866 {
867 /* every pin can do every function */
868 *groups = bcm2835_gpio_groups;
869 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
870
871 return 0;
872 }
873
874 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
875 unsigned func_selector,
876 unsigned group_selector)
877 {
878 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
879
880 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
881
882 return 0;
883 }
884
885 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
886 struct pinctrl_gpio_range *range,
887 unsigned offset)
888 {
889 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
890
891 /* disable by setting to GPIO_IN */
892 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
893 }
894
895 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
896 struct pinctrl_gpio_range *range,
897 unsigned offset,
898 bool input)
899 {
900 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
901 enum bcm2835_fsel fsel = input ?
902 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
903
904 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
905
906 return 0;
907 }
908
909 static const struct pinmux_ops bcm2835_pmx_ops = {
910 .free = bcm2835_pmx_free,
911 .get_functions_count = bcm2835_pmx_get_functions_count,
912 .get_function_name = bcm2835_pmx_get_function_name,
913 .get_function_groups = bcm2835_pmx_get_function_groups,
914 .set_mux = bcm2835_pmx_set,
915 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
916 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
917 };
918
919 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
920 unsigned pin, unsigned long *config)
921 {
922 /* No way to read back config in HW */
923 return -ENOTSUPP;
924 }
925
926 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
927 unsigned pin, unsigned long *configs,
928 unsigned num_configs)
929 {
930 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
931 enum bcm2835_pinconf_param param;
932 u16 arg;
933 u32 off, bit;
934 int i;
935
936 for (i = 0; i < num_configs; i++) {
937 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
938 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
939
940 if (param != BCM2835_PINCONF_PARAM_PULL)
941 return -EINVAL;
942
943 off = GPIO_REG_OFFSET(pin);
944 bit = GPIO_REG_SHIFT(pin);
945
946 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
947 /*
948 * BCM2835 datasheet say to wait 150 cycles, but not of what.
949 * But the VideoCore firmware delay for this operation
950 * based nearly on the same amount of VPU cycles and this clock
951 * runs at 250 MHz.
952 */
953 udelay(1);
954 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
955 udelay(1);
956 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
957 } /* for each config */
958
959 return 0;
960 }
961
962 static const struct pinconf_ops bcm2835_pinconf_ops = {
963 .pin_config_get = bcm2835_pinconf_get,
964 .pin_config_set = bcm2835_pinconf_set,
965 };
966
967 static struct pinctrl_desc bcm2835_pinctrl_desc = {
968 .name = MODULE_NAME,
969 .pins = bcm2835_gpio_pins,
970 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
971 .pctlops = &bcm2835_pctl_ops,
972 .pmxops = &bcm2835_pmx_ops,
973 .confops = &bcm2835_pinconf_ops,
974 .owner = THIS_MODULE,
975 };
976
977 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
978 .name = MODULE_NAME,
979 .npins = BCM2835_NUM_GPIOS,
980 };
981
982 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
983 {
984 struct device *dev = &pdev->dev;
985 struct device_node *np = dev->of_node;
986 struct bcm2835_pinctrl *pc;
987 struct resource iomem;
988 int err, i;
989 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
990 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
991
992 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
993 if (!pc)
994 return -ENOMEM;
995
996 platform_set_drvdata(pdev, pc);
997 pc->dev = dev;
998
999 err = of_address_to_resource(np, 0, &iomem);
1000 if (err) {
1001 dev_err(dev, "could not get IO memory\n");
1002 return err;
1003 }
1004
1005 pc->base = devm_ioremap_resource(dev, &iomem);
1006 if (IS_ERR(pc->base))
1007 return PTR_ERR(pc->base);
1008
1009 pc->gpio_chip = bcm2835_gpio_chip;
1010 pc->gpio_chip.parent = dev;
1011 pc->gpio_chip.of_node = np;
1012
1013 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
1014 &irq_domain_simple_ops, NULL);
1015 if (!pc->irq_domain) {
1016 dev_err(dev, "could not create IRQ domain\n");
1017 return -ENOMEM;
1018 }
1019
1020 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
1021 int irq = irq_create_mapping(pc->irq_domain, i);
1022 irq_set_lockdep_class(irq, &gpio_lock_class);
1023 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
1024 handle_level_irq);
1025 irq_set_chip_data(irq, pc);
1026 }
1027
1028 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1029 unsigned long events;
1030 unsigned offset;
1031
1032 /* clear event detection flags */
1033 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1034 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1035 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1036 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1037 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1038 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1039
1040 /* clear all the events */
1041 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1042 for_each_set_bit(offset, &events, 32)
1043 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1044
1045 spin_lock_init(&pc->irq_lock[i]);
1046 }
1047
1048 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1049 int len;
1050 char *name;
1051 pc->irq[i] = irq_of_parse_and_map(np, i);
1052 pc->irq_data[i].pc = pc;
1053 pc->irq_data[i].irqgroup = i;
1054
1055 len = strlen(dev_name(pc->dev)) + 16;
1056 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1057 if (!name)
1058 return -ENOMEM;
1059 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1060
1061 err = devm_request_irq(dev, pc->irq[i],
1062 bcm2835_gpio_irq_handler, IRQF_SHARED,
1063 name, &pc->irq_data[i]);
1064 if (err) {
1065 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1066 return err;
1067 }
1068 }
1069
1070 err = gpiochip_add_data(&pc->gpio_chip, pc);
1071 if (err) {
1072 dev_err(dev, "could not add GPIO chip\n");
1073 return err;
1074 }
1075
1076 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1077 if (IS_ERR(pc->pctl_dev)) {
1078 gpiochip_remove(&pc->gpio_chip);
1079 return PTR_ERR(pc->pctl_dev);
1080 }
1081
1082 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1083 pc->gpio_range.base = pc->gpio_chip.base;
1084 pc->gpio_range.gc = &pc->gpio_chip;
1085 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1086
1087 return 0;
1088 }
1089
1090 static const struct of_device_id bcm2835_pinctrl_match[] = {
1091 { .compatible = "brcm,bcm2835-gpio" },
1092 {}
1093 };
1094
1095 static struct platform_driver bcm2835_pinctrl_driver = {
1096 .probe = bcm2835_pinctrl_probe,
1097 .driver = {
1098 .name = MODULE_NAME,
1099 .of_match_table = bcm2835_pinctrl_match,
1100 .suppress_bind_attrs = true,
1101 },
1102 };
1103 builtin_platform_driver(bcm2835_pinctrl_driver);
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