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UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / pinctrl / bcm / pinctrl-bcm2835.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 *
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 *
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
10 */
11
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_address.h>
24 #include <linux/of.h>
25 #include <linux/of_irq.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/machine.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
34 #include <linux/slab.h>
35 #include <linux/spinlock.h>
36 #include <linux/types.h>
37 #include <dt-bindings/pinctrl/bcm2835.h>
38
39 #define MODULE_NAME "pinctrl-bcm2835"
40 #define BCM2835_NUM_GPIOS 54
41 #define BCM2711_NUM_GPIOS 58
42 #define BCM2835_NUM_BANKS 2
43 #define BCM2835_NUM_IRQS 3
44
45 /* GPIO register offsets */
46 #define GPFSEL0 0x0 /* Function Select */
47 #define GPSET0 0x1c /* Pin Output Set */
48 #define GPCLR0 0x28 /* Pin Output Clear */
49 #define GPLEV0 0x34 /* Pin Level */
50 #define GPEDS0 0x40 /* Pin Event Detect Status */
51 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
52 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
53 #define GPHEN0 0x64 /* Pin High Detect Enable */
54 #define GPLEN0 0x70 /* Pin Low Detect Enable */
55 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
56 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
57 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
58 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
59 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
60
61 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
62 #define FSEL_SHIFT(p) (((p) % 10) * 3)
63 #define GPIO_REG_OFFSET(p) ((p) / 32)
64 #define GPIO_REG_SHIFT(p) ((p) % 32)
65
66 #define PUD_2711_MASK 0x3
67 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
68 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
69
70 /* argument: bcm2835_pinconf_pull */
71 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
72
73 #define BCM2711_PULL_NONE 0x0
74 #define BCM2711_PULL_UP 0x1
75 #define BCM2711_PULL_DOWN 0x2
76
77 struct bcm2835_pinctrl {
78 struct device *dev;
79 void __iomem *base;
80 int *wake_irq;
81
82 /* note: locking assumes each bank will have its own unsigned long */
83 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
84 unsigned int irq_type[BCM2711_NUM_GPIOS];
85
86 struct pinctrl_dev *pctl_dev;
87 struct gpio_chip gpio_chip;
88 struct pinctrl_desc pctl_desc;
89 struct pinctrl_gpio_range gpio_range;
90
91 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
92 };
93
94 /* pins are just named GPIO0..GPIO53 */
95 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
96 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
97 BCM2835_GPIO_PIN(0),
98 BCM2835_GPIO_PIN(1),
99 BCM2835_GPIO_PIN(2),
100 BCM2835_GPIO_PIN(3),
101 BCM2835_GPIO_PIN(4),
102 BCM2835_GPIO_PIN(5),
103 BCM2835_GPIO_PIN(6),
104 BCM2835_GPIO_PIN(7),
105 BCM2835_GPIO_PIN(8),
106 BCM2835_GPIO_PIN(9),
107 BCM2835_GPIO_PIN(10),
108 BCM2835_GPIO_PIN(11),
109 BCM2835_GPIO_PIN(12),
110 BCM2835_GPIO_PIN(13),
111 BCM2835_GPIO_PIN(14),
112 BCM2835_GPIO_PIN(15),
113 BCM2835_GPIO_PIN(16),
114 BCM2835_GPIO_PIN(17),
115 BCM2835_GPIO_PIN(18),
116 BCM2835_GPIO_PIN(19),
117 BCM2835_GPIO_PIN(20),
118 BCM2835_GPIO_PIN(21),
119 BCM2835_GPIO_PIN(22),
120 BCM2835_GPIO_PIN(23),
121 BCM2835_GPIO_PIN(24),
122 BCM2835_GPIO_PIN(25),
123 BCM2835_GPIO_PIN(26),
124 BCM2835_GPIO_PIN(27),
125 BCM2835_GPIO_PIN(28),
126 BCM2835_GPIO_PIN(29),
127 BCM2835_GPIO_PIN(30),
128 BCM2835_GPIO_PIN(31),
129 BCM2835_GPIO_PIN(32),
130 BCM2835_GPIO_PIN(33),
131 BCM2835_GPIO_PIN(34),
132 BCM2835_GPIO_PIN(35),
133 BCM2835_GPIO_PIN(36),
134 BCM2835_GPIO_PIN(37),
135 BCM2835_GPIO_PIN(38),
136 BCM2835_GPIO_PIN(39),
137 BCM2835_GPIO_PIN(40),
138 BCM2835_GPIO_PIN(41),
139 BCM2835_GPIO_PIN(42),
140 BCM2835_GPIO_PIN(43),
141 BCM2835_GPIO_PIN(44),
142 BCM2835_GPIO_PIN(45),
143 BCM2835_GPIO_PIN(46),
144 BCM2835_GPIO_PIN(47),
145 BCM2835_GPIO_PIN(48),
146 BCM2835_GPIO_PIN(49),
147 BCM2835_GPIO_PIN(50),
148 BCM2835_GPIO_PIN(51),
149 BCM2835_GPIO_PIN(52),
150 BCM2835_GPIO_PIN(53),
151 BCM2835_GPIO_PIN(54),
152 BCM2835_GPIO_PIN(55),
153 BCM2835_GPIO_PIN(56),
154 BCM2835_GPIO_PIN(57),
155 };
156
157 /* one pin per group */
158 static const char * const bcm2835_gpio_groups[] = {
159 "gpio0",
160 "gpio1",
161 "gpio2",
162 "gpio3",
163 "gpio4",
164 "gpio5",
165 "gpio6",
166 "gpio7",
167 "gpio8",
168 "gpio9",
169 "gpio10",
170 "gpio11",
171 "gpio12",
172 "gpio13",
173 "gpio14",
174 "gpio15",
175 "gpio16",
176 "gpio17",
177 "gpio18",
178 "gpio19",
179 "gpio20",
180 "gpio21",
181 "gpio22",
182 "gpio23",
183 "gpio24",
184 "gpio25",
185 "gpio26",
186 "gpio27",
187 "gpio28",
188 "gpio29",
189 "gpio30",
190 "gpio31",
191 "gpio32",
192 "gpio33",
193 "gpio34",
194 "gpio35",
195 "gpio36",
196 "gpio37",
197 "gpio38",
198 "gpio39",
199 "gpio40",
200 "gpio41",
201 "gpio42",
202 "gpio43",
203 "gpio44",
204 "gpio45",
205 "gpio46",
206 "gpio47",
207 "gpio48",
208 "gpio49",
209 "gpio50",
210 "gpio51",
211 "gpio52",
212 "gpio53",
213 "gpio54",
214 "gpio55",
215 "gpio56",
216 "gpio57",
217 };
218
219 enum bcm2835_fsel {
220 BCM2835_FSEL_COUNT = 8,
221 BCM2835_FSEL_MASK = 0x7,
222 };
223
224 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
225 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
226 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
227 [BCM2835_FSEL_ALT0] = "alt0",
228 [BCM2835_FSEL_ALT1] = "alt1",
229 [BCM2835_FSEL_ALT2] = "alt2",
230 [BCM2835_FSEL_ALT3] = "alt3",
231 [BCM2835_FSEL_ALT4] = "alt4",
232 [BCM2835_FSEL_ALT5] = "alt5",
233 };
234
235 static const char * const irq_type_names[] = {
236 [IRQ_TYPE_NONE] = "none",
237 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
238 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
239 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
240 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
241 [IRQ_TYPE_LEVEL_LOW] = "level-low",
242 };
243
244 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
245 {
246 return readl(pc->base + reg);
247 }
248
249 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
250 u32 val)
251 {
252 writel(val, pc->base + reg);
253 }
254
255 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
256 unsigned bit)
257 {
258 reg += GPIO_REG_OFFSET(bit) * 4;
259 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
260 }
261
262 /* note NOT a read/modify/write cycle */
263 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
264 unsigned reg, unsigned bit)
265 {
266 reg += GPIO_REG_OFFSET(bit) * 4;
267 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
268 }
269
270 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
271 struct bcm2835_pinctrl *pc, unsigned pin)
272 {
273 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
274 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
275
276 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
277 bcm2835_functions[status]);
278
279 return status;
280 }
281
282 static inline void bcm2835_pinctrl_fsel_set(
283 struct bcm2835_pinctrl *pc, unsigned pin,
284 enum bcm2835_fsel fsel)
285 {
286 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
287 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
288
289 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
290 bcm2835_functions[cur]);
291
292 if (cur == fsel)
293 return;
294
295 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
296 /* always transition through GPIO_IN */
297 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
298 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
299
300 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
301 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
302 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
303 }
304
305 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
306 val |= fsel << FSEL_SHIFT(pin);
307
308 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
309 bcm2835_functions[fsel]);
310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
311 }
312
313 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
314 {
315 return pinctrl_gpio_direction_input(chip->base + offset);
316 }
317
318 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
319 {
320 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
321
322 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
323 }
324
325 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
326 {
327 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
329
330 /* Alternative function doesn't clearly provide a direction */
331 if (fsel > BCM2835_FSEL_GPIO_OUT)
332 return -EINVAL;
333
334 return (fsel == BCM2835_FSEL_GPIO_IN);
335 }
336
337 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
338 {
339 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
340
341 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
342 }
343
344 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
345 unsigned offset, int value)
346 {
347 bcm2835_gpio_set(chip, offset, value);
348 return pinctrl_gpio_direction_output(chip->base + offset);
349 }
350
351 static const struct gpio_chip bcm2835_gpio_chip = {
352 .label = MODULE_NAME,
353 .owner = THIS_MODULE,
354 .request = gpiochip_generic_request,
355 .free = gpiochip_generic_free,
356 .direction_input = bcm2835_gpio_direction_input,
357 .direction_output = bcm2835_gpio_direction_output,
358 .get_direction = bcm2835_gpio_get_direction,
359 .get = bcm2835_gpio_get,
360 .set = bcm2835_gpio_set,
361 .set_config = gpiochip_generic_config,
362 .base = -1,
363 .ngpio = BCM2835_NUM_GPIOS,
364 .can_sleep = false,
365 };
366
367 static const struct gpio_chip bcm2711_gpio_chip = {
368 .label = "pinctrl-bcm2711",
369 .owner = THIS_MODULE,
370 .request = gpiochip_generic_request,
371 .free = gpiochip_generic_free,
372 .direction_input = bcm2835_gpio_direction_input,
373 .direction_output = bcm2835_gpio_direction_output,
374 .get_direction = bcm2835_gpio_get_direction,
375 .get = bcm2835_gpio_get,
376 .set = bcm2835_gpio_set,
377 .set_config = gpiochip_generic_config,
378 .base = -1,
379 .ngpio = BCM2711_NUM_GPIOS,
380 .can_sleep = false,
381 };
382
383 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
384 unsigned int bank, u32 mask)
385 {
386 unsigned long events;
387 unsigned offset;
388 unsigned gpio;
389
390 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
391 events &= mask;
392 events &= pc->enabled_irq_map[bank];
393 for_each_set_bit(offset, &events, 32) {
394 gpio = (32 * bank) + offset;
395 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
396 gpio));
397 }
398 }
399
400 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
401 {
402 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
403 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
404 struct irq_chip *host_chip = irq_desc_get_chip(desc);
405 int irq = irq_desc_get_irq(desc);
406 int group;
407 int i;
408
409 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
410 if (chip->irq.parents[i] == irq) {
411 group = i;
412 break;
413 }
414 }
415 /* This should not happen, every IRQ has a bank */
416 if (i == BCM2835_NUM_IRQS)
417 BUG();
418
419 chained_irq_enter(host_chip, desc);
420
421 switch (group) {
422 case 0: /* IRQ0 covers GPIOs 0-27 */
423 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
424 break;
425 case 1: /* IRQ1 covers GPIOs 28-45 */
426 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
427 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
428 break;
429 case 2: /* IRQ2 covers GPIOs 46-57 */
430 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
431 break;
432 }
433
434 chained_irq_exit(host_chip, desc);
435 }
436
437 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
438 {
439 return IRQ_HANDLED;
440 }
441
442 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
443 unsigned reg, unsigned offset, bool enable)
444 {
445 u32 value;
446 reg += GPIO_REG_OFFSET(offset) * 4;
447 value = bcm2835_gpio_rd(pc, reg);
448 if (enable)
449 value |= BIT(GPIO_REG_SHIFT(offset));
450 else
451 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
452 bcm2835_gpio_wr(pc, reg, value);
453 }
454
455 /* fast path for IRQ handler */
456 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
457 unsigned offset, bool enable)
458 {
459 switch (pc->irq_type[offset]) {
460 case IRQ_TYPE_EDGE_RISING:
461 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
462 break;
463
464 case IRQ_TYPE_EDGE_FALLING:
465 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
466 break;
467
468 case IRQ_TYPE_EDGE_BOTH:
469 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
470 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
471 break;
472
473 case IRQ_TYPE_LEVEL_HIGH:
474 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
475 break;
476
477 case IRQ_TYPE_LEVEL_LOW:
478 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
479 break;
480 }
481 }
482
483 static void bcm2835_gpio_irq_enable(struct irq_data *data)
484 {
485 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
486 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
487 unsigned gpio = irqd_to_hwirq(data);
488 unsigned offset = GPIO_REG_SHIFT(gpio);
489 unsigned bank = GPIO_REG_OFFSET(gpio);
490 unsigned long flags;
491
492 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
493 set_bit(offset, &pc->enabled_irq_map[bank]);
494 bcm2835_gpio_irq_config(pc, gpio, true);
495 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
496 }
497
498 static void bcm2835_gpio_irq_disable(struct irq_data *data)
499 {
500 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
501 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
502 unsigned gpio = irqd_to_hwirq(data);
503 unsigned offset = GPIO_REG_SHIFT(gpio);
504 unsigned bank = GPIO_REG_OFFSET(gpio);
505 unsigned long flags;
506
507 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
508 bcm2835_gpio_irq_config(pc, gpio, false);
509 /* Clear events that were latched prior to clearing event sources */
510 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
511 clear_bit(offset, &pc->enabled_irq_map[bank]);
512 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
513 }
514
515 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
516 unsigned offset, unsigned int type)
517 {
518 switch (type) {
519 case IRQ_TYPE_NONE:
520 case IRQ_TYPE_EDGE_RISING:
521 case IRQ_TYPE_EDGE_FALLING:
522 case IRQ_TYPE_EDGE_BOTH:
523 case IRQ_TYPE_LEVEL_HIGH:
524 case IRQ_TYPE_LEVEL_LOW:
525 pc->irq_type[offset] = type;
526 break;
527
528 default:
529 return -EINVAL;
530 }
531 return 0;
532 }
533
534 /* slower path for reconfiguring IRQ type */
535 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
536 unsigned offset, unsigned int type)
537 {
538 switch (type) {
539 case IRQ_TYPE_NONE:
540 if (pc->irq_type[offset] != type) {
541 bcm2835_gpio_irq_config(pc, offset, false);
542 pc->irq_type[offset] = type;
543 }
544 break;
545
546 case IRQ_TYPE_EDGE_RISING:
547 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
548 /* RISING already enabled, disable FALLING */
549 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
550 bcm2835_gpio_irq_config(pc, offset, false);
551 pc->irq_type[offset] = type;
552 } else if (pc->irq_type[offset] != type) {
553 bcm2835_gpio_irq_config(pc, offset, false);
554 pc->irq_type[offset] = type;
555 bcm2835_gpio_irq_config(pc, offset, true);
556 }
557 break;
558
559 case IRQ_TYPE_EDGE_FALLING:
560 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
561 /* FALLING already enabled, disable RISING */
562 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
563 bcm2835_gpio_irq_config(pc, offset, false);
564 pc->irq_type[offset] = type;
565 } else if (pc->irq_type[offset] != type) {
566 bcm2835_gpio_irq_config(pc, offset, false);
567 pc->irq_type[offset] = type;
568 bcm2835_gpio_irq_config(pc, offset, true);
569 }
570 break;
571
572 case IRQ_TYPE_EDGE_BOTH:
573 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
574 /* RISING already enabled, enable FALLING too */
575 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
576 bcm2835_gpio_irq_config(pc, offset, true);
577 pc->irq_type[offset] = type;
578 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
579 /* FALLING already enabled, enable RISING too */
580 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
581 bcm2835_gpio_irq_config(pc, offset, true);
582 pc->irq_type[offset] = type;
583 } else if (pc->irq_type[offset] != type) {
584 bcm2835_gpio_irq_config(pc, offset, false);
585 pc->irq_type[offset] = type;
586 bcm2835_gpio_irq_config(pc, offset, true);
587 }
588 break;
589
590 case IRQ_TYPE_LEVEL_HIGH:
591 case IRQ_TYPE_LEVEL_LOW:
592 if (pc->irq_type[offset] != type) {
593 bcm2835_gpio_irq_config(pc, offset, false);
594 pc->irq_type[offset] = type;
595 bcm2835_gpio_irq_config(pc, offset, true);
596 }
597 break;
598
599 default:
600 return -EINVAL;
601 }
602 return 0;
603 }
604
605 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
606 {
607 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
608 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
609 unsigned gpio = irqd_to_hwirq(data);
610 unsigned offset = GPIO_REG_SHIFT(gpio);
611 unsigned bank = GPIO_REG_OFFSET(gpio);
612 unsigned long flags;
613 int ret;
614
615 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
616
617 if (test_bit(offset, &pc->enabled_irq_map[bank]))
618 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
619 else
620 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
621
622 if (type & IRQ_TYPE_EDGE_BOTH)
623 irq_set_handler_locked(data, handle_edge_irq);
624 else
625 irq_set_handler_locked(data, handle_level_irq);
626
627 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
628
629 return ret;
630 }
631
632 static void bcm2835_gpio_irq_ack(struct irq_data *data)
633 {
634 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
635 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
636 unsigned gpio = irqd_to_hwirq(data);
637
638 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
639 }
640
641 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
642 {
643 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
644 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
645 unsigned gpio = irqd_to_hwirq(data);
646 unsigned int irqgroup;
647 int ret = -EINVAL;
648
649 if (!pc->wake_irq)
650 return ret;
651
652 if (gpio <= 27)
653 irqgroup = 0;
654 else if (gpio >= 28 && gpio <= 45)
655 irqgroup = 1;
656 else if (gpio >= 46 && gpio <= 57)
657 irqgroup = 2;
658 else
659 return ret;
660
661 if (on)
662 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
663 else
664 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
665
666 return ret;
667 }
668
669 static struct irq_chip bcm2835_gpio_irq_chip = {
670 .name = MODULE_NAME,
671 .irq_enable = bcm2835_gpio_irq_enable,
672 .irq_disable = bcm2835_gpio_irq_disable,
673 .irq_set_type = bcm2835_gpio_irq_set_type,
674 .irq_ack = bcm2835_gpio_irq_ack,
675 .irq_mask = bcm2835_gpio_irq_disable,
676 .irq_unmask = bcm2835_gpio_irq_enable,
677 .irq_set_wake = bcm2835_gpio_irq_set_wake,
678 .flags = IRQCHIP_MASK_ON_SUSPEND,
679 };
680
681 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
682 {
683 return BCM2835_NUM_GPIOS;
684 }
685
686 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
687 unsigned selector)
688 {
689 return bcm2835_gpio_groups[selector];
690 }
691
692 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
693 unsigned selector,
694 const unsigned **pins,
695 unsigned *num_pins)
696 {
697 *pins = &bcm2835_gpio_pins[selector].number;
698 *num_pins = 1;
699
700 return 0;
701 }
702
703 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
704 struct seq_file *s,
705 unsigned offset)
706 {
707 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
708 struct gpio_chip *chip = &pc->gpio_chip;
709 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
710 const char *fname = bcm2835_functions[fsel];
711 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
712 int irq = irq_find_mapping(chip->irq.domain, offset);
713
714 seq_printf(s, "function %s in %s; irq %d (%s)",
715 fname, value ? "hi" : "lo",
716 irq, irq_type_names[pc->irq_type[offset]]);
717 }
718
719 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
720 struct pinctrl_map *maps, unsigned num_maps)
721 {
722 int i;
723
724 for (i = 0; i < num_maps; i++)
725 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
726 kfree(maps[i].data.configs.configs);
727
728 kfree(maps);
729 }
730
731 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
732 struct device_node *np, u32 pin, u32 fnum,
733 struct pinctrl_map **maps)
734 {
735 struct pinctrl_map *map = *maps;
736
737 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
738 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
739 return -EINVAL;
740 }
741
742 map->type = PIN_MAP_TYPE_MUX_GROUP;
743 map->data.mux.group = bcm2835_gpio_groups[pin];
744 map->data.mux.function = bcm2835_functions[fnum];
745 (*maps)++;
746
747 return 0;
748 }
749
750 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
751 struct device_node *np, u32 pin, u32 pull,
752 struct pinctrl_map **maps)
753 {
754 struct pinctrl_map *map = *maps;
755 unsigned long *configs;
756
757 if (pull > 2) {
758 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
759 return -EINVAL;
760 }
761
762 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
763 if (!configs)
764 return -ENOMEM;
765 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
766
767 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
768 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
769 map->data.configs.configs = configs;
770 map->data.configs.num_configs = 1;
771 (*maps)++;
772
773 return 0;
774 }
775
776 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
777 struct device_node *np,
778 struct pinctrl_map **map, unsigned int *num_maps)
779 {
780 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
781 struct property *pins, *funcs, *pulls;
782 int num_pins, num_funcs, num_pulls, maps_per_pin;
783 struct pinctrl_map *maps, *cur_map;
784 int i, err;
785 u32 pin, func, pull;
786
787 /* Check for generic binding in this node */
788 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
789 if (err || *num_maps)
790 return err;
791
792 /* Generic binding did not find anything continue with legacy parse */
793 pins = of_find_property(np, "brcm,pins", NULL);
794 if (!pins) {
795 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
796 return -EINVAL;
797 }
798
799 funcs = of_find_property(np, "brcm,function", NULL);
800 pulls = of_find_property(np, "brcm,pull", NULL);
801
802 if (!funcs && !pulls) {
803 dev_err(pc->dev,
804 "%pOF: neither brcm,function nor brcm,pull specified\n",
805 np);
806 return -EINVAL;
807 }
808
809 num_pins = pins->length / 4;
810 num_funcs = funcs ? (funcs->length / 4) : 0;
811 num_pulls = pulls ? (pulls->length / 4) : 0;
812
813 if (num_funcs > 1 && num_funcs != num_pins) {
814 dev_err(pc->dev,
815 "%pOF: brcm,function must have 1 or %d entries\n",
816 np, num_pins);
817 return -EINVAL;
818 }
819
820 if (num_pulls > 1 && num_pulls != num_pins) {
821 dev_err(pc->dev,
822 "%pOF: brcm,pull must have 1 or %d entries\n",
823 np, num_pins);
824 return -EINVAL;
825 }
826
827 maps_per_pin = 0;
828 if (num_funcs)
829 maps_per_pin++;
830 if (num_pulls)
831 maps_per_pin++;
832 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
833 GFP_KERNEL);
834 if (!maps)
835 return -ENOMEM;
836
837 for (i = 0; i < num_pins; i++) {
838 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
839 if (err)
840 goto out;
841 if (pin >= pc->pctl_desc.npins) {
842 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
843 np, pin);
844 err = -EINVAL;
845 goto out;
846 }
847
848 if (num_funcs) {
849 err = of_property_read_u32_index(np, "brcm,function",
850 (num_funcs > 1) ? i : 0, &func);
851 if (err)
852 goto out;
853 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
854 func, &cur_map);
855 if (err)
856 goto out;
857 }
858 if (num_pulls) {
859 err = of_property_read_u32_index(np, "brcm,pull",
860 (num_pulls > 1) ? i : 0, &pull);
861 if (err)
862 goto out;
863 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
864 pull, &cur_map);
865 if (err)
866 goto out;
867 }
868 }
869
870 *map = maps;
871 *num_maps = num_pins * maps_per_pin;
872
873 return 0;
874
875 out:
876 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
877 return err;
878 }
879
880 static const struct pinctrl_ops bcm2835_pctl_ops = {
881 .get_groups_count = bcm2835_pctl_get_groups_count,
882 .get_group_name = bcm2835_pctl_get_group_name,
883 .get_group_pins = bcm2835_pctl_get_group_pins,
884 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
885 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
886 .dt_free_map = bcm2835_pctl_dt_free_map,
887 };
888
889 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
890 unsigned offset)
891 {
892 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
893
894 /* disable by setting to GPIO_IN */
895 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
896 return 0;
897 }
898
899 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
900 {
901 return BCM2835_FSEL_COUNT;
902 }
903
904 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
905 unsigned selector)
906 {
907 return bcm2835_functions[selector];
908 }
909
910 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
911 unsigned selector,
912 const char * const **groups,
913 unsigned * const num_groups)
914 {
915 /* every pin can do every function */
916 *groups = bcm2835_gpio_groups;
917 *num_groups = BCM2835_NUM_GPIOS;
918
919 return 0;
920 }
921
922 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
923 unsigned func_selector,
924 unsigned group_selector)
925 {
926 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
927
928 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
929
930 return 0;
931 }
932
933 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
934 struct pinctrl_gpio_range *range,
935 unsigned offset)
936 {
937 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
938
939 /* disable by setting to GPIO_IN */
940 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
941 }
942
943 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
944 struct pinctrl_gpio_range *range,
945 unsigned offset,
946 bool input)
947 {
948 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
949 enum bcm2835_fsel fsel = input ?
950 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
951
952 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
953
954 return 0;
955 }
956
957 static const struct pinmux_ops bcm2835_pmx_ops = {
958 .free = bcm2835_pmx_free,
959 .get_functions_count = bcm2835_pmx_get_functions_count,
960 .get_function_name = bcm2835_pmx_get_function_name,
961 .get_function_groups = bcm2835_pmx_get_function_groups,
962 .set_mux = bcm2835_pmx_set,
963 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
964 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
965 };
966
967 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
968 unsigned pin, unsigned long *config)
969 {
970 /* No way to read back config in HW */
971 return -ENOTSUPP;
972 }
973
974 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
975 unsigned int pin, unsigned int arg)
976 {
977 u32 off, bit;
978
979 off = GPIO_REG_OFFSET(pin);
980 bit = GPIO_REG_SHIFT(pin);
981
982 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
983 /*
984 * BCM2835 datasheet say to wait 150 cycles, but not of what.
985 * But the VideoCore firmware delay for this operation
986 * based nearly on the same amount of VPU cycles and this clock
987 * runs at 250 MHz.
988 */
989 udelay(1);
990 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
991 udelay(1);
992 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
993 }
994
995 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
996 unsigned int pin, unsigned long *configs,
997 unsigned int num_configs)
998 {
999 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1000 u32 param, arg;
1001 int i;
1002
1003 for (i = 0; i < num_configs; i++) {
1004 param = pinconf_to_config_param(configs[i]);
1005 arg = pinconf_to_config_argument(configs[i]);
1006
1007 switch (param) {
1008 /* Set legacy brcm,pull */
1009 case BCM2835_PINCONF_PARAM_PULL:
1010 bcm2835_pull_config_set(pc, pin, arg);
1011 break;
1012
1013 /* Set pull generic bindings */
1014 case PIN_CONFIG_BIAS_DISABLE:
1015 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1016 break;
1017
1018 case PIN_CONFIG_BIAS_PULL_DOWN:
1019 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1020 break;
1021
1022 case PIN_CONFIG_BIAS_PULL_UP:
1023 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1024 break;
1025
1026 /* Set output-high or output-low */
1027 case PIN_CONFIG_OUTPUT:
1028 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1029 break;
1030
1031 default:
1032 return -ENOTSUPP;
1033
1034 } /* switch param type */
1035 } /* for each config */
1036
1037 return 0;
1038 }
1039
1040 static const struct pinconf_ops bcm2835_pinconf_ops = {
1041 .is_generic = true,
1042 .pin_config_get = bcm2835_pinconf_get,
1043 .pin_config_set = bcm2835_pinconf_set,
1044 };
1045
1046 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1047 unsigned int pin, unsigned int arg)
1048 {
1049 u32 shifter;
1050 u32 value;
1051 u32 off;
1052
1053 off = PUD_2711_REG_OFFSET(pin);
1054 shifter = PUD_2711_REG_SHIFT(pin);
1055
1056 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1057 value &= ~(PUD_2711_MASK << shifter);
1058 value |= (arg << shifter);
1059 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1060 }
1061
1062 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1063 unsigned int pin, unsigned long *configs,
1064 unsigned int num_configs)
1065 {
1066 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1067 u32 param, arg;
1068 int i;
1069
1070 for (i = 0; i < num_configs; i++) {
1071 param = pinconf_to_config_param(configs[i]);
1072 arg = pinconf_to_config_argument(configs[i]);
1073
1074 switch (param) {
1075 /* convert legacy brcm,pull */
1076 case BCM2835_PINCONF_PARAM_PULL:
1077 if (arg == BCM2835_PUD_UP)
1078 arg = BCM2711_PULL_UP;
1079 else if (arg == BCM2835_PUD_DOWN)
1080 arg = BCM2711_PULL_DOWN;
1081 else
1082 arg = BCM2711_PULL_NONE;
1083
1084 bcm2711_pull_config_set(pc, pin, arg);
1085 break;
1086
1087 /* Set pull generic bindings */
1088 case PIN_CONFIG_BIAS_DISABLE:
1089 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1090 break;
1091 case PIN_CONFIG_BIAS_PULL_DOWN:
1092 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1093 break;
1094 case PIN_CONFIG_BIAS_PULL_UP:
1095 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1096 break;
1097
1098 /* Set output-high or output-low */
1099 case PIN_CONFIG_OUTPUT:
1100 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1101 break;
1102
1103 default:
1104 return -ENOTSUPP;
1105 }
1106 } /* for each config */
1107
1108 return 0;
1109 }
1110
1111 static const struct pinconf_ops bcm2711_pinconf_ops = {
1112 .is_generic = true,
1113 .pin_config_get = bcm2835_pinconf_get,
1114 .pin_config_set = bcm2711_pinconf_set,
1115 };
1116
1117 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1118 .name = MODULE_NAME,
1119 .pins = bcm2835_gpio_pins,
1120 .npins = BCM2835_NUM_GPIOS,
1121 .pctlops = &bcm2835_pctl_ops,
1122 .pmxops = &bcm2835_pmx_ops,
1123 .confops = &bcm2835_pinconf_ops,
1124 .owner = THIS_MODULE,
1125 };
1126
1127 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1128 .name = "pinctrl-bcm2711",
1129 .pins = bcm2835_gpio_pins,
1130 .npins = BCM2711_NUM_GPIOS,
1131 .pctlops = &bcm2835_pctl_ops,
1132 .pmxops = &bcm2835_pmx_ops,
1133 .confops = &bcm2711_pinconf_ops,
1134 .owner = THIS_MODULE,
1135 };
1136
1137 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1138 .name = MODULE_NAME,
1139 .npins = BCM2835_NUM_GPIOS,
1140 };
1141
1142 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1143 .name = "pinctrl-bcm2711",
1144 .npins = BCM2711_NUM_GPIOS,
1145 };
1146
1147 struct bcm_plat_data {
1148 const struct gpio_chip *gpio_chip;
1149 const struct pinctrl_desc *pctl_desc;
1150 const struct pinctrl_gpio_range *gpio_range;
1151 };
1152
1153 static const struct bcm_plat_data bcm2835_plat_data = {
1154 .gpio_chip = &bcm2835_gpio_chip,
1155 .pctl_desc = &bcm2835_pinctrl_desc,
1156 .gpio_range = &bcm2835_pinctrl_gpio_range,
1157 };
1158
1159 static const struct bcm_plat_data bcm2711_plat_data = {
1160 .gpio_chip = &bcm2711_gpio_chip,
1161 .pctl_desc = &bcm2711_pinctrl_desc,
1162 .gpio_range = &bcm2711_pinctrl_gpio_range,
1163 };
1164
1165 static const struct of_device_id bcm2835_pinctrl_match[] = {
1166 {
1167 .compatible = "brcm,bcm2835-gpio",
1168 .data = &bcm2835_plat_data,
1169 },
1170 {
1171 .compatible = "brcm,bcm2711-gpio",
1172 .data = &bcm2711_plat_data,
1173 },
1174 {
1175 .compatible = "brcm,bcm7211-gpio",
1176 .data = &bcm2711_plat_data,
1177 },
1178 {}
1179 };
1180
1181 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1182 {
1183 struct device *dev = &pdev->dev;
1184 struct device_node *np = dev->of_node;
1185 const struct bcm_plat_data *pdata;
1186 struct bcm2835_pinctrl *pc;
1187 struct gpio_irq_chip *girq;
1188 struct resource iomem;
1189 int err, i;
1190 const struct of_device_id *match;
1191 int is_7211 = 0;
1192
1193 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1194 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1195
1196 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1197 if (!pc)
1198 return -ENOMEM;
1199
1200 platform_set_drvdata(pdev, pc);
1201 pc->dev = dev;
1202
1203 err = of_address_to_resource(np, 0, &iomem);
1204 if (err) {
1205 dev_err(dev, "could not get IO memory\n");
1206 return err;
1207 }
1208
1209 pc->base = devm_ioremap_resource(dev, &iomem);
1210 if (IS_ERR(pc->base))
1211 return PTR_ERR(pc->base);
1212
1213 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1214 if (!match)
1215 return -EINVAL;
1216
1217 pdata = match->data;
1218 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1219
1220 pc->gpio_chip = *pdata->gpio_chip;
1221 pc->gpio_chip.parent = dev;
1222 pc->gpio_chip.of_node = np;
1223
1224 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1225 unsigned long events;
1226 unsigned offset;
1227
1228 /* clear event detection flags */
1229 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1230 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1231 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1232 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1233 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1234 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1235
1236 /* clear all the events */
1237 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1238 for_each_set_bit(offset, &events, 32)
1239 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1240
1241 raw_spin_lock_init(&pc->irq_lock[i]);
1242 }
1243
1244 pc->pctl_desc = *pdata->pctl_desc;
1245 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1246 if (IS_ERR(pc->pctl_dev)) {
1247 gpiochip_remove(&pc->gpio_chip);
1248 return PTR_ERR(pc->pctl_dev);
1249 }
1250
1251 pc->gpio_range = *pdata->gpio_range;
1252 pc->gpio_range.base = pc->gpio_chip.base;
1253 pc->gpio_range.gc = &pc->gpio_chip;
1254 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1255
1256 girq = &pc->gpio_chip.irq;
1257 girq->chip = &bcm2835_gpio_irq_chip;
1258 girq->parent_handler = bcm2835_gpio_irq_handler;
1259 girq->num_parents = BCM2835_NUM_IRQS;
1260 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1261 sizeof(*girq->parents),
1262 GFP_KERNEL);
1263 if (!girq->parents) {
1264 err = -ENOMEM;
1265 goto out_remove;
1266 }
1267
1268 if (is_7211) {
1269 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1270 sizeof(*pc->wake_irq),
1271 GFP_KERNEL);
1272 if (!pc->wake_irq) {
1273 err = -ENOMEM;
1274 goto out_remove;
1275 }
1276 }
1277
1278 /*
1279 * Use the same handler for all groups: this is necessary
1280 * since we use one gpiochip to cover all lines - the
1281 * irq handler then needs to figure out which group and
1282 * bank that was firing the IRQ and look up the per-group
1283 * and bank data.
1284 */
1285 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1286 int len;
1287 char *name;
1288
1289 girq->parents[i] = irq_of_parse_and_map(np, i);
1290 if (!is_7211)
1291 continue;
1292
1293 /* Skip over the all banks interrupts */
1294 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1295 BCM2835_NUM_IRQS + 1);
1296
1297 len = strlen(dev_name(pc->dev)) + 16;
1298 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1299 if (!name) {
1300 err = -ENOMEM;
1301 goto out_remove;
1302 }
1303
1304 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1305
1306 /* These are optional interrupts */
1307 err = devm_request_irq(dev, pc->wake_irq[i],
1308 bcm2835_gpio_wake_irq_handler,
1309 IRQF_SHARED, name, pc);
1310 if (err)
1311 dev_warn(dev, "unable to request wake IRQ %d\n",
1312 pc->wake_irq[i]);
1313 }
1314
1315 girq->default_type = IRQ_TYPE_NONE;
1316 girq->handler = handle_level_irq;
1317
1318 err = gpiochip_add_data(&pc->gpio_chip, pc);
1319 if (err) {
1320 dev_err(dev, "could not add GPIO chip\n");
1321 goto out_remove;
1322 }
1323
1324 return 0;
1325
1326 out_remove:
1327 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1328 return err;
1329 }
1330
1331 static struct platform_driver bcm2835_pinctrl_driver = {
1332 .probe = bcm2835_pinctrl_probe,
1333 .driver = {
1334 .name = MODULE_NAME,
1335 .of_match_table = bcm2835_pinctrl_match,
1336 .suppress_bind_attrs = true,
1337 },
1338 };
1339 builtin_platform_driver(bcm2835_pinctrl_driver);
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