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Merge tag 'sh-pfc-for-v5.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-focal-kernel.git] / drivers / pinctrl / intel / pinctrl-cherryview.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Cherryview/Braswell pinctrl driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This driver is based on the original Cherryview GPIO driver by
9 * Ning Li <ning.li@intel.com>
10 * Alan Cox <alan@linux.intel.com>
11 */
12
13 #include <linux/acpi.h>
14 #include <linux/dmi.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/types.h>
20
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25
26 #include "pinctrl-intel.h"
27
28 #define CHV_INTSTAT 0x300
29 #define CHV_INTMASK 0x380
30
31 #define FAMILY_PAD_REGS_OFF 0x4400
32 #define FAMILY_PAD_REGS_SIZE 0x400
33 #define MAX_FAMILY_PAD_GPIO_NO 15
34 #define GPIO_REGS_SIZE 8
35
36 #define CHV_PADCTRL0 0x000
37 #define CHV_PADCTRL0_INTSEL_SHIFT 28
38 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
39 #define CHV_PADCTRL0_TERM_UP BIT(23)
40 #define CHV_PADCTRL0_TERM_SHIFT 20
41 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
42 #define CHV_PADCTRL0_TERM_20K 1
43 #define CHV_PADCTRL0_TERM_5K 2
44 #define CHV_PADCTRL0_TERM_1K 4
45 #define CHV_PADCTRL0_PMODE_SHIFT 16
46 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
47 #define CHV_PADCTRL0_GPIOEN BIT(15)
48 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
49 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
50 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
51 #define CHV_PADCTRL0_GPIOCFG_GPO 1
52 #define CHV_PADCTRL0_GPIOCFG_GPI 2
53 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
54 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
55 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
56
57 #define CHV_PADCTRL1 0x004
58 #define CHV_PADCTRL1_CFGLOCK BIT(31)
59 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
60 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
61 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
62 #define CHV_PADCTRL1_ODEN BIT(3)
63 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
64 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
65 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
66 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
67 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
68 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
69
70 /**
71 * struct chv_alternate_function - A per group or per pin alternate function
72 * @pin: Pin number (only used in per pin configs)
73 * @mode: Mode the pin should be set in
74 * @invert_oe: Invert OE for this pin
75 */
76 struct chv_alternate_function {
77 unsigned int pin;
78 u8 mode;
79 bool invert_oe;
80 };
81
82 /**
83 * struct chv_pincgroup - describes a CHV pin group
84 * @name: Name of the group
85 * @pins: An array of pins in this group
86 * @npins: Number of pins in this group
87 * @altfunc: Alternate function applied to all pins in this group
88 * @overrides: Alternate function override per pin or %NULL if not used
89 * @noverrides: Number of per pin alternate function overrides if
90 * @overrides != NULL.
91 */
92 struct chv_pingroup {
93 const char *name;
94 const unsigned int *pins;
95 size_t npins;
96 struct chv_alternate_function altfunc;
97 const struct chv_alternate_function *overrides;
98 size_t noverrides;
99 };
100
101 /**
102 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
103 * @base: Start pin number
104 * @npins: Number of pins in this range
105 */
106 struct chv_gpio_pinrange {
107 unsigned int base;
108 unsigned int npins;
109 };
110
111 /**
112 * struct chv_community - A community specific configuration
113 * @uid: ACPI _UID used to match the community
114 * @pins: All pins in this community
115 * @npins: Number of pins
116 * @groups: All groups in this community
117 * @ngroups: Number of groups
118 * @functions: All functions in this community
119 * @nfunctions: Number of functions
120 * @gpio_ranges: An array of GPIO ranges in this community
121 * @ngpio_ranges: Number of GPIO ranges
122 * @nirqs: Total number of IRQs this community can generate
123 * @acpi_space_id: An address space ID for ACPI OpRegion handler
124 */
125 struct chv_community {
126 const char *uid;
127 const struct pinctrl_pin_desc *pins;
128 size_t npins;
129 const struct chv_pingroup *groups;
130 size_t ngroups;
131 const struct intel_function *functions;
132 size_t nfunctions;
133 const struct chv_gpio_pinrange *gpio_ranges;
134 size_t ngpio_ranges;
135 size_t nirqs;
136 acpi_adr_space_type acpi_space_id;
137 };
138
139 struct chv_pin_context {
140 u32 padctrl0;
141 u32 padctrl1;
142 };
143
144 /**
145 * struct chv_pinctrl - CHV pinctrl private structure
146 * @dev: Pointer to the parent device
147 * @pctldesc: Pin controller description
148 * @pctldev: Pointer to the pin controller device
149 * @chip: GPIO chip in this pin controller
150 * @regs: MMIO registers
151 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
152 * offset (in GPIO number space)
153 * @community: Community this pinctrl instance represents
154 * @saved_intmask: Interrupt mask saved for system sleep
155 * @saved_pin_context: Pointer to a context of the pins saved for system sleep
156 *
157 * The first group in @groups is expected to contain all pins that can be
158 * used as GPIOs.
159 */
160 struct chv_pinctrl {
161 struct device *dev;
162 struct pinctrl_desc pctldesc;
163 struct pinctrl_dev *pctldev;
164 struct gpio_chip chip;
165 void __iomem *regs;
166 unsigned intr_lines[16];
167 const struct chv_community *community;
168 u32 saved_intmask;
169 struct chv_pin_context *saved_pin_context;
170 };
171
172 #define ALTERNATE_FUNCTION(p, m, i) \
173 { \
174 .pin = (p), \
175 .mode = (m), \
176 .invert_oe = (i), \
177 }
178
179 #define PIN_GROUP_WITH_ALT(n, p, m, i) \
180 { \
181 .name = (n), \
182 .pins = (p), \
183 .npins = ARRAY_SIZE((p)), \
184 .altfunc.mode = (m), \
185 .altfunc.invert_oe = (i), \
186 }
187
188 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
189 { \
190 .name = (n), \
191 .pins = (p), \
192 .npins = ARRAY_SIZE((p)), \
193 .altfunc.mode = (m), \
194 .altfunc.invert_oe = (i), \
195 .overrides = (o), \
196 .noverrides = ARRAY_SIZE((o)), \
197 }
198
199 #define GPIO_PINRANGE(start, end) \
200 { \
201 .base = (start), \
202 .npins = (end) - (start) + 1, \
203 }
204
205 static const struct pinctrl_pin_desc southwest_pins[] = {
206 PINCTRL_PIN(0, "FST_SPI_D2"),
207 PINCTRL_PIN(1, "FST_SPI_D0"),
208 PINCTRL_PIN(2, "FST_SPI_CLK"),
209 PINCTRL_PIN(3, "FST_SPI_D3"),
210 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
211 PINCTRL_PIN(5, "FST_SPI_D1"),
212 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
213 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
214
215 PINCTRL_PIN(15, "UART1_RTS_B"),
216 PINCTRL_PIN(16, "UART1_RXD"),
217 PINCTRL_PIN(17, "UART2_RXD"),
218 PINCTRL_PIN(18, "UART1_CTS_B"),
219 PINCTRL_PIN(19, "UART2_RTS_B"),
220 PINCTRL_PIN(20, "UART1_TXD"),
221 PINCTRL_PIN(21, "UART2_TXD"),
222 PINCTRL_PIN(22, "UART2_CTS_B"),
223
224 PINCTRL_PIN(30, "MF_HDA_CLK"),
225 PINCTRL_PIN(31, "MF_HDA_RSTB"),
226 PINCTRL_PIN(32, "MF_HDA_SDIO"),
227 PINCTRL_PIN(33, "MF_HDA_SDO"),
228 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
229 PINCTRL_PIN(35, "MF_HDA_SYNC"),
230 PINCTRL_PIN(36, "MF_HDA_SDI1"),
231 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
232
233 PINCTRL_PIN(45, "I2C5_SDA"),
234 PINCTRL_PIN(46, "I2C4_SDA"),
235 PINCTRL_PIN(47, "I2C6_SDA"),
236 PINCTRL_PIN(48, "I2C5_SCL"),
237 PINCTRL_PIN(49, "I2C_NFC_SDA"),
238 PINCTRL_PIN(50, "I2C4_SCL"),
239 PINCTRL_PIN(51, "I2C6_SCL"),
240 PINCTRL_PIN(52, "I2C_NFC_SCL"),
241
242 PINCTRL_PIN(60, "I2C1_SDA"),
243 PINCTRL_PIN(61, "I2C0_SDA"),
244 PINCTRL_PIN(62, "I2C2_SDA"),
245 PINCTRL_PIN(63, "I2C1_SCL"),
246 PINCTRL_PIN(64, "I2C3_SDA"),
247 PINCTRL_PIN(65, "I2C0_SCL"),
248 PINCTRL_PIN(66, "I2C2_SCL"),
249 PINCTRL_PIN(67, "I2C3_SCL"),
250
251 PINCTRL_PIN(75, "SATA_GP0"),
252 PINCTRL_PIN(76, "SATA_GP1"),
253 PINCTRL_PIN(77, "SATA_LEDN"),
254 PINCTRL_PIN(78, "SATA_GP2"),
255 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
256 PINCTRL_PIN(80, "SATA_GP3"),
257 PINCTRL_PIN(81, "MF_SMB_CLK"),
258 PINCTRL_PIN(82, "MF_SMB_DATA"),
259
260 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
261 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
262 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
263 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
264 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
265 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
266 PINCTRL_PIN(96, "GP_SSP_2_FS"),
267 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
268 };
269
270 static const unsigned southwest_uart0_pins[] = { 16, 20 };
271 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
272 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
273 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
274 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
275 static const unsigned southwest_lpe_pins[] = {
276 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
277 };
278 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
279 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
280 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
281 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
282 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
283 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
284 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
285 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
286
287 /* LPE I2S TXD pins need to have invert_oe set */
288 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
289 ALTERNATE_FUNCTION(30, 1, true),
290 ALTERNATE_FUNCTION(34, 1, true),
291 ALTERNATE_FUNCTION(97, 1, true),
292 };
293
294 /*
295 * Two spi3 chipselects are available in different mode than the main spi3
296 * functionality, which is using mode 1.
297 */
298 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
299 ALTERNATE_FUNCTION(76, 3, false),
300 ALTERNATE_FUNCTION(80, 3, false),
301 };
302
303 static const struct chv_pingroup southwest_groups[] = {
304 PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false),
305 PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false),
306 PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false),
307 PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false),
308 PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true),
309 PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true),
310 PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true),
311 PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true),
312 PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true),
313 PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true),
314 PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true),
315 PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
316
317 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
318 southwest_lpe_altfuncs),
319 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
320 southwest_spi3_altfuncs),
321 };
322
323 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
324 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
325 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
326 static const char * const southwest_hda_groups[] = { "hda_grp" };
327 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
328 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
329 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
330 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
331 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
332 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
333 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
334 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
335 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
336 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
337
338 /*
339 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
340 * enabled only as GPIOs.
341 */
342 static const struct intel_function southwest_functions[] = {
343 FUNCTION("uart0", southwest_uart0_groups),
344 FUNCTION("uart1", southwest_uart1_groups),
345 FUNCTION("uart2", southwest_uart2_groups),
346 FUNCTION("hda", southwest_hda_groups),
347 FUNCTION("lpe", southwest_lpe_groups),
348 FUNCTION("i2c0", southwest_i2c0_groups),
349 FUNCTION("i2c1", southwest_i2c1_groups),
350 FUNCTION("i2c2", southwest_i2c2_groups),
351 FUNCTION("i2c3", southwest_i2c3_groups),
352 FUNCTION("i2c4", southwest_i2c4_groups),
353 FUNCTION("i2c5", southwest_i2c5_groups),
354 FUNCTION("i2c6", southwest_i2c6_groups),
355 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
356 FUNCTION("spi3", southwest_spi3_groups),
357 };
358
359 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
360 GPIO_PINRANGE(0, 7),
361 GPIO_PINRANGE(15, 22),
362 GPIO_PINRANGE(30, 37),
363 GPIO_PINRANGE(45, 52),
364 GPIO_PINRANGE(60, 67),
365 GPIO_PINRANGE(75, 82),
366 GPIO_PINRANGE(90, 97),
367 };
368
369 static const struct chv_community southwest_community = {
370 .uid = "1",
371 .pins = southwest_pins,
372 .npins = ARRAY_SIZE(southwest_pins),
373 .groups = southwest_groups,
374 .ngroups = ARRAY_SIZE(southwest_groups),
375 .functions = southwest_functions,
376 .nfunctions = ARRAY_SIZE(southwest_functions),
377 .gpio_ranges = southwest_gpio_ranges,
378 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
379 /*
380 * Southwest community can benerate GPIO interrupts only for the
381 * first 8 interrupts. The upper half (8-15) can only be used to
382 * trigger GPEs.
383 */
384 .nirqs = 8,
385 .acpi_space_id = 0x91,
386 };
387
388 static const struct pinctrl_pin_desc north_pins[] = {
389 PINCTRL_PIN(0, "GPIO_DFX_0"),
390 PINCTRL_PIN(1, "GPIO_DFX_3"),
391 PINCTRL_PIN(2, "GPIO_DFX_7"),
392 PINCTRL_PIN(3, "GPIO_DFX_1"),
393 PINCTRL_PIN(4, "GPIO_DFX_5"),
394 PINCTRL_PIN(5, "GPIO_DFX_4"),
395 PINCTRL_PIN(6, "GPIO_DFX_8"),
396 PINCTRL_PIN(7, "GPIO_DFX_2"),
397 PINCTRL_PIN(8, "GPIO_DFX_6"),
398
399 PINCTRL_PIN(15, "GPIO_SUS0"),
400 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
401 PINCTRL_PIN(17, "GPIO_SUS3"),
402 PINCTRL_PIN(18, "GPIO_SUS7"),
403 PINCTRL_PIN(19, "GPIO_SUS1"),
404 PINCTRL_PIN(20, "GPIO_SUS5"),
405 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
406 PINCTRL_PIN(22, "GPIO_SUS4"),
407 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
408 PINCTRL_PIN(24, "GPIO_SUS2"),
409 PINCTRL_PIN(25, "GPIO_SUS6"),
410 PINCTRL_PIN(26, "CX_PREQ_B"),
411 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
412
413 PINCTRL_PIN(30, "TRST_B"),
414 PINCTRL_PIN(31, "TCK"),
415 PINCTRL_PIN(32, "PROCHOT_B"),
416 PINCTRL_PIN(33, "SVIDO_DATA"),
417 PINCTRL_PIN(34, "TMS"),
418 PINCTRL_PIN(35, "CX_PRDY_B_2"),
419 PINCTRL_PIN(36, "TDO_2"),
420 PINCTRL_PIN(37, "CX_PRDY_B"),
421 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
422 PINCTRL_PIN(39, "TDO"),
423 PINCTRL_PIN(40, "SVIDO_CLK"),
424 PINCTRL_PIN(41, "TDI"),
425
426 PINCTRL_PIN(45, "GP_CAMERASB_05"),
427 PINCTRL_PIN(46, "GP_CAMERASB_02"),
428 PINCTRL_PIN(47, "GP_CAMERASB_08"),
429 PINCTRL_PIN(48, "GP_CAMERASB_00"),
430 PINCTRL_PIN(49, "GP_CAMERASB_06"),
431 PINCTRL_PIN(50, "GP_CAMERASB_10"),
432 PINCTRL_PIN(51, "GP_CAMERASB_03"),
433 PINCTRL_PIN(52, "GP_CAMERASB_09"),
434 PINCTRL_PIN(53, "GP_CAMERASB_01"),
435 PINCTRL_PIN(54, "GP_CAMERASB_07"),
436 PINCTRL_PIN(55, "GP_CAMERASB_11"),
437 PINCTRL_PIN(56, "GP_CAMERASB_04"),
438
439 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
440 PINCTRL_PIN(61, "HV_DDI0_HPD"),
441 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
442 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
443 PINCTRL_PIN(64, "HV_DDI1_HPD"),
444 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
445 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
446 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
447 PINCTRL_PIN(68, "HV_DDI2_HPD"),
448 PINCTRL_PIN(69, "PANEL1_VDDEN"),
449 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
450 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
451 PINCTRL_PIN(72, "PANEL0_VDDEN"),
452 };
453
454 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
455 GPIO_PINRANGE(0, 8),
456 GPIO_PINRANGE(15, 27),
457 GPIO_PINRANGE(30, 41),
458 GPIO_PINRANGE(45, 56),
459 GPIO_PINRANGE(60, 72),
460 };
461
462 static const struct chv_community north_community = {
463 .uid = "2",
464 .pins = north_pins,
465 .npins = ARRAY_SIZE(north_pins),
466 .gpio_ranges = north_gpio_ranges,
467 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
468 /*
469 * North community can generate GPIO interrupts only for the first
470 * 8 interrupts. The upper half (8-15) can only be used to trigger
471 * GPEs.
472 */
473 .nirqs = 8,
474 .acpi_space_id = 0x92,
475 };
476
477 static const struct pinctrl_pin_desc east_pins[] = {
478 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
479 PINCTRL_PIN(1, "PMU_BATLOW_B"),
480 PINCTRL_PIN(2, "SUS_STAT_B"),
481 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
482 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
483 PINCTRL_PIN(5, "PMU_PLTRST_B"),
484 PINCTRL_PIN(6, "PMU_SUSCLK"),
485 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
486 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
487 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
488 PINCTRL_PIN(10, "PMU_WAKE_B"),
489 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
490
491 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
492 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
493 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
494 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
495 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
496 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
497 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
498 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
499 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
500 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
501 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
502 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
503 };
504
505 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
506 GPIO_PINRANGE(0, 11),
507 GPIO_PINRANGE(15, 26),
508 };
509
510 static const struct chv_community east_community = {
511 .uid = "3",
512 .pins = east_pins,
513 .npins = ARRAY_SIZE(east_pins),
514 .gpio_ranges = east_gpio_ranges,
515 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
516 .nirqs = 16,
517 .acpi_space_id = 0x93,
518 };
519
520 static const struct pinctrl_pin_desc southeast_pins[] = {
521 PINCTRL_PIN(0, "MF_PLT_CLK0"),
522 PINCTRL_PIN(1, "PWM1"),
523 PINCTRL_PIN(2, "MF_PLT_CLK1"),
524 PINCTRL_PIN(3, "MF_PLT_CLK4"),
525 PINCTRL_PIN(4, "MF_PLT_CLK3"),
526 PINCTRL_PIN(5, "PWM0"),
527 PINCTRL_PIN(6, "MF_PLT_CLK5"),
528 PINCTRL_PIN(7, "MF_PLT_CLK2"),
529
530 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
531 PINCTRL_PIN(16, "SDMMC1_CLK"),
532 PINCTRL_PIN(17, "SDMMC1_D0"),
533 PINCTRL_PIN(18, "SDMMC2_D1"),
534 PINCTRL_PIN(19, "SDMMC2_CLK"),
535 PINCTRL_PIN(20, "SDMMC1_D2"),
536 PINCTRL_PIN(21, "SDMMC2_D2"),
537 PINCTRL_PIN(22, "SDMMC2_CMD"),
538 PINCTRL_PIN(23, "SDMMC1_CMD"),
539 PINCTRL_PIN(24, "SDMMC1_D1"),
540 PINCTRL_PIN(25, "SDMMC2_D0"),
541 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
542
543 PINCTRL_PIN(30, "SDMMC3_D1"),
544 PINCTRL_PIN(31, "SDMMC3_CLK"),
545 PINCTRL_PIN(32, "SDMMC3_D3"),
546 PINCTRL_PIN(33, "SDMMC3_D2"),
547 PINCTRL_PIN(34, "SDMMC3_CMD"),
548 PINCTRL_PIN(35, "SDMMC3_D0"),
549
550 PINCTRL_PIN(45, "MF_LPC_AD2"),
551 PINCTRL_PIN(46, "LPC_CLKRUNB"),
552 PINCTRL_PIN(47, "MF_LPC_AD0"),
553 PINCTRL_PIN(48, "LPC_FRAMEB"),
554 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
555 PINCTRL_PIN(50, "MF_LPC_AD3"),
556 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
557 PINCTRL_PIN(52, "MF_LPC_AD1"),
558
559 PINCTRL_PIN(60, "SPI1_MISO"),
560 PINCTRL_PIN(61, "SPI1_CSO_B"),
561 PINCTRL_PIN(62, "SPI1_CLK"),
562 PINCTRL_PIN(63, "MMC1_D6"),
563 PINCTRL_PIN(64, "SPI1_MOSI"),
564 PINCTRL_PIN(65, "MMC1_D5"),
565 PINCTRL_PIN(66, "SPI1_CS1_B"),
566 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
567 PINCTRL_PIN(68, "MMC1_D7"),
568 PINCTRL_PIN(69, "MMC1_RCLK"),
569
570 PINCTRL_PIN(75, "USB_OC1_B"),
571 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
572 PINCTRL_PIN(77, "GPIO_ALERT"),
573 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
574 PINCTRL_PIN(79, "ILB_SERIRQ"),
575 PINCTRL_PIN(80, "USB_OC0_B"),
576 PINCTRL_PIN(81, "SDMMC3_CD_B"),
577 PINCTRL_PIN(82, "SPKR"),
578 PINCTRL_PIN(83, "SUSPWRDNACK"),
579 PINCTRL_PIN(84, "SPARE_PIN"),
580 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
581 };
582
583 static const unsigned southeast_pwm0_pins[] = { 5 };
584 static const unsigned southeast_pwm1_pins[] = { 1 };
585 static const unsigned southeast_sdmmc1_pins[] = {
586 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
587 };
588 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
589 static const unsigned southeast_sdmmc3_pins[] = {
590 30, 31, 32, 33, 34, 35, 78, 81, 85,
591 };
592 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
593 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
594
595 static const struct chv_pingroup southeast_groups[] = {
596 PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false),
597 PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false),
598 PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
599 PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
600 PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
601 PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false),
602 PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false),
603 };
604
605 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
606 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
607 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
608 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
609 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
610 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
611 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
612
613 static const struct intel_function southeast_functions[] = {
614 FUNCTION("pwm0", southeast_pwm0_groups),
615 FUNCTION("pwm1", southeast_pwm1_groups),
616 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
617 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
618 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
619 FUNCTION("spi1", southeast_spi1_groups),
620 FUNCTION("spi2", southeast_spi2_groups),
621 };
622
623 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
624 GPIO_PINRANGE(0, 7),
625 GPIO_PINRANGE(15, 26),
626 GPIO_PINRANGE(30, 35),
627 GPIO_PINRANGE(45, 52),
628 GPIO_PINRANGE(60, 69),
629 GPIO_PINRANGE(75, 85),
630 };
631
632 static const struct chv_community southeast_community = {
633 .uid = "4",
634 .pins = southeast_pins,
635 .npins = ARRAY_SIZE(southeast_pins),
636 .groups = southeast_groups,
637 .ngroups = ARRAY_SIZE(southeast_groups),
638 .functions = southeast_functions,
639 .nfunctions = ARRAY_SIZE(southeast_functions),
640 .gpio_ranges = southeast_gpio_ranges,
641 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
642 .nirqs = 16,
643 .acpi_space_id = 0x94,
644 };
645
646 static const struct chv_community *chv_communities[] = {
647 &southwest_community,
648 &north_community,
649 &east_community,
650 &southeast_community,
651 };
652
653 /*
654 * Lock to serialize register accesses
655 *
656 * Due to a silicon issue, a shared lock must be used to prevent
657 * concurrent accesses across the 4 GPIO controllers.
658 *
659 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
660 * errata #CHT34, for further information.
661 */
662 static DEFINE_RAW_SPINLOCK(chv_lock);
663
664 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset,
665 unsigned int reg)
666 {
667 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
668 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
669
670 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
671 GPIO_REGS_SIZE * pad_no;
672
673 return pctrl->regs + offset + reg;
674 }
675
676 static void chv_writel(u32 value, void __iomem *reg)
677 {
678 writel(value, reg);
679 /* simple readback to confirm the bus transferring done */
680 readl(reg);
681 }
682
683 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
684 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset)
685 {
686 void __iomem *reg;
687
688 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
689 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
690 }
691
692 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
693 {
694 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
695
696 return pctrl->community->ngroups;
697 }
698
699 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
700 unsigned int group)
701 {
702 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
703
704 return pctrl->community->groups[group].name;
705 }
706
707 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
708 const unsigned int **pins, unsigned int *npins)
709 {
710 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
711
712 *pins = pctrl->community->groups[group].pins;
713 *npins = pctrl->community->groups[group].npins;
714 return 0;
715 }
716
717 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
718 unsigned int offset)
719 {
720 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
721 unsigned long flags;
722 u32 ctrl0, ctrl1;
723 bool locked;
724
725 raw_spin_lock_irqsave(&chv_lock, flags);
726
727 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
728 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
729 locked = chv_pad_locked(pctrl, offset);
730
731 raw_spin_unlock_irqrestore(&chv_lock, flags);
732
733 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
734 seq_puts(s, "GPIO ");
735 } else {
736 u32 mode;
737
738 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
739 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
740
741 seq_printf(s, "mode %d ", mode);
742 }
743
744 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
745
746 if (locked)
747 seq_puts(s, " [LOCKED]");
748 }
749
750 static const struct pinctrl_ops chv_pinctrl_ops = {
751 .get_groups_count = chv_get_groups_count,
752 .get_group_name = chv_get_group_name,
753 .get_group_pins = chv_get_group_pins,
754 .pin_dbg_show = chv_pin_dbg_show,
755 };
756
757 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
758 {
759 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
760
761 return pctrl->community->nfunctions;
762 }
763
764 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
765 unsigned int function)
766 {
767 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
768
769 return pctrl->community->functions[function].name;
770 }
771
772 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
773 unsigned int function,
774 const char * const **groups,
775 unsigned int * const ngroups)
776 {
777 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
778
779 *groups = pctrl->community->functions[function].groups;
780 *ngroups = pctrl->community->functions[function].ngroups;
781 return 0;
782 }
783
784 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
785 unsigned int function, unsigned int group)
786 {
787 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
788 const struct chv_pingroup *grp;
789 unsigned long flags;
790 int i;
791
792 grp = &pctrl->community->groups[group];
793
794 raw_spin_lock_irqsave(&chv_lock, flags);
795
796 /* Check first that the pad is not locked */
797 for (i = 0; i < grp->npins; i++) {
798 if (chv_pad_locked(pctrl, grp->pins[i])) {
799 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
800 grp->pins[i]);
801 raw_spin_unlock_irqrestore(&chv_lock, flags);
802 return -EBUSY;
803 }
804 }
805
806 for (i = 0; i < grp->npins; i++) {
807 const struct chv_alternate_function *altfunc = &grp->altfunc;
808 int pin = grp->pins[i];
809 void __iomem *reg;
810 u32 value;
811
812 /* Check if there is pin-specific config */
813 if (grp->overrides) {
814 int j;
815
816 for (j = 0; j < grp->noverrides; j++) {
817 if (grp->overrides[j].pin == pin) {
818 altfunc = &grp->overrides[j];
819 break;
820 }
821 }
822 }
823
824 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
825 value = readl(reg);
826 /* Disable GPIO mode */
827 value &= ~CHV_PADCTRL0_GPIOEN;
828 /* Set to desired mode */
829 value &= ~CHV_PADCTRL0_PMODE_MASK;
830 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
831 chv_writel(value, reg);
832
833 /* Update for invert_oe */
834 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
835 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
836 if (altfunc->invert_oe)
837 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
838 chv_writel(value, reg);
839
840 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
841 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
842 }
843
844 raw_spin_unlock_irqrestore(&chv_lock, flags);
845
846 return 0;
847 }
848
849 static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl,
850 unsigned int offset)
851 {
852 void __iomem *reg;
853 u32 value;
854
855 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
856 value = readl(reg);
857 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
858 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
859 chv_writel(value, reg);
860 }
861
862 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
863 struct pinctrl_gpio_range *range,
864 unsigned int offset)
865 {
866 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
867 unsigned long flags;
868 void __iomem *reg;
869 u32 value;
870
871 raw_spin_lock_irqsave(&chv_lock, flags);
872
873 if (chv_pad_locked(pctrl, offset)) {
874 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
875 if (!(value & CHV_PADCTRL0_GPIOEN)) {
876 /* Locked so cannot enable */
877 raw_spin_unlock_irqrestore(&chv_lock, flags);
878 return -EBUSY;
879 }
880 } else {
881 int i;
882
883 /* Reset the interrupt mapping */
884 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
885 if (pctrl->intr_lines[i] == offset) {
886 pctrl->intr_lines[i] = 0;
887 break;
888 }
889 }
890
891 /* Disable interrupt generation */
892 chv_gpio_clear_triggering(pctrl, offset);
893
894 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
895 value = readl(reg);
896
897 /*
898 * If the pin is in HiZ mode (both TX and RX buffers are
899 * disabled) we turn it to be input now.
900 */
901 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
902 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
903 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
904 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
905 CHV_PADCTRL0_GPIOCFG_SHIFT;
906 }
907
908 /* Switch to a GPIO mode */
909 value |= CHV_PADCTRL0_GPIOEN;
910 chv_writel(value, reg);
911 }
912
913 raw_spin_unlock_irqrestore(&chv_lock, flags);
914
915 return 0;
916 }
917
918 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
919 struct pinctrl_gpio_range *range,
920 unsigned int offset)
921 {
922 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
923 unsigned long flags;
924
925 raw_spin_lock_irqsave(&chv_lock, flags);
926
927 if (!chv_pad_locked(pctrl, offset))
928 chv_gpio_clear_triggering(pctrl, offset);
929
930 raw_spin_unlock_irqrestore(&chv_lock, flags);
931 }
932
933 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
934 struct pinctrl_gpio_range *range,
935 unsigned int offset, bool input)
936 {
937 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
938 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
939 unsigned long flags;
940 u32 ctrl0;
941
942 raw_spin_lock_irqsave(&chv_lock, flags);
943
944 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
945 if (input)
946 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
947 else
948 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
949 chv_writel(ctrl0, reg);
950
951 raw_spin_unlock_irqrestore(&chv_lock, flags);
952
953 return 0;
954 }
955
956 static const struct pinmux_ops chv_pinmux_ops = {
957 .get_functions_count = chv_get_functions_count,
958 .get_function_name = chv_get_function_name,
959 .get_function_groups = chv_get_function_groups,
960 .set_mux = chv_pinmux_set_mux,
961 .gpio_request_enable = chv_gpio_request_enable,
962 .gpio_disable_free = chv_gpio_disable_free,
963 .gpio_set_direction = chv_gpio_set_direction,
964 };
965
966 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
967 unsigned long *config)
968 {
969 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
970 enum pin_config_param param = pinconf_to_config_param(*config);
971 unsigned long flags;
972 u32 ctrl0, ctrl1;
973 u16 arg = 0;
974 u32 term;
975
976 raw_spin_lock_irqsave(&chv_lock, flags);
977 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
978 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
979 raw_spin_unlock_irqrestore(&chv_lock, flags);
980
981 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
982
983 switch (param) {
984 case PIN_CONFIG_BIAS_DISABLE:
985 if (term)
986 return -EINVAL;
987 break;
988
989 case PIN_CONFIG_BIAS_PULL_UP:
990 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
991 return -EINVAL;
992
993 switch (term) {
994 case CHV_PADCTRL0_TERM_20K:
995 arg = 20000;
996 break;
997 case CHV_PADCTRL0_TERM_5K:
998 arg = 5000;
999 break;
1000 case CHV_PADCTRL0_TERM_1K:
1001 arg = 1000;
1002 break;
1003 }
1004
1005 break;
1006
1007 case PIN_CONFIG_BIAS_PULL_DOWN:
1008 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1009 return -EINVAL;
1010
1011 switch (term) {
1012 case CHV_PADCTRL0_TERM_20K:
1013 arg = 20000;
1014 break;
1015 case CHV_PADCTRL0_TERM_5K:
1016 arg = 5000;
1017 break;
1018 }
1019
1020 break;
1021
1022 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1023 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1024 return -EINVAL;
1025 break;
1026
1027 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1028 u32 cfg;
1029
1030 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1031 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1032 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1033 return -EINVAL;
1034
1035 break;
1036 }
1037
1038 default:
1039 return -ENOTSUPP;
1040 }
1041
1042 *config = pinconf_to_config_packed(param, arg);
1043 return 0;
1044 }
1045
1046 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin,
1047 enum pin_config_param param, u32 arg)
1048 {
1049 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1050 unsigned long flags;
1051 u32 ctrl0, pull;
1052
1053 raw_spin_lock_irqsave(&chv_lock, flags);
1054 ctrl0 = readl(reg);
1055
1056 switch (param) {
1057 case PIN_CONFIG_BIAS_DISABLE:
1058 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1059 break;
1060
1061 case PIN_CONFIG_BIAS_PULL_UP:
1062 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1063
1064 switch (arg) {
1065 case 1000:
1066 /* For 1k there is only pull up */
1067 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1068 break;
1069 case 5000:
1070 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1071 break;
1072 case 20000:
1073 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1074 break;
1075 default:
1076 raw_spin_unlock_irqrestore(&chv_lock, flags);
1077 return -EINVAL;
1078 }
1079
1080 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1081 break;
1082
1083 case PIN_CONFIG_BIAS_PULL_DOWN:
1084 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1085
1086 switch (arg) {
1087 case 5000:
1088 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1089 break;
1090 case 20000:
1091 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1092 break;
1093 default:
1094 raw_spin_unlock_irqrestore(&chv_lock, flags);
1095 return -EINVAL;
1096 }
1097
1098 ctrl0 |= pull;
1099 break;
1100
1101 default:
1102 raw_spin_unlock_irqrestore(&chv_lock, flags);
1103 return -EINVAL;
1104 }
1105
1106 chv_writel(ctrl0, reg);
1107 raw_spin_unlock_irqrestore(&chv_lock, flags);
1108
1109 return 0;
1110 }
1111
1112 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1113 bool enable)
1114 {
1115 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1116 unsigned long flags;
1117 u32 ctrl1;
1118
1119 raw_spin_lock_irqsave(&chv_lock, flags);
1120 ctrl1 = readl(reg);
1121
1122 if (enable)
1123 ctrl1 |= CHV_PADCTRL1_ODEN;
1124 else
1125 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1126
1127 chv_writel(ctrl1, reg);
1128 raw_spin_unlock_irqrestore(&chv_lock, flags);
1129
1130 return 0;
1131 }
1132
1133 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1134 unsigned long *configs, unsigned int nconfigs)
1135 {
1136 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1137 enum pin_config_param param;
1138 int i, ret;
1139 u32 arg;
1140
1141 if (chv_pad_locked(pctrl, pin))
1142 return -EBUSY;
1143
1144 for (i = 0; i < nconfigs; i++) {
1145 param = pinconf_to_config_param(configs[i]);
1146 arg = pinconf_to_config_argument(configs[i]);
1147
1148 switch (param) {
1149 case PIN_CONFIG_BIAS_DISABLE:
1150 case PIN_CONFIG_BIAS_PULL_UP:
1151 case PIN_CONFIG_BIAS_PULL_DOWN:
1152 ret = chv_config_set_pull(pctrl, pin, param, arg);
1153 if (ret)
1154 return ret;
1155 break;
1156
1157 case PIN_CONFIG_DRIVE_PUSH_PULL:
1158 ret = chv_config_set_oden(pctrl, pin, false);
1159 if (ret)
1160 return ret;
1161 break;
1162
1163 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1164 ret = chv_config_set_oden(pctrl, pin, true);
1165 if (ret)
1166 return ret;
1167 break;
1168
1169 default:
1170 return -ENOTSUPP;
1171 }
1172
1173 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1174 param, arg);
1175 }
1176
1177 return 0;
1178 }
1179
1180 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1181 unsigned int group,
1182 unsigned long *config)
1183 {
1184 const unsigned int *pins;
1185 unsigned int npins;
1186 int ret;
1187
1188 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1189 if (ret)
1190 return ret;
1191
1192 ret = chv_config_get(pctldev, pins[0], config);
1193 if (ret)
1194 return ret;
1195
1196 return 0;
1197 }
1198
1199 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1200 unsigned int group, unsigned long *configs,
1201 unsigned int num_configs)
1202 {
1203 const unsigned int *pins;
1204 unsigned int npins;
1205 int i, ret;
1206
1207 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1208 if (ret)
1209 return ret;
1210
1211 for (i = 0; i < npins; i++) {
1212 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 return 0;
1218 }
1219
1220 static const struct pinconf_ops chv_pinconf_ops = {
1221 .is_generic = true,
1222 .pin_config_set = chv_config_set,
1223 .pin_config_get = chv_config_get,
1224 .pin_config_group_get = chv_config_group_get,
1225 .pin_config_group_set = chv_config_group_set,
1226 };
1227
1228 static struct pinctrl_desc chv_pinctrl_desc = {
1229 .pctlops = &chv_pinctrl_ops,
1230 .pmxops = &chv_pinmux_ops,
1231 .confops = &chv_pinconf_ops,
1232 .owner = THIS_MODULE,
1233 };
1234
1235 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1236 {
1237 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1238 unsigned long flags;
1239 u32 ctrl0, cfg;
1240
1241 raw_spin_lock_irqsave(&chv_lock, flags);
1242 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1243 raw_spin_unlock_irqrestore(&chv_lock, flags);
1244
1245 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1246 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1247
1248 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1249 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1250 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1251 }
1252
1253 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1254 {
1255 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1256 unsigned long flags;
1257 void __iomem *reg;
1258 u32 ctrl0;
1259
1260 raw_spin_lock_irqsave(&chv_lock, flags);
1261
1262 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
1263 ctrl0 = readl(reg);
1264
1265 if (value)
1266 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1267 else
1268 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1269
1270 chv_writel(ctrl0, reg);
1271
1272 raw_spin_unlock_irqrestore(&chv_lock, flags);
1273 }
1274
1275 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1276 {
1277 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1278 u32 ctrl0, direction;
1279 unsigned long flags;
1280
1281 raw_spin_lock_irqsave(&chv_lock, flags);
1282 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
1283 raw_spin_unlock_irqrestore(&chv_lock, flags);
1284
1285 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1286 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1287
1288 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1289 }
1290
1291 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1292 {
1293 return pinctrl_gpio_direction_input(chip->base + offset);
1294 }
1295
1296 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1297 int value)
1298 {
1299 chv_gpio_set(chip, offset, value);
1300 return pinctrl_gpio_direction_output(chip->base + offset);
1301 }
1302
1303 static const struct gpio_chip chv_gpio_chip = {
1304 .owner = THIS_MODULE,
1305 .request = gpiochip_generic_request,
1306 .free = gpiochip_generic_free,
1307 .get_direction = chv_gpio_get_direction,
1308 .direction_input = chv_gpio_direction_input,
1309 .direction_output = chv_gpio_direction_output,
1310 .get = chv_gpio_get,
1311 .set = chv_gpio_set,
1312 };
1313
1314 static void chv_gpio_irq_ack(struct irq_data *d)
1315 {
1316 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1317 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1318 int pin = irqd_to_hwirq(d);
1319 u32 intr_line;
1320
1321 raw_spin_lock(&chv_lock);
1322
1323 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1324 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1325 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1326 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1327
1328 raw_spin_unlock(&chv_lock);
1329 }
1330
1331 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1332 {
1333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1334 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1335 int pin = irqd_to_hwirq(d);
1336 u32 value, intr_line;
1337 unsigned long flags;
1338
1339 raw_spin_lock_irqsave(&chv_lock, flags);
1340
1341 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1342 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1343 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1344
1345 value = readl(pctrl->regs + CHV_INTMASK);
1346 if (mask)
1347 value &= ~BIT(intr_line);
1348 else
1349 value |= BIT(intr_line);
1350 chv_writel(value, pctrl->regs + CHV_INTMASK);
1351
1352 raw_spin_unlock_irqrestore(&chv_lock, flags);
1353 }
1354
1355 static void chv_gpio_irq_mask(struct irq_data *d)
1356 {
1357 chv_gpio_irq_mask_unmask(d, true);
1358 }
1359
1360 static void chv_gpio_irq_unmask(struct irq_data *d)
1361 {
1362 chv_gpio_irq_mask_unmask(d, false);
1363 }
1364
1365 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1366 {
1367 /*
1368 * Check if the interrupt has been requested with 0 as triggering
1369 * type. In that case it is assumed that the current values
1370 * programmed to the hardware are used (e.g BIOS configured
1371 * defaults).
1372 *
1373 * In that case ->irq_set_type() will never be called so we need to
1374 * read back the values from hardware now, set correct flow handler
1375 * and update mappings before the interrupt is being used.
1376 */
1377 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1378 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1379 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1380 unsigned int pin = irqd_to_hwirq(d);
1381 irq_flow_handler_t handler;
1382 unsigned long flags;
1383 u32 intsel, value;
1384
1385 raw_spin_lock_irqsave(&chv_lock, flags);
1386 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1387 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1388 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1389
1390 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1391 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1392 handler = handle_level_irq;
1393 else
1394 handler = handle_edge_irq;
1395
1396 if (!pctrl->intr_lines[intsel]) {
1397 irq_set_handler_locked(d, handler);
1398 pctrl->intr_lines[intsel] = pin;
1399 }
1400 raw_spin_unlock_irqrestore(&chv_lock, flags);
1401 }
1402
1403 chv_gpio_irq_unmask(d);
1404 return 0;
1405 }
1406
1407 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1408 {
1409 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1410 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1411 unsigned int pin = irqd_to_hwirq(d);
1412 unsigned long flags;
1413 u32 value;
1414
1415 raw_spin_lock_irqsave(&chv_lock, flags);
1416
1417 /*
1418 * Pins which can be used as shared interrupt are configured in
1419 * BIOS. Driver trusts BIOS configurations and assigns different
1420 * handler according to the irq type.
1421 *
1422 * Driver needs to save the mapping between each pin and
1423 * its interrupt line.
1424 * 1. If the pin cfg is locked in BIOS:
1425 * Trust BIOS has programmed IntWakeCfg bits correctly,
1426 * driver just needs to save the mapping.
1427 * 2. If the pin cfg is not locked in BIOS:
1428 * Driver programs the IntWakeCfg bits and save the mapping.
1429 */
1430 if (!chv_pad_locked(pctrl, pin)) {
1431 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1432
1433 value = readl(reg);
1434 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1435 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1436
1437 if (type & IRQ_TYPE_EDGE_BOTH) {
1438 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1439 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1440 else if (type & IRQ_TYPE_EDGE_RISING)
1441 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1442 else if (type & IRQ_TYPE_EDGE_FALLING)
1443 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1444 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1445 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1446 if (type & IRQ_TYPE_LEVEL_LOW)
1447 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1448 }
1449
1450 chv_writel(value, reg);
1451 }
1452
1453 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1454 value &= CHV_PADCTRL0_INTSEL_MASK;
1455 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1456
1457 pctrl->intr_lines[value] = pin;
1458
1459 if (type & IRQ_TYPE_EDGE_BOTH)
1460 irq_set_handler_locked(d, handle_edge_irq);
1461 else if (type & IRQ_TYPE_LEVEL_MASK)
1462 irq_set_handler_locked(d, handle_level_irq);
1463
1464 raw_spin_unlock_irqrestore(&chv_lock, flags);
1465
1466 return 0;
1467 }
1468
1469 static struct irq_chip chv_gpio_irqchip = {
1470 .name = "chv-gpio",
1471 .irq_startup = chv_gpio_irq_startup,
1472 .irq_ack = chv_gpio_irq_ack,
1473 .irq_mask = chv_gpio_irq_mask,
1474 .irq_unmask = chv_gpio_irq_unmask,
1475 .irq_set_type = chv_gpio_irq_type,
1476 .flags = IRQCHIP_SKIP_SET_WAKE,
1477 };
1478
1479 static void chv_gpio_irq_handler(struct irq_desc *desc)
1480 {
1481 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1482 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1483 struct irq_chip *chip = irq_desc_get_chip(desc);
1484 unsigned long pending;
1485 u32 intr_line;
1486
1487 chained_irq_enter(chip, desc);
1488
1489 pending = readl(pctrl->regs + CHV_INTSTAT);
1490 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1491 unsigned irq, offset;
1492
1493 offset = pctrl->intr_lines[intr_line];
1494 irq = irq_find_mapping(gc->irq.domain, offset);
1495 generic_handle_irq(irq);
1496 }
1497
1498 chained_irq_exit(chip, desc);
1499 }
1500
1501 /*
1502 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1503 * tables. Since we leave GPIOs that are not capable of generating
1504 * interrupts out of the irqdomain the numbering will be different and
1505 * cause devices using the hardcoded IRQ numbers fail. In order not to
1506 * break such machines we will only mask pins from irqdomain if the machine
1507 * is not listed below.
1508 */
1509 static const struct dmi_system_id chv_no_valid_mask[] = {
1510 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1511 {
1512 .ident = "Intel_Strago based Chromebooks (All models)",
1513 .matches = {
1514 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1515 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1516 DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
1517 },
1518 },
1519 {
1520 .ident = "HP Chromebook 11 G5 (Setzer)",
1521 .matches = {
1522 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1523 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1524 DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
1525 },
1526 },
1527 {
1528 .ident = "Acer Chromebook R11 (Cyan)",
1529 .matches = {
1530 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1531 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1532 DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
1533 },
1534 },
1535 {
1536 .ident = "Samsung Chromebook 3 (Celes)",
1537 .matches = {
1538 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1539 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1540 DMI_MATCH(DMI_PRODUCT_VERSION, "1.0"),
1541 },
1542 },
1543 {}
1544 };
1545
1546 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1547 {
1548 const struct chv_gpio_pinrange *range;
1549 struct gpio_chip *chip = &pctrl->chip;
1550 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1551 const struct chv_community *community = pctrl->community;
1552 int ret, i, irq_base;
1553
1554 *chip = chv_gpio_chip;
1555
1556 chip->ngpio = community->pins[community->npins - 1].number + 1;
1557 chip->label = dev_name(pctrl->dev);
1558 chip->parent = pctrl->dev;
1559 chip->base = -1;
1560 chip->irq.need_valid_mask = need_valid_mask;
1561
1562 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1563 if (ret) {
1564 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1565 return ret;
1566 }
1567
1568 for (i = 0; i < community->ngpio_ranges; i++) {
1569 range = &community->gpio_ranges[i];
1570 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1571 range->base, range->base,
1572 range->npins);
1573 if (ret) {
1574 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1575 return ret;
1576 }
1577 }
1578
1579 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1580 for (i = 0; i < community->npins; i++) {
1581 const struct pinctrl_pin_desc *desc;
1582 u32 intsel;
1583
1584 desc = &community->pins[i];
1585
1586 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1587 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1588 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1589
1590 if (need_valid_mask && intsel >= community->nirqs)
1591 clear_bit(i, chip->irq.valid_mask);
1592 }
1593
1594 /*
1595 * The same set of machines in chv_no_valid_mask[] have incorrectly
1596 * configured GPIOs that generate spurious interrupts so we use
1597 * this same list to apply another quirk for them.
1598 *
1599 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1600 */
1601 if (!need_valid_mask) {
1602 /*
1603 * Mask all interrupts the community is able to generate
1604 * but leave the ones that can only generate GPEs unmasked.
1605 */
1606 chv_writel(GENMASK(31, pctrl->community->nirqs),
1607 pctrl->regs + CHV_INTMASK);
1608 }
1609
1610 /* Clear all interrupts */
1611 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1612
1613 if (!need_valid_mask) {
1614 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1615 community->npins, NUMA_NO_NODE);
1616 if (irq_base < 0) {
1617 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1618 return irq_base;
1619 }
1620 }
1621
1622 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
1623 handle_bad_irq, IRQ_TYPE_NONE);
1624 if (ret) {
1625 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1626 return ret;
1627 }
1628
1629 if (!need_valid_mask) {
1630 for (i = 0; i < community->ngpio_ranges; i++) {
1631 range = &community->gpio_ranges[i];
1632
1633 irq_domain_associate_many(chip->irq.domain, irq_base,
1634 range->base, range->npins);
1635 irq_base += range->npins;
1636 }
1637 }
1638
1639 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1640 chv_gpio_irq_handler);
1641 return 0;
1642 }
1643
1644 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1645 acpi_physical_address address, u32 bits, u64 *value,
1646 void *handler_context, void *region_context)
1647 {
1648 struct chv_pinctrl *pctrl = region_context;
1649 unsigned long flags;
1650 acpi_status ret = AE_OK;
1651
1652 raw_spin_lock_irqsave(&chv_lock, flags);
1653
1654 if (function == ACPI_WRITE)
1655 chv_writel((u32)(*value), pctrl->regs + (u32)address);
1656 else if (function == ACPI_READ)
1657 *value = readl(pctrl->regs + (u32)address);
1658 else
1659 ret = AE_BAD_PARAMETER;
1660
1661 raw_spin_unlock_irqrestore(&chv_lock, flags);
1662
1663 return ret;
1664 }
1665
1666 static int chv_pinctrl_probe(struct platform_device *pdev)
1667 {
1668 struct chv_pinctrl *pctrl;
1669 struct acpi_device *adev;
1670 struct resource *res;
1671 acpi_status status;
1672 int ret, irq, i;
1673
1674 adev = ACPI_COMPANION(&pdev->dev);
1675 if (!adev)
1676 return -ENODEV;
1677
1678 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1679 if (!pctrl)
1680 return -ENOMEM;
1681
1682 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1683 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1684 pctrl->community = chv_communities[i];
1685 break;
1686 }
1687 if (i == ARRAY_SIZE(chv_communities))
1688 return -ENODEV;
1689
1690 pctrl->dev = &pdev->dev;
1691
1692 #ifdef CONFIG_PM_SLEEP
1693 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1694 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1695 GFP_KERNEL);
1696 if (!pctrl->saved_pin_context)
1697 return -ENOMEM;
1698 #endif
1699
1700 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1701 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1702 if (IS_ERR(pctrl->regs))
1703 return PTR_ERR(pctrl->regs);
1704
1705 irq = platform_get_irq(pdev, 0);
1706 if (irq < 0) {
1707 dev_err(&pdev->dev, "failed to get interrupt number\n");
1708 return irq;
1709 }
1710
1711 pctrl->pctldesc = chv_pinctrl_desc;
1712 pctrl->pctldesc.name = dev_name(&pdev->dev);
1713 pctrl->pctldesc.pins = pctrl->community->pins;
1714 pctrl->pctldesc.npins = pctrl->community->npins;
1715
1716 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1717 pctrl);
1718 if (IS_ERR(pctrl->pctldev)) {
1719 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1720 return PTR_ERR(pctrl->pctldev);
1721 }
1722
1723 ret = chv_gpio_probe(pctrl, irq);
1724 if (ret)
1725 return ret;
1726
1727 status = acpi_install_address_space_handler(adev->handle,
1728 pctrl->community->acpi_space_id,
1729 chv_pinctrl_mmio_access_handler,
1730 NULL, pctrl);
1731 if (ACPI_FAILURE(status))
1732 dev_err(&pdev->dev, "failed to install ACPI addr space handler\n");
1733
1734 platform_set_drvdata(pdev, pctrl);
1735
1736 return 0;
1737 }
1738
1739 static int chv_pinctrl_remove(struct platform_device *pdev)
1740 {
1741 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1742
1743 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1744 pctrl->community->acpi_space_id,
1745 chv_pinctrl_mmio_access_handler);
1746
1747 return 0;
1748 }
1749
1750 #ifdef CONFIG_PM_SLEEP
1751 static int chv_pinctrl_suspend_noirq(struct device *dev)
1752 {
1753 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1754 unsigned long flags;
1755 int i;
1756
1757 raw_spin_lock_irqsave(&chv_lock, flags);
1758
1759 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1760
1761 for (i = 0; i < pctrl->community->npins; i++) {
1762 const struct pinctrl_pin_desc *desc;
1763 struct chv_pin_context *ctx;
1764 void __iomem *reg;
1765
1766 desc = &pctrl->community->pins[i];
1767 if (chv_pad_locked(pctrl, desc->number))
1768 continue;
1769
1770 ctx = &pctrl->saved_pin_context[i];
1771
1772 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1773 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1774
1775 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1776 ctx->padctrl1 = readl(reg);
1777 }
1778
1779 raw_spin_unlock_irqrestore(&chv_lock, flags);
1780
1781 return 0;
1782 }
1783
1784 static int chv_pinctrl_resume_noirq(struct device *dev)
1785 {
1786 struct chv_pinctrl *pctrl = dev_get_drvdata(dev);
1787 unsigned long flags;
1788 int i;
1789
1790 raw_spin_lock_irqsave(&chv_lock, flags);
1791
1792 /*
1793 * Mask all interrupts before restoring per-pin configuration
1794 * registers because we don't know in which state BIOS left them
1795 * upon exiting suspend.
1796 */
1797 chv_writel(0, pctrl->regs + CHV_INTMASK);
1798
1799 for (i = 0; i < pctrl->community->npins; i++) {
1800 const struct pinctrl_pin_desc *desc;
1801 const struct chv_pin_context *ctx;
1802 void __iomem *reg;
1803 u32 val;
1804
1805 desc = &pctrl->community->pins[i];
1806 if (chv_pad_locked(pctrl, desc->number))
1807 continue;
1808
1809 ctx = &pctrl->saved_pin_context[i];
1810
1811 /* Only restore if our saved state differs from the current */
1812 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1813 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1814 if (ctx->padctrl0 != val) {
1815 chv_writel(ctx->padctrl0, reg);
1816 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1817 desc->number, readl(reg));
1818 }
1819
1820 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1821 val = readl(reg);
1822 if (ctx->padctrl1 != val) {
1823 chv_writel(ctx->padctrl1, reg);
1824 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1825 desc->number, readl(reg));
1826 }
1827 }
1828
1829 /*
1830 * Now that all pins are restored to known state, we can restore
1831 * the interrupt mask register as well.
1832 */
1833 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1834 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1835
1836 raw_spin_unlock_irqrestore(&chv_lock, flags);
1837
1838 return 0;
1839 }
1840 #endif
1841
1842 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1843 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1844 chv_pinctrl_resume_noirq)
1845 };
1846
1847 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1848 { "INT33FF" },
1849 { }
1850 };
1851 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1852
1853 static struct platform_driver chv_pinctrl_driver = {
1854 .probe = chv_pinctrl_probe,
1855 .remove = chv_pinctrl_remove,
1856 .driver = {
1857 .name = "cherryview-pinctrl",
1858 .pm = &chv_pinctrl_pm_ops,
1859 .acpi_match_table = chv_pinctrl_acpi_match,
1860 },
1861 };
1862
1863 static int __init chv_pinctrl_init(void)
1864 {
1865 return platform_driver_register(&chv_pinctrl_driver);
1866 }
1867 subsys_initcall(chv_pinctrl_init);
1868
1869 static void __exit chv_pinctrl_exit(void)
1870 {
1871 platform_driver_unregister(&chv_pinctrl_driver);
1872 }
1873 module_exit(chv_pinctrl_exit);
1874
1875 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1876 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1877 MODULE_LICENSE("GPL v2");
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