2 * Cherryview/Braswell pinctrl driver
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/dmi.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/types.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/acpi.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/platform_device.h>
30 #define CHV_INTSTAT 0x300
31 #define CHV_INTMASK 0x380
33 #define FAMILY_PAD_REGS_OFF 0x4400
34 #define FAMILY_PAD_REGS_SIZE 0x400
35 #define MAX_FAMILY_PAD_GPIO_NO 15
36 #define GPIO_REGS_SIZE 8
38 #define CHV_PADCTRL0 0x000
39 #define CHV_PADCTRL0_INTSEL_SHIFT 28
40 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
41 #define CHV_PADCTRL0_TERM_UP BIT(23)
42 #define CHV_PADCTRL0_TERM_SHIFT 20
43 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
44 #define CHV_PADCTRL0_TERM_20K 1
45 #define CHV_PADCTRL0_TERM_5K 2
46 #define CHV_PADCTRL0_TERM_1K 4
47 #define CHV_PADCTRL0_PMODE_SHIFT 16
48 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
49 #define CHV_PADCTRL0_GPIOEN BIT(15)
50 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
51 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
52 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
53 #define CHV_PADCTRL0_GPIOCFG_GPO 1
54 #define CHV_PADCTRL0_GPIOCFG_GPI 2
55 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
56 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
57 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
59 #define CHV_PADCTRL1 0x004
60 #define CHV_PADCTRL1_CFGLOCK BIT(31)
61 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
62 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
63 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
64 #define CHV_PADCTRL1_ODEN BIT(3)
65 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
66 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
67 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
68 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
69 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
70 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
73 * struct chv_alternate_function - A per group or per pin alternate function
74 * @pin: Pin number (only used in per pin configs)
75 * @mode: Mode the pin should be set in
76 * @invert_oe: Invert OE for this pin
78 struct chv_alternate_function
{
85 * struct chv_pincgroup - describes a CHV pin group
86 * @name: Name of the group
87 * @pins: An array of pins in this group
88 * @npins: Number of pins in this group
89 * @altfunc: Alternate function applied to all pins in this group
90 * @overrides: Alternate function override per pin or %NULL if not used
91 * @noverrides: Number of per pin alternate function overrides if
98 struct chv_alternate_function altfunc
;
99 const struct chv_alternate_function
*overrides
;
104 * struct chv_function - A CHV pinmux function
105 * @name: Name of the function
106 * @groups: An array of groups for this function
107 * @ngroups: Number of groups in @groups
109 struct chv_function
{
111 const char * const *groups
;
116 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
117 * @base: Start pin number
118 * @npins: Number of pins in this range
120 struct chv_gpio_pinrange
{
126 * struct chv_community - A community specific configuration
127 * @uid: ACPI _UID used to match the community
128 * @pins: All pins in this community
129 * @npins: Number of pins
130 * @groups: All groups in this community
131 * @ngroups: Number of groups
132 * @functions: All functions in this community
133 * @nfunctions: Number of functions
134 * @ngpios: Number of GPIOs in this community
135 * @gpio_ranges: An array of GPIO ranges in this community
136 * @ngpio_ranges: Number of GPIO ranges
137 * @ngpios: Total number of GPIOs in this community
138 * @nirqs: Total number of IRQs this community can generate
140 struct chv_community
{
142 const struct pinctrl_pin_desc
*pins
;
144 const struct chv_pingroup
*groups
;
146 const struct chv_function
*functions
;
148 const struct chv_gpio_pinrange
*gpio_ranges
;
152 acpi_adr_space_type acpi_space_id
;
155 struct chv_pin_context
{
161 * struct chv_pinctrl - CHV pinctrl private structure
162 * @dev: Pointer to the parent device
163 * @pctldesc: Pin controller description
164 * @pctldev: Pointer to the pin controller device
165 * @chip: GPIO chip in this pin controller
166 * @regs: MMIO registers
167 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
168 * offset (in GPIO number space)
169 * @community: Community this pinctrl instance represents
171 * The first group in @groups is expected to contain all pins that can be
176 struct pinctrl_desc pctldesc
;
177 struct pinctrl_dev
*pctldev
;
178 struct gpio_chip chip
;
180 unsigned intr_lines
[16];
181 const struct chv_community
*community
;
183 struct chv_pin_context
*saved_pin_context
;
186 #define ALTERNATE_FUNCTION(p, m, i) \
193 #define PIN_GROUP(n, p, m, i) \
197 .npins = ARRAY_SIZE((p)), \
198 .altfunc.mode = (m), \
199 .altfunc.invert_oe = (i), \
202 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
206 .npins = ARRAY_SIZE((p)), \
207 .altfunc.mode = (m), \
208 .altfunc.invert_oe = (i), \
210 .noverrides = ARRAY_SIZE((o)), \
213 #define FUNCTION(n, g) \
217 .ngroups = ARRAY_SIZE((g)), \
220 #define GPIO_PINRANGE(start, end) \
223 .npins = (end) - (start) + 1, \
226 static const struct pinctrl_pin_desc southwest_pins
[] = {
227 PINCTRL_PIN(0, "FST_SPI_D2"),
228 PINCTRL_PIN(1, "FST_SPI_D0"),
229 PINCTRL_PIN(2, "FST_SPI_CLK"),
230 PINCTRL_PIN(3, "FST_SPI_D3"),
231 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
232 PINCTRL_PIN(5, "FST_SPI_D1"),
233 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
234 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
236 PINCTRL_PIN(15, "UART1_RTS_B"),
237 PINCTRL_PIN(16, "UART1_RXD"),
238 PINCTRL_PIN(17, "UART2_RXD"),
239 PINCTRL_PIN(18, "UART1_CTS_B"),
240 PINCTRL_PIN(19, "UART2_RTS_B"),
241 PINCTRL_PIN(20, "UART1_TXD"),
242 PINCTRL_PIN(21, "UART2_TXD"),
243 PINCTRL_PIN(22, "UART2_CTS_B"),
245 PINCTRL_PIN(30, "MF_HDA_CLK"),
246 PINCTRL_PIN(31, "MF_HDA_RSTB"),
247 PINCTRL_PIN(32, "MF_HDA_SDIO"),
248 PINCTRL_PIN(33, "MF_HDA_SDO"),
249 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
250 PINCTRL_PIN(35, "MF_HDA_SYNC"),
251 PINCTRL_PIN(36, "MF_HDA_SDI1"),
252 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
254 PINCTRL_PIN(45, "I2C5_SDA"),
255 PINCTRL_PIN(46, "I2C4_SDA"),
256 PINCTRL_PIN(47, "I2C6_SDA"),
257 PINCTRL_PIN(48, "I2C5_SCL"),
258 PINCTRL_PIN(49, "I2C_NFC_SDA"),
259 PINCTRL_PIN(50, "I2C4_SCL"),
260 PINCTRL_PIN(51, "I2C6_SCL"),
261 PINCTRL_PIN(52, "I2C_NFC_SCL"),
263 PINCTRL_PIN(60, "I2C1_SDA"),
264 PINCTRL_PIN(61, "I2C0_SDA"),
265 PINCTRL_PIN(62, "I2C2_SDA"),
266 PINCTRL_PIN(63, "I2C1_SCL"),
267 PINCTRL_PIN(64, "I2C3_SDA"),
268 PINCTRL_PIN(65, "I2C0_SCL"),
269 PINCTRL_PIN(66, "I2C2_SCL"),
270 PINCTRL_PIN(67, "I2C3_SCL"),
272 PINCTRL_PIN(75, "SATA_GP0"),
273 PINCTRL_PIN(76, "SATA_GP1"),
274 PINCTRL_PIN(77, "SATA_LEDN"),
275 PINCTRL_PIN(78, "SATA_GP2"),
276 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
277 PINCTRL_PIN(80, "SATA_GP3"),
278 PINCTRL_PIN(81, "MF_SMB_CLK"),
279 PINCTRL_PIN(82, "MF_SMB_DATA"),
281 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
282 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
283 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
284 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
285 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
286 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
287 PINCTRL_PIN(96, "GP_SSP_2_FS"),
288 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
291 static const unsigned southwest_fspi_pins
[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
292 static const unsigned southwest_uart0_pins
[] = { 16, 20 };
293 static const unsigned southwest_uart1_pins
[] = { 15, 16, 18, 20 };
294 static const unsigned southwest_uart2_pins
[] = { 17, 19, 21, 22 };
295 static const unsigned southwest_i2c0_pins
[] = { 61, 65 };
296 static const unsigned southwest_hda_pins
[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
297 static const unsigned southwest_lpe_pins
[] = {
298 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
300 static const unsigned southwest_i2c1_pins
[] = { 60, 63 };
301 static const unsigned southwest_i2c2_pins
[] = { 62, 66 };
302 static const unsigned southwest_i2c3_pins
[] = { 64, 67 };
303 static const unsigned southwest_i2c4_pins
[] = { 46, 50 };
304 static const unsigned southwest_i2c5_pins
[] = { 45, 48 };
305 static const unsigned southwest_i2c6_pins
[] = { 47, 51 };
306 static const unsigned southwest_i2c_nfc_pins
[] = { 49, 52 };
307 static const unsigned southwest_smbus_pins
[] = { 79, 81, 82 };
308 static const unsigned southwest_spi3_pins
[] = { 76, 79, 80, 81, 82 };
310 /* LPE I2S TXD pins need to have invert_oe set */
311 static const struct chv_alternate_function southwest_lpe_altfuncs
[] = {
312 ALTERNATE_FUNCTION(30, 1, true),
313 ALTERNATE_FUNCTION(34, 1, true),
314 ALTERNATE_FUNCTION(97, 1, true),
318 * Two spi3 chipselects are available in different mode than the main spi3
319 * functionality, which is using mode 1.
321 static const struct chv_alternate_function southwest_spi3_altfuncs
[] = {
322 ALTERNATE_FUNCTION(76, 3, false),
323 ALTERNATE_FUNCTION(80, 3, false),
326 static const struct chv_pingroup southwest_groups
[] = {
327 PIN_GROUP("uart0_grp", southwest_uart0_pins
, 2, false),
328 PIN_GROUP("uart1_grp", southwest_uart1_pins
, 1, false),
329 PIN_GROUP("uart2_grp", southwest_uart2_pins
, 1, false),
330 PIN_GROUP("hda_grp", southwest_hda_pins
, 2, false),
331 PIN_GROUP("i2c0_grp", southwest_i2c0_pins
, 1, true),
332 PIN_GROUP("i2c1_grp", southwest_i2c1_pins
, 1, true),
333 PIN_GROUP("i2c2_grp", southwest_i2c2_pins
, 1, true),
334 PIN_GROUP("i2c3_grp", southwest_i2c3_pins
, 1, true),
335 PIN_GROUP("i2c4_grp", southwest_i2c4_pins
, 1, true),
336 PIN_GROUP("i2c5_grp", southwest_i2c5_pins
, 1, true),
337 PIN_GROUP("i2c6_grp", southwest_i2c6_pins
, 1, true),
338 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins
, 2, true),
340 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins
, 1, false,
341 southwest_lpe_altfuncs
),
342 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins
, 2, false,
343 southwest_spi3_altfuncs
),
346 static const char * const southwest_uart0_groups
[] = { "uart0_grp" };
347 static const char * const southwest_uart1_groups
[] = { "uart1_grp" };
348 static const char * const southwest_uart2_groups
[] = { "uart2_grp" };
349 static const char * const southwest_hda_groups
[] = { "hda_grp" };
350 static const char * const southwest_lpe_groups
[] = { "lpe_grp" };
351 static const char * const southwest_i2c0_groups
[] = { "i2c0_grp" };
352 static const char * const southwest_i2c1_groups
[] = { "i2c1_grp" };
353 static const char * const southwest_i2c2_groups
[] = { "i2c2_grp" };
354 static const char * const southwest_i2c3_groups
[] = { "i2c3_grp" };
355 static const char * const southwest_i2c4_groups
[] = { "i2c4_grp" };
356 static const char * const southwest_i2c5_groups
[] = { "i2c5_grp" };
357 static const char * const southwest_i2c6_groups
[] = { "i2c6_grp" };
358 static const char * const southwest_i2c_nfc_groups
[] = { "i2c_nfc_grp" };
359 static const char * const southwest_spi3_groups
[] = { "spi3_grp" };
362 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
363 * enabled only as GPIOs.
365 static const struct chv_function southwest_functions
[] = {
366 FUNCTION("uart0", southwest_uart0_groups
),
367 FUNCTION("uart1", southwest_uart1_groups
),
368 FUNCTION("uart2", southwest_uart2_groups
),
369 FUNCTION("hda", southwest_hda_groups
),
370 FUNCTION("lpe", southwest_lpe_groups
),
371 FUNCTION("i2c0", southwest_i2c0_groups
),
372 FUNCTION("i2c1", southwest_i2c1_groups
),
373 FUNCTION("i2c2", southwest_i2c2_groups
),
374 FUNCTION("i2c3", southwest_i2c3_groups
),
375 FUNCTION("i2c4", southwest_i2c4_groups
),
376 FUNCTION("i2c5", southwest_i2c5_groups
),
377 FUNCTION("i2c6", southwest_i2c6_groups
),
378 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups
),
379 FUNCTION("spi3", southwest_spi3_groups
),
382 static const struct chv_gpio_pinrange southwest_gpio_ranges
[] = {
384 GPIO_PINRANGE(15, 22),
385 GPIO_PINRANGE(30, 37),
386 GPIO_PINRANGE(45, 52),
387 GPIO_PINRANGE(60, 67),
388 GPIO_PINRANGE(75, 82),
389 GPIO_PINRANGE(90, 97),
392 static const struct chv_community southwest_community
= {
394 .pins
= southwest_pins
,
395 .npins
= ARRAY_SIZE(southwest_pins
),
396 .groups
= southwest_groups
,
397 .ngroups
= ARRAY_SIZE(southwest_groups
),
398 .functions
= southwest_functions
,
399 .nfunctions
= ARRAY_SIZE(southwest_functions
),
400 .gpio_ranges
= southwest_gpio_ranges
,
401 .ngpio_ranges
= ARRAY_SIZE(southwest_gpio_ranges
),
402 .ngpios
= ARRAY_SIZE(southwest_pins
),
404 * Southwest community can benerate GPIO interrupts only for the
405 * first 8 interrupts. The upper half (8-15) can only be used to
409 .acpi_space_id
= 0x91,
412 static const struct pinctrl_pin_desc north_pins
[] = {
413 PINCTRL_PIN(0, "GPIO_DFX_0"),
414 PINCTRL_PIN(1, "GPIO_DFX_3"),
415 PINCTRL_PIN(2, "GPIO_DFX_7"),
416 PINCTRL_PIN(3, "GPIO_DFX_1"),
417 PINCTRL_PIN(4, "GPIO_DFX_5"),
418 PINCTRL_PIN(5, "GPIO_DFX_4"),
419 PINCTRL_PIN(6, "GPIO_DFX_8"),
420 PINCTRL_PIN(7, "GPIO_DFX_2"),
421 PINCTRL_PIN(8, "GPIO_DFX_6"),
423 PINCTRL_PIN(15, "GPIO_SUS0"),
424 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
425 PINCTRL_PIN(17, "GPIO_SUS3"),
426 PINCTRL_PIN(18, "GPIO_SUS7"),
427 PINCTRL_PIN(19, "GPIO_SUS1"),
428 PINCTRL_PIN(20, "GPIO_SUS5"),
429 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
430 PINCTRL_PIN(22, "GPIO_SUS4"),
431 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
432 PINCTRL_PIN(24, "GPIO_SUS2"),
433 PINCTRL_PIN(25, "GPIO_SUS6"),
434 PINCTRL_PIN(26, "CX_PREQ_B"),
435 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
437 PINCTRL_PIN(30, "TRST_B"),
438 PINCTRL_PIN(31, "TCK"),
439 PINCTRL_PIN(32, "PROCHOT_B"),
440 PINCTRL_PIN(33, "SVIDO_DATA"),
441 PINCTRL_PIN(34, "TMS"),
442 PINCTRL_PIN(35, "CX_PRDY_B_2"),
443 PINCTRL_PIN(36, "TDO_2"),
444 PINCTRL_PIN(37, "CX_PRDY_B"),
445 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
446 PINCTRL_PIN(39, "TDO"),
447 PINCTRL_PIN(40, "SVIDO_CLK"),
448 PINCTRL_PIN(41, "TDI"),
450 PINCTRL_PIN(45, "GP_CAMERASB_05"),
451 PINCTRL_PIN(46, "GP_CAMERASB_02"),
452 PINCTRL_PIN(47, "GP_CAMERASB_08"),
453 PINCTRL_PIN(48, "GP_CAMERASB_00"),
454 PINCTRL_PIN(49, "GP_CAMERASB_06"),
455 PINCTRL_PIN(50, "GP_CAMERASB_10"),
456 PINCTRL_PIN(51, "GP_CAMERASB_03"),
457 PINCTRL_PIN(52, "GP_CAMERASB_09"),
458 PINCTRL_PIN(53, "GP_CAMERASB_01"),
459 PINCTRL_PIN(54, "GP_CAMERASB_07"),
460 PINCTRL_PIN(55, "GP_CAMERASB_11"),
461 PINCTRL_PIN(56, "GP_CAMERASB_04"),
463 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
464 PINCTRL_PIN(61, "HV_DDI0_HPD"),
465 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
466 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
467 PINCTRL_PIN(64, "HV_DDI1_HPD"),
468 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
469 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
470 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
471 PINCTRL_PIN(68, "HV_DDI2_HPD"),
472 PINCTRL_PIN(69, "PANEL1_VDDEN"),
473 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
474 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
475 PINCTRL_PIN(72, "PANEL0_VDDEN"),
478 static const struct chv_gpio_pinrange north_gpio_ranges
[] = {
480 GPIO_PINRANGE(15, 27),
481 GPIO_PINRANGE(30, 41),
482 GPIO_PINRANGE(45, 56),
483 GPIO_PINRANGE(60, 72),
486 static const struct chv_community north_community
= {
489 .npins
= ARRAY_SIZE(north_pins
),
490 .gpio_ranges
= north_gpio_ranges
,
491 .ngpio_ranges
= ARRAY_SIZE(north_gpio_ranges
),
492 .ngpios
= ARRAY_SIZE(north_pins
),
494 * North community can benerate GPIO interrupts only for the first
495 * 8 interrupts. The upper half (8-15) can only be used to trigger
499 .acpi_space_id
= 0x92,
502 static const struct pinctrl_pin_desc east_pins
[] = {
503 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
504 PINCTRL_PIN(1, "PMU_BATLOW_B"),
505 PINCTRL_PIN(2, "SUS_STAT_B"),
506 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
507 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
508 PINCTRL_PIN(5, "PMU_PLTRST_B"),
509 PINCTRL_PIN(6, "PMU_SUSCLK"),
510 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
511 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
512 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
513 PINCTRL_PIN(10, "PMU_WAKE_B"),
514 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
516 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
517 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
518 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
519 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
520 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
521 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
522 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
523 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
524 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
525 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
526 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
527 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
530 static const struct chv_gpio_pinrange east_gpio_ranges
[] = {
531 GPIO_PINRANGE(0, 11),
532 GPIO_PINRANGE(15, 26),
535 static const struct chv_community east_community
= {
538 .npins
= ARRAY_SIZE(east_pins
),
539 .gpio_ranges
= east_gpio_ranges
,
540 .ngpio_ranges
= ARRAY_SIZE(east_gpio_ranges
),
541 .ngpios
= ARRAY_SIZE(east_pins
),
543 .acpi_space_id
= 0x93,
546 static const struct pinctrl_pin_desc southeast_pins
[] = {
547 PINCTRL_PIN(0, "MF_PLT_CLK0"),
548 PINCTRL_PIN(1, "PWM1"),
549 PINCTRL_PIN(2, "MF_PLT_CLK1"),
550 PINCTRL_PIN(3, "MF_PLT_CLK4"),
551 PINCTRL_PIN(4, "MF_PLT_CLK3"),
552 PINCTRL_PIN(5, "PWM0"),
553 PINCTRL_PIN(6, "MF_PLT_CLK5"),
554 PINCTRL_PIN(7, "MF_PLT_CLK2"),
556 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
557 PINCTRL_PIN(16, "SDMMC1_CLK"),
558 PINCTRL_PIN(17, "SDMMC1_D0"),
559 PINCTRL_PIN(18, "SDMMC2_D1"),
560 PINCTRL_PIN(19, "SDMMC2_CLK"),
561 PINCTRL_PIN(20, "SDMMC1_D2"),
562 PINCTRL_PIN(21, "SDMMC2_D2"),
563 PINCTRL_PIN(22, "SDMMC2_CMD"),
564 PINCTRL_PIN(23, "SDMMC1_CMD"),
565 PINCTRL_PIN(24, "SDMMC1_D1"),
566 PINCTRL_PIN(25, "SDMMC2_D0"),
567 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
569 PINCTRL_PIN(30, "SDMMC3_D1"),
570 PINCTRL_PIN(31, "SDMMC3_CLK"),
571 PINCTRL_PIN(32, "SDMMC3_D3"),
572 PINCTRL_PIN(33, "SDMMC3_D2"),
573 PINCTRL_PIN(34, "SDMMC3_CMD"),
574 PINCTRL_PIN(35, "SDMMC3_D0"),
576 PINCTRL_PIN(45, "MF_LPC_AD2"),
577 PINCTRL_PIN(46, "LPC_CLKRUNB"),
578 PINCTRL_PIN(47, "MF_LPC_AD0"),
579 PINCTRL_PIN(48, "LPC_FRAMEB"),
580 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
581 PINCTRL_PIN(50, "MF_LPC_AD3"),
582 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
583 PINCTRL_PIN(52, "MF_LPC_AD1"),
585 PINCTRL_PIN(60, "SPI1_MISO"),
586 PINCTRL_PIN(61, "SPI1_CSO_B"),
587 PINCTRL_PIN(62, "SPI1_CLK"),
588 PINCTRL_PIN(63, "MMC1_D6"),
589 PINCTRL_PIN(64, "SPI1_MOSI"),
590 PINCTRL_PIN(65, "MMC1_D5"),
591 PINCTRL_PIN(66, "SPI1_CS1_B"),
592 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
593 PINCTRL_PIN(68, "MMC1_D7"),
594 PINCTRL_PIN(69, "MMC1_RCLK"),
596 PINCTRL_PIN(75, "USB_OC1_B"),
597 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
598 PINCTRL_PIN(77, "GPIO_ALERT"),
599 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
600 PINCTRL_PIN(79, "ILB_SERIRQ"),
601 PINCTRL_PIN(80, "USB_OC0_B"),
602 PINCTRL_PIN(81, "SDMMC3_CD_B"),
603 PINCTRL_PIN(82, "SPKR"),
604 PINCTRL_PIN(83, "SUSPWRDNACK"),
605 PINCTRL_PIN(84, "SPARE_PIN"),
606 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
609 static const unsigned southeast_pwm0_pins
[] = { 5 };
610 static const unsigned southeast_pwm1_pins
[] = { 1 };
611 static const unsigned southeast_sdmmc1_pins
[] = {
612 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
614 static const unsigned southeast_sdmmc2_pins
[] = { 15, 18, 19, 21, 22, 25 };
615 static const unsigned southeast_sdmmc3_pins
[] = {
616 30, 31, 32, 33, 34, 35, 78, 81, 85,
618 static const unsigned southeast_spi1_pins
[] = { 60, 61, 62, 64, 66 };
619 static const unsigned southeast_spi2_pins
[] = { 2, 3, 4, 6, 7 };
621 static const struct chv_pingroup southeast_groups
[] = {
622 PIN_GROUP("pwm0_grp", southeast_pwm0_pins
, 1, false),
623 PIN_GROUP("pwm1_grp", southeast_pwm1_pins
, 1, false),
624 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins
, 1, false),
625 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins
, 1, false),
626 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins
, 1, false),
627 PIN_GROUP("spi1_grp", southeast_spi1_pins
, 1, false),
628 PIN_GROUP("spi2_grp", southeast_spi2_pins
, 4, false),
631 static const char * const southeast_pwm0_groups
[] = { "pwm0_grp" };
632 static const char * const southeast_pwm1_groups
[] = { "pwm1_grp" };
633 static const char * const southeast_sdmmc1_groups
[] = { "sdmmc1_grp" };
634 static const char * const southeast_sdmmc2_groups
[] = { "sdmmc2_grp" };
635 static const char * const southeast_sdmmc3_groups
[] = { "sdmmc3_grp" };
636 static const char * const southeast_spi1_groups
[] = { "spi1_grp" };
637 static const char * const southeast_spi2_groups
[] = { "spi2_grp" };
639 static const struct chv_function southeast_functions
[] = {
640 FUNCTION("pwm0", southeast_pwm0_groups
),
641 FUNCTION("pwm1", southeast_pwm1_groups
),
642 FUNCTION("sdmmc1", southeast_sdmmc1_groups
),
643 FUNCTION("sdmmc2", southeast_sdmmc2_groups
),
644 FUNCTION("sdmmc3", southeast_sdmmc3_groups
),
645 FUNCTION("spi1", southeast_spi1_groups
),
646 FUNCTION("spi2", southeast_spi2_groups
),
649 static const struct chv_gpio_pinrange southeast_gpio_ranges
[] = {
651 GPIO_PINRANGE(15, 26),
652 GPIO_PINRANGE(30, 35),
653 GPIO_PINRANGE(45, 52),
654 GPIO_PINRANGE(60, 69),
655 GPIO_PINRANGE(75, 85),
658 static const struct chv_community southeast_community
= {
660 .pins
= southeast_pins
,
661 .npins
= ARRAY_SIZE(southeast_pins
),
662 .groups
= southeast_groups
,
663 .ngroups
= ARRAY_SIZE(southeast_groups
),
664 .functions
= southeast_functions
,
665 .nfunctions
= ARRAY_SIZE(southeast_functions
),
666 .gpio_ranges
= southeast_gpio_ranges
,
667 .ngpio_ranges
= ARRAY_SIZE(southeast_gpio_ranges
),
668 .ngpios
= ARRAY_SIZE(southeast_pins
),
670 .acpi_space_id
= 0x94,
673 static const struct chv_community
*chv_communities
[] = {
674 &southwest_community
,
677 &southeast_community
,
681 * Lock to serialize register accesses
683 * Due to a silicon issue, a shared lock must be used to prevent
684 * concurrent accesses across the 4 GPIO controllers.
686 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
687 * errata #CHT34, for further information.
689 static DEFINE_RAW_SPINLOCK(chv_lock
);
691 static void __iomem
*chv_padreg(struct chv_pinctrl
*pctrl
, unsigned offset
,
694 unsigned family_no
= offset
/ MAX_FAMILY_PAD_GPIO_NO
;
695 unsigned pad_no
= offset
% MAX_FAMILY_PAD_GPIO_NO
;
697 offset
= FAMILY_PAD_REGS_OFF
+ FAMILY_PAD_REGS_SIZE
* family_no
+
698 GPIO_REGS_SIZE
* pad_no
;
700 return pctrl
->regs
+ offset
+ reg
;
703 static void chv_writel(u32 value
, void __iomem
*reg
)
706 /* simple readback to confirm the bus transferring done */
710 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
711 static bool chv_pad_locked(struct chv_pinctrl
*pctrl
, unsigned offset
)
715 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL1
);
716 return readl(reg
) & CHV_PADCTRL1_CFGLOCK
;
719 static int chv_get_groups_count(struct pinctrl_dev
*pctldev
)
721 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
723 return pctrl
->community
->ngroups
;
726 static const char *chv_get_group_name(struct pinctrl_dev
*pctldev
,
729 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
731 return pctrl
->community
->groups
[group
].name
;
734 static int chv_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned group
,
735 const unsigned **pins
, unsigned *npins
)
737 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
739 *pins
= pctrl
->community
->groups
[group
].pins
;
740 *npins
= pctrl
->community
->groups
[group
].npins
;
744 static void chv_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
747 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
752 raw_spin_lock_irqsave(&chv_lock
, flags
);
754 ctrl0
= readl(chv_padreg(pctrl
, offset
, CHV_PADCTRL0
));
755 ctrl1
= readl(chv_padreg(pctrl
, offset
, CHV_PADCTRL1
));
756 locked
= chv_pad_locked(pctrl
, offset
);
758 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
760 if (ctrl0
& CHV_PADCTRL0_GPIOEN
) {
761 seq_puts(s
, "GPIO ");
765 mode
= ctrl0
& CHV_PADCTRL0_PMODE_MASK
;
766 mode
>>= CHV_PADCTRL0_PMODE_SHIFT
;
768 seq_printf(s
, "mode %d ", mode
);
771 seq_printf(s
, "0x%08x 0x%08x", ctrl0
, ctrl1
);
774 seq_puts(s
, " [LOCKED]");
777 static const struct pinctrl_ops chv_pinctrl_ops
= {
778 .get_groups_count
= chv_get_groups_count
,
779 .get_group_name
= chv_get_group_name
,
780 .get_group_pins
= chv_get_group_pins
,
781 .pin_dbg_show
= chv_pin_dbg_show
,
784 static int chv_get_functions_count(struct pinctrl_dev
*pctldev
)
786 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
788 return pctrl
->community
->nfunctions
;
791 static const char *chv_get_function_name(struct pinctrl_dev
*pctldev
,
794 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
796 return pctrl
->community
->functions
[function
].name
;
799 static int chv_get_function_groups(struct pinctrl_dev
*pctldev
,
801 const char * const **groups
,
802 unsigned * const ngroups
)
804 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
806 *groups
= pctrl
->community
->functions
[function
].groups
;
807 *ngroups
= pctrl
->community
->functions
[function
].ngroups
;
811 static int chv_pinmux_set_mux(struct pinctrl_dev
*pctldev
, unsigned function
,
814 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
815 const struct chv_pingroup
*grp
;
819 grp
= &pctrl
->community
->groups
[group
];
821 raw_spin_lock_irqsave(&chv_lock
, flags
);
823 /* Check first that the pad is not locked */
824 for (i
= 0; i
< grp
->npins
; i
++) {
825 if (chv_pad_locked(pctrl
, grp
->pins
[i
])) {
826 dev_warn(pctrl
->dev
, "unable to set mode for locked pin %u\n",
828 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
833 for (i
= 0; i
< grp
->npins
; i
++) {
834 const struct chv_alternate_function
*altfunc
= &grp
->altfunc
;
835 int pin
= grp
->pins
[i
];
839 /* Check if there is pin-specific config */
840 if (grp
->overrides
) {
843 for (j
= 0; j
< grp
->noverrides
; j
++) {
844 if (grp
->overrides
[j
].pin
== pin
) {
845 altfunc
= &grp
->overrides
[j
];
851 reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL0
);
853 /* Disable GPIO mode */
854 value
&= ~CHV_PADCTRL0_GPIOEN
;
855 /* Set to desired mode */
856 value
&= ~CHV_PADCTRL0_PMODE_MASK
;
857 value
|= altfunc
->mode
<< CHV_PADCTRL0_PMODE_SHIFT
;
858 chv_writel(value
, reg
);
860 /* Update for invert_oe */
861 reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL1
);
862 value
= readl(reg
) & ~CHV_PADCTRL1_INVRXTX_MASK
;
863 if (altfunc
->invert_oe
)
864 value
|= CHV_PADCTRL1_INVRXTX_TXENABLE
;
865 chv_writel(value
, reg
);
867 dev_dbg(pctrl
->dev
, "configured pin %u mode %u OE %sinverted\n",
868 pin
, altfunc
->mode
, altfunc
->invert_oe
? "" : "not ");
871 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
876 static int chv_gpio_request_enable(struct pinctrl_dev
*pctldev
,
877 struct pinctrl_gpio_range
*range
,
880 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
885 raw_spin_lock_irqsave(&chv_lock
, flags
);
887 if (chv_pad_locked(pctrl
, offset
)) {
888 value
= readl(chv_padreg(pctrl
, offset
, CHV_PADCTRL0
));
889 if (!(value
& CHV_PADCTRL0_GPIOEN
)) {
890 /* Locked so cannot enable */
891 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
897 /* Reset the interrupt mapping */
898 for (i
= 0; i
< ARRAY_SIZE(pctrl
->intr_lines
); i
++) {
899 if (pctrl
->intr_lines
[i
] == offset
) {
900 pctrl
->intr_lines
[i
] = 0;
905 /* Disable interrupt generation */
906 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL1
);
908 value
&= ~CHV_PADCTRL1_INTWAKECFG_MASK
;
909 value
&= ~CHV_PADCTRL1_INVRXTX_MASK
;
910 chv_writel(value
, reg
);
912 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL0
);
916 * If the pin is in HiZ mode (both TX and RX buffers are
917 * disabled) we turn it to be input now.
919 if ((value
& CHV_PADCTRL0_GPIOCFG_MASK
) ==
920 (CHV_PADCTRL0_GPIOCFG_HIZ
<< CHV_PADCTRL0_GPIOCFG_SHIFT
)) {
921 value
&= ~CHV_PADCTRL0_GPIOCFG_MASK
;
922 value
|= CHV_PADCTRL0_GPIOCFG_GPI
<<
923 CHV_PADCTRL0_GPIOCFG_SHIFT
;
926 /* Switch to a GPIO mode */
927 value
|= CHV_PADCTRL0_GPIOEN
;
928 chv_writel(value
, reg
);
931 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
936 static void chv_gpio_disable_free(struct pinctrl_dev
*pctldev
,
937 struct pinctrl_gpio_range
*range
,
940 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
945 raw_spin_lock_irqsave(&chv_lock
, flags
);
947 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL0
);
948 value
= readl(reg
) & ~CHV_PADCTRL0_GPIOEN
;
949 chv_writel(value
, reg
);
951 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
954 static int chv_gpio_set_direction(struct pinctrl_dev
*pctldev
,
955 struct pinctrl_gpio_range
*range
,
956 unsigned offset
, bool input
)
958 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
959 void __iomem
*reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL0
);
963 raw_spin_lock_irqsave(&chv_lock
, flags
);
965 ctrl0
= readl(reg
) & ~CHV_PADCTRL0_GPIOCFG_MASK
;
967 ctrl0
|= CHV_PADCTRL0_GPIOCFG_GPI
<< CHV_PADCTRL0_GPIOCFG_SHIFT
;
969 ctrl0
|= CHV_PADCTRL0_GPIOCFG_GPO
<< CHV_PADCTRL0_GPIOCFG_SHIFT
;
970 chv_writel(ctrl0
, reg
);
972 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
977 static const struct pinmux_ops chv_pinmux_ops
= {
978 .get_functions_count
= chv_get_functions_count
,
979 .get_function_name
= chv_get_function_name
,
980 .get_function_groups
= chv_get_function_groups
,
981 .set_mux
= chv_pinmux_set_mux
,
982 .gpio_request_enable
= chv_gpio_request_enable
,
983 .gpio_disable_free
= chv_gpio_disable_free
,
984 .gpio_set_direction
= chv_gpio_set_direction
,
987 static int chv_config_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
988 unsigned long *config
)
990 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
991 enum pin_config_param param
= pinconf_to_config_param(*config
);
997 raw_spin_lock_irqsave(&chv_lock
, flags
);
998 ctrl0
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
999 ctrl1
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL1
));
1000 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1002 term
= (ctrl0
& CHV_PADCTRL0_TERM_MASK
) >> CHV_PADCTRL0_TERM_SHIFT
;
1005 case PIN_CONFIG_BIAS_DISABLE
:
1010 case PIN_CONFIG_BIAS_PULL_UP
:
1011 if (!(ctrl0
& CHV_PADCTRL0_TERM_UP
))
1015 case CHV_PADCTRL0_TERM_20K
:
1018 case CHV_PADCTRL0_TERM_5K
:
1021 case CHV_PADCTRL0_TERM_1K
:
1028 case PIN_CONFIG_BIAS_PULL_DOWN
:
1029 if (!term
|| (ctrl0
& CHV_PADCTRL0_TERM_UP
))
1033 case CHV_PADCTRL0_TERM_20K
:
1036 case CHV_PADCTRL0_TERM_5K
:
1043 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
1044 if (!(ctrl1
& CHV_PADCTRL1_ODEN
))
1048 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE
: {
1051 cfg
= ctrl0
& CHV_PADCTRL0_GPIOCFG_MASK
;
1052 cfg
>>= CHV_PADCTRL0_GPIOCFG_SHIFT
;
1053 if (cfg
!= CHV_PADCTRL0_GPIOCFG_HIZ
)
1063 *config
= pinconf_to_config_packed(param
, arg
);
1067 static int chv_config_set_pull(struct chv_pinctrl
*pctrl
, unsigned pin
,
1068 enum pin_config_param param
, u32 arg
)
1070 void __iomem
*reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL0
);
1071 unsigned long flags
;
1074 raw_spin_lock_irqsave(&chv_lock
, flags
);
1078 case PIN_CONFIG_BIAS_DISABLE
:
1079 ctrl0
&= ~(CHV_PADCTRL0_TERM_MASK
| CHV_PADCTRL0_TERM_UP
);
1082 case PIN_CONFIG_BIAS_PULL_UP
:
1083 ctrl0
&= ~(CHV_PADCTRL0_TERM_MASK
| CHV_PADCTRL0_TERM_UP
);
1087 /* For 1k there is only pull up */
1088 pull
= CHV_PADCTRL0_TERM_1K
<< CHV_PADCTRL0_TERM_SHIFT
;
1091 pull
= CHV_PADCTRL0_TERM_5K
<< CHV_PADCTRL0_TERM_SHIFT
;
1094 pull
= CHV_PADCTRL0_TERM_20K
<< CHV_PADCTRL0_TERM_SHIFT
;
1097 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1101 ctrl0
|= CHV_PADCTRL0_TERM_UP
| pull
;
1104 case PIN_CONFIG_BIAS_PULL_DOWN
:
1105 ctrl0
&= ~(CHV_PADCTRL0_TERM_MASK
| CHV_PADCTRL0_TERM_UP
);
1109 pull
= CHV_PADCTRL0_TERM_5K
<< CHV_PADCTRL0_TERM_SHIFT
;
1112 pull
= CHV_PADCTRL0_TERM_20K
<< CHV_PADCTRL0_TERM_SHIFT
;
1115 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1123 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1127 chv_writel(ctrl0
, reg
);
1128 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1133 static int chv_config_set_oden(struct chv_pinctrl
*pctrl
, unsigned int pin
,
1136 void __iomem
*reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL1
);
1137 unsigned long flags
;
1140 raw_spin_lock_irqsave(&chv_lock
, flags
);
1144 ctrl1
|= CHV_PADCTRL1_ODEN
;
1146 ctrl1
&= ~CHV_PADCTRL1_ODEN
;
1148 chv_writel(ctrl1
, reg
);
1149 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1154 static int chv_config_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
1155 unsigned long *configs
, unsigned nconfigs
)
1157 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
1158 enum pin_config_param param
;
1162 if (chv_pad_locked(pctrl
, pin
))
1165 for (i
= 0; i
< nconfigs
; i
++) {
1166 param
= pinconf_to_config_param(configs
[i
]);
1167 arg
= pinconf_to_config_argument(configs
[i
]);
1170 case PIN_CONFIG_BIAS_DISABLE
:
1171 case PIN_CONFIG_BIAS_PULL_UP
:
1172 case PIN_CONFIG_BIAS_PULL_DOWN
:
1173 ret
= chv_config_set_pull(pctrl
, pin
, param
, arg
);
1178 case PIN_CONFIG_DRIVE_PUSH_PULL
:
1179 ret
= chv_config_set_oden(pctrl
, pin
, false);
1184 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
1185 ret
= chv_config_set_oden(pctrl
, pin
, true);
1194 dev_dbg(pctrl
->dev
, "pin %d set config %d arg %u\n", pin
,
1201 static int chv_config_group_get(struct pinctrl_dev
*pctldev
,
1203 unsigned long *config
)
1205 const unsigned int *pins
;
1209 ret
= chv_get_group_pins(pctldev
, group
, &pins
, &npins
);
1213 ret
= chv_config_get(pctldev
, pins
[0], config
);
1220 static int chv_config_group_set(struct pinctrl_dev
*pctldev
,
1221 unsigned int group
, unsigned long *configs
,
1222 unsigned int num_configs
)
1224 const unsigned int *pins
;
1228 ret
= chv_get_group_pins(pctldev
, group
, &pins
, &npins
);
1232 for (i
= 0; i
< npins
; i
++) {
1233 ret
= chv_config_set(pctldev
, pins
[i
], configs
, num_configs
);
1241 static const struct pinconf_ops chv_pinconf_ops
= {
1243 .pin_config_set
= chv_config_set
,
1244 .pin_config_get
= chv_config_get
,
1245 .pin_config_group_get
= chv_config_group_get
,
1246 .pin_config_group_set
= chv_config_group_set
,
1249 static struct pinctrl_desc chv_pinctrl_desc
= {
1250 .pctlops
= &chv_pinctrl_ops
,
1251 .pmxops
= &chv_pinmux_ops
,
1252 .confops
= &chv_pinconf_ops
,
1253 .owner
= THIS_MODULE
,
1256 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl
*pctrl
,
1259 return pctrl
->community
->pins
[offset
].number
;
1262 static int chv_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1264 struct chv_pinctrl
*pctrl
= gpiochip_get_data(chip
);
1265 int pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1266 unsigned long flags
;
1269 raw_spin_lock_irqsave(&chv_lock
, flags
);
1270 ctrl0
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1271 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1273 cfg
= ctrl0
& CHV_PADCTRL0_GPIOCFG_MASK
;
1274 cfg
>>= CHV_PADCTRL0_GPIOCFG_SHIFT
;
1276 if (cfg
== CHV_PADCTRL0_GPIOCFG_GPO
)
1277 return !!(ctrl0
& CHV_PADCTRL0_GPIOTXSTATE
);
1278 return !!(ctrl0
& CHV_PADCTRL0_GPIORXSTATE
);
1281 static void chv_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1283 struct chv_pinctrl
*pctrl
= gpiochip_get_data(chip
);
1284 unsigned pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1285 unsigned long flags
;
1289 raw_spin_lock_irqsave(&chv_lock
, flags
);
1291 reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL0
);
1295 ctrl0
|= CHV_PADCTRL0_GPIOTXSTATE
;
1297 ctrl0
&= ~CHV_PADCTRL0_GPIOTXSTATE
;
1299 chv_writel(ctrl0
, reg
);
1301 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1304 static int chv_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
1306 struct chv_pinctrl
*pctrl
= gpiochip_get_data(chip
);
1307 unsigned pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1308 u32 ctrl0
, direction
;
1309 unsigned long flags
;
1311 raw_spin_lock_irqsave(&chv_lock
, flags
);
1312 ctrl0
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1313 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1315 direction
= ctrl0
& CHV_PADCTRL0_GPIOCFG_MASK
;
1316 direction
>>= CHV_PADCTRL0_GPIOCFG_SHIFT
;
1318 return direction
!= CHV_PADCTRL0_GPIOCFG_GPO
;
1321 static int chv_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1323 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
1326 static int chv_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1329 chv_gpio_set(chip
, offset
, value
);
1330 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
1333 static const struct gpio_chip chv_gpio_chip
= {
1334 .owner
= THIS_MODULE
,
1335 .request
= gpiochip_generic_request
,
1336 .free
= gpiochip_generic_free
,
1337 .get_direction
= chv_gpio_get_direction
,
1338 .direction_input
= chv_gpio_direction_input
,
1339 .direction_output
= chv_gpio_direction_output
,
1340 .get
= chv_gpio_get
,
1341 .set
= chv_gpio_set
,
1344 static void chv_gpio_irq_ack(struct irq_data
*d
)
1346 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1347 struct chv_pinctrl
*pctrl
= gpiochip_get_data(gc
);
1348 int pin
= chv_gpio_offset_to_pin(pctrl
, irqd_to_hwirq(d
));
1351 raw_spin_lock(&chv_lock
);
1353 intr_line
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1354 intr_line
&= CHV_PADCTRL0_INTSEL_MASK
;
1355 intr_line
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1356 chv_writel(BIT(intr_line
), pctrl
->regs
+ CHV_INTSTAT
);
1358 raw_spin_unlock(&chv_lock
);
1361 static void chv_gpio_irq_mask_unmask(struct irq_data
*d
, bool mask
)
1363 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1364 struct chv_pinctrl
*pctrl
= gpiochip_get_data(gc
);
1365 int pin
= chv_gpio_offset_to_pin(pctrl
, irqd_to_hwirq(d
));
1366 u32 value
, intr_line
;
1367 unsigned long flags
;
1369 raw_spin_lock_irqsave(&chv_lock
, flags
);
1371 intr_line
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1372 intr_line
&= CHV_PADCTRL0_INTSEL_MASK
;
1373 intr_line
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1375 value
= readl(pctrl
->regs
+ CHV_INTMASK
);
1377 value
&= ~BIT(intr_line
);
1379 value
|= BIT(intr_line
);
1380 chv_writel(value
, pctrl
->regs
+ CHV_INTMASK
);
1382 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1385 static void chv_gpio_irq_mask(struct irq_data
*d
)
1387 chv_gpio_irq_mask_unmask(d
, true);
1390 static void chv_gpio_irq_unmask(struct irq_data
*d
)
1392 chv_gpio_irq_mask_unmask(d
, false);
1395 static unsigned chv_gpio_irq_startup(struct irq_data
*d
)
1398 * Check if the interrupt has been requested with 0 as triggering
1399 * type. In that case it is assumed that the current values
1400 * programmed to the hardware are used (e.g BIOS configured
1403 * In that case ->irq_set_type() will never be called so we need to
1404 * read back the values from hardware now, set correct flow handler
1405 * and update mappings before the interrupt is being used.
1407 if (irqd_get_trigger_type(d
) == IRQ_TYPE_NONE
) {
1408 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1409 struct chv_pinctrl
*pctrl
= gpiochip_get_data(gc
);
1410 unsigned offset
= irqd_to_hwirq(d
);
1411 int pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1412 irq_flow_handler_t handler
;
1413 unsigned long flags
;
1416 raw_spin_lock_irqsave(&chv_lock
, flags
);
1417 intsel
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1418 intsel
&= CHV_PADCTRL0_INTSEL_MASK
;
1419 intsel
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1421 value
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL1
));
1422 if (value
& CHV_PADCTRL1_INTWAKECFG_LEVEL
)
1423 handler
= handle_level_irq
;
1425 handler
= handle_edge_irq
;
1427 if (!pctrl
->intr_lines
[intsel
]) {
1428 irq_set_handler_locked(d
, handler
);
1429 pctrl
->intr_lines
[intsel
] = offset
;
1431 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1434 chv_gpio_irq_unmask(d
);
1438 static int chv_gpio_irq_type(struct irq_data
*d
, unsigned type
)
1440 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1441 struct chv_pinctrl
*pctrl
= gpiochip_get_data(gc
);
1442 unsigned offset
= irqd_to_hwirq(d
);
1443 int pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1444 unsigned long flags
;
1447 raw_spin_lock_irqsave(&chv_lock
, flags
);
1450 * Pins which can be used as shared interrupt are configured in
1451 * BIOS. Driver trusts BIOS configurations and assigns different
1452 * handler according to the irq type.
1454 * Driver needs to save the mapping between each pin and
1455 * its interrupt line.
1456 * 1. If the pin cfg is locked in BIOS:
1457 * Trust BIOS has programmed IntWakeCfg bits correctly,
1458 * driver just needs to save the mapping.
1459 * 2. If the pin cfg is not locked in BIOS:
1460 * Driver programs the IntWakeCfg bits and save the mapping.
1462 if (!chv_pad_locked(pctrl
, pin
)) {
1463 void __iomem
*reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL1
);
1466 value
&= ~CHV_PADCTRL1_INTWAKECFG_MASK
;
1467 value
&= ~CHV_PADCTRL1_INVRXTX_MASK
;
1469 if (type
& IRQ_TYPE_EDGE_BOTH
) {
1470 if ((type
& IRQ_TYPE_EDGE_BOTH
) == IRQ_TYPE_EDGE_BOTH
)
1471 value
|= CHV_PADCTRL1_INTWAKECFG_BOTH
;
1472 else if (type
& IRQ_TYPE_EDGE_RISING
)
1473 value
|= CHV_PADCTRL1_INTWAKECFG_RISING
;
1474 else if (type
& IRQ_TYPE_EDGE_FALLING
)
1475 value
|= CHV_PADCTRL1_INTWAKECFG_FALLING
;
1476 } else if (type
& IRQ_TYPE_LEVEL_MASK
) {
1477 value
|= CHV_PADCTRL1_INTWAKECFG_LEVEL
;
1478 if (type
& IRQ_TYPE_LEVEL_LOW
)
1479 value
|= CHV_PADCTRL1_INVRXTX_RXDATA
;
1482 chv_writel(value
, reg
);
1485 value
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1486 value
&= CHV_PADCTRL0_INTSEL_MASK
;
1487 value
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1489 pctrl
->intr_lines
[value
] = offset
;
1491 if (type
& IRQ_TYPE_EDGE_BOTH
)
1492 irq_set_handler_locked(d
, handle_edge_irq
);
1493 else if (type
& IRQ_TYPE_LEVEL_MASK
)
1494 irq_set_handler_locked(d
, handle_level_irq
);
1496 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1501 static struct irq_chip chv_gpio_irqchip
= {
1503 .irq_startup
= chv_gpio_irq_startup
,
1504 .irq_ack
= chv_gpio_irq_ack
,
1505 .irq_mask
= chv_gpio_irq_mask
,
1506 .irq_unmask
= chv_gpio_irq_unmask
,
1507 .irq_set_type
= chv_gpio_irq_type
,
1508 .flags
= IRQCHIP_SKIP_SET_WAKE
,
1511 static void chv_gpio_irq_handler(struct irq_desc
*desc
)
1513 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
1514 struct chv_pinctrl
*pctrl
= gpiochip_get_data(gc
);
1515 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1516 unsigned long pending
;
1519 chained_irq_enter(chip
, desc
);
1521 pending
= readl(pctrl
->regs
+ CHV_INTSTAT
);
1522 for_each_set_bit(intr_line
, &pending
, pctrl
->community
->nirqs
) {
1523 unsigned irq
, offset
;
1525 offset
= pctrl
->intr_lines
[intr_line
];
1526 irq
= irq_find_mapping(gc
->irqdomain
, offset
);
1527 generic_handle_irq(irq
);
1530 chained_irq_exit(chip
, desc
);
1534 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1535 * tables. Since we leave GPIOs that are not capable of generating
1536 * interrupts out of the irqdomain the numbering will be different and
1537 * cause devices using the hardcoded IRQ numbers fail. In order not to
1538 * break such machines we will only mask pins from irqdomain if the machine
1539 * is not listed below.
1541 static const struct dmi_system_id chv_no_valid_mask
[] = {
1542 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1544 .ident
= "Intel_Strago based Chromebooks (All models)",
1546 DMI_MATCH(DMI_SYS_VENDOR
, "GOOGLE"),
1547 DMI_MATCH(DMI_PRODUCT_FAMILY
, "Intel_Strago"),
1551 .ident
= "Acer Chromebook R11 (Cyan)",
1553 DMI_MATCH(DMI_SYS_VENDOR
, "GOOGLE"),
1554 DMI_MATCH(DMI_PRODUCT_NAME
, "Cyan"),
1558 .ident
= "Samsung Chromebook 3 (Celes)",
1560 DMI_MATCH(DMI_SYS_VENDOR
, "GOOGLE"),
1561 DMI_MATCH(DMI_PRODUCT_NAME
, "Celes"),
1567 static int chv_gpio_probe(struct chv_pinctrl
*pctrl
, int irq
)
1569 const struct chv_gpio_pinrange
*range
;
1570 struct gpio_chip
*chip
= &pctrl
->chip
;
1571 bool need_valid_mask
= !dmi_check_system(chv_no_valid_mask
);
1574 *chip
= chv_gpio_chip
;
1576 chip
->ngpio
= pctrl
->community
->ngpios
;
1577 chip
->label
= dev_name(pctrl
->dev
);
1578 chip
->parent
= pctrl
->dev
;
1580 chip
->irq_need_valid_mask
= need_valid_mask
;
1582 ret
= devm_gpiochip_add_data(pctrl
->dev
, chip
, pctrl
);
1584 dev_err(pctrl
->dev
, "Failed to register gpiochip\n");
1588 for (i
= 0, offset
= 0; i
< pctrl
->community
->ngpio_ranges
; i
++) {
1589 range
= &pctrl
->community
->gpio_ranges
[i
];
1590 ret
= gpiochip_add_pin_range(chip
, dev_name(pctrl
->dev
), offset
,
1591 range
->base
, range
->npins
);
1593 dev_err(pctrl
->dev
, "failed to add GPIO pin range\n");
1597 offset
+= range
->npins
;
1600 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1601 for (i
= 0; i
< pctrl
->community
->npins
; i
++) {
1602 const struct pinctrl_pin_desc
*desc
;
1605 desc
= &pctrl
->community
->pins
[i
];
1607 intsel
= readl(chv_padreg(pctrl
, desc
->number
, CHV_PADCTRL0
));
1608 intsel
&= CHV_PADCTRL0_INTSEL_MASK
;
1609 intsel
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1611 if (need_valid_mask
&& intsel
>= pctrl
->community
->nirqs
)
1612 clear_bit(i
, chip
->irq_valid_mask
);
1615 /* Clear all interrupts */
1616 chv_writel(0xffff, pctrl
->regs
+ CHV_INTSTAT
);
1618 ret
= gpiochip_irqchip_add(chip
, &chv_gpio_irqchip
, 0,
1619 handle_bad_irq
, IRQ_TYPE_NONE
);
1621 dev_err(pctrl
->dev
, "failed to add IRQ chip\n");
1625 gpiochip_set_chained_irqchip(chip
, &chv_gpio_irqchip
, irq
,
1626 chv_gpio_irq_handler
);
1630 static acpi_status
chv_pinctrl_mmio_access_handler(u32 function
,
1631 acpi_physical_address address
, u32 bits
, u64
*value
,
1632 void *handler_context
, void *region_context
)
1634 struct chv_pinctrl
*pctrl
= region_context
;
1635 unsigned long flags
;
1636 acpi_status ret
= AE_OK
;
1638 raw_spin_lock_irqsave(&chv_lock
, flags
);
1640 if (function
== ACPI_WRITE
)
1641 chv_writel((u32
)(*value
), pctrl
->regs
+ (u32
)address
);
1642 else if (function
== ACPI_READ
)
1643 *value
= readl(pctrl
->regs
+ (u32
)address
);
1645 ret
= AE_BAD_PARAMETER
;
1647 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1652 static int chv_pinctrl_probe(struct platform_device
*pdev
)
1654 struct chv_pinctrl
*pctrl
;
1655 struct acpi_device
*adev
;
1656 struct resource
*res
;
1660 adev
= ACPI_COMPANION(&pdev
->dev
);
1664 pctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctrl
), GFP_KERNEL
);
1668 for (i
= 0; i
< ARRAY_SIZE(chv_communities
); i
++)
1669 if (!strcmp(adev
->pnp
.unique_id
, chv_communities
[i
]->uid
)) {
1670 pctrl
->community
= chv_communities
[i
];
1673 if (i
== ARRAY_SIZE(chv_communities
))
1676 pctrl
->dev
= &pdev
->dev
;
1678 #ifdef CONFIG_PM_SLEEP
1679 pctrl
->saved_pin_context
= devm_kcalloc(pctrl
->dev
,
1680 pctrl
->community
->npins
, sizeof(*pctrl
->saved_pin_context
),
1682 if (!pctrl
->saved_pin_context
)
1686 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1687 pctrl
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1688 if (IS_ERR(pctrl
->regs
))
1689 return PTR_ERR(pctrl
->regs
);
1691 irq
= platform_get_irq(pdev
, 0);
1693 dev_err(&pdev
->dev
, "failed to get interrupt number\n");
1697 pctrl
->pctldesc
= chv_pinctrl_desc
;
1698 pctrl
->pctldesc
.name
= dev_name(&pdev
->dev
);
1699 pctrl
->pctldesc
.pins
= pctrl
->community
->pins
;
1700 pctrl
->pctldesc
.npins
= pctrl
->community
->npins
;
1702 pctrl
->pctldev
= devm_pinctrl_register(&pdev
->dev
, &pctrl
->pctldesc
,
1704 if (IS_ERR(pctrl
->pctldev
)) {
1705 dev_err(&pdev
->dev
, "failed to register pinctrl driver\n");
1706 return PTR_ERR(pctrl
->pctldev
);
1709 ret
= chv_gpio_probe(pctrl
, irq
);
1713 status
= acpi_install_address_space_handler(adev
->handle
,
1714 pctrl
->community
->acpi_space_id
,
1715 chv_pinctrl_mmio_access_handler
,
1717 if (ACPI_FAILURE(status
))
1718 dev_err(&pdev
->dev
, "failed to install ACPI addr space handler\n");
1720 platform_set_drvdata(pdev
, pctrl
);
1725 static int chv_pinctrl_remove(struct platform_device
*pdev
)
1727 struct chv_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
1729 acpi_remove_address_space_handler(ACPI_COMPANION(&pdev
->dev
),
1730 pctrl
->community
->acpi_space_id
,
1731 chv_pinctrl_mmio_access_handler
);
1736 #ifdef CONFIG_PM_SLEEP
1737 static int chv_pinctrl_suspend_noirq(struct device
*dev
)
1739 struct platform_device
*pdev
= to_platform_device(dev
);
1740 struct chv_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
1741 unsigned long flags
;
1744 raw_spin_lock_irqsave(&chv_lock
, flags
);
1746 pctrl
->saved_intmask
= readl(pctrl
->regs
+ CHV_INTMASK
);
1748 for (i
= 0; i
< pctrl
->community
->npins
; i
++) {
1749 const struct pinctrl_pin_desc
*desc
;
1750 struct chv_pin_context
*ctx
;
1753 desc
= &pctrl
->community
->pins
[i
];
1754 if (chv_pad_locked(pctrl
, desc
->number
))
1757 ctx
= &pctrl
->saved_pin_context
[i
];
1759 reg
= chv_padreg(pctrl
, desc
->number
, CHV_PADCTRL0
);
1760 ctx
->padctrl0
= readl(reg
) & ~CHV_PADCTRL0_GPIORXSTATE
;
1762 reg
= chv_padreg(pctrl
, desc
->number
, CHV_PADCTRL1
);
1763 ctx
->padctrl1
= readl(reg
);
1766 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1771 static int chv_pinctrl_resume_noirq(struct device
*dev
)
1773 struct platform_device
*pdev
= to_platform_device(dev
);
1774 struct chv_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
1775 unsigned long flags
;
1778 raw_spin_lock_irqsave(&chv_lock
, flags
);
1781 * Mask all interrupts before restoring per-pin configuration
1782 * registers because we don't know in which state BIOS left them
1783 * upon exiting suspend.
1785 chv_writel(0, pctrl
->regs
+ CHV_INTMASK
);
1787 for (i
= 0; i
< pctrl
->community
->npins
; i
++) {
1788 const struct pinctrl_pin_desc
*desc
;
1789 const struct chv_pin_context
*ctx
;
1793 desc
= &pctrl
->community
->pins
[i
];
1794 if (chv_pad_locked(pctrl
, desc
->number
))
1797 ctx
= &pctrl
->saved_pin_context
[i
];
1799 /* Only restore if our saved state differs from the current */
1800 reg
= chv_padreg(pctrl
, desc
->number
, CHV_PADCTRL0
);
1801 val
= readl(reg
) & ~CHV_PADCTRL0_GPIORXSTATE
;
1802 if (ctx
->padctrl0
!= val
) {
1803 chv_writel(ctx
->padctrl0
, reg
);
1804 dev_dbg(pctrl
->dev
, "restored pin %2u ctrl0 0x%08x\n",
1805 desc
->number
, readl(reg
));
1808 reg
= chv_padreg(pctrl
, desc
->number
, CHV_PADCTRL1
);
1810 if (ctx
->padctrl1
!= val
) {
1811 chv_writel(ctx
->padctrl1
, reg
);
1812 dev_dbg(pctrl
->dev
, "restored pin %2u ctrl1 0x%08x\n",
1813 desc
->number
, readl(reg
));
1818 * Now that all pins are restored to known state, we can restore
1819 * the interrupt mask register as well.
1821 chv_writel(0xffff, pctrl
->regs
+ CHV_INTSTAT
);
1822 chv_writel(pctrl
->saved_intmask
, pctrl
->regs
+ CHV_INTMASK
);
1824 raw_spin_unlock_irqrestore(&chv_lock
, flags
);
1830 static const struct dev_pm_ops chv_pinctrl_pm_ops
= {
1831 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq
,
1832 chv_pinctrl_resume_noirq
)
1835 static const struct acpi_device_id chv_pinctrl_acpi_match
[] = {
1839 MODULE_DEVICE_TABLE(acpi
, chv_pinctrl_acpi_match
);
1841 static struct platform_driver chv_pinctrl_driver
= {
1842 .probe
= chv_pinctrl_probe
,
1843 .remove
= chv_pinctrl_remove
,
1845 .name
= "cherryview-pinctrl",
1846 .pm
= &chv_pinctrl_pm_ops
,
1847 .acpi_match_table
= chv_pinctrl_acpi_match
,
1851 static int __init
chv_pinctrl_init(void)
1853 return platform_driver_register(&chv_pinctrl_driver
);
1855 subsys_initcall(chv_pinctrl_init
);
1857 static void __exit
chv_pinctrl_exit(void)
1859 platform_driver_unregister(&chv_pinctrl_driver
);
1861 module_exit(chv_pinctrl_exit
);
1863 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1864 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1865 MODULE_LICENSE("GPL v2");