2 * Cherryview/Braswell pinctrl driver
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/acpi.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/platform_device.h>
29 #define CHV_INTSTAT 0x300
30 #define CHV_INTMASK 0x380
32 #define FAMILY_PAD_REGS_OFF 0x4400
33 #define FAMILY_PAD_REGS_SIZE 0x400
34 #define MAX_FAMILY_PAD_GPIO_NO 15
35 #define GPIO_REGS_SIZE 8
37 #define CHV_PADCTRL0 0x000
38 #define CHV_PADCTRL0_INTSEL_SHIFT 28
39 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
40 #define CHV_PADCTRL0_TERM_UP BIT(23)
41 #define CHV_PADCTRL0_TERM_SHIFT 20
42 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
43 #define CHV_PADCTRL0_TERM_20K 1
44 #define CHV_PADCTRL0_TERM_5K 2
45 #define CHV_PADCTRL0_TERM_1K 4
46 #define CHV_PADCTRL0_PMODE_SHIFT 16
47 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
48 #define CHV_PADCTRL0_GPIOEN BIT(15)
49 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
50 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
51 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
52 #define CHV_PADCTRL0_GPIOCFG_GPO 1
53 #define CHV_PADCTRL0_GPIOCFG_GPI 2
54 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
55 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
56 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
58 #define CHV_PADCTRL1 0x004
59 #define CHV_PADCTRL1_CFGLOCK BIT(31)
60 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
61 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
62 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
63 #define CHV_PADCTRL1_ODEN BIT(3)
64 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
65 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
66 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
67 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
68 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
69 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
72 * struct chv_alternate_function - A per group or per pin alternate function
73 * @pin: Pin number (only used in per pin configs)
74 * @mode: Mode the pin should be set in
75 * @invert_oe: Invert OE for this pin
77 struct chv_alternate_function
{
84 * struct chv_pincgroup - describes a CHV pin group
85 * @name: Name of the group
86 * @pins: An array of pins in this group
87 * @npins: Number of pins in this group
88 * @altfunc: Alternate function applied to all pins in this group
89 * @overrides: Alternate function override per pin or %NULL if not used
90 * @noverrides: Number of per pin alternate function overrides if
97 struct chv_alternate_function altfunc
;
98 const struct chv_alternate_function
*overrides
;
103 * struct chv_function - A CHV pinmux function
104 * @name: Name of the function
105 * @groups: An array of groups for this function
106 * @ngroups: Number of groups in @groups
108 struct chv_function
{
110 const char * const *groups
;
115 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
116 * @base: Start pin number
117 * @npins: Number of pins in this range
119 struct chv_gpio_pinrange
{
125 * struct chv_community - A community specific configuration
126 * @uid: ACPI _UID used to match the community
127 * @pins: All pins in this community
128 * @npins: Number of pins
129 * @groups: All groups in this community
130 * @ngroups: Number of groups
131 * @functions: All functions in this community
132 * @nfunctions: Number of functions
133 * @ngpios: Number of GPIOs in this community
134 * @gpio_ranges: An array of GPIO ranges in this community
135 * @ngpio_ranges: Number of GPIO ranges
136 * @ngpios: Total number of GPIOs in this community
138 struct chv_community
{
140 const struct pinctrl_pin_desc
*pins
;
142 const struct chv_pingroup
*groups
;
144 const struct chv_function
*functions
;
146 const struct chv_gpio_pinrange
*gpio_ranges
;
152 * struct chv_pinctrl - CHV pinctrl private structure
153 * @dev: Pointer to the parent device
154 * @pctldesc: Pin controller description
155 * @pctldev: Pointer to the pin controller device
156 * @chip: GPIO chip in this pin controller
157 * @regs: MMIO registers
158 * @lock: Lock to serialize register accesses
159 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
160 * offset (in GPIO number space)
161 * @community: Community this pinctrl instance represents
163 * The first group in @groups is expected to contain all pins that can be
168 struct pinctrl_desc pctldesc
;
169 struct pinctrl_dev
*pctldev
;
170 struct gpio_chip chip
;
173 unsigned intr_lines
[16];
174 const struct chv_community
*community
;
177 #define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip)
179 #define ALTERNATE_FUNCTION(p, m, i) \
186 #define PIN_GROUP(n, p, m, i) \
190 .npins = ARRAY_SIZE((p)), \
191 .altfunc.mode = (m), \
192 .altfunc.invert_oe = (i), \
195 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
199 .npins = ARRAY_SIZE((p)), \
200 .altfunc.mode = (m), \
201 .altfunc.invert_oe = (i), \
203 .noverrides = ARRAY_SIZE((o)), \
206 #define FUNCTION(n, g) \
210 .ngroups = ARRAY_SIZE((g)), \
213 #define GPIO_PINRANGE(start, end) \
216 .npins = (end) - (start) + 1, \
219 static const struct pinctrl_pin_desc southwest_pins
[] = {
220 PINCTRL_PIN(0, "FST_SPI_D2"),
221 PINCTRL_PIN(1, "FST_SPI_D0"),
222 PINCTRL_PIN(2, "FST_SPI_CLK"),
223 PINCTRL_PIN(3, "FST_SPI_D3"),
224 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
225 PINCTRL_PIN(5, "FST_SPI_D1"),
226 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
227 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
229 PINCTRL_PIN(15, "UART1_RTS_B"),
230 PINCTRL_PIN(16, "UART1_RXD"),
231 PINCTRL_PIN(17, "UART2_RXD"),
232 PINCTRL_PIN(18, "UART1_CTS_B"),
233 PINCTRL_PIN(19, "UART2_RTS_B"),
234 PINCTRL_PIN(20, "UART1_TXD"),
235 PINCTRL_PIN(21, "UART2_TXD"),
236 PINCTRL_PIN(22, "UART2_CTS_B"),
238 PINCTRL_PIN(30, "MF_HDA_CLK"),
239 PINCTRL_PIN(31, "MF_HDA_RSTB"),
240 PINCTRL_PIN(32, "MF_HDA_SDIO"),
241 PINCTRL_PIN(33, "MF_HDA_SDO"),
242 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
243 PINCTRL_PIN(35, "MF_HDA_SYNC"),
244 PINCTRL_PIN(36, "MF_HDA_SDI1"),
245 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
247 PINCTRL_PIN(45, "I2C5_SDA"),
248 PINCTRL_PIN(46, "I2C4_SDA"),
249 PINCTRL_PIN(47, "I2C6_SDA"),
250 PINCTRL_PIN(48, "I2C5_SCL"),
251 PINCTRL_PIN(49, "I2C_NFC_SDA"),
252 PINCTRL_PIN(50, "I2C4_SCL"),
253 PINCTRL_PIN(51, "I2C6_SCL"),
254 PINCTRL_PIN(52, "I2C_NFC_SCL"),
256 PINCTRL_PIN(60, "I2C1_SDA"),
257 PINCTRL_PIN(61, "I2C0_SDA"),
258 PINCTRL_PIN(62, "I2C2_SDA"),
259 PINCTRL_PIN(63, "I2C1_SCL"),
260 PINCTRL_PIN(64, "I2C3_SDA"),
261 PINCTRL_PIN(65, "I2C0_SCL"),
262 PINCTRL_PIN(66, "I2C2_SCL"),
263 PINCTRL_PIN(67, "I2C3_SCL"),
265 PINCTRL_PIN(75, "SATA_GP0"),
266 PINCTRL_PIN(76, "SATA_GP1"),
267 PINCTRL_PIN(77, "SATA_LEDN"),
268 PINCTRL_PIN(78, "SATA_GP2"),
269 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
270 PINCTRL_PIN(80, "SATA_GP3"),
271 PINCTRL_PIN(81, "MF_SMB_CLK"),
272 PINCTRL_PIN(82, "MF_SMB_DATA"),
274 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
275 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
276 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
277 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
278 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
279 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
280 PINCTRL_PIN(96, "GP_SSP_2_FS"),
281 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
284 static const unsigned southwest_fspi_pins
[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
285 static const unsigned southwest_uart0_pins
[] = { 16, 20 };
286 static const unsigned southwest_uart1_pins
[] = { 15, 16, 18, 20 };
287 static const unsigned southwest_uart2_pins
[] = { 17, 19, 21, 22 };
288 static const unsigned southwest_i2c0_pins
[] = { 61, 65 };
289 static const unsigned southwest_hda_pins
[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
290 static const unsigned southwest_lpe_pins
[] = {
291 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
293 static const unsigned southwest_i2c1_pins
[] = { 60, 63 };
294 static const unsigned southwest_i2c2_pins
[] = { 62, 66 };
295 static const unsigned southwest_i2c3_pins
[] = { 64, 67 };
296 static const unsigned southwest_i2c4_pins
[] = { 46, 50 };
297 static const unsigned southwest_i2c5_pins
[] = { 45, 48 };
298 static const unsigned southwest_i2c6_pins
[] = { 47, 51 };
299 static const unsigned southwest_i2c_nfc_pins
[] = { 49, 52 };
300 static const unsigned southwest_smbus_pins
[] = { 79, 81, 82 };
301 static const unsigned southwest_spi3_pins
[] = { 76, 79, 80, 81, 82 };
303 /* LPE I2S TXD pins need to have invert_oe set */
304 static const struct chv_alternate_function southwest_lpe_altfuncs
[] = {
305 ALTERNATE_FUNCTION(30, 1, true),
306 ALTERNATE_FUNCTION(34, 1, true),
307 ALTERNATE_FUNCTION(97, 1, true),
311 * Two spi3 chipselects are available in different mode than the main spi3
312 * functionality, which is using mode 1.
314 static const struct chv_alternate_function southwest_spi3_altfuncs
[] = {
315 ALTERNATE_FUNCTION(76, 3, false),
316 ALTERNATE_FUNCTION(80, 3, false),
319 static const struct chv_pingroup southwest_groups
[] = {
320 PIN_GROUP("uart0_grp", southwest_uart0_pins
, 2, false),
321 PIN_GROUP("uart1_grp", southwest_uart1_pins
, 1, false),
322 PIN_GROUP("uart2_grp", southwest_uart2_pins
, 1, false),
323 PIN_GROUP("hda_grp", southwest_hda_pins
, 2, false),
324 PIN_GROUP("i2c0_grp", southwest_i2c0_pins
, 1, true),
325 PIN_GROUP("i2c1_grp", southwest_i2c1_pins
, 1, true),
326 PIN_GROUP("i2c2_grp", southwest_i2c2_pins
, 1, true),
327 PIN_GROUP("i2c3_grp", southwest_i2c3_pins
, 1, true),
328 PIN_GROUP("i2c4_grp", southwest_i2c4_pins
, 1, true),
329 PIN_GROUP("i2c5_grp", southwest_i2c5_pins
, 1, true),
330 PIN_GROUP("i2c6_grp", southwest_i2c6_pins
, 1, true),
331 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins
, 2, true),
333 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins
, 1, false,
334 southwest_lpe_altfuncs
),
335 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins
, 2, false,
336 southwest_spi3_altfuncs
),
339 static const char * const southwest_uart0_groups
[] = { "uart0_grp" };
340 static const char * const southwest_uart1_groups
[] = { "uart1_grp" };
341 static const char * const southwest_uart2_groups
[] = { "uart2_grp" };
342 static const char * const southwest_hda_groups
[] = { "hda_grp" };
343 static const char * const southwest_lpe_groups
[] = { "lpe_grp" };
344 static const char * const southwest_i2c0_groups
[] = { "i2c0_grp" };
345 static const char * const southwest_i2c1_groups
[] = { "i2c1_grp" };
346 static const char * const southwest_i2c2_groups
[] = { "i2c2_grp" };
347 static const char * const southwest_i2c3_groups
[] = { "i2c3_grp" };
348 static const char * const southwest_i2c4_groups
[] = { "i2c4_grp" };
349 static const char * const southwest_i2c5_groups
[] = { "i2c5_grp" };
350 static const char * const southwest_i2c6_groups
[] = { "i2c6_grp" };
351 static const char * const southwest_i2c_nfc_groups
[] = { "i2c_nfc_grp" };
352 static const char * const southwest_spi3_groups
[] = { "spi3_grp" };
355 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
356 * enabled only as GPIOs.
358 static const struct chv_function southwest_functions
[] = {
359 FUNCTION("uart0", southwest_uart0_groups
),
360 FUNCTION("uart1", southwest_uart1_groups
),
361 FUNCTION("uart2", southwest_uart2_groups
),
362 FUNCTION("hda", southwest_hda_groups
),
363 FUNCTION("lpe", southwest_lpe_groups
),
364 FUNCTION("i2c0", southwest_i2c0_groups
),
365 FUNCTION("i2c1", southwest_i2c1_groups
),
366 FUNCTION("i2c2", southwest_i2c2_groups
),
367 FUNCTION("i2c3", southwest_i2c3_groups
),
368 FUNCTION("i2c4", southwest_i2c4_groups
),
369 FUNCTION("i2c5", southwest_i2c5_groups
),
370 FUNCTION("i2c6", southwest_i2c6_groups
),
371 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups
),
372 FUNCTION("spi3", southwest_spi3_groups
),
375 static const struct chv_gpio_pinrange southwest_gpio_ranges
[] = {
377 GPIO_PINRANGE(15, 22),
378 GPIO_PINRANGE(30, 37),
379 GPIO_PINRANGE(45, 52),
380 GPIO_PINRANGE(60, 67),
381 GPIO_PINRANGE(75, 82),
382 GPIO_PINRANGE(90, 97),
385 static const struct chv_community southwest_community
= {
387 .pins
= southwest_pins
,
388 .npins
= ARRAY_SIZE(southwest_pins
),
389 .groups
= southwest_groups
,
390 .ngroups
= ARRAY_SIZE(southwest_groups
),
391 .functions
= southwest_functions
,
392 .nfunctions
= ARRAY_SIZE(southwest_functions
),
393 .gpio_ranges
= southwest_gpio_ranges
,
394 .ngpio_ranges
= ARRAY_SIZE(southwest_gpio_ranges
),
395 .ngpios
= ARRAY_SIZE(southwest_pins
),
398 static const struct pinctrl_pin_desc north_pins
[] = {
399 PINCTRL_PIN(0, "GPIO_DFX_0"),
400 PINCTRL_PIN(1, "GPIO_DFX_3"),
401 PINCTRL_PIN(2, "GPIO_DFX_7"),
402 PINCTRL_PIN(3, "GPIO_DFX_1"),
403 PINCTRL_PIN(4, "GPIO_DFX_5"),
404 PINCTRL_PIN(5, "GPIO_DFX_4"),
405 PINCTRL_PIN(6, "GPIO_DFX_8"),
406 PINCTRL_PIN(7, "GPIO_DFX_2"),
407 PINCTRL_PIN(8, "GPIO_DFX_6"),
409 PINCTRL_PIN(15, "GPIO_SUS0"),
410 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
411 PINCTRL_PIN(17, "GPIO_SUS3"),
412 PINCTRL_PIN(18, "GPIO_SUS7"),
413 PINCTRL_PIN(19, "GPIO_SUS1"),
414 PINCTRL_PIN(20, "GPIO_SUS5"),
415 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
416 PINCTRL_PIN(22, "GPIO_SUS4"),
417 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
418 PINCTRL_PIN(24, "GPIO_SUS2"),
419 PINCTRL_PIN(25, "GPIO_SUS6"),
420 PINCTRL_PIN(26, "CX_PREQ_B"),
421 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
423 PINCTRL_PIN(30, "TRST_B"),
424 PINCTRL_PIN(31, "TCK"),
425 PINCTRL_PIN(32, "PROCHOT_B"),
426 PINCTRL_PIN(33, "SVIDO_DATA"),
427 PINCTRL_PIN(34, "TMS"),
428 PINCTRL_PIN(35, "CX_PRDY_B_2"),
429 PINCTRL_PIN(36, "TDO_2"),
430 PINCTRL_PIN(37, "CX_PRDY_B"),
431 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
432 PINCTRL_PIN(39, "TDO"),
433 PINCTRL_PIN(40, "SVIDO_CLK"),
434 PINCTRL_PIN(41, "TDI"),
436 PINCTRL_PIN(45, "GP_CAMERASB_05"),
437 PINCTRL_PIN(46, "GP_CAMERASB_02"),
438 PINCTRL_PIN(47, "GP_CAMERASB_08"),
439 PINCTRL_PIN(48, "GP_CAMERASB_00"),
440 PINCTRL_PIN(49, "GP_CAMERASB_06"),
441 PINCTRL_PIN(50, "GP_CAMERASB_10"),
442 PINCTRL_PIN(51, "GP_CAMERASB_03"),
443 PINCTRL_PIN(52, "GP_CAMERASB_09"),
444 PINCTRL_PIN(53, "GP_CAMERASB_01"),
445 PINCTRL_PIN(54, "GP_CAMERASB_07"),
446 PINCTRL_PIN(55, "GP_CAMERASB_11"),
447 PINCTRL_PIN(56, "GP_CAMERASB_04"),
449 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
450 PINCTRL_PIN(61, "HV_DDI0_HPD"),
451 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
452 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
453 PINCTRL_PIN(64, "HV_DDI1_HPD"),
454 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
455 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
456 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
457 PINCTRL_PIN(68, "HV_DDI2_HPD"),
458 PINCTRL_PIN(69, "PANEL1_VDDEN"),
459 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
460 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
461 PINCTRL_PIN(72, "PANEL0_VDDEN"),
464 static const struct chv_gpio_pinrange north_gpio_ranges
[] = {
466 GPIO_PINRANGE(15, 27),
467 GPIO_PINRANGE(30, 41),
468 GPIO_PINRANGE(45, 56),
469 GPIO_PINRANGE(60, 72),
472 static const struct chv_community north_community
= {
475 .npins
= ARRAY_SIZE(north_pins
),
476 .gpio_ranges
= north_gpio_ranges
,
477 .ngpio_ranges
= ARRAY_SIZE(north_gpio_ranges
),
478 .ngpios
= ARRAY_SIZE(north_pins
),
481 static const struct pinctrl_pin_desc east_pins
[] = {
482 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
483 PINCTRL_PIN(1, "PMU_BATLOW_B"),
484 PINCTRL_PIN(2, "SUS_STAT_B"),
485 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
486 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
487 PINCTRL_PIN(5, "PMU_PLTRST_B"),
488 PINCTRL_PIN(6, "PMU_SUSCLK"),
489 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
490 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
491 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
492 PINCTRL_PIN(10, "PMU_WAKE_B"),
493 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
495 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
496 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
497 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
498 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
499 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
500 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
501 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
502 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
503 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
504 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
505 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
506 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
509 static const struct chv_gpio_pinrange east_gpio_ranges
[] = {
510 GPIO_PINRANGE(0, 11),
511 GPIO_PINRANGE(15, 26),
514 static const struct chv_community east_community
= {
517 .npins
= ARRAY_SIZE(east_pins
),
518 .gpio_ranges
= east_gpio_ranges
,
519 .ngpio_ranges
= ARRAY_SIZE(east_gpio_ranges
),
520 .ngpios
= ARRAY_SIZE(east_pins
),
523 static const struct pinctrl_pin_desc southeast_pins
[] = {
524 PINCTRL_PIN(0, "MF_PLT_CLK0"),
525 PINCTRL_PIN(1, "PWM1"),
526 PINCTRL_PIN(2, "MF_PLT_CLK1"),
527 PINCTRL_PIN(3, "MF_PLT_CLK4"),
528 PINCTRL_PIN(4, "MF_PLT_CLK3"),
529 PINCTRL_PIN(5, "PWM0"),
530 PINCTRL_PIN(6, "MF_PLT_CLK5"),
531 PINCTRL_PIN(7, "MF_PLT_CLK2"),
533 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
534 PINCTRL_PIN(16, "SDMMC1_CLK"),
535 PINCTRL_PIN(17, "SDMMC1_D0"),
536 PINCTRL_PIN(18, "SDMMC2_D1"),
537 PINCTRL_PIN(19, "SDMMC2_CLK"),
538 PINCTRL_PIN(20, "SDMMC1_D2"),
539 PINCTRL_PIN(21, "SDMMC2_D2"),
540 PINCTRL_PIN(22, "SDMMC2_CMD"),
541 PINCTRL_PIN(23, "SDMMC1_CMD"),
542 PINCTRL_PIN(24, "SDMMC1_D1"),
543 PINCTRL_PIN(25, "SDMMC2_D0"),
544 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
546 PINCTRL_PIN(30, "SDMMC3_D1"),
547 PINCTRL_PIN(31, "SDMMC3_CLK"),
548 PINCTRL_PIN(32, "SDMMC3_D3"),
549 PINCTRL_PIN(33, "SDMMC3_D2"),
550 PINCTRL_PIN(34, "SDMMC3_CMD"),
551 PINCTRL_PIN(35, "SDMMC3_D0"),
553 PINCTRL_PIN(45, "MF_LPC_AD2"),
554 PINCTRL_PIN(46, "LPC_CLKRUNB"),
555 PINCTRL_PIN(47, "MF_LPC_AD0"),
556 PINCTRL_PIN(48, "LPC_FRAMEB"),
557 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
558 PINCTRL_PIN(50, "MF_LPC_AD3"),
559 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
560 PINCTRL_PIN(52, "MF_LPC_AD1"),
562 PINCTRL_PIN(60, "SPI1_MISO"),
563 PINCTRL_PIN(61, "SPI1_CSO_B"),
564 PINCTRL_PIN(62, "SPI1_CLK"),
565 PINCTRL_PIN(63, "MMC1_D6"),
566 PINCTRL_PIN(64, "SPI1_MOSI"),
567 PINCTRL_PIN(65, "MMC1_D5"),
568 PINCTRL_PIN(66, "SPI1_CS1_B"),
569 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
570 PINCTRL_PIN(68, "MMC1_D7"),
571 PINCTRL_PIN(69, "MMC1_RCLK"),
573 PINCTRL_PIN(75, "USB_OC1_B"),
574 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
575 PINCTRL_PIN(77, "GPIO_ALERT"),
576 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
577 PINCTRL_PIN(79, "ILB_SERIRQ"),
578 PINCTRL_PIN(80, "USB_OC0_B"),
579 PINCTRL_PIN(81, "SDMMC3_CD_B"),
580 PINCTRL_PIN(82, "SPKR"),
581 PINCTRL_PIN(83, "SUSPWRDNACK"),
582 PINCTRL_PIN(84, "SPARE_PIN"),
583 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
586 static const unsigned southeast_pwm0_pins
[] = { 5 };
587 static const unsigned southeast_pwm1_pins
[] = { 1 };
588 static const unsigned southeast_sdmmc1_pins
[] = {
589 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
591 static const unsigned southeast_sdmmc2_pins
[] = { 15, 18, 19, 21, 22, 25 };
592 static const unsigned southeast_sdmmc3_pins
[] = {
593 30, 31, 32, 33, 34, 35, 78, 81, 85,
595 static const unsigned southeast_spi1_pins
[] = { 60, 61, 62, 64, 66 };
596 static const unsigned southeast_spi2_pins
[] = { 2, 3, 4, 6, 7 };
598 static const struct chv_pingroup southeast_groups
[] = {
599 PIN_GROUP("pwm0_grp", southeast_pwm0_pins
, 1, false),
600 PIN_GROUP("pwm1_grp", southeast_pwm1_pins
, 1, false),
601 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins
, 1, false),
602 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins
, 1, false),
603 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins
, 1, false),
604 PIN_GROUP("spi1_grp", southeast_spi1_pins
, 1, false),
605 PIN_GROUP("spi2_grp", southeast_spi2_pins
, 4, false),
608 static const char * const southeast_pwm0_groups
[] = { "pwm0_grp" };
609 static const char * const southeast_pwm1_groups
[] = { "pwm1_grp" };
610 static const char * const southeast_sdmmc1_groups
[] = { "sdmmc1_grp" };
611 static const char * const southeast_sdmmc2_groups
[] = { "sdmmc2_grp" };
612 static const char * const southeast_sdmmc3_groups
[] = { "sdmmc3_grp" };
613 static const char * const southeast_spi1_groups
[] = { "spi1_grp" };
614 static const char * const southeast_spi2_groups
[] = { "spi2_grp" };
616 static const struct chv_function southeast_functions
[] = {
617 FUNCTION("pwm0", southeast_pwm0_groups
),
618 FUNCTION("pwm1", southeast_pwm1_groups
),
619 FUNCTION("sdmmc1", southeast_sdmmc1_groups
),
620 FUNCTION("sdmmc2", southeast_sdmmc2_groups
),
621 FUNCTION("sdmmc3", southeast_sdmmc3_groups
),
622 FUNCTION("spi1", southeast_spi1_groups
),
623 FUNCTION("spi2", southeast_spi2_groups
),
626 static const struct chv_gpio_pinrange southeast_gpio_ranges
[] = {
628 GPIO_PINRANGE(15, 26),
629 GPIO_PINRANGE(30, 35),
630 GPIO_PINRANGE(45, 52),
631 GPIO_PINRANGE(60, 69),
632 GPIO_PINRANGE(75, 85),
635 static const struct chv_community southeast_community
= {
637 .pins
= southeast_pins
,
638 .npins
= ARRAY_SIZE(southeast_pins
),
639 .groups
= southeast_groups
,
640 .ngroups
= ARRAY_SIZE(southeast_groups
),
641 .functions
= southeast_functions
,
642 .nfunctions
= ARRAY_SIZE(southeast_functions
),
643 .gpio_ranges
= southeast_gpio_ranges
,
644 .ngpio_ranges
= ARRAY_SIZE(southeast_gpio_ranges
),
645 .ngpios
= ARRAY_SIZE(southeast_pins
),
648 static const struct chv_community
*chv_communities
[] = {
649 &southwest_community
,
652 &southeast_community
,
655 static void __iomem
*chv_padreg(struct chv_pinctrl
*pctrl
, unsigned offset
,
658 unsigned family_no
= offset
/ MAX_FAMILY_PAD_GPIO_NO
;
659 unsigned pad_no
= offset
% MAX_FAMILY_PAD_GPIO_NO
;
661 offset
= FAMILY_PAD_REGS_OFF
+ FAMILY_PAD_REGS_SIZE
* family_no
+
662 GPIO_REGS_SIZE
* pad_no
;
664 return pctrl
->regs
+ offset
+ reg
;
667 static void chv_writel(u32 value
, void __iomem
*reg
)
670 /* simple readback to confirm the bus transferring done */
674 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
675 static bool chv_pad_locked(struct chv_pinctrl
*pctrl
, unsigned offset
)
679 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL1
);
680 return readl(reg
) & CHV_PADCTRL1_CFGLOCK
;
683 static int chv_get_groups_count(struct pinctrl_dev
*pctldev
)
685 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
687 return pctrl
->community
->ngroups
;
690 static const char *chv_get_group_name(struct pinctrl_dev
*pctldev
,
693 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
695 return pctrl
->community
->groups
[group
].name
;
698 static int chv_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned group
,
699 const unsigned **pins
, unsigned *npins
)
701 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
703 *pins
= pctrl
->community
->groups
[group
].pins
;
704 *npins
= pctrl
->community
->groups
[group
].npins
;
708 static void chv_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
711 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
716 spin_lock_irqsave(&pctrl
->lock
, flags
);
718 ctrl0
= readl(chv_padreg(pctrl
, offset
, CHV_PADCTRL0
));
719 ctrl1
= readl(chv_padreg(pctrl
, offset
, CHV_PADCTRL1
));
720 locked
= chv_pad_locked(pctrl
, offset
);
722 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
724 if (ctrl0
& CHV_PADCTRL0_GPIOEN
) {
725 seq_puts(s
, "GPIO ");
729 mode
= ctrl0
& CHV_PADCTRL0_PMODE_MASK
;
730 mode
>>= CHV_PADCTRL0_PMODE_SHIFT
;
732 seq_printf(s
, "mode %d ", mode
);
735 seq_printf(s
, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0
, ctrl1
);
738 seq_puts(s
, " [LOCKED]");
741 static const struct pinctrl_ops chv_pinctrl_ops
= {
742 .get_groups_count
= chv_get_groups_count
,
743 .get_group_name
= chv_get_group_name
,
744 .get_group_pins
= chv_get_group_pins
,
745 .pin_dbg_show
= chv_pin_dbg_show
,
748 static int chv_get_functions_count(struct pinctrl_dev
*pctldev
)
750 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
752 return pctrl
->community
->nfunctions
;
755 static const char *chv_get_function_name(struct pinctrl_dev
*pctldev
,
758 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
760 return pctrl
->community
->functions
[function
].name
;
763 static int chv_get_function_groups(struct pinctrl_dev
*pctldev
,
765 const char * const **groups
,
766 unsigned * const ngroups
)
768 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
770 *groups
= pctrl
->community
->functions
[function
].groups
;
771 *ngroups
= pctrl
->community
->functions
[function
].ngroups
;
775 static int chv_pinmux_set_mux(struct pinctrl_dev
*pctldev
, unsigned function
,
778 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
779 const struct chv_pingroup
*grp
;
783 grp
= &pctrl
->community
->groups
[group
];
785 spin_lock_irqsave(&pctrl
->lock
, flags
);
787 /* Check first that the pad is not locked */
788 for (i
= 0; i
< grp
->npins
; i
++) {
789 if (chv_pad_locked(pctrl
, grp
->pins
[i
])) {
790 dev_warn(pctrl
->dev
, "unable to set mode for locked pin %u\n",
792 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
797 for (i
= 0; i
< grp
->npins
; i
++) {
798 const struct chv_alternate_function
*altfunc
= &grp
->altfunc
;
799 int pin
= grp
->pins
[i
];
803 /* Check if there is pin-specific config */
804 if (grp
->overrides
) {
807 for (j
= 0; j
< grp
->noverrides
; j
++) {
808 if (grp
->overrides
[j
].pin
== pin
) {
809 altfunc
= &grp
->overrides
[j
];
815 reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL0
);
817 /* Disable GPIO mode */
818 value
&= ~CHV_PADCTRL0_GPIOEN
;
819 /* Set to desired mode */
820 value
&= ~CHV_PADCTRL0_PMODE_MASK
;
821 value
|= altfunc
->mode
<< CHV_PADCTRL0_PMODE_SHIFT
;
822 chv_writel(value
, reg
);
824 /* Update for invert_oe */
825 reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL1
);
826 value
= readl(reg
) & ~CHV_PADCTRL1_INVRXTX_MASK
;
827 if (altfunc
->invert_oe
)
828 value
|= CHV_PADCTRL1_INVRXTX_TXENABLE
;
829 chv_writel(value
, reg
);
831 dev_dbg(pctrl
->dev
, "configured pin %u mode %u OE %sinverted\n",
832 pin
, altfunc
->mode
, altfunc
->invert_oe
? "" : "not ");
835 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
840 static int chv_gpio_request_enable(struct pinctrl_dev
*pctldev
,
841 struct pinctrl_gpio_range
*range
,
844 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
849 spin_lock_irqsave(&pctrl
->lock
, flags
);
851 if (chv_pad_locked(pctrl
, offset
)) {
852 value
= readl(chv_padreg(pctrl
, offset
, CHV_PADCTRL0
));
853 if (!(value
& CHV_PADCTRL0_GPIOEN
)) {
854 /* Locked so cannot enable */
855 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
861 /* Reset the interrupt mapping */
862 for (i
= 0; i
< ARRAY_SIZE(pctrl
->intr_lines
); i
++) {
863 if (pctrl
->intr_lines
[i
] == offset
) {
864 pctrl
->intr_lines
[i
] = 0;
869 /* Disable interrupt generation */
870 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL1
);
872 value
&= ~CHV_PADCTRL1_INTWAKECFG_MASK
;
873 value
&= ~CHV_PADCTRL1_INVRXTX_MASK
;
874 chv_writel(value
, reg
);
876 /* Switch to a GPIO mode */
877 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL0
);
878 value
= readl(reg
) | CHV_PADCTRL0_GPIOEN
;
879 chv_writel(value
, reg
);
882 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
887 static void chv_gpio_disable_free(struct pinctrl_dev
*pctldev
,
888 struct pinctrl_gpio_range
*range
,
891 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
896 spin_lock_irqsave(&pctrl
->lock
, flags
);
898 reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL0
);
899 value
= readl(reg
) & ~CHV_PADCTRL0_GPIOEN
;
900 chv_writel(value
, reg
);
902 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
905 static int chv_gpio_set_direction(struct pinctrl_dev
*pctldev
,
906 struct pinctrl_gpio_range
*range
,
907 unsigned offset
, bool input
)
909 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
910 void __iomem
*reg
= chv_padreg(pctrl
, offset
, CHV_PADCTRL0
);
914 spin_lock_irqsave(&pctrl
->lock
, flags
);
916 ctrl0
= readl(reg
) & ~CHV_PADCTRL0_GPIOCFG_MASK
;
918 ctrl0
|= CHV_PADCTRL0_GPIOCFG_GPI
<< CHV_PADCTRL0_GPIOCFG_SHIFT
;
920 ctrl0
|= CHV_PADCTRL0_GPIOCFG_GPO
<< CHV_PADCTRL0_GPIOCFG_SHIFT
;
921 chv_writel(ctrl0
, reg
);
923 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
928 static const struct pinmux_ops chv_pinmux_ops
= {
929 .get_functions_count
= chv_get_functions_count
,
930 .get_function_name
= chv_get_function_name
,
931 .get_function_groups
= chv_get_function_groups
,
932 .set_mux
= chv_pinmux_set_mux
,
933 .gpio_request_enable
= chv_gpio_request_enable
,
934 .gpio_disable_free
= chv_gpio_disable_free
,
935 .gpio_set_direction
= chv_gpio_set_direction
,
938 static int chv_config_get(struct pinctrl_dev
*pctldev
, unsigned pin
,
939 unsigned long *config
)
941 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
942 enum pin_config_param param
= pinconf_to_config_param(*config
);
948 spin_lock_irqsave(&pctrl
->lock
, flags
);
949 ctrl0
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
950 ctrl1
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL1
));
951 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
953 term
= (ctrl0
& CHV_PADCTRL0_TERM_MASK
) >> CHV_PADCTRL0_TERM_SHIFT
;
956 case PIN_CONFIG_BIAS_DISABLE
:
961 case PIN_CONFIG_BIAS_PULL_UP
:
962 if (!(ctrl0
& CHV_PADCTRL0_TERM_UP
))
966 case CHV_PADCTRL0_TERM_20K
:
969 case CHV_PADCTRL0_TERM_5K
:
972 case CHV_PADCTRL0_TERM_1K
:
979 case PIN_CONFIG_BIAS_PULL_DOWN
:
980 if (!term
|| (ctrl0
& CHV_PADCTRL0_TERM_UP
))
984 case CHV_PADCTRL0_TERM_20K
:
987 case CHV_PADCTRL0_TERM_5K
:
994 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
995 if (!(ctrl1
& CHV_PADCTRL1_ODEN
))
999 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE
: {
1002 cfg
= ctrl0
& CHV_PADCTRL0_GPIOCFG_MASK
;
1003 cfg
>>= CHV_PADCTRL0_GPIOCFG_SHIFT
;
1004 if (cfg
!= CHV_PADCTRL0_GPIOCFG_HIZ
)
1014 *config
= pinconf_to_config_packed(param
, arg
);
1018 static int chv_config_set_pull(struct chv_pinctrl
*pctrl
, unsigned pin
,
1019 enum pin_config_param param
, u16 arg
)
1021 void __iomem
*reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL0
);
1022 unsigned long flags
;
1025 spin_lock_irqsave(&pctrl
->lock
, flags
);
1029 case PIN_CONFIG_BIAS_DISABLE
:
1030 ctrl0
&= ~(CHV_PADCTRL0_TERM_MASK
| CHV_PADCTRL0_TERM_UP
);
1033 case PIN_CONFIG_BIAS_PULL_UP
:
1034 ctrl0
&= ~(CHV_PADCTRL0_TERM_MASK
| CHV_PADCTRL0_TERM_UP
);
1038 /* For 1k there is only pull up */
1039 pull
= CHV_PADCTRL0_TERM_1K
<< CHV_PADCTRL0_TERM_SHIFT
;
1042 pull
= CHV_PADCTRL0_TERM_5K
<< CHV_PADCTRL0_TERM_SHIFT
;
1045 pull
= CHV_PADCTRL0_TERM_20K
<< CHV_PADCTRL0_TERM_SHIFT
;
1048 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1052 ctrl0
|= CHV_PADCTRL0_TERM_UP
| pull
;
1055 case PIN_CONFIG_BIAS_PULL_DOWN
:
1056 ctrl0
&= ~(CHV_PADCTRL0_TERM_MASK
| CHV_PADCTRL0_TERM_UP
);
1060 pull
= CHV_PADCTRL0_TERM_5K
<< CHV_PADCTRL0_TERM_SHIFT
;
1063 pull
= CHV_PADCTRL0_TERM_20K
<< CHV_PADCTRL0_TERM_SHIFT
;
1066 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1074 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1078 chv_writel(ctrl0
, reg
);
1079 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1084 static int chv_config_set(struct pinctrl_dev
*pctldev
, unsigned pin
,
1085 unsigned long *configs
, unsigned nconfigs
)
1087 struct chv_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
1088 enum pin_config_param param
;
1092 if (chv_pad_locked(pctrl
, pin
))
1095 for (i
= 0; i
< nconfigs
; i
++) {
1096 param
= pinconf_to_config_param(configs
[i
]);
1097 arg
= pinconf_to_config_argument(configs
[i
]);
1100 case PIN_CONFIG_BIAS_DISABLE
:
1101 case PIN_CONFIG_BIAS_PULL_UP
:
1102 case PIN_CONFIG_BIAS_PULL_DOWN
:
1103 ret
= chv_config_set_pull(pctrl
, pin
, param
, arg
);
1112 dev_dbg(pctrl
->dev
, "pin %d set config %d arg %u\n", pin
,
1119 static const struct pinconf_ops chv_pinconf_ops
= {
1121 .pin_config_set
= chv_config_set
,
1122 .pin_config_get
= chv_config_get
,
1125 static struct pinctrl_desc chv_pinctrl_desc
= {
1126 .pctlops
= &chv_pinctrl_ops
,
1127 .pmxops
= &chv_pinmux_ops
,
1128 .confops
= &chv_pinconf_ops
,
1129 .owner
= THIS_MODULE
,
1132 static int chv_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1134 return pinctrl_request_gpio(chip
->base
+ offset
);
1137 static void chv_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
1139 pinctrl_free_gpio(chip
->base
+ offset
);
1142 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl
*pctrl
,
1145 return pctrl
->community
->pins
[offset
].number
;
1148 static int chv_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1150 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(chip
);
1151 int pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1154 ctrl0
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1156 cfg
= ctrl0
& CHV_PADCTRL0_GPIOCFG_MASK
;
1157 cfg
>>= CHV_PADCTRL0_GPIOCFG_SHIFT
;
1159 if (cfg
== CHV_PADCTRL0_GPIOCFG_GPO
)
1160 return !!(ctrl0
& CHV_PADCTRL0_GPIOTXSTATE
);
1161 return !!(ctrl0
& CHV_PADCTRL0_GPIORXSTATE
);
1164 static void chv_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1166 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(chip
);
1167 unsigned pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1168 unsigned long flags
;
1172 spin_lock_irqsave(&pctrl
->lock
, flags
);
1174 reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL0
);
1178 ctrl0
|= CHV_PADCTRL0_GPIOTXSTATE
;
1180 ctrl0
&= ~CHV_PADCTRL0_GPIOTXSTATE
;
1182 chv_writel(ctrl0
, reg
);
1184 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1187 static int chv_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
1189 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(chip
);
1190 unsigned pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1191 u32 ctrl0
, direction
;
1193 ctrl0
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1195 direction
= ctrl0
& CHV_PADCTRL0_GPIOCFG_MASK
;
1196 direction
>>= CHV_PADCTRL0_GPIOCFG_SHIFT
;
1198 return direction
!= CHV_PADCTRL0_GPIOCFG_GPO
;
1201 static int chv_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
1203 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
1206 static int chv_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
,
1209 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
1212 static const struct gpio_chip chv_gpio_chip
= {
1213 .owner
= THIS_MODULE
,
1214 .request
= chv_gpio_request
,
1215 .free
= chv_gpio_free
,
1216 .get_direction
= chv_gpio_get_direction
,
1217 .direction_input
= chv_gpio_direction_input
,
1218 .direction_output
= chv_gpio_direction_output
,
1219 .get
= chv_gpio_get
,
1220 .set
= chv_gpio_set
,
1223 static void chv_gpio_irq_ack(struct irq_data
*d
)
1225 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1226 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(gc
);
1227 int pin
= chv_gpio_offset_to_pin(pctrl
, irqd_to_hwirq(d
));
1230 spin_lock(&pctrl
->lock
);
1232 intr_line
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1233 intr_line
&= CHV_PADCTRL0_INTSEL_MASK
;
1234 intr_line
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1235 chv_writel(BIT(intr_line
), pctrl
->regs
+ CHV_INTSTAT
);
1237 spin_unlock(&pctrl
->lock
);
1240 static void chv_gpio_irq_mask_unmask(struct irq_data
*d
, bool mask
)
1242 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1243 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(gc
);
1244 int pin
= chv_gpio_offset_to_pin(pctrl
, irqd_to_hwirq(d
));
1245 u32 value
, intr_line
;
1246 unsigned long flags
;
1248 spin_lock_irqsave(&pctrl
->lock
, flags
);
1250 intr_line
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1251 intr_line
&= CHV_PADCTRL0_INTSEL_MASK
;
1252 intr_line
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1254 value
= readl(pctrl
->regs
+ CHV_INTMASK
);
1256 value
&= ~BIT(intr_line
);
1258 value
|= BIT(intr_line
);
1259 chv_writel(value
, pctrl
->regs
+ CHV_INTMASK
);
1261 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1264 static void chv_gpio_irq_mask(struct irq_data
*d
)
1266 chv_gpio_irq_mask_unmask(d
, true);
1269 static void chv_gpio_irq_unmask(struct irq_data
*d
)
1271 chv_gpio_irq_mask_unmask(d
, false);
1274 static int chv_gpio_irq_type(struct irq_data
*d
, unsigned type
)
1276 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
1277 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(gc
);
1278 unsigned offset
= irqd_to_hwirq(d
);
1279 int pin
= chv_gpio_offset_to_pin(pctrl
, offset
);
1280 unsigned long flags
;
1283 spin_lock_irqsave(&pctrl
->lock
, flags
);
1286 * Pins which can be used as shared interrupt are configured in
1287 * BIOS. Driver trusts BIOS configurations and assigns different
1288 * handler according to the irq type.
1290 * Driver needs to save the mapping between each pin and
1291 * its interrupt line.
1292 * 1. If the pin cfg is locked in BIOS:
1293 * Trust BIOS has programmed IntWakeCfg bits correctly,
1294 * driver just needs to save the mapping.
1295 * 2. If the pin cfg is not locked in BIOS:
1296 * Driver programs the IntWakeCfg bits and save the mapping.
1298 if (!chv_pad_locked(pctrl
, pin
)) {
1299 void __iomem
*reg
= chv_padreg(pctrl
, pin
, CHV_PADCTRL1
);
1302 value
&= ~CHV_PADCTRL1_INTWAKECFG_MASK
;
1303 value
&= ~CHV_PADCTRL1_INVRXTX_MASK
;
1305 if (type
& IRQ_TYPE_EDGE_BOTH
) {
1306 if ((type
& IRQ_TYPE_EDGE_BOTH
) == IRQ_TYPE_EDGE_BOTH
)
1307 value
|= CHV_PADCTRL1_INTWAKECFG_BOTH
;
1308 else if (type
& IRQ_TYPE_EDGE_RISING
)
1309 value
|= CHV_PADCTRL1_INTWAKECFG_RISING
;
1310 else if (type
& IRQ_TYPE_EDGE_FALLING
)
1311 value
|= CHV_PADCTRL1_INTWAKECFG_FALLING
;
1312 } else if (type
& IRQ_TYPE_LEVEL_MASK
) {
1313 value
|= CHV_PADCTRL1_INTWAKECFG_LEVEL
;
1314 if (type
& IRQ_TYPE_LEVEL_LOW
)
1315 value
|= CHV_PADCTRL1_INVRXTX_RXDATA
;
1318 chv_writel(value
, reg
);
1321 value
= readl(chv_padreg(pctrl
, pin
, CHV_PADCTRL0
));
1322 value
&= CHV_PADCTRL0_INTSEL_MASK
;
1323 value
>>= CHV_PADCTRL0_INTSEL_SHIFT
;
1325 pctrl
->intr_lines
[value
] = offset
;
1327 if (type
& IRQ_TYPE_EDGE_BOTH
)
1328 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
1329 else if (type
& IRQ_TYPE_LEVEL_MASK
)
1330 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
1332 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
1337 static struct irq_chip chv_gpio_irqchip
= {
1339 .irq_ack
= chv_gpio_irq_ack
,
1340 .irq_mask
= chv_gpio_irq_mask
,
1341 .irq_unmask
= chv_gpio_irq_unmask
,
1342 .irq_set_type
= chv_gpio_irq_type
,
1343 .flags
= IRQCHIP_SKIP_SET_WAKE
,
1346 static void chv_gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
1348 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
1349 struct chv_pinctrl
*pctrl
= gpiochip_to_pinctrl(gc
);
1350 struct irq_chip
*chip
= irq_get_chip(irq
);
1351 unsigned long pending
;
1354 chained_irq_enter(chip
, desc
);
1356 pending
= readl(pctrl
->regs
+ CHV_INTSTAT
);
1357 for_each_set_bit(intr_line
, &pending
, 16) {
1358 unsigned irq
, offset
;
1360 offset
= pctrl
->intr_lines
[intr_line
];
1361 irq
= irq_find_mapping(gc
->irqdomain
, offset
);
1362 generic_handle_irq(irq
);
1365 chained_irq_exit(chip
, desc
);
1368 static int chv_gpio_probe(struct chv_pinctrl
*pctrl
, int irq
)
1370 const struct chv_gpio_pinrange
*range
;
1371 struct gpio_chip
*chip
= &pctrl
->chip
;
1374 *chip
= chv_gpio_chip
;
1376 chip
->ngpio
= pctrl
->community
->ngpios
;
1377 chip
->label
= dev_name(pctrl
->dev
);
1378 chip
->dev
= pctrl
->dev
;
1381 ret
= gpiochip_add(chip
);
1383 dev_err(pctrl
->dev
, "Failed to register gpiochip\n");
1387 for (i
= 0, offset
= 0; i
< pctrl
->community
->ngpio_ranges
; i
++) {
1388 range
= &pctrl
->community
->gpio_ranges
[i
];
1389 ret
= gpiochip_add_pin_range(chip
, dev_name(pctrl
->dev
), offset
,
1390 range
->base
, range
->npins
);
1392 dev_err(pctrl
->dev
, "failed to add GPIO pin range\n");
1396 offset
+= range
->npins
;
1399 /* Mask and clear all interrupts */
1400 chv_writel(0, pctrl
->regs
+ CHV_INTMASK
);
1401 chv_writel(0xffff, pctrl
->regs
+ CHV_INTSTAT
);
1403 ret
= gpiochip_irqchip_add(chip
, &chv_gpio_irqchip
, 0,
1404 handle_simple_irq
, IRQ_TYPE_NONE
);
1406 dev_err(pctrl
->dev
, "failed to add IRQ chip\n");
1410 gpiochip_set_chained_irqchip(chip
, &chv_gpio_irqchip
, irq
,
1411 chv_gpio_irq_handler
);
1415 gpiochip_remove(chip
);
1420 static int chv_pinctrl_probe(struct platform_device
*pdev
)
1422 struct chv_pinctrl
*pctrl
;
1423 struct acpi_device
*adev
;
1424 struct resource
*res
;
1427 adev
= ACPI_COMPANION(&pdev
->dev
);
1431 pctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctrl
), GFP_KERNEL
);
1435 for (i
= 0; i
< ARRAY_SIZE(chv_communities
); i
++)
1436 if (!strcmp(adev
->pnp
.unique_id
, chv_communities
[i
]->uid
)) {
1437 pctrl
->community
= chv_communities
[i
];
1440 if (i
== ARRAY_SIZE(chv_communities
))
1443 spin_lock_init(&pctrl
->lock
);
1444 pctrl
->dev
= &pdev
->dev
;
1446 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1447 pctrl
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1448 if (IS_ERR(pctrl
->regs
))
1449 return PTR_ERR(pctrl
->regs
);
1451 irq
= platform_get_irq(pdev
, 0);
1453 dev_err(&pdev
->dev
, "failed to get interrupt number\n");
1457 pctrl
->pctldesc
= chv_pinctrl_desc
;
1458 pctrl
->pctldesc
.name
= dev_name(&pdev
->dev
);
1459 pctrl
->pctldesc
.pins
= pctrl
->community
->pins
;
1460 pctrl
->pctldesc
.npins
= pctrl
->community
->npins
;
1462 pctrl
->pctldev
= pinctrl_register(&pctrl
->pctldesc
, &pdev
->dev
, pctrl
);
1463 if (!pctrl
->pctldev
) {
1464 dev_err(&pdev
->dev
, "failed to register pinctrl driver\n");
1468 ret
= chv_gpio_probe(pctrl
, irq
);
1470 pinctrl_unregister(pctrl
->pctldev
);
1474 platform_set_drvdata(pdev
, pctrl
);
1479 static int chv_pinctrl_remove(struct platform_device
*pdev
)
1481 struct chv_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
1483 gpiochip_remove(&pctrl
->chip
);
1484 pinctrl_unregister(pctrl
->pctldev
);
1489 static const struct acpi_device_id chv_pinctrl_acpi_match
[] = {
1493 MODULE_DEVICE_TABLE(acpi
, chv_pinctrl_acpi_match
);
1495 static struct platform_driver chv_pinctrl_driver
= {
1496 .probe
= chv_pinctrl_probe
,
1497 .remove
= chv_pinctrl_remove
,
1499 .name
= "cherryview-pinctrl",
1500 .owner
= THIS_MODULE
,
1501 .acpi_match_table
= chv_pinctrl_acpi_match
,
1505 static int __init
chv_pinctrl_init(void)
1507 return platform_driver_register(&chv_pinctrl_driver
);
1509 subsys_initcall(chv_pinctrl_init
);
1511 static void __exit
chv_pinctrl_exit(void)
1513 platform_driver_unregister(&chv_pinctrl_driver
);
1515 module_exit(chv_pinctrl_exit
);
1517 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1518 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1519 MODULE_LICENSE("GPL v2");