2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/gpio/driver.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/bitops.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
37 #include <dt-bindings/pinctrl/mt65xx.h>
40 #include "../pinconf.h"
41 #include "../pinctrl-utils.h"
42 #include "pinctrl-mtk-common.h"
44 #define MAX_GPIO_MODE_PER_REG 5
45 #define GPIO_MODE_BITS 3
47 static const char * const mtk_gpio_functions
[] = {
48 "func0", "func1", "func2", "func3",
49 "func4", "func5", "func6", "func7",
53 * There are two base address for pull related configuration
54 * in mt8135, and different GPIO pins use different base address.
55 * When pin number greater than type1_start and less than type1_end,
56 * should use the second base address.
58 static struct regmap
*mtk_get_regmap(struct mtk_pinctrl
*pctl
,
61 if (pin
>= pctl
->devdata
->type1_start
&& pin
< pctl
->devdata
->type1_end
)
66 static unsigned int mtk_get_port(struct mtk_pinctrl
*pctl
, unsigned long pin
)
68 /* Different SoC has different mask and port shift. */
69 return ((pin
>> 4) & pctl
->devdata
->port_mask
)
70 << pctl
->devdata
->port_shf
;
73 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
74 struct pinctrl_gpio_range
*range
, unsigned offset
,
77 unsigned int reg_addr
;
79 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
81 reg_addr
= mtk_get_port(pctl
, offset
) + pctl
->devdata
->dir_offset
;
82 bit
= BIT(offset
& 0xf);
85 /* Different SoC has different alignment offset. */
86 reg_addr
= CLR_ADDR(reg_addr
, pctl
);
88 reg_addr
= SET_ADDR(reg_addr
, pctl
);
90 regmap_write(mtk_get_regmap(pctl
, offset
), reg_addr
, bit
);
94 static void mtk_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
96 unsigned int reg_addr
;
98 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
100 reg_addr
= mtk_get_port(pctl
, offset
) + pctl
->devdata
->dout_offset
;
101 bit
= BIT(offset
& 0xf);
104 reg_addr
= SET_ADDR(reg_addr
, pctl
);
106 reg_addr
= CLR_ADDR(reg_addr
, pctl
);
108 regmap_write(mtk_get_regmap(pctl
, offset
), reg_addr
, bit
);
111 static int mtk_pconf_set_ies_smt(struct mtk_pinctrl
*pctl
, unsigned pin
,
112 int value
, enum pin_config_param arg
)
114 unsigned int reg_addr
, offset
;
118 * Due to some soc are not support ies/smt config, add this special
119 * control to handle it.
121 if (!pctl
->devdata
->spec_ies_smt_set
&&
122 pctl
->devdata
->ies_offset
== MTK_PINCTRL_NOT_SUPPORT
&&
123 arg
== PIN_CONFIG_INPUT_ENABLE
)
126 if (!pctl
->devdata
->spec_ies_smt_set
&&
127 pctl
->devdata
->smt_offset
== MTK_PINCTRL_NOT_SUPPORT
&&
128 arg
== PIN_CONFIG_INPUT_SCHMITT_ENABLE
)
132 * Due to some pins are irregular, their input enable and smt
133 * control register are discontinuous, so we need this special handle.
135 if (pctl
->devdata
->spec_ies_smt_set
) {
136 return pctl
->devdata
->spec_ies_smt_set(mtk_get_regmap(pctl
, pin
),
137 pin
, pctl
->devdata
->port_align
, value
, arg
);
140 bit
= BIT(pin
& 0xf);
142 if (arg
== PIN_CONFIG_INPUT_ENABLE
)
143 offset
= pctl
->devdata
->ies_offset
;
145 offset
= pctl
->devdata
->smt_offset
;
148 reg_addr
= SET_ADDR(mtk_get_port(pctl
, pin
) + offset
, pctl
);
150 reg_addr
= CLR_ADDR(mtk_get_port(pctl
, pin
) + offset
, pctl
);
152 regmap_write(mtk_get_regmap(pctl
, pin
), reg_addr
, bit
);
156 int mtk_pconf_spec_set_ies_smt_range(struct regmap
*regmap
,
157 const struct mtk_pin_ies_smt_set
*ies_smt_infos
, unsigned int info_num
,
158 unsigned int pin
, unsigned char align
, int value
)
160 unsigned int i
, reg_addr
, bit
;
162 for (i
= 0; i
< info_num
; i
++) {
163 if (pin
>= ies_smt_infos
[i
].start
&&
164 pin
<= ies_smt_infos
[i
].end
) {
173 reg_addr
= ies_smt_infos
[i
].offset
+ align
;
175 reg_addr
= ies_smt_infos
[i
].offset
+ (align
<< 1);
177 bit
= BIT(ies_smt_infos
[i
].bit
);
178 regmap_write(regmap
, reg_addr
, bit
);
182 static const struct mtk_pin_drv_grp
*mtk_find_pin_drv_grp_by_pin(
183 struct mtk_pinctrl
*pctl
, unsigned long pin
) {
186 for (i
= 0; i
< pctl
->devdata
->n_pin_drv_grps
; i
++) {
187 const struct mtk_pin_drv_grp
*pin_drv
=
188 pctl
->devdata
->pin_drv_grp
+ i
;
189 if (pin
== pin_drv
->pin
)
196 static int mtk_pconf_set_driving(struct mtk_pinctrl
*pctl
,
197 unsigned int pin
, unsigned char driving
)
199 const struct mtk_pin_drv_grp
*pin_drv
;
201 unsigned int bits
, mask
, shift
;
202 const struct mtk_drv_group_desc
*drv_grp
;
204 if (pin
>= pctl
->devdata
->npins
)
207 pin_drv
= mtk_find_pin_drv_grp_by_pin(pctl
, pin
);
208 if (!pin_drv
|| pin_drv
->grp
> pctl
->devdata
->n_grp_cls
)
211 drv_grp
= pctl
->devdata
->grp_desc
+ pin_drv
->grp
;
212 if (driving
>= drv_grp
->min_drv
&& driving
<= drv_grp
->max_drv
213 && !(driving
% drv_grp
->step
)) {
214 val
= driving
/ drv_grp
->step
- 1;
215 bits
= drv_grp
->high_bit
- drv_grp
->low_bit
+ 1;
216 mask
= BIT(bits
) - 1;
217 shift
= pin_drv
->bit
+ drv_grp
->low_bit
;
220 return regmap_update_bits(mtk_get_regmap(pctl
, pin
),
221 pin_drv
->offset
, mask
, val
);
227 int mtk_pctrl_spec_pull_set_samereg(struct regmap
*regmap
,
228 const struct mtk_pin_spec_pupd_set_samereg
*pupd_infos
,
229 unsigned int info_num
, unsigned int pin
,
230 unsigned char align
, bool isup
, unsigned int r1r0
)
233 unsigned int reg_pupd
, reg_set
, reg_rst
;
234 unsigned int bit_pupd
, bit_r0
, bit_r1
;
235 const struct mtk_pin_spec_pupd_set_samereg
*spec_pupd_pin
;
238 for (i
= 0; i
< info_num
; i
++) {
239 if (pin
== pupd_infos
[i
].pin
) {
248 spec_pupd_pin
= pupd_infos
+ i
;
249 reg_set
= spec_pupd_pin
->offset
+ align
;
250 reg_rst
= spec_pupd_pin
->offset
+ (align
<< 1);
257 bit_pupd
= BIT(spec_pupd_pin
->pupd_bit
);
258 regmap_write(regmap
, reg_pupd
, bit_pupd
);
260 bit_r0
= BIT(spec_pupd_pin
->r0_bit
);
261 bit_r1
= BIT(spec_pupd_pin
->r1_bit
);
264 case MTK_PUPD_SET_R1R0_00
:
265 regmap_write(regmap
, reg_rst
, bit_r0
);
266 regmap_write(regmap
, reg_rst
, bit_r1
);
268 case MTK_PUPD_SET_R1R0_01
:
269 regmap_write(regmap
, reg_set
, bit_r0
);
270 regmap_write(regmap
, reg_rst
, bit_r1
);
272 case MTK_PUPD_SET_R1R0_10
:
273 regmap_write(regmap
, reg_rst
, bit_r0
);
274 regmap_write(regmap
, reg_set
, bit_r1
);
276 case MTK_PUPD_SET_R1R0_11
:
277 regmap_write(regmap
, reg_set
, bit_r0
);
278 regmap_write(regmap
, reg_set
, bit_r1
);
287 static int mtk_pconf_set_pull_select(struct mtk_pinctrl
*pctl
,
288 unsigned int pin
, bool enable
, bool isup
, unsigned int arg
)
291 unsigned int reg_pullen
, reg_pullsel
;
294 /* Some pins' pull setting are very different,
295 * they have separate pull up/down bit, R0 and R1
296 * resistor bit, so we need this special handle.
298 if (pctl
->devdata
->spec_pull_set
) {
299 ret
= pctl
->devdata
->spec_pull_set(mtk_get_regmap(pctl
, pin
),
300 pin
, pctl
->devdata
->port_align
, isup
, arg
);
305 /* For generic pull config, default arg value should be 0 or 1. */
306 if (arg
!= 0 && arg
!= 1) {
307 dev_err(pctl
->dev
, "invalid pull-up argument %d on pin %d .\n",
312 bit
= BIT(pin
& 0xf);
314 reg_pullen
= SET_ADDR(mtk_get_port(pctl
, pin
) +
315 pctl
->devdata
->pullen_offset
, pctl
);
317 reg_pullen
= CLR_ADDR(mtk_get_port(pctl
, pin
) +
318 pctl
->devdata
->pullen_offset
, pctl
);
321 reg_pullsel
= SET_ADDR(mtk_get_port(pctl
, pin
) +
322 pctl
->devdata
->pullsel_offset
, pctl
);
324 reg_pullsel
= CLR_ADDR(mtk_get_port(pctl
, pin
) +
325 pctl
->devdata
->pullsel_offset
, pctl
);
327 regmap_write(mtk_get_regmap(pctl
, pin
), reg_pullen
, bit
);
328 regmap_write(mtk_get_regmap(pctl
, pin
), reg_pullsel
, bit
);
332 static int mtk_pconf_parse_conf(struct pinctrl_dev
*pctldev
,
333 unsigned int pin
, enum pin_config_param param
,
334 enum pin_config_param arg
)
337 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
340 case PIN_CONFIG_BIAS_DISABLE
:
341 ret
= mtk_pconf_set_pull_select(pctl
, pin
, false, false, arg
);
343 case PIN_CONFIG_BIAS_PULL_UP
:
344 ret
= mtk_pconf_set_pull_select(pctl
, pin
, true, true, arg
);
346 case PIN_CONFIG_BIAS_PULL_DOWN
:
347 ret
= mtk_pconf_set_pull_select(pctl
, pin
, true, false, arg
);
349 case PIN_CONFIG_INPUT_ENABLE
:
350 mtk_pmx_gpio_set_direction(pctldev
, NULL
, pin
, true);
351 ret
= mtk_pconf_set_ies_smt(pctl
, pin
, arg
, param
);
353 case PIN_CONFIG_OUTPUT
:
354 mtk_gpio_set(pctl
->chip
, pin
, arg
);
355 ret
= mtk_pmx_gpio_set_direction(pctldev
, NULL
, pin
, false);
357 case PIN_CONFIG_INPUT_SCHMITT_ENABLE
:
358 mtk_pmx_gpio_set_direction(pctldev
, NULL
, pin
, true);
359 ret
= mtk_pconf_set_ies_smt(pctl
, pin
, arg
, param
);
361 case PIN_CONFIG_DRIVE_STRENGTH
:
362 ret
= mtk_pconf_set_driving(pctl
, pin
, arg
);
371 static int mtk_pconf_group_get(struct pinctrl_dev
*pctldev
,
373 unsigned long *config
)
375 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
377 *config
= pctl
->groups
[group
].config
;
382 static int mtk_pconf_group_set(struct pinctrl_dev
*pctldev
, unsigned group
,
383 unsigned long *configs
, unsigned num_configs
)
385 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
386 struct mtk_pinctrl_group
*g
= &pctl
->groups
[group
];
389 for (i
= 0; i
< num_configs
; i
++) {
390 ret
= mtk_pconf_parse_conf(pctldev
, g
->pin
,
391 pinconf_to_config_param(configs
[i
]),
392 pinconf_to_config_argument(configs
[i
]));
396 g
->config
= configs
[i
];
402 static const struct pinconf_ops mtk_pconf_ops
= {
403 .pin_config_group_get
= mtk_pconf_group_get
,
404 .pin_config_group_set
= mtk_pconf_group_set
,
407 static struct mtk_pinctrl_group
*
408 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl
*pctl
, u32 pin
)
412 for (i
= 0; i
< pctl
->ngroups
; i
++) {
413 struct mtk_pinctrl_group
*grp
= pctl
->groups
+ i
;
422 static const struct mtk_desc_function
*mtk_pctrl_find_function_by_pin(
423 struct mtk_pinctrl
*pctl
, u32 pin_num
, u32 fnum
)
425 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ pin_num
;
426 const struct mtk_desc_function
*func
= pin
->functions
;
428 while (func
&& func
->name
) {
429 if (func
->muxval
== fnum
)
437 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl
*pctl
,
438 u32 pin_num
, u32 fnum
)
442 for (i
= 0; i
< pctl
->devdata
->npins
; i
++) {
443 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ i
;
445 if (pin
->pin
.number
== pin_num
) {
446 const struct mtk_desc_function
*func
=
449 while (func
&& func
->name
) {
450 if (func
->muxval
== fnum
)
462 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl
*pctl
,
463 u32 pin
, u32 fnum
, struct mtk_pinctrl_group
*grp
,
464 struct pinctrl_map
**map
, unsigned *reserved_maps
,
469 if (*num_maps
== *reserved_maps
)
472 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
473 (*map
)[*num_maps
].data
.mux
.group
= grp
->name
;
475 ret
= mtk_pctrl_is_function_valid(pctl
, pin
, fnum
);
477 dev_err(pctl
->dev
, "invalid function %d on pin %d .\n",
482 (*map
)[*num_maps
].data
.mux
.function
= mtk_gpio_functions
[fnum
];
488 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev
*pctldev
,
489 struct device_node
*node
,
490 struct pinctrl_map
**map
,
491 unsigned *reserved_maps
,
494 struct property
*pins
;
495 u32 pinfunc
, pin
, func
;
496 int num_pins
, num_funcs
, maps_per_pin
;
497 unsigned long *configs
;
498 unsigned int num_configs
;
501 unsigned reserve
= 0;
502 struct mtk_pinctrl_group
*grp
;
503 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
505 pins
= of_find_property(node
, "pinmux", NULL
);
507 dev_err(pctl
->dev
, "missing pins property in node %s .\n",
512 err
= pinconf_generic_parse_dt_config(node
, pctldev
, &configs
,
520 num_pins
= pins
->length
/ sizeof(u32
);
521 num_funcs
= num_pins
;
525 if (has_config
&& num_pins
>= 1)
528 if (!num_pins
|| !maps_per_pin
) {
533 reserve
= num_pins
* maps_per_pin
;
535 err
= pinctrl_utils_reserve_map(pctldev
, map
,
536 reserved_maps
, num_maps
, reserve
);
540 for (i
= 0; i
< num_pins
; i
++) {
541 err
= of_property_read_u32_index(node
, "pinmux",
546 pin
= MTK_GET_PIN_NO(pinfunc
);
547 func
= MTK_GET_PIN_FUNC(pinfunc
);
549 if (pin
>= pctl
->devdata
->npins
||
550 func
>= ARRAY_SIZE(mtk_gpio_functions
)) {
551 dev_err(pctl
->dev
, "invalid pins value.\n");
556 grp
= mtk_pctrl_find_group_by_pin(pctl
, pin
);
558 dev_err(pctl
->dev
, "unable to match pin %d to group\n",
564 err
= mtk_pctrl_dt_node_to_map_func(pctl
, pin
, func
, grp
, map
,
565 reserved_maps
, num_maps
);
570 err
= pinctrl_utils_add_map_configs(pctldev
, map
,
571 reserved_maps
, num_maps
, grp
->name
,
572 configs
, num_configs
,
573 PIN_MAP_TYPE_CONFIGS_GROUP
);
586 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev
*pctldev
,
587 struct device_node
*np_config
,
588 struct pinctrl_map
**map
, unsigned *num_maps
)
590 struct device_node
*np
;
591 unsigned reserved_maps
;
598 for_each_child_of_node(np_config
, np
) {
599 ret
= mtk_pctrl_dt_subnode_to_map(pctldev
, np
, map
,
600 &reserved_maps
, num_maps
);
602 pinctrl_utils_dt_free_map(pctldev
, *map
, *num_maps
);
611 static int mtk_pctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
613 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
615 return pctl
->ngroups
;
618 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev
*pctldev
,
621 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
623 return pctl
->groups
[group
].name
;
626 static int mtk_pctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
628 const unsigned **pins
,
631 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
633 *pins
= (unsigned *)&pctl
->groups
[group
].pin
;
639 static const struct pinctrl_ops mtk_pctrl_ops
= {
640 .dt_node_to_map
= mtk_pctrl_dt_node_to_map
,
641 .dt_free_map
= pinctrl_utils_dt_free_map
,
642 .get_groups_count
= mtk_pctrl_get_groups_count
,
643 .get_group_name
= mtk_pctrl_get_group_name
,
644 .get_group_pins
= mtk_pctrl_get_group_pins
,
647 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
649 return ARRAY_SIZE(mtk_gpio_functions
);
652 static const char *mtk_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
655 return mtk_gpio_functions
[selector
];
658 static int mtk_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
660 const char * const **groups
,
661 unsigned * const num_groups
)
663 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
665 *groups
= pctl
->grp_names
;
666 *num_groups
= pctl
->ngroups
;
671 static int mtk_pmx_set_mode(struct pinctrl_dev
*pctldev
,
672 unsigned long pin
, unsigned long mode
)
674 unsigned int reg_addr
;
677 unsigned int mask
= (1L << GPIO_MODE_BITS
) - 1;
678 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
680 reg_addr
= ((pin
/ MAX_GPIO_MODE_PER_REG
) << pctl
->devdata
->port_shf
)
681 + pctl
->devdata
->pinmux_offset
;
683 bit
= pin
% MAX_GPIO_MODE_PER_REG
;
684 mask
<<= (GPIO_MODE_BITS
* bit
);
685 val
= (mode
<< (GPIO_MODE_BITS
* bit
));
686 return regmap_update_bits(mtk_get_regmap(pctl
, pin
),
687 reg_addr
, mask
, val
);
690 static const struct mtk_desc_pin
*
691 mtk_find_pin_by_eint_num(struct mtk_pinctrl
*pctl
, unsigned int eint_num
)
694 const struct mtk_desc_pin
*pin
;
696 for (i
= 0; i
< pctl
->devdata
->npins
; i
++) {
697 pin
= pctl
->devdata
->pins
+ i
;
698 if (pin
->eint
.eintnum
== eint_num
)
705 static int mtk_pmx_set_mux(struct pinctrl_dev
*pctldev
,
710 const struct mtk_desc_function
*desc
;
711 struct mtk_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
712 struct mtk_pinctrl_group
*g
= pctl
->groups
+ group
;
714 ret
= mtk_pctrl_is_function_valid(pctl
, g
->pin
, function
);
716 dev_err(pctl
->dev
, "invalid function %d on group %d .\n",
721 desc
= mtk_pctrl_find_function_by_pin(pctl
, g
->pin
, function
);
724 mtk_pmx_set_mode(pctldev
, g
->pin
, desc
->muxval
);
728 static const struct pinmux_ops mtk_pmx_ops
= {
729 .get_functions_count
= mtk_pmx_get_funcs_cnt
,
730 .get_function_name
= mtk_pmx_get_func_name
,
731 .get_function_groups
= mtk_pmx_get_func_groups
,
732 .set_mux
= mtk_pmx_set_mux
,
733 .gpio_set_direction
= mtk_pmx_gpio_set_direction
,
736 static int mtk_gpio_direction_input(struct gpio_chip
*chip
,
739 return pinctrl_gpio_direction_input(chip
->base
+ offset
);
742 static int mtk_gpio_direction_output(struct gpio_chip
*chip
,
743 unsigned offset
, int value
)
745 mtk_gpio_set(chip
, offset
, value
);
746 return pinctrl_gpio_direction_output(chip
->base
+ offset
);
749 static int mtk_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
751 unsigned int reg_addr
;
753 unsigned int read_val
= 0;
755 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
757 reg_addr
= mtk_get_port(pctl
, offset
) + pctl
->devdata
->dir_offset
;
758 bit
= BIT(offset
& 0xf);
759 regmap_read(pctl
->regmap1
, reg_addr
, &read_val
);
760 return !(read_val
& bit
);
763 static int mtk_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
765 unsigned int reg_addr
;
767 unsigned int read_val
= 0;
768 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
770 reg_addr
= mtk_get_port(pctl
, offset
) +
771 pctl
->devdata
->din_offset
;
773 bit
= BIT(offset
& 0xf);
774 regmap_read(pctl
->regmap1
, reg_addr
, &read_val
);
775 return !!(read_val
& bit
);
778 static int mtk_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
780 const struct mtk_desc_pin
*pin
;
781 struct mtk_pinctrl
*pctl
= gpiochip_get_data(chip
);
784 pin
= pctl
->devdata
->pins
+ offset
;
785 if (pin
->eint
.eintnum
== NO_EINT_SUPPORT
)
788 irq
= irq_find_mapping(pctl
->domain
, pin
->eint
.eintnum
);
795 static int mtk_pinctrl_irq_request_resources(struct irq_data
*d
)
797 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
798 const struct mtk_desc_pin
*pin
;
801 pin
= mtk_find_pin_by_eint_num(pctl
, d
->hwirq
);
804 dev_err(pctl
->dev
, "Can not find pin\n");
808 ret
= gpiochip_lock_as_irq(pctl
->chip
, pin
->pin
.number
);
810 dev_err(pctl
->dev
, "unable to lock HW IRQ %lu for IRQ\n",
815 /* set mux to INT mode */
816 mtk_pmx_set_mode(pctl
->pctl_dev
, pin
->pin
.number
, pin
->eint
.eintmux
);
821 static void mtk_pinctrl_irq_release_resources(struct irq_data
*d
)
823 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
824 const struct mtk_desc_pin
*pin
;
826 pin
= mtk_find_pin_by_eint_num(pctl
, d
->hwirq
);
829 dev_err(pctl
->dev
, "Can not find pin\n");
833 gpiochip_unlock_as_irq(pctl
->chip
, pin
->pin
.number
);
836 static void __iomem
*mtk_eint_get_offset(struct mtk_pinctrl
*pctl
,
837 unsigned int eint_num
, unsigned int offset
)
839 unsigned int eint_base
= 0;
842 if (eint_num
>= pctl
->devdata
->ap_num
)
843 eint_base
= pctl
->devdata
->ap_num
;
845 reg
= pctl
->eint_reg_base
+ offset
+ ((eint_num
- eint_base
) / 32) * 4;
851 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
852 * @eint_num: the EINT number to setmtk_pinctrl
854 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl
*pctl
,
855 unsigned int eint_num
)
858 unsigned int bit
= BIT(eint_num
% 32);
859 const struct mtk_eint_offsets
*eint_offsets
=
860 &pctl
->devdata
->eint_offsets
;
862 void __iomem
*reg
= mtk_eint_get_offset(pctl
, eint_num
,
865 if (readl(reg
) & bit
)
866 sens
= MT_LEVEL_SENSITIVE
;
868 sens
= MT_EDGE_SENSITIVE
;
870 if ((eint_num
< pctl
->devdata
->db_cnt
) && (sens
!= MT_EDGE_SENSITIVE
))
877 * mtk_eint_get_mask: To get the eint mask
878 * @eint_num: the EINT number to get
880 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl
*pctl
,
881 unsigned int eint_num
)
883 unsigned int bit
= BIT(eint_num
% 32);
884 const struct mtk_eint_offsets
*eint_offsets
=
885 &pctl
->devdata
->eint_offsets
;
887 void __iomem
*reg
= mtk_eint_get_offset(pctl
, eint_num
,
890 return !!(readl(reg
) & bit
);
893 static int mtk_eint_flip_edge(struct mtk_pinctrl
*pctl
, int hwirq
)
895 int start_level
, curr_level
;
896 unsigned int reg_offset
;
897 const struct mtk_eint_offsets
*eint_offsets
= &(pctl
->devdata
->eint_offsets
);
898 u32 mask
= BIT(hwirq
& 0x1f);
899 u32 port
= (hwirq
>> 5) & eint_offsets
->port_mask
;
900 void __iomem
*reg
= pctl
->eint_reg_base
+ (port
<< 2);
901 const struct mtk_desc_pin
*pin
;
903 pin
= mtk_find_pin_by_eint_num(pctl
, hwirq
);
904 curr_level
= mtk_gpio_get(pctl
->chip
, pin
->pin
.number
);
906 start_level
= curr_level
;
908 reg_offset
= eint_offsets
->pol_clr
;
910 reg_offset
= eint_offsets
->pol_set
;
911 writel(mask
, reg
+ reg_offset
);
913 curr_level
= mtk_gpio_get(pctl
->chip
, pin
->pin
.number
);
914 } while (start_level
!= curr_level
);
919 static void mtk_eint_mask(struct irq_data
*d
)
921 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
922 const struct mtk_eint_offsets
*eint_offsets
=
923 &pctl
->devdata
->eint_offsets
;
924 u32 mask
= BIT(d
->hwirq
& 0x1f);
925 void __iomem
*reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
926 eint_offsets
->mask_set
);
931 static void mtk_eint_unmask(struct irq_data
*d
)
933 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
934 const struct mtk_eint_offsets
*eint_offsets
=
935 &pctl
->devdata
->eint_offsets
;
936 u32 mask
= BIT(d
->hwirq
& 0x1f);
937 void __iomem
*reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
938 eint_offsets
->mask_clr
);
942 if (pctl
->eint_dual_edges
[d
->hwirq
])
943 mtk_eint_flip_edge(pctl
, d
->hwirq
);
946 static int mtk_gpio_set_debounce(struct gpio_chip
*chip
, unsigned offset
,
949 struct mtk_pinctrl
*pctl
= dev_get_drvdata(chip
->parent
);
950 int eint_num
, virq
, eint_offset
;
951 unsigned int set_offset
, bit
, clr_bit
, clr_offset
, rst
, i
, unmask
, dbnc
;
952 static const unsigned int dbnc_arr
[] = {0 , 1, 16, 32, 64, 128, 256};
953 const struct mtk_desc_pin
*pin
;
956 pin
= pctl
->devdata
->pins
+ offset
;
957 if (pin
->eint
.eintnum
== NO_EINT_SUPPORT
)
960 eint_num
= pin
->eint
.eintnum
;
961 virq
= irq_find_mapping(pctl
->domain
, eint_num
);
962 eint_offset
= (eint_num
% 4) * 8;
963 d
= irq_get_irq_data(virq
);
965 set_offset
= (eint_num
/ 4) * 4 + pctl
->devdata
->eint_offsets
.dbnc_set
;
966 clr_offset
= (eint_num
/ 4) * 4 + pctl
->devdata
->eint_offsets
.dbnc_clr
;
967 if (!mtk_eint_can_en_debounce(pctl
, eint_num
))
970 dbnc
= ARRAY_SIZE(dbnc_arr
);
971 for (i
= 0; i
< ARRAY_SIZE(dbnc_arr
); i
++) {
972 if (debounce
<= dbnc_arr
[i
]) {
978 if (!mtk_eint_get_mask(pctl
, eint_num
)) {
985 clr_bit
= 0xff << eint_offset
;
986 writel(clr_bit
, pctl
->eint_reg_base
+ clr_offset
);
988 bit
= ((dbnc
<< EINT_DBNC_SET_DBNC_BITS
) | EINT_DBNC_SET_EN
) <<
990 rst
= EINT_DBNC_RST_BIT
<< eint_offset
;
991 writel(rst
| bit
, pctl
->eint_reg_base
+ set_offset
);
993 /* Delay a while (more than 2T) to wait for hw debounce counter reset
1002 static struct gpio_chip mtk_gpio_chip
= {
1003 .owner
= THIS_MODULE
,
1004 .request
= gpiochip_generic_request
,
1005 .free
= gpiochip_generic_free
,
1006 .get_direction
= mtk_gpio_get_direction
,
1007 .direction_input
= mtk_gpio_direction_input
,
1008 .direction_output
= mtk_gpio_direction_output
,
1009 .get
= mtk_gpio_get
,
1010 .set
= mtk_gpio_set
,
1011 .to_irq
= mtk_gpio_to_irq
,
1012 .set_debounce
= mtk_gpio_set_debounce
,
1013 .of_gpio_n_cells
= 2,
1016 static int mtk_eint_set_type(struct irq_data
*d
,
1019 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
1020 const struct mtk_eint_offsets
*eint_offsets
=
1021 &pctl
->devdata
->eint_offsets
;
1022 u32 mask
= BIT(d
->hwirq
& 0x1f);
1025 if (((type
& IRQ_TYPE_EDGE_BOTH
) && (type
& IRQ_TYPE_LEVEL_MASK
)) ||
1026 ((type
& IRQ_TYPE_LEVEL_MASK
) == IRQ_TYPE_LEVEL_MASK
)) {
1027 dev_err(pctl
->dev
, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1028 d
->irq
, d
->hwirq
, type
);
1032 if ((type
& IRQ_TYPE_EDGE_BOTH
) == IRQ_TYPE_EDGE_BOTH
)
1033 pctl
->eint_dual_edges
[d
->hwirq
] = 1;
1035 pctl
->eint_dual_edges
[d
->hwirq
] = 0;
1037 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_EDGE_FALLING
)) {
1038 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1039 eint_offsets
->pol_clr
);
1042 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1043 eint_offsets
->pol_set
);
1047 if (type
& (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
)) {
1048 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1049 eint_offsets
->sens_clr
);
1052 reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1053 eint_offsets
->sens_set
);
1057 if (pctl
->eint_dual_edges
[d
->hwirq
])
1058 mtk_eint_flip_edge(pctl
, d
->hwirq
);
1063 static int mtk_eint_irq_set_wake(struct irq_data
*d
, unsigned int on
)
1065 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
1066 int shift
= d
->hwirq
& 0x1f;
1067 int reg
= d
->hwirq
>> 5;
1070 pctl
->wake_mask
[reg
] |= BIT(shift
);
1072 pctl
->wake_mask
[reg
] &= ~BIT(shift
);
1077 static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets
*chip
,
1078 void __iomem
*eint_reg_base
, u32
*buf
)
1083 for (port
= 0; port
< chip
->ports
; port
++) {
1084 reg
= eint_reg_base
+ (port
<< 2);
1085 writel_relaxed(~buf
[port
], reg
+ chip
->mask_set
);
1086 writel_relaxed(buf
[port
], reg
+ chip
->mask_clr
);
1090 static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets
*chip
,
1091 void __iomem
*eint_reg_base
, u32
*buf
)
1096 for (port
= 0; port
< chip
->ports
; port
++) {
1097 reg
= eint_reg_base
+ chip
->mask
+ (port
<< 2);
1098 buf
[port
] = ~readl_relaxed(reg
);
1099 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1103 static int mtk_eint_suspend(struct device
*device
)
1106 struct mtk_pinctrl
*pctl
= dev_get_drvdata(device
);
1107 const struct mtk_eint_offsets
*eint_offsets
=
1108 &pctl
->devdata
->eint_offsets
;
1110 reg
= pctl
->eint_reg_base
;
1111 mtk_eint_chip_read_mask(eint_offsets
, reg
, pctl
->cur_mask
);
1112 mtk_eint_chip_write_mask(eint_offsets
, reg
, pctl
->wake_mask
);
1117 static int mtk_eint_resume(struct device
*device
)
1119 struct mtk_pinctrl
*pctl
= dev_get_drvdata(device
);
1120 const struct mtk_eint_offsets
*eint_offsets
=
1121 &pctl
->devdata
->eint_offsets
;
1123 mtk_eint_chip_write_mask(eint_offsets
,
1124 pctl
->eint_reg_base
, pctl
->cur_mask
);
1129 const struct dev_pm_ops mtk_eint_pm_ops
= {
1130 .suspend
= mtk_eint_suspend
,
1131 .resume
= mtk_eint_resume
,
1134 static void mtk_eint_ack(struct irq_data
*d
)
1136 struct mtk_pinctrl
*pctl
= irq_data_get_irq_chip_data(d
);
1137 const struct mtk_eint_offsets
*eint_offsets
=
1138 &pctl
->devdata
->eint_offsets
;
1139 u32 mask
= BIT(d
->hwirq
& 0x1f);
1140 void __iomem
*reg
= mtk_eint_get_offset(pctl
, d
->hwirq
,
1146 static struct irq_chip mtk_pinctrl_irq_chip
= {
1148 .irq_disable
= mtk_eint_mask
,
1149 .irq_mask
= mtk_eint_mask
,
1150 .irq_unmask
= mtk_eint_unmask
,
1151 .irq_ack
= mtk_eint_ack
,
1152 .irq_set_type
= mtk_eint_set_type
,
1153 .irq_set_wake
= mtk_eint_irq_set_wake
,
1154 .irq_request_resources
= mtk_pinctrl_irq_request_resources
,
1155 .irq_release_resources
= mtk_pinctrl_irq_release_resources
,
1158 static unsigned int mtk_eint_init(struct mtk_pinctrl
*pctl
)
1160 const struct mtk_eint_offsets
*eint_offsets
=
1161 &pctl
->devdata
->eint_offsets
;
1162 void __iomem
*reg
= pctl
->eint_reg_base
+ eint_offsets
->dom_en
;
1165 for (i
= 0; i
< pctl
->devdata
->ap_num
; i
+= 32) {
1166 writel(0xffffffff, reg
);
1173 mtk_eint_debounce_process(struct mtk_pinctrl
*pctl
, int index
)
1175 unsigned int rst
, ctrl_offset
;
1176 unsigned int bit
, dbnc
;
1177 const struct mtk_eint_offsets
*eint_offsets
=
1178 &pctl
->devdata
->eint_offsets
;
1180 ctrl_offset
= (index
/ 4) * 4 + eint_offsets
->dbnc_ctrl
;
1181 dbnc
= readl(pctl
->eint_reg_base
+ ctrl_offset
);
1182 bit
= EINT_DBNC_SET_EN
<< ((index
% 4) * 8);
1183 if ((bit
& dbnc
) > 0) {
1184 ctrl_offset
= (index
/ 4) * 4 + eint_offsets
->dbnc_set
;
1185 rst
= EINT_DBNC_RST_BIT
<< ((index
% 4) * 8);
1186 writel(rst
, pctl
->eint_reg_base
+ ctrl_offset
);
1190 static void mtk_eint_irq_handler(struct irq_desc
*desc
)
1192 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1193 struct mtk_pinctrl
*pctl
= irq_desc_get_handler_data(desc
);
1194 unsigned int status
, eint_num
;
1195 int offset
, index
, virq
;
1196 const struct mtk_eint_offsets
*eint_offsets
=
1197 &pctl
->devdata
->eint_offsets
;
1198 void __iomem
*reg
= mtk_eint_get_offset(pctl
, 0, eint_offsets
->stat
);
1199 int dual_edges
, start_level
, curr_level
;
1200 const struct mtk_desc_pin
*pin
;
1202 chained_irq_enter(chip
, desc
);
1203 for (eint_num
= 0; eint_num
< pctl
->devdata
->ap_num
; eint_num
+= 32) {
1204 status
= readl(reg
);
1207 offset
= __ffs(status
);
1208 index
= eint_num
+ offset
;
1209 virq
= irq_find_mapping(pctl
->domain
, index
);
1210 status
&= ~BIT(offset
);
1212 dual_edges
= pctl
->eint_dual_edges
[index
];
1214 /* Clear soft-irq in case we raised it
1216 writel(BIT(offset
), reg
- eint_offsets
->stat
+
1217 eint_offsets
->soft_clr
);
1219 pin
= mtk_find_pin_by_eint_num(pctl
, index
);
1220 start_level
= mtk_gpio_get(pctl
->chip
,
1224 generic_handle_irq(virq
);
1227 curr_level
= mtk_eint_flip_edge(pctl
, index
);
1229 /* If level changed, we might lost one edge
1230 interrupt, raised it through soft-irq */
1231 if (start_level
!= curr_level
)
1232 writel(BIT(offset
), reg
-
1233 eint_offsets
->stat
+
1234 eint_offsets
->soft_set
);
1237 if (index
< pctl
->devdata
->db_cnt
)
1238 mtk_eint_debounce_process(pctl
, index
);
1241 chained_irq_exit(chip
, desc
);
1244 static int mtk_pctrl_build_state(struct platform_device
*pdev
)
1246 struct mtk_pinctrl
*pctl
= platform_get_drvdata(pdev
);
1249 pctl
->ngroups
= pctl
->devdata
->npins
;
1251 /* Allocate groups */
1252 pctl
->groups
= devm_kcalloc(&pdev
->dev
, pctl
->ngroups
,
1253 sizeof(*pctl
->groups
), GFP_KERNEL
);
1257 /* We assume that one pin is one group, use pin name as group name. */
1258 pctl
->grp_names
= devm_kcalloc(&pdev
->dev
, pctl
->ngroups
,
1259 sizeof(*pctl
->grp_names
), GFP_KERNEL
);
1260 if (!pctl
->grp_names
)
1263 for (i
= 0; i
< pctl
->devdata
->npins
; i
++) {
1264 const struct mtk_desc_pin
*pin
= pctl
->devdata
->pins
+ i
;
1265 struct mtk_pinctrl_group
*group
= pctl
->groups
+ i
;
1267 group
->name
= pin
->pin
.name
;
1268 group
->pin
= pin
->pin
.number
;
1270 pctl
->grp_names
[i
] = pin
->pin
.name
;
1276 int mtk_pctrl_init(struct platform_device
*pdev
,
1277 const struct mtk_pinctrl_devdata
*data
,
1278 struct regmap
*regmap
)
1280 struct pinctrl_pin_desc
*pins
;
1281 struct mtk_pinctrl
*pctl
;
1282 struct device_node
*np
= pdev
->dev
.of_node
, *node
;
1283 struct property
*prop
;
1284 struct resource
*res
;
1285 int i
, ret
, irq
, ports_buf
;
1287 pctl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
), GFP_KERNEL
);
1291 platform_set_drvdata(pdev
, pctl
);
1293 prop
= of_find_property(np
, "pins-are-numbered", NULL
);
1295 dev_err(&pdev
->dev
, "only support pins-are-numbered format\n");
1299 node
= of_parse_phandle(np
, "mediatek,pctl-regmap", 0);
1301 pctl
->regmap1
= syscon_node_to_regmap(node
);
1302 if (IS_ERR(pctl
->regmap1
))
1303 return PTR_ERR(pctl
->regmap1
);
1304 } else if (regmap
) {
1305 pctl
->regmap1
= regmap
;
1307 dev_err(&pdev
->dev
, "Pinctrl node has not register regmap.\n");
1311 /* Only 8135 has two base addr, other SoCs have only one. */
1312 node
= of_parse_phandle(np
, "mediatek,pctl-regmap", 1);
1314 pctl
->regmap2
= syscon_node_to_regmap(node
);
1315 if (IS_ERR(pctl
->regmap2
))
1316 return PTR_ERR(pctl
->regmap2
);
1319 pctl
->devdata
= data
;
1320 ret
= mtk_pctrl_build_state(pdev
);
1322 dev_err(&pdev
->dev
, "build state failed: %d\n", ret
);
1326 pins
= devm_kcalloc(&pdev
->dev
, pctl
->devdata
->npins
, sizeof(*pins
),
1331 for (i
= 0; i
< pctl
->devdata
->npins
; i
++)
1332 pins
[i
] = pctl
->devdata
->pins
[i
].pin
;
1334 pctl
->pctl_desc
.name
= dev_name(&pdev
->dev
);
1335 pctl
->pctl_desc
.owner
= THIS_MODULE
;
1336 pctl
->pctl_desc
.pins
= pins
;
1337 pctl
->pctl_desc
.npins
= pctl
->devdata
->npins
;
1338 pctl
->pctl_desc
.confops
= &mtk_pconf_ops
;
1339 pctl
->pctl_desc
.pctlops
= &mtk_pctrl_ops
;
1340 pctl
->pctl_desc
.pmxops
= &mtk_pmx_ops
;
1341 pctl
->dev
= &pdev
->dev
;
1343 pctl
->pctl_dev
= pinctrl_register(&pctl
->pctl_desc
, &pdev
->dev
, pctl
);
1344 if (IS_ERR(pctl
->pctl_dev
)) {
1345 dev_err(&pdev
->dev
, "couldn't register pinctrl driver\n");
1346 return PTR_ERR(pctl
->pctl_dev
);
1349 pctl
->chip
= devm_kzalloc(&pdev
->dev
, sizeof(*pctl
->chip
), GFP_KERNEL
);
1355 *pctl
->chip
= mtk_gpio_chip
;
1356 pctl
->chip
->ngpio
= pctl
->devdata
->npins
;
1357 pctl
->chip
->label
= dev_name(&pdev
->dev
);
1358 pctl
->chip
->parent
= &pdev
->dev
;
1359 pctl
->chip
->base
= -1;
1361 ret
= gpiochip_add_data(pctl
->chip
, pctl
);
1367 /* Register the GPIO to pin mappings. */
1368 ret
= gpiochip_add_pin_range(pctl
->chip
, dev_name(&pdev
->dev
),
1369 0, 0, pctl
->devdata
->npins
);
1375 if (!of_property_read_bool(np
, "interrupt-controller"))
1378 /* Get EINT register base from dts. */
1379 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1381 dev_err(&pdev
->dev
, "Unable to get Pinctrl resource\n");
1386 pctl
->eint_reg_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1387 if (IS_ERR(pctl
->eint_reg_base
)) {
1392 ports_buf
= pctl
->devdata
->eint_offsets
.ports
;
1393 pctl
->wake_mask
= devm_kcalloc(&pdev
->dev
, ports_buf
,
1394 sizeof(*pctl
->wake_mask
), GFP_KERNEL
);
1395 if (!pctl
->wake_mask
) {
1400 pctl
->cur_mask
= devm_kcalloc(&pdev
->dev
, ports_buf
,
1401 sizeof(*pctl
->cur_mask
), GFP_KERNEL
);
1402 if (!pctl
->cur_mask
) {
1407 pctl
->eint_dual_edges
= devm_kcalloc(&pdev
->dev
, pctl
->devdata
->ap_num
,
1408 sizeof(int), GFP_KERNEL
);
1409 if (!pctl
->eint_dual_edges
) {
1414 irq
= irq_of_parse_and_map(np
, 0);
1416 dev_err(&pdev
->dev
, "couldn't parse and map irq\n");
1421 pctl
->domain
= irq_domain_add_linear(np
,
1422 pctl
->devdata
->ap_num
, &irq_domain_simple_ops
, NULL
);
1423 if (!pctl
->domain
) {
1424 dev_err(&pdev
->dev
, "Couldn't register IRQ domain\n");
1429 mtk_eint_init(pctl
);
1430 for (i
= 0; i
< pctl
->devdata
->ap_num
; i
++) {
1431 int virq
= irq_create_mapping(pctl
->domain
, i
);
1433 irq_set_chip_and_handler(virq
, &mtk_pinctrl_irq_chip
,
1435 irq_set_chip_data(virq
, pctl
);
1438 irq_set_chained_handler_and_data(irq
, mtk_eint_irq_handler
, pctl
);
1442 gpiochip_remove(pctl
->chip
);
1444 pinctrl_unregister(pctl
->pctl_dev
);
1448 MODULE_LICENSE("GPL");
1449 MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1450 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");