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[mirror_ubuntu-kernels.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
1 /*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26
27 #include "../pinctrl-utils.h"
28
29 #define OUTPUT_EN 0x0
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
34
35 #define IRQ_EN 0x0
36 #define IRQ_POL 0x08
37 #define IRQ_STATUS 0x10
38 #define IRQ_WKUP 0x18
39
40 #define NB_FUNCS 3
41 #define GPIO_PER_REG 32
42
43 /**
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
46 * pins.
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
49 * the group
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
57 */
58 struct armada_37xx_pin_group {
59 const char *name;
60 unsigned int start_pin;
61 unsigned int npins;
62 u32 reg_mask;
63 u32 val[NB_FUNCS];
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
67 unsigned int *pins;
68 };
69
70 struct armada_37xx_pin_data {
71 u8 nr_pins;
72 char *name;
73 struct armada_37xx_pin_group *groups;
74 int ngroups;
75 };
76
77 struct armada_37xx_pmx_func {
78 const char *name;
79 const char **groups;
80 unsigned int ngroups;
81 };
82
83 struct armada_37xx_pm_state {
84 u32 out_en_l;
85 u32 out_en_h;
86 u32 out_val_l;
87 u32 out_val_h;
88 u32 irq_en_l;
89 u32 irq_en_h;
90 u32 irq_pol_l;
91 u32 irq_pol_h;
92 u32 selection;
93 };
94
95 struct armada_37xx_pinctrl {
96 struct regmap *regmap;
97 void __iomem *base;
98 const struct armada_37xx_pin_data *data;
99 struct device *dev;
100 struct gpio_chip gpio_chip;
101 struct irq_chip irq_chip;
102 spinlock_t irq_lock;
103 struct pinctrl_desc pctl;
104 struct pinctrl_dev *pctl_dev;
105 struct armada_37xx_pin_group *groups;
106 unsigned int ngroups;
107 struct armada_37xx_pmx_func *funcs;
108 unsigned int nfuncs;
109 struct armada_37xx_pm_state pm;
110 };
111
112 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
113 { \
114 .name = _name, \
115 .start_pin = _start, \
116 .npins = _nr, \
117 .reg_mask = _mask, \
118 .val = {0, _mask}, \
119 .funcs = {_func1, _func2} \
120 }
121
122 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
123 { \
124 .name = _name, \
125 .start_pin = _start, \
126 .npins = _nr, \
127 .reg_mask = _mask, \
128 .val = {0, _mask}, \
129 .funcs = {_func1, "gpio"} \
130 }
131
132 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
133 { \
134 .name = _name, \
135 .start_pin = _start, \
136 .npins = _nr, \
137 .reg_mask = _mask, \
138 .val = {_val1, _val2}, \
139 .funcs = {_func1, "gpio"} \
140 }
141
142 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
143 { \
144 .name = _name, \
145 .start_pin = _start, \
146 .npins = _nr, \
147 .reg_mask = _mask, \
148 .val = {_v1, _v2, _v3}, \
149 .funcs = {_f1, _f2, "gpio"} \
150 }
151
152 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
153 _f1, _f2) \
154 { \
155 .name = _name, \
156 .start_pin = _start, \
157 .npins = _nr, \
158 .reg_mask = _mask, \
159 .val = {_v1, _v2}, \
160 .extra_pin = _start2, \
161 .extra_npins = _nr2, \
162 .funcs = {_f1, _f2} \
163 }
164
165 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
166 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
167 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
168 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
169 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
170 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
171 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
172 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
173 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
174 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
175 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
176 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
177 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
178 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
179 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
180 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
181 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
182 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
183 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
184 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
185 18, 2, "gpio", "uart"),
186 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
187 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
188 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
189 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
190
191 };
192
193 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
194 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
195 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
196 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
197 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
198 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
199 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
200 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
201 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
202 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
203 "mii", "mii_err"),
204 };
205
206 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
207 .nr_pins = 36,
208 .name = "GPIO1",
209 .groups = armada_37xx_nb_groups,
210 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
211 };
212
213 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
214 .nr_pins = 30,
215 .name = "GPIO2",
216 .groups = armada_37xx_sb_groups,
217 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
218 };
219
220 static inline void armada_37xx_update_reg(unsigned int *reg,
221 unsigned int offset)
222 {
223 /* We never have more than 2 registers */
224 if (offset >= GPIO_PER_REG) {
225 offset -= GPIO_PER_REG;
226 *reg += sizeof(u32);
227 }
228 }
229
230 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
231 struct armada_37xx_pinctrl *info, int pin, int *grp)
232 {
233 while (*grp < info->ngroups) {
234 struct armada_37xx_pin_group *group = &info->groups[*grp];
235 int j;
236
237 *grp = *grp + 1;
238 for (j = 0; j < (group->npins + group->extra_npins); j++)
239 if (group->pins[j] == pin)
240 return group;
241 }
242 return NULL;
243 }
244
245 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
246 unsigned int selector, unsigned long *config)
247 {
248 return -ENOTSUPP;
249 }
250
251 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
252 unsigned int selector, unsigned long *configs,
253 unsigned int num_configs)
254 {
255 return -ENOTSUPP;
256 }
257
258 static const struct pinconf_ops armada_37xx_pinconf_ops = {
259 .is_generic = true,
260 .pin_config_group_get = armada_37xx_pin_config_group_get,
261 .pin_config_group_set = armada_37xx_pin_config_group_set,
262 };
263
264 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
265 {
266 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
267
268 return info->ngroups;
269 }
270
271 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
272 unsigned int group)
273 {
274 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
275
276 return info->groups[group].name;
277 }
278
279 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
280 unsigned int selector,
281 const unsigned int **pins,
282 unsigned int *npins)
283 {
284 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
285
286 if (selector >= info->ngroups)
287 return -EINVAL;
288
289 *pins = info->groups[selector].pins;
290 *npins = info->groups[selector].npins +
291 info->groups[selector].extra_npins;
292
293 return 0;
294 }
295
296 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
297 .get_groups_count = armada_37xx_get_groups_count,
298 .get_group_name = armada_37xx_get_group_name,
299 .get_group_pins = armada_37xx_get_group_pins,
300 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
301 .dt_free_map = pinctrl_utils_free_map,
302 };
303
304 /*
305 * Pinmux_ops handling
306 */
307
308 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
309 {
310 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
311
312 return info->nfuncs;
313 }
314
315 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
316 unsigned int selector)
317 {
318 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
319
320 return info->funcs[selector].name;
321 }
322
323 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
324 unsigned int selector,
325 const char * const **groups,
326 unsigned int * const num_groups)
327 {
328 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
329
330 *groups = info->funcs[selector].groups;
331 *num_groups = info->funcs[selector].ngroups;
332
333 return 0;
334 }
335
336 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
337 const char *name,
338 struct armada_37xx_pin_group *grp)
339 {
340 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
341 unsigned int reg = SELECTION;
342 unsigned int mask = grp->reg_mask;
343 int func, val;
344
345 dev_dbg(info->dev, "enable function %s group %s\n",
346 name, grp->name);
347
348 func = match_string(grp->funcs, NB_FUNCS, name);
349 if (func < 0)
350 return -ENOTSUPP;
351
352 val = grp->val[func];
353
354 regmap_update_bits(info->regmap, reg, mask, val);
355
356 return 0;
357 }
358
359 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
360 unsigned int selector,
361 unsigned int group)
362 {
363
364 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
365 struct armada_37xx_pin_group *grp = &info->groups[group];
366 const char *name = info->funcs[selector].name;
367
368 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
369 }
370
371 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
372 struct irq_data *d)
373 {
374 int offset = irqd_to_hwirq(d);
375
376 armada_37xx_update_reg(reg, offset);
377 }
378
379 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
380 unsigned int offset)
381 {
382 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
383 unsigned int reg = OUTPUT_EN;
384 unsigned int mask;
385
386 armada_37xx_update_reg(&reg, offset);
387 mask = BIT(offset);
388
389 return regmap_update_bits(info->regmap, reg, mask, 0);
390 }
391
392 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
393 unsigned int offset)
394 {
395 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
396 unsigned int reg = OUTPUT_EN;
397 unsigned int val, mask;
398
399 armada_37xx_update_reg(&reg, offset);
400 mask = BIT(offset);
401 regmap_read(info->regmap, reg, &val);
402
403 return !(val & mask);
404 }
405
406 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
407 unsigned int offset, int value)
408 {
409 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
410 unsigned int reg = OUTPUT_EN;
411 unsigned int mask, val, ret;
412
413 armada_37xx_update_reg(&reg, offset);
414 mask = BIT(offset);
415
416 ret = regmap_update_bits(info->regmap, reg, mask, mask);
417
418 if (ret)
419 return ret;
420
421 reg = OUTPUT_VAL;
422 val = value ? mask : 0;
423 regmap_update_bits(info->regmap, reg, mask, val);
424
425 return 0;
426 }
427
428 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
429 {
430 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
431 unsigned int reg = INPUT_VAL;
432 unsigned int val, mask;
433
434 armada_37xx_update_reg(&reg, offset);
435 mask = BIT(offset);
436
437 regmap_read(info->regmap, reg, &val);
438
439 return (val & mask) != 0;
440 }
441
442 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
443 int value)
444 {
445 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
446 unsigned int reg = OUTPUT_VAL;
447 unsigned int mask, val;
448
449 armada_37xx_update_reg(&reg, offset);
450 mask = BIT(offset);
451 val = value ? mask : 0;
452
453 regmap_update_bits(info->regmap, reg, mask, val);
454 }
455
456 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
457 struct pinctrl_gpio_range *range,
458 unsigned int offset, bool input)
459 {
460 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 struct gpio_chip *chip = range->gc;
462
463 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
464 offset, range->name, offset, input ? "input" : "output");
465
466 if (input)
467 armada_37xx_gpio_direction_input(chip, offset);
468 else
469 armada_37xx_gpio_direction_output(chip, offset, 0);
470
471 return 0;
472 }
473
474 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
475 struct pinctrl_gpio_range *range,
476 unsigned int offset)
477 {
478 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
479 struct armada_37xx_pin_group *group;
480 int grp = 0;
481
482 dev_dbg(info->dev, "requesting gpio %d\n", offset);
483
484 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
485 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
486
487 return 0;
488 }
489
490 static const struct pinmux_ops armada_37xx_pmx_ops = {
491 .get_functions_count = armada_37xx_pmx_get_funcs_count,
492 .get_function_name = armada_37xx_pmx_get_func_name,
493 .get_function_groups = armada_37xx_pmx_get_groups,
494 .set_mux = armada_37xx_pmx_set,
495 .gpio_request_enable = armada_37xx_gpio_request_enable,
496 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
497 };
498
499 static const struct gpio_chip armada_37xx_gpiolib_chip = {
500 .request = gpiochip_generic_request,
501 .free = gpiochip_generic_free,
502 .set = armada_37xx_gpio_set,
503 .get = armada_37xx_gpio_get,
504 .get_direction = armada_37xx_gpio_get_direction,
505 .direction_input = armada_37xx_gpio_direction_input,
506 .direction_output = armada_37xx_gpio_direction_output,
507 .owner = THIS_MODULE,
508 };
509
510 static void armada_37xx_irq_ack(struct irq_data *d)
511 {
512 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
513 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
514 u32 reg = IRQ_STATUS;
515 unsigned long flags;
516
517 armada_37xx_irq_update_reg(&reg, d);
518 spin_lock_irqsave(&info->irq_lock, flags);
519 writel(d->mask, info->base + reg);
520 spin_unlock_irqrestore(&info->irq_lock, flags);
521 }
522
523 static void armada_37xx_irq_mask(struct irq_data *d)
524 {
525 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
526 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
527 u32 val, reg = IRQ_EN;
528 unsigned long flags;
529
530 armada_37xx_irq_update_reg(&reg, d);
531 spin_lock_irqsave(&info->irq_lock, flags);
532 val = readl(info->base + reg);
533 writel(val & ~d->mask, info->base + reg);
534 spin_unlock_irqrestore(&info->irq_lock, flags);
535 }
536
537 static void armada_37xx_irq_unmask(struct irq_data *d)
538 {
539 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
540 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
541 u32 val, reg = IRQ_EN;
542 unsigned long flags;
543
544 armada_37xx_irq_update_reg(&reg, d);
545 spin_lock_irqsave(&info->irq_lock, flags);
546 val = readl(info->base + reg);
547 writel(val | d->mask, info->base + reg);
548 spin_unlock_irqrestore(&info->irq_lock, flags);
549 }
550
551 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
552 {
553 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
554 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
555 u32 val, reg = IRQ_WKUP;
556 unsigned long flags;
557
558 armada_37xx_irq_update_reg(&reg, d);
559 spin_lock_irqsave(&info->irq_lock, flags);
560 val = readl(info->base + reg);
561 if (on)
562 val |= (BIT(d->hwirq % GPIO_PER_REG));
563 else
564 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
565 writel(val, info->base + reg);
566 spin_unlock_irqrestore(&info->irq_lock, flags);
567
568 return 0;
569 }
570
571 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
572 {
573 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
574 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
575 u32 val, reg = IRQ_POL;
576 unsigned long flags;
577
578 spin_lock_irqsave(&info->irq_lock, flags);
579 armada_37xx_irq_update_reg(&reg, d);
580 val = readl(info->base + reg);
581 switch (type) {
582 case IRQ_TYPE_EDGE_RISING:
583 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
584 break;
585 case IRQ_TYPE_EDGE_FALLING:
586 val |= (BIT(d->hwirq % GPIO_PER_REG));
587 break;
588 case IRQ_TYPE_EDGE_BOTH: {
589 u32 in_val, in_reg = INPUT_VAL;
590
591 armada_37xx_irq_update_reg(&in_reg, d);
592 regmap_read(info->regmap, in_reg, &in_val);
593
594 /* Set initial polarity based on current input level. */
595 if (in_val & d->mask)
596 val |= d->mask; /* falling */
597 else
598 val &= ~d->mask; /* rising */
599 break;
600 }
601 default:
602 spin_unlock_irqrestore(&info->irq_lock, flags);
603 return -EINVAL;
604 }
605 writel(val, info->base + reg);
606 spin_unlock_irqrestore(&info->irq_lock, flags);
607
608 return 0;
609 }
610
611 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
612 u32 pin_idx)
613 {
614 u32 reg_idx = pin_idx / GPIO_PER_REG;
615 u32 bit_num = pin_idx % GPIO_PER_REG;
616 u32 p, l, ret;
617 unsigned long flags;
618
619 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
620
621 spin_lock_irqsave(&info->irq_lock, flags);
622 p = readl(info->base + IRQ_POL + 4 * reg_idx);
623 if ((p ^ l) & (1 << bit_num)) {
624 /*
625 * For the gpios which are used for both-edge irqs, when their
626 * interrupts happen, their input levels are changed,
627 * yet their interrupt polarities are kept in old values, we
628 * should synchronize their interrupt polarities; for example,
629 * at first a gpio's input level is low and its interrupt
630 * polarity control is "Detect rising edge", then the gpio has
631 * a interrupt , its level turns to high, we should change its
632 * polarity control to "Detect falling edge" correspondingly.
633 */
634 p ^= 1 << bit_num;
635 writel(p, info->base + IRQ_POL + 4 * reg_idx);
636 ret = 0;
637 } else {
638 /* Spurious irq */
639 ret = -1;
640 }
641
642 spin_unlock_irqrestore(&info->irq_lock, flags);
643 return ret;
644 }
645
646 static void armada_37xx_irq_handler(struct irq_desc *desc)
647 {
648 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
649 struct irq_chip *chip = irq_desc_get_chip(desc);
650 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
651 struct irq_domain *d = gc->irq.domain;
652 int i;
653
654 chained_irq_enter(chip, desc);
655 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
656 u32 status;
657 unsigned long flags;
658
659 spin_lock_irqsave(&info->irq_lock, flags);
660 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
661 /* Manage only the interrupt that was enabled */
662 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
663 spin_unlock_irqrestore(&info->irq_lock, flags);
664 while (status) {
665 u32 hwirq = ffs(status) - 1;
666 u32 virq = irq_find_mapping(d, hwirq +
667 i * GPIO_PER_REG);
668 u32 t = irq_get_trigger_type(virq);
669
670 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
671 /* Swap polarity (race with GPIO line) */
672 if (armada_37xx_edge_both_irq_swap_pol(info,
673 hwirq + i * GPIO_PER_REG)) {
674 /*
675 * For spurious irq, which gpio level
676 * is not as expected after incoming
677 * edge, just ack the gpio irq.
678 */
679 writel(1 << hwirq,
680 info->base +
681 IRQ_STATUS + 4 * i);
682 goto update_status;
683 }
684 }
685
686 generic_handle_irq(virq);
687
688 update_status:
689 /* Update status in case a new IRQ appears */
690 spin_lock_irqsave(&info->irq_lock, flags);
691 status = readl_relaxed(info->base +
692 IRQ_STATUS + 4 * i);
693 /* Manage only the interrupt that was enabled */
694 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
695 spin_unlock_irqrestore(&info->irq_lock, flags);
696 }
697 }
698 chained_irq_exit(chip, desc);
699 }
700
701 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
702 {
703 /*
704 * The mask field is a "precomputed bitmask for accessing the
705 * chip registers" which was introduced for the generic
706 * irqchip framework. As we don't use this framework, we can
707 * reuse this field for our own usage.
708 */
709 d->mask = BIT(d->hwirq % GPIO_PER_REG);
710
711 armada_37xx_irq_unmask(d);
712
713 return 0;
714 }
715
716 static int armada_37xx_irqchip_register(struct platform_device *pdev,
717 struct armada_37xx_pinctrl *info)
718 {
719 struct device_node *np = info->dev->of_node;
720 struct gpio_chip *gc = &info->gpio_chip;
721 struct irq_chip *irqchip = &info->irq_chip;
722 struct resource res;
723 int ret = -ENODEV, i, nr_irq_parent;
724
725 /* Check if we have at least one gpio-controller child node */
726 for_each_child_of_node(info->dev->of_node, np) {
727 if (of_property_read_bool(np, "gpio-controller")) {
728 ret = 0;
729 break;
730 }
731 };
732 if (ret)
733 return ret;
734
735 nr_irq_parent = of_irq_count(np);
736 spin_lock_init(&info->irq_lock);
737
738 if (!nr_irq_parent) {
739 dev_err(&pdev->dev, "Invalid or no IRQ\n");
740 return 0;
741 }
742
743 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
744 dev_err(info->dev, "cannot find IO resource\n");
745 return -ENOENT;
746 }
747
748 info->base = devm_ioremap_resource(info->dev, &res);
749 if (IS_ERR(info->base))
750 return PTR_ERR(info->base);
751
752 irqchip->irq_ack = armada_37xx_irq_ack;
753 irqchip->irq_mask = armada_37xx_irq_mask;
754 irqchip->irq_unmask = armada_37xx_irq_unmask;
755 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
756 irqchip->irq_set_type = armada_37xx_irq_set_type;
757 irqchip->irq_startup = armada_37xx_irq_startup;
758 irqchip->name = info->data->name;
759 ret = gpiochip_irqchip_add(gc, irqchip, 0,
760 handle_edge_irq, IRQ_TYPE_NONE);
761 if (ret) {
762 dev_info(&pdev->dev, "could not add irqchip\n");
763 return ret;
764 }
765
766 /*
767 * Many interrupts are connected to the parent interrupt
768 * controller. But we do not take advantage of this and use
769 * the chained irq with all of them.
770 */
771 for (i = 0; i < nr_irq_parent; i++) {
772 int irq = irq_of_parse_and_map(np, i);
773
774 if (irq < 0)
775 continue;
776
777 gpiochip_set_chained_irqchip(gc, irqchip, irq,
778 armada_37xx_irq_handler);
779 }
780
781 return 0;
782 }
783
784 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
785 struct armada_37xx_pinctrl *info)
786 {
787 struct device_node *np;
788 struct gpio_chip *gc;
789 int ret = -ENODEV;
790
791 for_each_child_of_node(info->dev->of_node, np) {
792 if (of_find_property(np, "gpio-controller", NULL)) {
793 ret = 0;
794 break;
795 }
796 };
797 if (ret)
798 return ret;
799
800 info->gpio_chip = armada_37xx_gpiolib_chip;
801
802 gc = &info->gpio_chip;
803 gc->ngpio = info->data->nr_pins;
804 gc->parent = &pdev->dev;
805 gc->base = -1;
806 gc->of_node = np;
807 gc->label = info->data->name;
808
809 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
810 if (ret)
811 return ret;
812 ret = armada_37xx_irqchip_register(pdev, info);
813 if (ret)
814 return ret;
815
816 return 0;
817 }
818
819 /**
820 * armada_37xx_add_function() - Add a new function to the list
821 * @funcs: array of function to add the new one
822 * @funcsize: size of the remaining space for the function
823 * @name: name of the function to add
824 *
825 * If it is a new function then create it by adding its name else
826 * increment the number of group associated to this function.
827 */
828 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
829 int *funcsize, const char *name)
830 {
831 int i = 0;
832
833 if (*funcsize <= 0)
834 return -EOVERFLOW;
835
836 while (funcs->ngroups) {
837 /* function already there */
838 if (strcmp(funcs->name, name) == 0) {
839 funcs->ngroups++;
840
841 return -EEXIST;
842 }
843 funcs++;
844 i++;
845 }
846
847 /* append new unique function */
848 funcs->name = name;
849 funcs->ngroups = 1;
850 (*funcsize)--;
851
852 return 0;
853 }
854
855 /**
856 * armada_37xx_fill_group() - complete the group array
857 * @info: info driver instance
858 *
859 * Based on the data available from the armada_37xx_pin_group array
860 * completes the last member of the struct for each function: the list
861 * of the groups associated to this function.
862 *
863 */
864 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
865 {
866 int n, num = 0, funcsize = info->data->nr_pins;
867
868 for (n = 0; n < info->ngroups; n++) {
869 struct armada_37xx_pin_group *grp = &info->groups[n];
870 int i, j, f;
871
872 grp->pins = devm_kcalloc(info->dev,
873 grp->npins + grp->extra_npins,
874 sizeof(*grp->pins),
875 GFP_KERNEL);
876 if (!grp->pins)
877 return -ENOMEM;
878
879 for (i = 0; i < grp->npins; i++)
880 grp->pins[i] = grp->start_pin + i;
881
882 for (j = 0; j < grp->extra_npins; j++)
883 grp->pins[i+j] = grp->extra_pin + j;
884
885 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
886 int ret;
887 /* check for unique functions and count groups */
888 ret = armada_37xx_add_function(info->funcs, &funcsize,
889 grp->funcs[f]);
890 if (ret == -EOVERFLOW)
891 dev_err(info->dev,
892 "More functions than pins(%d)\n",
893 info->data->nr_pins);
894 if (ret < 0)
895 continue;
896 num++;
897 }
898 }
899
900 info->nfuncs = num;
901
902 return 0;
903 }
904
905 /**
906 * armada_37xx_fill_funcs() - complete the funcs array
907 * @info: info driver instance
908 *
909 * Based on the data available from the armada_37xx_pin_group array
910 * completes the last two member of the struct for each group:
911 * - the list of the pins included in the group
912 * - the list of pinmux functions that can be selected for this group
913 *
914 */
915 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
916 {
917 struct armada_37xx_pmx_func *funcs = info->funcs;
918 int n;
919
920 for (n = 0; n < info->nfuncs; n++) {
921 const char *name = funcs[n].name;
922 const char **groups;
923 int g;
924
925 funcs[n].groups = devm_kcalloc(info->dev,
926 funcs[n].ngroups,
927 sizeof(*(funcs[n].groups)),
928 GFP_KERNEL);
929 if (!funcs[n].groups)
930 return -ENOMEM;
931
932 groups = funcs[n].groups;
933
934 for (g = 0; g < info->ngroups; g++) {
935 struct armada_37xx_pin_group *gp = &info->groups[g];
936 int f;
937
938 f = match_string(gp->funcs, NB_FUNCS, name);
939 if (f < 0)
940 continue;
941
942 *groups = gp->name;
943 groups++;
944 }
945 }
946 return 0;
947 }
948
949 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
950 struct armada_37xx_pinctrl *info)
951 {
952 const struct armada_37xx_pin_data *pin_data = info->data;
953 struct pinctrl_desc *ctrldesc = &info->pctl;
954 struct pinctrl_pin_desc *pindesc, *pdesc;
955 int pin, ret;
956
957 info->groups = pin_data->groups;
958 info->ngroups = pin_data->ngroups;
959
960 ctrldesc->name = "armada_37xx-pinctrl";
961 ctrldesc->owner = THIS_MODULE;
962 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
963 ctrldesc->pmxops = &armada_37xx_pmx_ops;
964 ctrldesc->confops = &armada_37xx_pinconf_ops;
965
966 pindesc = devm_kcalloc(&pdev->dev,
967 pin_data->nr_pins, sizeof(*pindesc),
968 GFP_KERNEL);
969 if (!pindesc)
970 return -ENOMEM;
971
972 ctrldesc->pins = pindesc;
973 ctrldesc->npins = pin_data->nr_pins;
974
975 pdesc = pindesc;
976 for (pin = 0; pin < pin_data->nr_pins; pin++) {
977 pdesc->number = pin;
978 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
979 pin_data->name, pin);
980 pdesc++;
981 }
982
983 /*
984 * we allocate functions for number of pins and hope there are
985 * fewer unique functions than pins available
986 */
987 info->funcs = devm_kcalloc(&pdev->dev,
988 pin_data->nr_pins,
989 sizeof(struct armada_37xx_pmx_func),
990 GFP_KERNEL);
991 if (!info->funcs)
992 return -ENOMEM;
993
994
995 ret = armada_37xx_fill_group(info);
996 if (ret)
997 return ret;
998
999 ret = armada_37xx_fill_func(info);
1000 if (ret)
1001 return ret;
1002
1003 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1004 if (IS_ERR(info->pctl_dev)) {
1005 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1006 return PTR_ERR(info->pctl_dev);
1007 }
1008
1009 return 0;
1010 }
1011
1012 #if defined(CONFIG_PM)
1013 static int armada_3700_pinctrl_suspend(struct device *dev)
1014 {
1015 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1016
1017 /* Save GPIO state */
1018 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1019 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1020 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1021 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1022 &info->pm.out_val_h);
1023
1024 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1025 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1026 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1027 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1028
1029 /* Save pinctrl state */
1030 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1031
1032 return 0;
1033 }
1034
1035 static int armada_3700_pinctrl_resume(struct device *dev)
1036 {
1037 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1038 struct gpio_chip *gc;
1039 struct irq_domain *d;
1040 int i;
1041
1042 /* Restore GPIO state */
1043 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1044 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1045 info->pm.out_en_h);
1046 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1047 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1048 info->pm.out_val_h);
1049
1050 /*
1051 * Input levels may change during suspend, which is not monitored at
1052 * that time. GPIOs used for both-edge IRQs may not be synchronized
1053 * anymore with their polarities (rising/falling edge) and must be
1054 * re-configured manually.
1055 */
1056 gc = &info->gpio_chip;
1057 d = gc->irq.domain;
1058 for (i = 0; i < gc->ngpio; i++) {
1059 u32 irq_bit = BIT(i % GPIO_PER_REG);
1060 u32 mask, *irq_pol, input_reg, virq, type, level;
1061
1062 if (i < GPIO_PER_REG) {
1063 mask = info->pm.irq_en_l;
1064 irq_pol = &info->pm.irq_pol_l;
1065 input_reg = INPUT_VAL;
1066 } else {
1067 mask = info->pm.irq_en_h;
1068 irq_pol = &info->pm.irq_pol_h;
1069 input_reg = INPUT_VAL + sizeof(u32);
1070 }
1071
1072 if (!(mask & irq_bit))
1073 continue;
1074
1075 virq = irq_find_mapping(d, i);
1076 type = irq_get_trigger_type(virq);
1077
1078 /*
1079 * Synchronize level and polarity for both-edge irqs:
1080 * - a high input level expects a falling edge,
1081 * - a low input level exepects a rising edge.
1082 */
1083 if ((type & IRQ_TYPE_SENSE_MASK) ==
1084 IRQ_TYPE_EDGE_BOTH) {
1085 regmap_read(info->regmap, input_reg, &level);
1086 if ((*irq_pol ^ level) & irq_bit)
1087 *irq_pol ^= irq_bit;
1088 }
1089 }
1090
1091 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1092 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1093 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1094 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1095
1096 /* Restore pinctrl state */
1097 regmap_write(info->regmap, SELECTION, info->pm.selection);
1098
1099 return 0;
1100 }
1101
1102 /*
1103 * Since pinctrl is an infrastructure module, its resume should be issued prior
1104 * to other IO drivers.
1105 */
1106 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1107 .suspend_late = armada_3700_pinctrl_suspend,
1108 .resume_early = armada_3700_pinctrl_resume,
1109 };
1110
1111 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1112 #else
1113 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1114 #endif /* CONFIG_PM */
1115
1116 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1117 {
1118 .compatible = "marvell,armada3710-sb-pinctrl",
1119 .data = &armada_37xx_pin_sb,
1120 },
1121 {
1122 .compatible = "marvell,armada3710-nb-pinctrl",
1123 .data = &armada_37xx_pin_nb,
1124 },
1125 { },
1126 };
1127
1128 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1129 {
1130 struct armada_37xx_pinctrl *info;
1131 struct device *dev = &pdev->dev;
1132 struct device_node *np = dev->of_node;
1133 struct regmap *regmap;
1134 int ret;
1135
1136 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1137 GFP_KERNEL);
1138 if (!info)
1139 return -ENOMEM;
1140
1141 info->dev = dev;
1142
1143 regmap = syscon_node_to_regmap(np);
1144 if (IS_ERR(regmap)) {
1145 dev_err(&pdev->dev, "cannot get regmap\n");
1146 return PTR_ERR(regmap);
1147 }
1148 info->regmap = regmap;
1149
1150 info->data = of_device_get_match_data(dev);
1151
1152 ret = armada_37xx_pinctrl_register(pdev, info);
1153 if (ret)
1154 return ret;
1155
1156 ret = armada_37xx_gpiochip_register(pdev, info);
1157 if (ret)
1158 return ret;
1159
1160 platform_set_drvdata(pdev, info);
1161
1162 return 0;
1163 }
1164
1165 static struct platform_driver armada_37xx_pinctrl_driver = {
1166 .driver = {
1167 .name = "armada-37xx-pinctrl",
1168 .of_match_table = armada_37xx_pinctrl_of_match,
1169 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1170 },
1171 };
1172
1173 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1174 armada_37xx_pinctrl_probe);
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