2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "../pinctrl-utils.h"
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
37 #define IRQ_STATUS 0x10
41 #define GPIO_PER_REG 32
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
58 struct armada_37xx_pin_group
{
60 unsigned int start_pin
;
64 unsigned int extra_pin
;
65 unsigned int extra_npins
;
66 const char *funcs
[NB_FUNCS
];
70 struct armada_37xx_pin_data
{
73 struct armada_37xx_pin_group
*groups
;
77 struct armada_37xx_pmx_func
{
83 struct armada_37xx_pm_state
{
95 struct armada_37xx_pinctrl
{
96 struct regmap
*regmap
;
98 const struct armada_37xx_pin_data
*data
;
100 struct gpio_chip gpio_chip
;
101 struct irq_chip irq_chip
;
103 struct pinctrl_desc pctl
;
104 struct pinctrl_dev
*pctl_dev
;
105 struct armada_37xx_pin_group
*groups
;
106 unsigned int ngroups
;
107 struct armada_37xx_pmx_func
*funcs
;
109 struct armada_37xx_pm_state pm
;
112 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
115 .start_pin = _start, \
119 .funcs = {_func1, _func2} \
122 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
125 .start_pin = _start, \
129 .funcs = {_func1, "gpio"} \
132 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
135 .start_pin = _start, \
138 .val = {_val1, _val2}, \
139 .funcs = {_func1, "gpio"} \
142 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
145 .start_pin = _start, \
148 .val = {_v1, _v2, _v3}, \
149 .funcs = {_f1, _f2, "gpio"} \
152 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
156 .start_pin = _start, \
160 .extra_pin = _start2, \
161 .extra_npins = _nr2, \
162 .funcs = {_f1, _f2} \
165 static struct armada_37xx_pin_group armada_37xx_nb_groups
[] = {
166 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
167 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
168 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
169 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
170 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
171 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
172 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
173 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
174 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
175 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
176 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
177 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
178 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
179 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
180 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
181 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
182 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
183 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
184 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
185 18, 2, "gpio", "uart"),
186 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
187 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
188 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
189 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
193 static struct armada_37xx_pin_group armada_37xx_sb_groups
[] = {
194 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
195 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
196 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
197 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
198 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
199 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
200 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
201 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
202 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
203 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
204 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
205 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
209 static const struct armada_37xx_pin_data armada_37xx_pin_nb
= {
212 .groups
= armada_37xx_nb_groups
,
213 .ngroups
= ARRAY_SIZE(armada_37xx_nb_groups
),
216 static const struct armada_37xx_pin_data armada_37xx_pin_sb
= {
219 .groups
= armada_37xx_sb_groups
,
220 .ngroups
= ARRAY_SIZE(armada_37xx_sb_groups
),
223 static inline void armada_37xx_update_reg(unsigned int *reg
,
226 /* We never have more than 2 registers */
227 if (offset
>= GPIO_PER_REG
) {
228 offset
-= GPIO_PER_REG
;
233 static struct armada_37xx_pin_group
*armada_37xx_find_next_grp_by_pin(
234 struct armada_37xx_pinctrl
*info
, int pin
, int *grp
)
236 while (*grp
< info
->ngroups
) {
237 struct armada_37xx_pin_group
*group
= &info
->groups
[*grp
];
241 for (j
= 0; j
< (group
->npins
+ group
->extra_npins
); j
++)
242 if (group
->pins
[j
] == pin
)
248 static int armada_37xx_pin_config_group_get(struct pinctrl_dev
*pctldev
,
249 unsigned int selector
, unsigned long *config
)
254 static int armada_37xx_pin_config_group_set(struct pinctrl_dev
*pctldev
,
255 unsigned int selector
, unsigned long *configs
,
256 unsigned int num_configs
)
261 static const struct pinconf_ops armada_37xx_pinconf_ops
= {
263 .pin_config_group_get
= armada_37xx_pin_config_group_get
,
264 .pin_config_group_set
= armada_37xx_pin_config_group_set
,
267 static int armada_37xx_get_groups_count(struct pinctrl_dev
*pctldev
)
269 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
271 return info
->ngroups
;
274 static const char *armada_37xx_get_group_name(struct pinctrl_dev
*pctldev
,
277 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
279 return info
->groups
[group
].name
;
282 static int armada_37xx_get_group_pins(struct pinctrl_dev
*pctldev
,
283 unsigned int selector
,
284 const unsigned int **pins
,
287 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
289 if (selector
>= info
->ngroups
)
292 *pins
= info
->groups
[selector
].pins
;
293 *npins
= info
->groups
[selector
].npins
+
294 info
->groups
[selector
].extra_npins
;
299 static const struct pinctrl_ops armada_37xx_pctrl_ops
= {
300 .get_groups_count
= armada_37xx_get_groups_count
,
301 .get_group_name
= armada_37xx_get_group_name
,
302 .get_group_pins
= armada_37xx_get_group_pins
,
303 .dt_node_to_map
= pinconf_generic_dt_node_to_map_group
,
304 .dt_free_map
= pinctrl_utils_free_map
,
308 * Pinmux_ops handling
311 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev
*pctldev
)
313 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
318 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
319 unsigned int selector
)
321 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
323 return info
->funcs
[selector
].name
;
326 static int armada_37xx_pmx_get_groups(struct pinctrl_dev
*pctldev
,
327 unsigned int selector
,
328 const char * const **groups
,
329 unsigned int * const num_groups
)
331 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
333 *groups
= info
->funcs
[selector
].groups
;
334 *num_groups
= info
->funcs
[selector
].ngroups
;
339 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev
*pctldev
,
341 struct armada_37xx_pin_group
*grp
)
343 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
344 unsigned int reg
= SELECTION
;
345 unsigned int mask
= grp
->reg_mask
;
348 dev_dbg(info
->dev
, "enable function %s group %s\n",
351 func
= match_string(grp
->funcs
, NB_FUNCS
, name
);
355 val
= grp
->val
[func
];
357 regmap_update_bits(info
->regmap
, reg
, mask
, val
);
362 static int armada_37xx_pmx_set(struct pinctrl_dev
*pctldev
,
363 unsigned int selector
,
367 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
368 struct armada_37xx_pin_group
*grp
= &info
->groups
[group
];
369 const char *name
= info
->funcs
[selector
].name
;
371 return armada_37xx_pmx_set_by_name(pctldev
, name
, grp
);
374 static inline void armada_37xx_irq_update_reg(unsigned int *reg
,
377 int offset
= irqd_to_hwirq(d
);
379 armada_37xx_update_reg(reg
, offset
);
382 static int armada_37xx_gpio_direction_input(struct gpio_chip
*chip
,
385 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
386 unsigned int reg
= OUTPUT_EN
;
389 armada_37xx_update_reg(®
, offset
);
392 return regmap_update_bits(info
->regmap
, reg
, mask
, 0);
395 static int armada_37xx_gpio_get_direction(struct gpio_chip
*chip
,
398 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
399 unsigned int reg
= OUTPUT_EN
;
400 unsigned int val
, mask
;
402 armada_37xx_update_reg(®
, offset
);
404 regmap_read(info
->regmap
, reg
, &val
);
406 return !(val
& mask
);
409 static int armada_37xx_gpio_direction_output(struct gpio_chip
*chip
,
410 unsigned int offset
, int value
)
412 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
413 unsigned int reg
= OUTPUT_EN
;
414 unsigned int mask
, val
, ret
;
416 armada_37xx_update_reg(®
, offset
);
419 ret
= regmap_update_bits(info
->regmap
, reg
, mask
, mask
);
425 val
= value
? mask
: 0;
426 regmap_update_bits(info
->regmap
, reg
, mask
, val
);
431 static int armada_37xx_gpio_get(struct gpio_chip
*chip
, unsigned int offset
)
433 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
434 unsigned int reg
= INPUT_VAL
;
435 unsigned int val
, mask
;
437 armada_37xx_update_reg(®
, offset
);
440 regmap_read(info
->regmap
, reg
, &val
);
442 return (val
& mask
) != 0;
445 static void armada_37xx_gpio_set(struct gpio_chip
*chip
, unsigned int offset
,
448 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
449 unsigned int reg
= OUTPUT_VAL
;
450 unsigned int mask
, val
;
452 armada_37xx_update_reg(®
, offset
);
454 val
= value
? mask
: 0;
456 regmap_update_bits(info
->regmap
, reg
, mask
, val
);
459 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev
,
460 struct pinctrl_gpio_range
*range
,
461 unsigned int offset
, bool input
)
463 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
464 struct gpio_chip
*chip
= range
->gc
;
466 dev_dbg(info
->dev
, "gpio_direction for pin %u as %s-%d to %s\n",
467 offset
, range
->name
, offset
, input
? "input" : "output");
470 armada_37xx_gpio_direction_input(chip
, offset
);
472 armada_37xx_gpio_direction_output(chip
, offset
, 0);
477 static int armada_37xx_gpio_request_enable(struct pinctrl_dev
*pctldev
,
478 struct pinctrl_gpio_range
*range
,
481 struct armada_37xx_pinctrl
*info
= pinctrl_dev_get_drvdata(pctldev
);
482 struct armada_37xx_pin_group
*group
;
485 dev_dbg(info
->dev
, "requesting gpio %d\n", offset
);
487 while ((group
= armada_37xx_find_next_grp_by_pin(info
, offset
, &grp
)))
488 armada_37xx_pmx_set_by_name(pctldev
, "gpio", group
);
493 static const struct pinmux_ops armada_37xx_pmx_ops
= {
494 .get_functions_count
= armada_37xx_pmx_get_funcs_count
,
495 .get_function_name
= armada_37xx_pmx_get_func_name
,
496 .get_function_groups
= armada_37xx_pmx_get_groups
,
497 .set_mux
= armada_37xx_pmx_set
,
498 .gpio_request_enable
= armada_37xx_gpio_request_enable
,
499 .gpio_set_direction
= armada_37xx_pmx_gpio_set_direction
,
502 static const struct gpio_chip armada_37xx_gpiolib_chip
= {
503 .request
= gpiochip_generic_request
,
504 .free
= gpiochip_generic_free
,
505 .set
= armada_37xx_gpio_set
,
506 .get
= armada_37xx_gpio_get
,
507 .get_direction
= armada_37xx_gpio_get_direction
,
508 .direction_input
= armada_37xx_gpio_direction_input
,
509 .direction_output
= armada_37xx_gpio_direction_output
,
510 .owner
= THIS_MODULE
,
513 static void armada_37xx_irq_ack(struct irq_data
*d
)
515 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
516 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
517 u32 reg
= IRQ_STATUS
;
520 armada_37xx_irq_update_reg(®
, d
);
521 spin_lock_irqsave(&info
->irq_lock
, flags
);
522 writel(d
->mask
, info
->base
+ reg
);
523 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
526 static void armada_37xx_irq_mask(struct irq_data
*d
)
528 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
529 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
530 u32 val
, reg
= IRQ_EN
;
533 armada_37xx_irq_update_reg(®
, d
);
534 spin_lock_irqsave(&info
->irq_lock
, flags
);
535 val
= readl(info
->base
+ reg
);
536 writel(val
& ~d
->mask
, info
->base
+ reg
);
537 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
540 static void armada_37xx_irq_unmask(struct irq_data
*d
)
542 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
543 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
544 u32 val
, reg
= IRQ_EN
;
547 armada_37xx_irq_update_reg(®
, d
);
548 spin_lock_irqsave(&info
->irq_lock
, flags
);
549 val
= readl(info
->base
+ reg
);
550 writel(val
| d
->mask
, info
->base
+ reg
);
551 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
554 static int armada_37xx_irq_set_wake(struct irq_data
*d
, unsigned int on
)
556 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
557 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
558 u32 val
, reg
= IRQ_WKUP
;
561 armada_37xx_irq_update_reg(®
, d
);
562 spin_lock_irqsave(&info
->irq_lock
, flags
);
563 val
= readl(info
->base
+ reg
);
565 val
|= (BIT(d
->hwirq
% GPIO_PER_REG
));
567 val
&= ~(BIT(d
->hwirq
% GPIO_PER_REG
));
568 writel(val
, info
->base
+ reg
);
569 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
574 static int armada_37xx_irq_set_type(struct irq_data
*d
, unsigned int type
)
576 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
577 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(chip
);
578 u32 val
, reg
= IRQ_POL
;
581 spin_lock_irqsave(&info
->irq_lock
, flags
);
582 armada_37xx_irq_update_reg(®
, d
);
583 val
= readl(info
->base
+ reg
);
585 case IRQ_TYPE_EDGE_RISING
:
586 val
&= ~(BIT(d
->hwirq
% GPIO_PER_REG
));
588 case IRQ_TYPE_EDGE_FALLING
:
589 val
|= (BIT(d
->hwirq
% GPIO_PER_REG
));
591 case IRQ_TYPE_EDGE_BOTH
: {
592 u32 in_val
, in_reg
= INPUT_VAL
;
594 armada_37xx_irq_update_reg(&in_reg
, d
);
595 regmap_read(info
->regmap
, in_reg
, &in_val
);
597 /* Set initial polarity based on current input level. */
598 if (in_val
& d
->mask
)
599 val
|= d
->mask
; /* falling */
601 val
&= ~d
->mask
; /* rising */
605 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
608 writel(val
, info
->base
+ reg
);
609 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
614 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl
*info
,
617 u32 reg_idx
= pin_idx
/ GPIO_PER_REG
;
618 u32 bit_num
= pin_idx
% GPIO_PER_REG
;
622 regmap_read(info
->regmap
, INPUT_VAL
+ 4*reg_idx
, &l
);
624 spin_lock_irqsave(&info
->irq_lock
, flags
);
625 p
= readl(info
->base
+ IRQ_POL
+ 4 * reg_idx
);
626 if ((p
^ l
) & (1 << bit_num
)) {
628 * For the gpios which are used for both-edge irqs, when their
629 * interrupts happen, their input levels are changed,
630 * yet their interrupt polarities are kept in old values, we
631 * should synchronize their interrupt polarities; for example,
632 * at first a gpio's input level is low and its interrupt
633 * polarity control is "Detect rising edge", then the gpio has
634 * a interrupt , its level turns to high, we should change its
635 * polarity control to "Detect falling edge" correspondingly.
638 writel(p
, info
->base
+ IRQ_POL
+ 4 * reg_idx
);
645 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
649 static void armada_37xx_irq_handler(struct irq_desc
*desc
)
651 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
652 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
653 struct armada_37xx_pinctrl
*info
= gpiochip_get_data(gc
);
654 struct irq_domain
*d
= gc
->irq
.domain
;
657 chained_irq_enter(chip
, desc
);
658 for (i
= 0; i
<= d
->revmap_size
/ GPIO_PER_REG
; i
++) {
662 spin_lock_irqsave(&info
->irq_lock
, flags
);
663 status
= readl_relaxed(info
->base
+ IRQ_STATUS
+ 4 * i
);
664 /* Manage only the interrupt that was enabled */
665 status
&= readl_relaxed(info
->base
+ IRQ_EN
+ 4 * i
);
666 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
668 u32 hwirq
= ffs(status
) - 1;
669 u32 virq
= irq_find_mapping(d
, hwirq
+
671 u32 t
= irq_get_trigger_type(virq
);
673 if ((t
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
) {
674 /* Swap polarity (race with GPIO line) */
675 if (armada_37xx_edge_both_irq_swap_pol(info
,
676 hwirq
+ i
* GPIO_PER_REG
)) {
678 * For spurious irq, which gpio level
679 * is not as expected after incoming
680 * edge, just ack the gpio irq.
689 generic_handle_irq(virq
);
692 /* Update status in case a new IRQ appears */
693 spin_lock_irqsave(&info
->irq_lock
, flags
);
694 status
= readl_relaxed(info
->base
+
696 /* Manage only the interrupt that was enabled */
697 status
&= readl_relaxed(info
->base
+ IRQ_EN
+ 4 * i
);
698 spin_unlock_irqrestore(&info
->irq_lock
, flags
);
701 chained_irq_exit(chip
, desc
);
704 static unsigned int armada_37xx_irq_startup(struct irq_data
*d
)
707 * The mask field is a "precomputed bitmask for accessing the
708 * chip registers" which was introduced for the generic
709 * irqchip framework. As we don't use this framework, we can
710 * reuse this field for our own usage.
712 d
->mask
= BIT(d
->hwirq
% GPIO_PER_REG
);
714 armada_37xx_irq_unmask(d
);
719 static int armada_37xx_irqchip_register(struct platform_device
*pdev
,
720 struct armada_37xx_pinctrl
*info
)
722 struct device_node
*np
= info
->dev
->of_node
;
723 struct gpio_chip
*gc
= &info
->gpio_chip
;
724 struct irq_chip
*irqchip
= &info
->irq_chip
;
726 int ret
= -ENODEV
, i
, nr_irq_parent
;
728 /* Check if we have at least one gpio-controller child node */
729 for_each_child_of_node(info
->dev
->of_node
, np
) {
730 if (of_property_read_bool(np
, "gpio-controller")) {
738 nr_irq_parent
= of_irq_count(np
);
739 spin_lock_init(&info
->irq_lock
);
741 if (!nr_irq_parent
) {
742 dev_err(&pdev
->dev
, "Invalid or no IRQ\n");
746 if (of_address_to_resource(info
->dev
->of_node
, 1, &res
)) {
747 dev_err(info
->dev
, "cannot find IO resource\n");
751 info
->base
= devm_ioremap_resource(info
->dev
, &res
);
752 if (IS_ERR(info
->base
))
753 return PTR_ERR(info
->base
);
755 irqchip
->irq_ack
= armada_37xx_irq_ack
;
756 irqchip
->irq_mask
= armada_37xx_irq_mask
;
757 irqchip
->irq_unmask
= armada_37xx_irq_unmask
;
758 irqchip
->irq_set_wake
= armada_37xx_irq_set_wake
;
759 irqchip
->irq_set_type
= armada_37xx_irq_set_type
;
760 irqchip
->irq_startup
= armada_37xx_irq_startup
;
761 irqchip
->name
= info
->data
->name
;
762 ret
= gpiochip_irqchip_add(gc
, irqchip
, 0,
763 handle_edge_irq
, IRQ_TYPE_NONE
);
765 dev_info(&pdev
->dev
, "could not add irqchip\n");
770 * Many interrupts are connected to the parent interrupt
771 * controller. But we do not take advantage of this and use
772 * the chained irq with all of them.
774 for (i
= 0; i
< nr_irq_parent
; i
++) {
775 int irq
= irq_of_parse_and_map(np
, i
);
780 gpiochip_set_chained_irqchip(gc
, irqchip
, irq
,
781 armada_37xx_irq_handler
);
787 static int armada_37xx_gpiochip_register(struct platform_device
*pdev
,
788 struct armada_37xx_pinctrl
*info
)
790 struct device_node
*np
;
791 struct gpio_chip
*gc
;
794 for_each_child_of_node(info
->dev
->of_node
, np
) {
795 if (of_find_property(np
, "gpio-controller", NULL
)) {
803 info
->gpio_chip
= armada_37xx_gpiolib_chip
;
805 gc
= &info
->gpio_chip
;
806 gc
->ngpio
= info
->data
->nr_pins
;
807 gc
->parent
= &pdev
->dev
;
810 gc
->label
= info
->data
->name
;
812 ret
= devm_gpiochip_add_data(&pdev
->dev
, gc
, info
);
815 ret
= armada_37xx_irqchip_register(pdev
, info
);
823 * armada_37xx_add_function() - Add a new function to the list
824 * @funcs: array of function to add the new one
825 * @funcsize: size of the remaining space for the function
826 * @name: name of the function to add
828 * If it is a new function then create it by adding its name else
829 * increment the number of group associated to this function.
831 static int armada_37xx_add_function(struct armada_37xx_pmx_func
*funcs
,
832 int *funcsize
, const char *name
)
839 while (funcs
->ngroups
) {
840 /* function already there */
841 if (strcmp(funcs
->name
, name
) == 0) {
850 /* append new unique function */
859 * armada_37xx_fill_group() - complete the group array
860 * @info: info driver instance
862 * Based on the data available from the armada_37xx_pin_group array
863 * completes the last member of the struct for each function: the list
864 * of the groups associated to this function.
867 static int armada_37xx_fill_group(struct armada_37xx_pinctrl
*info
)
869 int n
, num
= 0, funcsize
= info
->data
->nr_pins
;
871 for (n
= 0; n
< info
->ngroups
; n
++) {
872 struct armada_37xx_pin_group
*grp
= &info
->groups
[n
];
875 grp
->pins
= devm_kcalloc(info
->dev
,
876 grp
->npins
+ grp
->extra_npins
,
882 for (i
= 0; i
< grp
->npins
; i
++)
883 grp
->pins
[i
] = grp
->start_pin
+ i
;
885 for (j
= 0; j
< grp
->extra_npins
; j
++)
886 grp
->pins
[i
+j
] = grp
->extra_pin
+ j
;
888 for (f
= 0; (f
< NB_FUNCS
) && grp
->funcs
[f
]; f
++) {
890 /* check for unique functions and count groups */
891 ret
= armada_37xx_add_function(info
->funcs
, &funcsize
,
893 if (ret
== -EOVERFLOW
)
895 "More functions than pins(%d)\n",
896 info
->data
->nr_pins
);
909 * armada_37xx_fill_funcs() - complete the funcs array
910 * @info: info driver instance
912 * Based on the data available from the armada_37xx_pin_group array
913 * completes the last two member of the struct for each group:
914 * - the list of the pins included in the group
915 * - the list of pinmux functions that can be selected for this group
918 static int armada_37xx_fill_func(struct armada_37xx_pinctrl
*info
)
920 struct armada_37xx_pmx_func
*funcs
= info
->funcs
;
923 for (n
= 0; n
< info
->nfuncs
; n
++) {
924 const char *name
= funcs
[n
].name
;
928 funcs
[n
].groups
= devm_kcalloc(info
->dev
,
930 sizeof(*(funcs
[n
].groups
)),
932 if (!funcs
[n
].groups
)
935 groups
= funcs
[n
].groups
;
937 for (g
= 0; g
< info
->ngroups
; g
++) {
938 struct armada_37xx_pin_group
*gp
= &info
->groups
[g
];
941 f
= match_string(gp
->funcs
, NB_FUNCS
, name
);
952 static int armada_37xx_pinctrl_register(struct platform_device
*pdev
,
953 struct armada_37xx_pinctrl
*info
)
955 const struct armada_37xx_pin_data
*pin_data
= info
->data
;
956 struct pinctrl_desc
*ctrldesc
= &info
->pctl
;
957 struct pinctrl_pin_desc
*pindesc
, *pdesc
;
960 info
->groups
= pin_data
->groups
;
961 info
->ngroups
= pin_data
->ngroups
;
963 ctrldesc
->name
= "armada_37xx-pinctrl";
964 ctrldesc
->owner
= THIS_MODULE
;
965 ctrldesc
->pctlops
= &armada_37xx_pctrl_ops
;
966 ctrldesc
->pmxops
= &armada_37xx_pmx_ops
;
967 ctrldesc
->confops
= &armada_37xx_pinconf_ops
;
969 pindesc
= devm_kcalloc(&pdev
->dev
,
970 pin_data
->nr_pins
, sizeof(*pindesc
),
975 ctrldesc
->pins
= pindesc
;
976 ctrldesc
->npins
= pin_data
->nr_pins
;
979 for (pin
= 0; pin
< pin_data
->nr_pins
; pin
++) {
981 pdesc
->name
= kasprintf(GFP_KERNEL
, "%s-%d",
982 pin_data
->name
, pin
);
987 * we allocate functions for number of pins and hope there are
988 * fewer unique functions than pins available
990 info
->funcs
= devm_kcalloc(&pdev
->dev
,
992 sizeof(struct armada_37xx_pmx_func
),
998 ret
= armada_37xx_fill_group(info
);
1002 ret
= armada_37xx_fill_func(info
);
1006 info
->pctl_dev
= devm_pinctrl_register(&pdev
->dev
, ctrldesc
, info
);
1007 if (IS_ERR(info
->pctl_dev
)) {
1008 dev_err(&pdev
->dev
, "could not register pinctrl driver\n");
1009 return PTR_ERR(info
->pctl_dev
);
1015 #if defined(CONFIG_PM)
1016 static int armada_3700_pinctrl_suspend(struct device
*dev
)
1018 struct armada_37xx_pinctrl
*info
= dev_get_drvdata(dev
);
1020 /* Save GPIO state */
1021 regmap_read(info
->regmap
, OUTPUT_EN
, &info
->pm
.out_en_l
);
1022 regmap_read(info
->regmap
, OUTPUT_EN
+ sizeof(u32
), &info
->pm
.out_en_h
);
1023 regmap_read(info
->regmap
, OUTPUT_VAL
, &info
->pm
.out_val_l
);
1024 regmap_read(info
->regmap
, OUTPUT_VAL
+ sizeof(u32
),
1025 &info
->pm
.out_val_h
);
1027 info
->pm
.irq_en_l
= readl(info
->base
+ IRQ_EN
);
1028 info
->pm
.irq_en_h
= readl(info
->base
+ IRQ_EN
+ sizeof(u32
));
1029 info
->pm
.irq_pol_l
= readl(info
->base
+ IRQ_POL
);
1030 info
->pm
.irq_pol_h
= readl(info
->base
+ IRQ_POL
+ sizeof(u32
));
1032 /* Save pinctrl state */
1033 regmap_read(info
->regmap
, SELECTION
, &info
->pm
.selection
);
1038 static int armada_3700_pinctrl_resume(struct device
*dev
)
1040 struct armada_37xx_pinctrl
*info
= dev_get_drvdata(dev
);
1041 struct gpio_chip
*gc
;
1042 struct irq_domain
*d
;
1045 /* Restore GPIO state */
1046 regmap_write(info
->regmap
, OUTPUT_EN
, info
->pm
.out_en_l
);
1047 regmap_write(info
->regmap
, OUTPUT_EN
+ sizeof(u32
),
1049 regmap_write(info
->regmap
, OUTPUT_VAL
, info
->pm
.out_val_l
);
1050 regmap_write(info
->regmap
, OUTPUT_VAL
+ sizeof(u32
),
1051 info
->pm
.out_val_h
);
1054 * Input levels may change during suspend, which is not monitored at
1055 * that time. GPIOs used for both-edge IRQs may not be synchronized
1056 * anymore with their polarities (rising/falling edge) and must be
1057 * re-configured manually.
1059 gc
= &info
->gpio_chip
;
1061 for (i
= 0; i
< gc
->ngpio
; i
++) {
1062 u32 irq_bit
= BIT(i
% GPIO_PER_REG
);
1063 u32 mask
, *irq_pol
, input_reg
, virq
, type
, level
;
1065 if (i
< GPIO_PER_REG
) {
1066 mask
= info
->pm
.irq_en_l
;
1067 irq_pol
= &info
->pm
.irq_pol_l
;
1068 input_reg
= INPUT_VAL
;
1070 mask
= info
->pm
.irq_en_h
;
1071 irq_pol
= &info
->pm
.irq_pol_h
;
1072 input_reg
= INPUT_VAL
+ sizeof(u32
);
1075 if (!(mask
& irq_bit
))
1078 virq
= irq_find_mapping(d
, i
);
1079 type
= irq_get_trigger_type(virq
);
1082 * Synchronize level and polarity for both-edge irqs:
1083 * - a high input level expects a falling edge,
1084 * - a low input level exepects a rising edge.
1086 if ((type
& IRQ_TYPE_SENSE_MASK
) ==
1087 IRQ_TYPE_EDGE_BOTH
) {
1088 regmap_read(info
->regmap
, input_reg
, &level
);
1089 if ((*irq_pol
^ level
) & irq_bit
)
1090 *irq_pol
^= irq_bit
;
1094 writel(info
->pm
.irq_en_l
, info
->base
+ IRQ_EN
);
1095 writel(info
->pm
.irq_en_h
, info
->base
+ IRQ_EN
+ sizeof(u32
));
1096 writel(info
->pm
.irq_pol_l
, info
->base
+ IRQ_POL
);
1097 writel(info
->pm
.irq_pol_h
, info
->base
+ IRQ_POL
+ sizeof(u32
));
1099 /* Restore pinctrl state */
1100 regmap_write(info
->regmap
, SELECTION
, info
->pm
.selection
);
1106 * Since pinctrl is an infrastructure module, its resume should be issued prior
1107 * to other IO drivers.
1109 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops
= {
1110 .suspend_noirq
= armada_3700_pinctrl_suspend
,
1111 .resume_noirq
= armada_3700_pinctrl_resume
,
1114 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1116 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1117 #endif /* CONFIG_PM */
1119 static const struct of_device_id armada_37xx_pinctrl_of_match
[] = {
1121 .compatible
= "marvell,armada3710-sb-pinctrl",
1122 .data
= &armada_37xx_pin_sb
,
1125 .compatible
= "marvell,armada3710-nb-pinctrl",
1126 .data
= &armada_37xx_pin_nb
,
1131 static int __init
armada_37xx_pinctrl_probe(struct platform_device
*pdev
)
1133 struct armada_37xx_pinctrl
*info
;
1134 struct device
*dev
= &pdev
->dev
;
1135 struct device_node
*np
= dev
->of_node
;
1136 struct regmap
*regmap
;
1139 info
= devm_kzalloc(dev
, sizeof(struct armada_37xx_pinctrl
),
1146 regmap
= syscon_node_to_regmap(np
);
1147 if (IS_ERR(regmap
)) {
1148 dev_err(&pdev
->dev
, "cannot get regmap\n");
1149 return PTR_ERR(regmap
);
1151 info
->regmap
= regmap
;
1153 info
->data
= of_device_get_match_data(dev
);
1155 ret
= armada_37xx_pinctrl_register(pdev
, info
);
1159 ret
= armada_37xx_gpiochip_register(pdev
, info
);
1163 platform_set_drvdata(pdev
, info
);
1168 static struct platform_driver armada_37xx_pinctrl_driver
= {
1170 .name
= "armada-37xx-pinctrl",
1171 .of_match_table
= armada_37xx_pinctrl_of_match
,
1172 .pm
= PINCTRL_ARMADA_37XX_DEV_PM_OPS
,
1176 builtin_platform_driver_probe(armada_37xx_pinctrl_driver
,
1177 armada_37xx_pinctrl_probe
);