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Merge branch 'ib-mvebu-98dx3236' into devel
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / mvebu / pinctrl-armada-xp.c
1 /*
2 * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This file supports the three variants of Armada XP SoCs that are
14 * available: mv78230, mv78260 and mv78460. From a pin muxing
15 * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
16 * both have 67 MPP pins (more GPIOs and address lines for the memory
17 * bus mainly).
18 */
19
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/bitops.h>
30
31 #include "pinctrl-mvebu.h"
32
33 static u32 *mpp_saved_regs;
34
35 enum armada_xp_variant {
36 V_MV78230 = BIT(0),
37 V_MV78260 = BIT(1),
38 V_MV78460 = BIT(2),
39 V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460),
40 V_MV78260_PLUS = (V_MV78260 | V_MV78460),
41 V_98DX3236 = BIT(3),
42 V_98DX3336 = BIT(4),
43 V_98DX4251 = BIT(5),
44 V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251),
45 };
46
47 static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
48 MPP_MODE(0,
49 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
50 MPP_VAR_FUNCTION(0x1, "ge0", "txclkout", V_MV78230_PLUS),
51 MPP_VAR_FUNCTION(0x4, "lcd", "d0", V_MV78230_PLUS)),
52 MPP_MODE(1,
53 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
54 MPP_VAR_FUNCTION(0x1, "ge0", "txd0", V_MV78230_PLUS),
55 MPP_VAR_FUNCTION(0x4, "lcd", "d1", V_MV78230_PLUS)),
56 MPP_MODE(2,
57 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
58 MPP_VAR_FUNCTION(0x1, "ge0", "txd1", V_MV78230_PLUS),
59 MPP_VAR_FUNCTION(0x4, "lcd", "d2", V_MV78230_PLUS)),
60 MPP_MODE(3,
61 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
62 MPP_VAR_FUNCTION(0x1, "ge0", "txd2", V_MV78230_PLUS),
63 MPP_VAR_FUNCTION(0x4, "lcd", "d3", V_MV78230_PLUS)),
64 MPP_MODE(4,
65 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
66 MPP_VAR_FUNCTION(0x1, "ge0", "txd3", V_MV78230_PLUS),
67 MPP_VAR_FUNCTION(0x4, "lcd", "d4", V_MV78230_PLUS)),
68 MPP_MODE(5,
69 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
70 MPP_VAR_FUNCTION(0x1, "ge0", "txctl", V_MV78230_PLUS),
71 MPP_VAR_FUNCTION(0x4, "lcd", "d5", V_MV78230_PLUS)),
72 MPP_MODE(6,
73 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
74 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0", V_MV78230_PLUS),
75 MPP_VAR_FUNCTION(0x4, "lcd", "d6", V_MV78230_PLUS)),
76 MPP_MODE(7,
77 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
78 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1", V_MV78230_PLUS),
79 MPP_VAR_FUNCTION(0x4, "lcd", "d7", V_MV78230_PLUS)),
80 MPP_MODE(8,
81 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
82 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2", V_MV78230_PLUS),
83 MPP_VAR_FUNCTION(0x4, "lcd", "d8", V_MV78230_PLUS)),
84 MPP_MODE(9,
85 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
86 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3", V_MV78230_PLUS),
87 MPP_VAR_FUNCTION(0x4, "lcd", "d9", V_MV78230_PLUS)),
88 MPP_MODE(10,
89 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
90 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl", V_MV78230_PLUS),
91 MPP_VAR_FUNCTION(0x4, "lcd", "d10", V_MV78230_PLUS)),
92 MPP_MODE(11,
93 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
94 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk", V_MV78230_PLUS),
95 MPP_VAR_FUNCTION(0x4, "lcd", "d11", V_MV78230_PLUS)),
96 MPP_MODE(12,
97 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
98 MPP_VAR_FUNCTION(0x1, "ge0", "txd4", V_MV78230_PLUS),
99 MPP_VAR_FUNCTION(0x2, "ge1", "txclkout", V_MV78230_PLUS),
100 MPP_VAR_FUNCTION(0x4, "lcd", "d12", V_MV78230_PLUS)),
101 MPP_MODE(13,
102 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
103 MPP_VAR_FUNCTION(0x1, "ge0", "txd5", V_MV78230_PLUS),
104 MPP_VAR_FUNCTION(0x2, "ge1", "txd0", V_MV78230_PLUS),
105 MPP_VAR_FUNCTION(0x3, "spi1", "mosi", V_MV78230_PLUS),
106 MPP_VAR_FUNCTION(0x4, "lcd", "d13", V_MV78230_PLUS)),
107 MPP_MODE(14,
108 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
109 MPP_VAR_FUNCTION(0x1, "ge0", "txd6", V_MV78230_PLUS),
110 MPP_VAR_FUNCTION(0x2, "ge1", "txd1", V_MV78230_PLUS),
111 MPP_VAR_FUNCTION(0x3, "spi1", "sck", V_MV78230_PLUS),
112 MPP_VAR_FUNCTION(0x4, "lcd", "d14", V_MV78230_PLUS)),
113 MPP_MODE(15,
114 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
115 MPP_VAR_FUNCTION(0x1, "ge0", "txd7", V_MV78230_PLUS),
116 MPP_VAR_FUNCTION(0x2, "ge1", "txd2", V_MV78230_PLUS),
117 MPP_VAR_FUNCTION(0x4, "lcd", "d15", V_MV78230_PLUS)),
118 MPP_MODE(16,
119 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
120 MPP_VAR_FUNCTION(0x1, "ge0", "txclk", V_MV78230_PLUS),
121 MPP_VAR_FUNCTION(0x2, "ge1", "txd3", V_MV78230_PLUS),
122 MPP_VAR_FUNCTION(0x3, "spi1", "cs0", V_MV78230_PLUS),
123 MPP_VAR_FUNCTION(0x4, "lcd", "d16", V_MV78230_PLUS)),
124 MPP_MODE(17,
125 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
126 MPP_VAR_FUNCTION(0x1, "ge0", "col", V_MV78230_PLUS),
127 MPP_VAR_FUNCTION(0x2, "ge1", "txctl", V_MV78230_PLUS),
128 MPP_VAR_FUNCTION(0x3, "spi1", "miso", V_MV78230_PLUS),
129 MPP_VAR_FUNCTION(0x4, "lcd", "d17", V_MV78230_PLUS)),
130 MPP_MODE(18,
131 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
132 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr", V_MV78230_PLUS),
133 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0", V_MV78230_PLUS),
134 MPP_VAR_FUNCTION(0x3, "ptp", "trig", V_MV78230_PLUS),
135 MPP_VAR_FUNCTION(0x4, "lcd", "d18", V_MV78230_PLUS)),
136 MPP_MODE(19,
137 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
138 MPP_VAR_FUNCTION(0x1, "ge0", "crs", V_MV78230_PLUS),
139 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1", V_MV78230_PLUS),
140 MPP_VAR_FUNCTION(0x3, "ptp", "evreq", V_MV78230_PLUS),
141 MPP_VAR_FUNCTION(0x4, "lcd", "d19", V_MV78230_PLUS)),
142 MPP_MODE(20,
143 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
144 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4", V_MV78230_PLUS),
145 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2", V_MV78230_PLUS),
146 MPP_VAR_FUNCTION(0x3, "ptp", "clk", V_MV78230_PLUS),
147 MPP_VAR_FUNCTION(0x4, "lcd", "d20", V_MV78230_PLUS)),
148 MPP_MODE(21,
149 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
150 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5", V_MV78230_PLUS),
151 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3", V_MV78230_PLUS),
152 MPP_VAR_FUNCTION(0x3, "dram", "bat", V_MV78230_PLUS),
153 MPP_VAR_FUNCTION(0x4, "lcd", "d21", V_MV78230_PLUS)),
154 MPP_MODE(22,
155 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
156 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6", V_MV78230_PLUS),
157 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl", V_MV78230_PLUS),
158 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt", V_MV78230_PLUS),
159 MPP_VAR_FUNCTION(0x4, "lcd", "d22", V_MV78230_PLUS)),
160 MPP_MODE(23,
161 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
162 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7", V_MV78230_PLUS),
163 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk", V_MV78230_PLUS),
164 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
165 MPP_VAR_FUNCTION(0x4, "lcd", "d23", V_MV78230_PLUS)),
166 MPP_MODE(24,
167 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
168 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS),
169 MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS),
170 MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)),
171 MPP_MODE(25,
172 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
173 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS),
174 MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS),
175 MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)),
176 MPP_MODE(26,
177 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
178 MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS),
179 MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)),
180 MPP_MODE(27,
181 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
182 MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS),
183 MPP_VAR_FUNCTION(0x3, "tdm", "dtx", V_MV78230_PLUS),
184 MPP_VAR_FUNCTION(0x4, "lcd", "e", V_MV78230_PLUS)),
185 MPP_MODE(28,
186 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
187 MPP_VAR_FUNCTION(0x1, "ptp", "evreq", V_MV78230_PLUS),
188 MPP_VAR_FUNCTION(0x3, "tdm", "drx", V_MV78230_PLUS),
189 MPP_VAR_FUNCTION(0x4, "lcd", "pwm", V_MV78230_PLUS)),
190 MPP_MODE(29,
191 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
192 MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS),
193 MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS),
194 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)),
195 MPP_MODE(30,
196 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
197 MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS),
198 MPP_VAR_FUNCTION(0x3, "tdm", "int1", V_MV78230_PLUS)),
199 MPP_MODE(31,
200 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
201 MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS),
202 MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)),
203 MPP_MODE(32,
204 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
205 MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS),
206 MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)),
207 MPP_MODE(33,
208 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
209 MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS),
210 MPP_VAR_FUNCTION(0x3, "tdm", "int4", V_MV78230_PLUS),
211 MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
212 MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS)),
213 MPP_MODE(34,
214 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
215 MPP_VAR_FUNCTION(0x1, "sd0", "d2", V_MV78230_PLUS),
216 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt", V_MV78230_PLUS),
217 MPP_VAR_FUNCTION(0x3, "tdm", "int5", V_MV78230_PLUS),
218 MPP_VAR_FUNCTION(0x4, "dram", "deccerr", V_MV78230_PLUS)),
219 MPP_MODE(35,
220 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
221 MPP_VAR_FUNCTION(0x1, "sd0", "d3", V_MV78230_PLUS),
222 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt", V_MV78230_PLUS),
223 MPP_VAR_FUNCTION(0x3, "tdm", "int6", V_MV78230_PLUS)),
224 MPP_MODE(36,
225 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
226 MPP_VAR_FUNCTION(0x1, "spi0", "mosi", V_MV78230_PLUS)),
227 MPP_MODE(37,
228 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
229 MPP_VAR_FUNCTION(0x1, "spi0", "miso", V_MV78230_PLUS)),
230 MPP_MODE(38,
231 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
232 MPP_VAR_FUNCTION(0x1, "spi0", "sck", V_MV78230_PLUS)),
233 MPP_MODE(39,
234 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
235 MPP_VAR_FUNCTION(0x1, "spi0", "cs0", V_MV78230_PLUS)),
236 MPP_MODE(40,
237 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
238 MPP_VAR_FUNCTION(0x1, "spi0", "cs1", V_MV78230_PLUS),
239 MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS),
240 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS),
241 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS),
242 MPP_VAR_FUNCTION(0x6, "spi1", "cs1", V_MV78230_PLUS)),
243 MPP_MODE(41,
244 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
245 MPP_VAR_FUNCTION(0x1, "spi0", "cs2", V_MV78230_PLUS),
246 MPP_VAR_FUNCTION(0x2, "uart2", "rts", V_MV78230_PLUS),
247 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt", V_MV78230_PLUS),
248 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync", V_MV78230_PLUS),
249 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1", V_MV78230_PLUS),
250 MPP_VAR_FUNCTION(0x6, "spi1", "cs2", V_MV78230_PLUS)),
251 MPP_MODE(42,
252 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
253 MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS),
254 MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS),
255 MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS),
256 MPP_VAR_FUNCTION(0x4, "tdm", "timer", V_MV78230_PLUS)),
257 MPP_MODE(43,
258 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
259 MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS),
260 MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS),
261 MPP_VAR_FUNCTION(0x3, "spi0", "cs3", V_MV78230_PLUS),
262 MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS),
263 MPP_VAR_FUNCTION(0x6, "spi1", "cs3", V_MV78230_PLUS)),
264 MPP_MODE(44,
265 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
266 MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS),
267 MPP_VAR_FUNCTION(0x2, "uart3", "rxd", V_MV78230_PLUS),
268 MPP_VAR_FUNCTION(0x3, "spi0", "cs4", V_MV78230_PLUS),
269 MPP_VAR_FUNCTION(0x4, "dram", "bat", V_MV78230_PLUS),
270 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2", V_MV78230_PLUS),
271 MPP_VAR_FUNCTION(0x6, "spi1", "cs4", V_MV78230_PLUS)),
272 MPP_MODE(45,
273 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
274 MPP_VAR_FUNCTION(0x1, "uart2", "rts", V_MV78230_PLUS),
275 MPP_VAR_FUNCTION(0x2, "uart3", "txd", V_MV78230_PLUS),
276 MPP_VAR_FUNCTION(0x3, "spi0", "cs5", V_MV78230_PLUS),
277 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V_MV78230_PLUS),
278 MPP_VAR_FUNCTION(0x5, "dram", "vttctrl", V_MV78230_PLUS),
279 MPP_VAR_FUNCTION(0x6, "spi1", "cs5", V_MV78230_PLUS)),
280 MPP_MODE(46,
281 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
282 MPP_VAR_FUNCTION(0x1, "uart3", "rts", V_MV78230_PLUS),
283 MPP_VAR_FUNCTION(0x2, "uart1", "rts", V_MV78230_PLUS),
284 MPP_VAR_FUNCTION(0x3, "spi0", "cs6", V_MV78230_PLUS),
285 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V_MV78230_PLUS),
286 MPP_VAR_FUNCTION(0x6, "spi1", "cs6", V_MV78230_PLUS)),
287 MPP_MODE(47,
288 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
289 MPP_VAR_FUNCTION(0x1, "uart3", "cts", V_MV78230_PLUS),
290 MPP_VAR_FUNCTION(0x2, "uart1", "cts", V_MV78230_PLUS),
291 MPP_VAR_FUNCTION(0x3, "spi0", "cs7", V_MV78230_PLUS),
292 MPP_VAR_FUNCTION(0x4, "ref", "clkout", V_MV78230_PLUS),
293 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS),
294 MPP_VAR_FUNCTION(0x6, "spi1", "cs7", V_MV78230_PLUS)),
295 MPP_MODE(48,
296 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS),
297 MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS),
298 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS),
299 MPP_VAR_FUNCTION(0x3, "nand", "rb", V_MV78230_PLUS)),
300 MPP_MODE(49,
301 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
302 MPP_VAR_FUNCTION(0x1, "dev", "we3", V_MV78260_PLUS)),
303 MPP_MODE(50,
304 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
305 MPP_VAR_FUNCTION(0x1, "dev", "we2", V_MV78260_PLUS)),
306 MPP_MODE(51,
307 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
308 MPP_VAR_FUNCTION(0x1, "dev", "ad16", V_MV78260_PLUS)),
309 MPP_MODE(52,
310 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
311 MPP_VAR_FUNCTION(0x1, "dev", "ad17", V_MV78260_PLUS)),
312 MPP_MODE(53,
313 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
314 MPP_VAR_FUNCTION(0x1, "dev", "ad18", V_MV78260_PLUS)),
315 MPP_MODE(54,
316 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
317 MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)),
318 MPP_MODE(55,
319 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
320 MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)),
321 MPP_MODE(56,
322 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
323 MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)),
324 MPP_MODE(57,
325 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
326 MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)),
327 MPP_MODE(58,
328 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
329 MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)),
330 MPP_MODE(59,
331 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
332 MPP_VAR_FUNCTION(0x1, "dev", "ad24", V_MV78260_PLUS)),
333 MPP_MODE(60,
334 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
335 MPP_VAR_FUNCTION(0x1, "dev", "ad25", V_MV78260_PLUS)),
336 MPP_MODE(61,
337 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
338 MPP_VAR_FUNCTION(0x1, "dev", "ad26", V_MV78260_PLUS)),
339 MPP_MODE(62,
340 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
341 MPP_VAR_FUNCTION(0x1, "dev", "ad27", V_MV78260_PLUS)),
342 MPP_MODE(63,
343 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
344 MPP_VAR_FUNCTION(0x1, "dev", "ad28", V_MV78260_PLUS)),
345 MPP_MODE(64,
346 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
347 MPP_VAR_FUNCTION(0x1, "dev", "ad29", V_MV78260_PLUS)),
348 MPP_MODE(65,
349 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
350 MPP_VAR_FUNCTION(0x1, "dev", "ad30", V_MV78260_PLUS)),
351 MPP_MODE(66,
352 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS),
353 MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)),
354 };
355
356 static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
357 MPP_MODE(0,
358 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
359 MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS),
360 MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)),
361 MPP_MODE(1,
362 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
363 MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS),
364 MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)),
365 MPP_MODE(2,
366 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
367 MPP_VAR_FUNCTION(0x2, "spi0", "sck", V_98DX3236_PLUS),
368 MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)),
369 MPP_MODE(3,
370 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
371 MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS),
372 MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)),
373 MPP_MODE(4,
374 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
375 MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS),
376 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
377 MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)),
378 MPP_MODE(5,
379 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
380 MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS),
381 MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251),
382 MPP_VAR_FUNCTION(0x4, "dev", "bootcs", V_98DX3236_PLUS)),
383 MPP_MODE(6,
384 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
385 MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251),
386 MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)),
387 MPP_MODE(7,
388 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
389 MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251),
390 MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)),
391 MPP_MODE(8,
392 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
393 MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251),
394 MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)),
395 MPP_MODE(9,
396 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
397 MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251),
398 MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)),
399 MPP_MODE(10,
400 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
401 MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251),
402 MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)),
403 MPP_MODE(11,
404 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
405 MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS),
406 MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS),
407 MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)),
408 MPP_MODE(12,
409 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
410 MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS),
411 MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS),
412 MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)),
413 MPP_MODE(13,
414 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
415 MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS),
416 MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)),
417 MPP_MODE(14,
418 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
419 MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)),
420 MPP_MODE(15,
421 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
422 MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)),
423 MPP_MODE(16,
424 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
425 MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)),
426 MPP_MODE(17,
427 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
428 MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)),
429 MPP_MODE(18,
430 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
431 MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)),
432 MPP_MODE(19,
433 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
434 MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS),
435 MPP_VAR_FUNCTION(0x4, "dev", "rb", V_98DX3236_PLUS)),
436 MPP_MODE(20,
437 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
438 MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)),
439 MPP_MODE(21,
440 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
441 MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)),
442 MPP_MODE(22,
443 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
444 MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)),
445 MPP_MODE(23,
446 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
447 MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)),
448 MPP_MODE(24,
449 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
450 MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)),
451 MPP_MODE(25,
452 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
453 MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)),
454 MPP_MODE(26,
455 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
456 MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)),
457 MPP_MODE(27,
458 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
459 MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)),
460 MPP_MODE(28,
461 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
462 MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)),
463 MPP_MODE(29,
464 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
465 MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)),
466 MPP_MODE(30,
467 MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS),
468 MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)),
469 MPP_MODE(31,
470 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
471 MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),
472 MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS),
473 MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)),
474 MPP_MODE(32,
475 MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS),
476 MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS),
477 MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS),
478 MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)),
479 };
480
481 static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
482
483 static const struct of_device_id armada_xp_pinctrl_of_match[] = {
484 {
485 .compatible = "marvell,mv78230-pinctrl",
486 .data = (void *) V_MV78230,
487 },
488 {
489 .compatible = "marvell,mv78260-pinctrl",
490 .data = (void *) V_MV78260,
491 },
492 {
493 .compatible = "marvell,mv78460-pinctrl",
494 .data = (void *) V_MV78460,
495 },
496 {
497 .compatible = "marvell,98dx3236-pinctrl",
498 .data = (void *) V_98DX3236,
499 },
500 {
501 .compatible = "marvell,98dx4251-pinctrl",
502 .data = (void *) V_98DX4251,
503 },
504 { },
505 };
506
507 static const struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
508 MPP_FUNC_CTRL(0, 48, NULL, mvebu_mmio_mpp_ctrl),
509 };
510
511 static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
512 MPP_GPIO_RANGE(0, 0, 0, 32),
513 MPP_GPIO_RANGE(1, 32, 32, 17),
514 };
515
516 static const struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
517 MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl),
518 };
519
520 static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
521 MPP_GPIO_RANGE(0, 0, 0, 32),
522 MPP_GPIO_RANGE(1, 32, 32, 32),
523 MPP_GPIO_RANGE(2, 64, 64, 3),
524 };
525
526 static const struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
527 MPP_FUNC_CTRL(0, 66, NULL, mvebu_mmio_mpp_ctrl),
528 };
529
530 static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
531 MPP_GPIO_RANGE(0, 0, 0, 32),
532 MPP_GPIO_RANGE(1, 32, 32, 32),
533 MPP_GPIO_RANGE(2, 64, 64, 3),
534 };
535
536 static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
537 MPP_FUNC_CTRL(0, 32, NULL, mvebu_mmio_mpp_ctrl),
538 };
539
540 static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = {
541 MPP_GPIO_RANGE(0, 0, 0, 32),
542 };
543
544 static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
545 pm_message_t state)
546 {
547 struct mvebu_pinctrl_soc_info *soc =
548 platform_get_drvdata(pdev);
549 int i, nregs;
550
551 nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
552
553 for (i = 0; i < nregs; i++)
554 mpp_saved_regs[i] = readl(soc->control_data[0].base + i * 4);
555
556 return 0;
557 }
558
559 static int armada_xp_pinctrl_resume(struct platform_device *pdev)
560 {
561 struct mvebu_pinctrl_soc_info *soc =
562 platform_get_drvdata(pdev);
563 int i, nregs;
564
565 nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
566
567 for (i = 0; i < nregs; i++)
568 writel(mpp_saved_regs[i], soc->control_data[0].base + i * 4);
569
570 return 0;
571 }
572
573 static int armada_xp_pinctrl_probe(struct platform_device *pdev)
574 {
575 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
576 const struct of_device_id *match =
577 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
578 int nregs;
579
580 if (!match)
581 return -ENODEV;
582
583 soc->variant = (unsigned) match->data & 0xff;
584
585 switch (soc->variant) {
586 case V_MV78230:
587 soc->controls = mv78230_mpp_controls;
588 soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
589 soc->modes = armada_xp_mpp_modes;
590 /* We don't necessarily want the full list of the
591 * armada_xp_mpp_modes, but only the first 'n' ones
592 * that are available on this SoC */
593 soc->nmodes = mv78230_mpp_controls[0].npins;
594 soc->gpioranges = mv78230_mpp_gpio_ranges;
595 soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
596 break;
597 case V_MV78260:
598 soc->controls = mv78260_mpp_controls;
599 soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
600 soc->modes = armada_xp_mpp_modes;
601 /* We don't necessarily want the full list of the
602 * armada_xp_mpp_modes, but only the first 'n' ones
603 * that are available on this SoC */
604 soc->nmodes = mv78260_mpp_controls[0].npins;
605 soc->gpioranges = mv78260_mpp_gpio_ranges;
606 soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
607 break;
608 case V_MV78460:
609 soc->controls = mv78460_mpp_controls;
610 soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
611 soc->modes = armada_xp_mpp_modes;
612 /* We don't necessarily want the full list of the
613 * armada_xp_mpp_modes, but only the first 'n' ones
614 * that are available on this SoC */
615 soc->nmodes = mv78460_mpp_controls[0].npins;
616 soc->gpioranges = mv78460_mpp_gpio_ranges;
617 soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
618 break;
619 case V_98DX3236:
620 case V_98DX3336:
621 case V_98DX4251:
622 /* fall-through */
623 soc->controls = mv98dx3236_mpp_controls;
624 soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls);
625 soc->modes = mv98dx3236_mpp_modes;
626 soc->nmodes = mv98dx3236_mpp_controls[0].npins;
627 soc->gpioranges = mv98dx3236_mpp_gpio_ranges;
628 soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges);
629 break;
630 }
631
632 nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
633
634 mpp_saved_regs = devm_kmalloc(&pdev->dev, nregs * sizeof(u32),
635 GFP_KERNEL);
636 if (!mpp_saved_regs)
637 return -ENOMEM;
638
639 pdev->dev.platform_data = soc;
640
641 return mvebu_pinctrl_simple_mmio_probe(pdev);
642 }
643
644 static struct platform_driver armada_xp_pinctrl_driver = {
645 .driver = {
646 .name = "armada-xp-pinctrl",
647 .of_match_table = armada_xp_pinctrl_of_match,
648 },
649 .probe = armada_xp_pinctrl_probe,
650 .suspend = armada_xp_pinctrl_suspend,
651 .resume = armada_xp_pinctrl_resume,
652 };
653
654 module_platform_driver(armada_xp_pinctrl_driver);
655
656 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
657 MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
658 MODULE_LICENSE("GPL v2");
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