drivers/pinctrl/mvebu/pinctrl-dove.c

   1 /*
   2  * Marvell Dove pinctrl driver based on mvebu pinctrl core
   3  *
   4  * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/bitops.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/pinctrl/pinctrl.h>
  23 #include <linux/regmap.h>
  24
  25 #include "pinctrl-mvebu.h"
  26
  27 /* Internal registers can be configured at any 1 MiB aligned address */
  28 #define INT_REGS_MASK           ~(SZ_1M - 1)
  29 #define MPP4_REGS_OFFS          0xd0440
  30 #define PMU_REGS_OFFS           0xd802c
  31 #define GC_REGS_OFFS            0xe802c
  32
  33 /* MPP Base registers */
  34 #define PMU_MPP_GENERAL_CTRL    0x10
  35 #define  AU0_AC97_SEL           BIT(16)
  36
  37 /* MPP Control 4 register */
  38 #define SPI_GPIO_SEL            BIT(5)
  39 #define UART1_GPIO_SEL          BIT(4)
  40 #define AU1_GPIO_SEL            BIT(3)
  41 #define CAM_GPIO_SEL            BIT(2)
  42 #define SD1_GPIO_SEL            BIT(1)
  43 #define SD0_GPIO_SEL            BIT(0)
  44
  45 /* PMU Signal Select registers */
  46 #define PMU_SIGNAL_SELECT_0     0x00
  47 #define PMU_SIGNAL_SELECT_1     0x04
  48
  49 /* Global Config regmap registers */
  50 #define GLOBAL_CONFIG_1         0x00
  51 #define  TWSI_ENABLE_OPTION1    BIT(7)
  52 #define GLOBAL_CONFIG_2         0x04
  53 #define  TWSI_ENABLE_OPTION2    BIT(20)
  54 #define  TWSI_ENABLE_OPTION3    BIT(21)
  55 #define  TWSI_OPTION3_GPIO      BIT(22)
  56 #define SSP_CTRL_STATUS_1       0x08
  57 #define  SSP_ON_AU1             BIT(0)
  58 #define MPP_GENERAL_CONFIG      0x10
  59 #define  AU1_SPDIFO_GPIO_EN     BIT(1)
  60 #define  NAND_GPIO_EN           BIT(0)
  61
  62 #define CONFIG_PMU      BIT(4)
  63
  64 static void __iomem *mpp4_base;
  65 static void __iomem *pmu_base;
  66 static struct regmap *gconfmap;
  67
  68 static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
  69                                  unsigned pid, unsigned long *config)
  70 {
  71         unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
  72         unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
  73         unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
  74         unsigned long func;
  75
  76         if ((pmu & BIT(pid)) == 0)
  77                 return mvebu_mmio_mpp_ctrl_get(data, pid, config);
  78
  79         func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
  80         *config = (func >> shift) & MVEBU_MPP_MASK;
  81         *config |= CONFIG_PMU;
  82
  83         return 0;
  84 }
  85
  86 static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
  87                                  unsigned pid, unsigned long config)
  88 {
  89         unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
  90         unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
  91         unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
  92         unsigned long func;
  93
  94         if ((config & CONFIG_PMU) == 0) {
  95                 writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
  96                 return mvebu_mmio_mpp_ctrl_set(data, pid, config);
  97         }
  98
  99         writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
 100         func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
 101         func &= ~(MVEBU_MPP_MASK << shift);
 102         func |= (config & MVEBU_MPP_MASK) << shift;
 103         writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
 104
 105         return 0;
 106 }
 107
 108 static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 109                               unsigned long *config)
 110 {
 111         unsigned long mpp4 = readl(mpp4_base);
 112         unsigned long mask;
 113
 114         switch (pid) {
 115         case 24: /* mpp_camera */
 116                 mask = CAM_GPIO_SEL;
 117                 break;
 118         case 40: /* mpp_sdio0 */
 119                 mask = SD0_GPIO_SEL;
 120                 break;
 121         case 46: /* mpp_sdio1 */
 122                 mask = SD1_GPIO_SEL;
 123                 break;
 124         case 58: /* mpp_spi0 */
 125                 mask = SPI_GPIO_SEL;
 126                 break;
 127         case 62: /* mpp_uart1 */
 128                 mask = UART1_GPIO_SEL;
 129                 break;
 130         default:
 131                 return -EINVAL;
 132         }
 133
 134         *config = ((mpp4 & mask) != 0);
 135
 136         return 0;
 137 }
 138
 139 static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 140                               unsigned long config)
 141 {
 142         unsigned long mpp4 = readl(mpp4_base);
 143         unsigned long mask;
 144
 145         switch (pid) {
 146         case 24: /* mpp_camera */
 147                 mask = CAM_GPIO_SEL;
 148                 break;
 149         case 40: /* mpp_sdio0 */
 150                 mask = SD0_GPIO_SEL;
 151                 break;
 152         case 46: /* mpp_sdio1 */
 153                 mask = SD1_GPIO_SEL;
 154                 break;
 155         case 58: /* mpp_spi0 */
 156                 mask = SPI_GPIO_SEL;
 157                 break;
 158         case 62: /* mpp_uart1 */
 159                 mask = UART1_GPIO_SEL;
 160                 break;
 161         default:
 162                 return -EINVAL;
 163         }
 164
 165         mpp4 &= ~mask;
 166         if (config)
 167                 mpp4 |= mask;
 168
 169         writel(mpp4, mpp4_base);
 170
 171         return 0;
 172 }
 173
 174 static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 175                               unsigned long *config)
 176 {
 177         unsigned int gmpp;
 178
 179         regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
 180         *config = ((gmpp & NAND_GPIO_EN) != 0);
 181
 182         return 0;
 183 }
 184
 185 static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 186                               unsigned long config)
 187 {
 188         regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
 189                            NAND_GPIO_EN,
 190                            (config) ? NAND_GPIO_EN : 0);
 191         return 0;
 192 }
 193
 194 static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 195                                 unsigned long *config)
 196 {
 197         unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
 198
 199         *config = ((pmu & AU0_AC97_SEL) != 0);
 200
 201         return 0;
 202 }
 203
 204 static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 205                                 unsigned long config)
 206 {
 207         unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
 208
 209         pmu &= ~AU0_AC97_SEL;
 210         if (config)
 211                 pmu |= AU0_AC97_SEL;
 212         writel(pmu, data->base + PMU_MPP_GENERAL_CTRL);
 213
 214         return 0;
 215 }
 216
 217 static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 218                                 unsigned long *config)
 219 {
 220         unsigned int mpp4 = readl(mpp4_base);
 221         unsigned int sspc1;
 222         unsigned int gmpp;
 223         unsigned int gcfg2;
 224
 225         regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
 226         regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
 227         regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
 228
 229         *config = 0;
 230         if (mpp4 & AU1_GPIO_SEL)
 231                 *config |= BIT(3);
 232         if (sspc1 & SSP_ON_AU1)
 233                 *config |= BIT(2);
 234         if (gmpp & AU1_SPDIFO_GPIO_EN)
 235                 *config |= BIT(1);
 236         if (gcfg2 & TWSI_OPTION3_GPIO)
 237                 *config |= BIT(0);
 238
 239         /* SSP/TWSI only if I2S1 not set*/
 240         if ((*config & BIT(3)) == 0)
 241                 *config &= ~(BIT(2) | BIT(0));
 242         /* TWSI only if SPDIFO not set*/
 243         if ((*config & BIT(1)) == 0)
 244                 *config &= ~BIT(0);
 245         return 0;
 246 }
 247
 248 static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 249                                 unsigned long config)
 250 {
 251         unsigned int mpp4 = readl(mpp4_base);
 252
 253         mpp4 &= ~AU1_GPIO_SEL;
 254         if (config & BIT(3))
 255                 mpp4 |= AU1_GPIO_SEL;
 256         writel(mpp4, mpp4_base);
 257
 258         regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
 259                            SSP_ON_AU1,
 260                            (config & BIT(2)) ? SSP_ON_AU1 : 0);
 261         regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
 262                            AU1_SPDIFO_GPIO_EN,
 263                            (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
 264         regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
 265                            TWSI_OPTION3_GPIO,
 266                            (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
 267
 268         return 0;
 269 }
 270
 271 /* mpp[52:57] gpio pins depend heavily on current config;
 272  * gpio_req does not try to mux in gpio capabilities to not
 273  * break other functions. If you require all mpps as gpio
 274  * enforce gpio setting by pinctrl mapping.
 275  */
 276 static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data,
 277                                      unsigned pid)
 278 {
 279         unsigned long config;
 280
 281         dove_audio1_ctrl_get(data, pid, &config);
 282
 283         switch (config) {
 284         case 0x02: /* i2s1 : gpio[56:57] */
 285         case 0x0e: /* ssp  : gpio[56:57] */
 286                 if (pid >= 56)
 287                         return 0;
 288                 return -ENOTSUPP;
 289         case 0x08: /* spdifo : gpio[52:55] */
 290         case 0x0b: /* twsi   : gpio[52:55] */
 291                 if (pid <= 55)
 292                         return 0;
 293                 return -ENOTSUPP;
 294         case 0x0a: /* all gpio */
 295                 return 0;
 296         /* 0x00 : i2s1/spdifo : no gpio */
 297         /* 0x0c : ssp/spdifo  : no gpio */
 298         /* 0x0f : ssp/twsi    : no gpio */
 299         }
 300         return -ENOTSUPP;
 301 }
 302
 303 /* mpp[52:57] has gpio pins capable of in and out */
 304 static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data,
 305                                      unsigned pid, bool input)
 306 {
 307         if (pid < 52 || pid > 57)
 308                 return -ENOTSUPP;
 309         return 0;
 310 }
 311
 312 static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 313                               unsigned long *config)
 314 {
 315         unsigned int gcfg1;
 316         unsigned int gcfg2;
 317
 318         regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
 319         regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
 320
 321         *config = 0;
 322         if (gcfg1 & TWSI_ENABLE_OPTION1)
 323                 *config = 1;
 324         else if (gcfg2 & TWSI_ENABLE_OPTION2)
 325                 *config = 2;
 326         else if (gcfg2 & TWSI_ENABLE_OPTION3)
 327                 *config = 3;
 328
 329         return 0;
 330 }
 331
 332 static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
 333                               unsigned long config)
 334 {
 335         unsigned int gcfg1 = 0;
 336         unsigned int gcfg2 = 0;
 337
 338         switch (config) {
 339         case 1:
 340                 gcfg1 = TWSI_ENABLE_OPTION1;
 341                 break;
 342         case 2:
 343                 gcfg2 = TWSI_ENABLE_OPTION2;
 344                 break;
 345         case 3:
 346                 gcfg2 = TWSI_ENABLE_OPTION3;
 347                 break;
 348         }
 349
 350         regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
 351                            TWSI_ENABLE_OPTION1,
 352                            gcfg1);
 353         regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
 354                            TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
 355                            gcfg2);
 356
 357         return 0;
 358 }
 359
 360 static const struct mvebu_mpp_ctrl dove_mpp_controls[] = {
 361         MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
 362         MPP_FUNC_CTRL(16, 23, NULL, mvebu_mmio_mpp_ctrl),
 363         MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
 364         MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
 365         MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
 366         MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
 367         MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
 368         MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
 369         MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
 370         MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
 371         MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
 372 };
 373
 374 static struct mvebu_mpp_mode dove_mpp_modes[] = {
 375         MPP_MODE(0,
 376                 MPP_FUNCTION(0x00, "gpio", NULL),
 377                 MPP_FUNCTION(0x02, "uart2", "rts"),
 378                 MPP_FUNCTION(0x03, "sdio0", "cd"),
 379                 MPP_FUNCTION(0x0f, "lcd0", "pwm"),
 380                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 381                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 382                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 383                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 384                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 385                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 386                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 387                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 388                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 389                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 390                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 391                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 392         MPP_MODE(1,
 393                 MPP_FUNCTION(0x00, "gpio", NULL),
 394                 MPP_FUNCTION(0x02, "uart2", "cts"),
 395                 MPP_FUNCTION(0x03, "sdio0", "wp"),
 396                 MPP_FUNCTION(0x0f, "lcd1", "pwm"),
 397                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 398                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 399                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 400                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 401                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 402                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 403                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 404                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 405                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 406                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 407                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 408                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 409         MPP_MODE(2,
 410                 MPP_FUNCTION(0x00, "gpio", NULL),
 411                 MPP_FUNCTION(0x01, "sata", "prsnt"),
 412                 MPP_FUNCTION(0x02, "uart2", "txd"),
 413                 MPP_FUNCTION(0x03, "sdio0", "buspwr"),
 414                 MPP_FUNCTION(0x04, "uart1", "rts"),
 415                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 416                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 417                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 418                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 419                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 420                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 421                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 422                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 423                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 424                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 425                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 426                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 427         MPP_MODE(3,
 428                 MPP_FUNCTION(0x00, "gpio", NULL),
 429                 MPP_FUNCTION(0x01, "sata", "act"),
 430                 MPP_FUNCTION(0x02, "uart2", "rxd"),
 431                 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
 432                 MPP_FUNCTION(0x04, "uart1", "cts"),
 433                 MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
 434                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 435                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 436                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 437                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 438                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 439                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 440                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 441                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 442                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 443                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 444                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 445                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 446         MPP_MODE(4,
 447                 MPP_FUNCTION(0x00, "gpio", NULL),
 448                 MPP_FUNCTION(0x02, "uart3", "rts"),
 449                 MPP_FUNCTION(0x03, "sdio1", "cd"),
 450                 MPP_FUNCTION(0x04, "spi1", "miso"),
 451                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 452                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 453                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 454                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 455                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 456                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 457                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 458                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 459                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 460                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 461                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 462                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 463         MPP_MODE(5,
 464                 MPP_FUNCTION(0x00, "gpio", NULL),
 465                 MPP_FUNCTION(0x02, "uart3", "cts"),
 466                 MPP_FUNCTION(0x03, "sdio1", "wp"),
 467                 MPP_FUNCTION(0x04, "spi1", "cs"),
 468                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 469                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 470                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 471                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 472                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 473                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 474                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 475                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 476                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 477                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 478                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 479                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 480         MPP_MODE(6,
 481                 MPP_FUNCTION(0x00, "gpio", NULL),
 482                 MPP_FUNCTION(0x02, "uart3", "txd"),
 483                 MPP_FUNCTION(0x03, "sdio1", "buspwr"),
 484                 MPP_FUNCTION(0x04, "spi1", "mosi"),
 485                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 486                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 487                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 488                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 489                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 490                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 491                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 492                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 493                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 494                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 495                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 496                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 497         MPP_MODE(7,
 498                 MPP_FUNCTION(0x00, "gpio", NULL),
 499                 MPP_FUNCTION(0x02, "uart3", "rxd"),
 500                 MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
 501                 MPP_FUNCTION(0x04, "spi1", "sck"),
 502                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 503                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 504                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 505                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 506                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 507                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 508                 MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
 509                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 510                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 511                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 512                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 513                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 514         MPP_MODE(8,
 515                 MPP_FUNCTION(0x00, "gpio", NULL),
 516                 MPP_FUNCTION(0x01, "watchdog", "rstout"),
 517                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 518                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 519                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 520                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 521                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 522                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 523                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 524                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 525                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 526                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 527                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 528                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 529         MPP_MODE(9,
 530                 MPP_FUNCTION(0x00, "gpio", NULL),
 531                 MPP_FUNCTION(0x05, "pex1", "clkreq"),
 532                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 533                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 534                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 535                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 536                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 537                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 538                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 539                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 540                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 541                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 542                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 543                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 544         MPP_MODE(10,
 545                 MPP_FUNCTION(0x00, "gpio", NULL),
 546                 MPP_FUNCTION(0x05, "ssp", "sclk"),
 547                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 548                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 549                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 550                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 551                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 552                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 553                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 554                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 555                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 556                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 557                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 558                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 559         MPP_MODE(11,
 560                 MPP_FUNCTION(0x00, "gpio", NULL),
 561                 MPP_FUNCTION(0x01, "sata", "prsnt"),
 562                 MPP_FUNCTION(0x02, "sata-1", "act"),
 563                 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
 564                 MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
 565                 MPP_FUNCTION(0x05, "pex0", "clkreq"),
 566                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 567                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 568                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 569                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 570                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 571                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 572                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 573                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 574                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 575                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 576                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 577                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 578         MPP_MODE(12,
 579                 MPP_FUNCTION(0x00, "gpio", NULL),
 580                 MPP_FUNCTION(0x01, "sata", "act"),
 581                 MPP_FUNCTION(0x02, "uart2", "rts"),
 582                 MPP_FUNCTION(0x03, "audio0", "extclk"),
 583                 MPP_FUNCTION(0x04, "sdio1", "cd"),
 584                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 585                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 586                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 587                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 588                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 589                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 590                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 591                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 592                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 593                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 594                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 595                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 596         MPP_MODE(13,
 597                 MPP_FUNCTION(0x00, "gpio", NULL),
 598                 MPP_FUNCTION(0x02, "uart2", "cts"),
 599                 MPP_FUNCTION(0x03, "audio1", "extclk"),
 600                 MPP_FUNCTION(0x04, "sdio1", "wp"),
 601                 MPP_FUNCTION(0x05, "ssp", "extclk"),
 602                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 603                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 604                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 605                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 606                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 607                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 608                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 609                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 610                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 611                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 612                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 613                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 614         MPP_MODE(14,
 615                 MPP_FUNCTION(0x00, "gpio", NULL),
 616                 MPP_FUNCTION(0x02, "uart2", "txd"),
 617                 MPP_FUNCTION(0x04, "sdio1", "buspwr"),
 618                 MPP_FUNCTION(0x05, "ssp", "rxd"),
 619                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 620                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 621                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 622                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 623                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 624                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 625                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 626                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 627                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 628                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 629                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 630                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 631         MPP_MODE(15,
 632                 MPP_FUNCTION(0x00, "gpio", NULL),
 633                 MPP_FUNCTION(0x02, "uart2", "rxd"),
 634                 MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
 635                 MPP_FUNCTION(0x05, "ssp", "sfrm"),
 636                 MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
 637                 MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
 638                 MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
 639                 MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
 640                 MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
 641                 MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
 642                 MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
 643                 MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
 644                 MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
 645                 MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
 646                 MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
 647                 MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
 648         MPP_MODE(16,
 649                 MPP_FUNCTION(0x00, "gpio", NULL),
 650                 MPP_FUNCTION(0x02, "uart3", "rts"),
 651                 MPP_FUNCTION(0x03, "sdio0", "cd"),
 652                 MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
 653                 MPP_FUNCTION(0x05, "ac97", "sdi1")),
 654         MPP_MODE(17,
 655                 MPP_FUNCTION(0x00, "gpio", NULL),
 656                 MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
 657                 MPP_FUNCTION(0x02, "uart3", "cts"),
 658                 MPP_FUNCTION(0x03, "sdio0", "wp"),
 659                 MPP_FUNCTION(0x04, "twsi", "sda"),
 660                 MPP_FUNCTION(0x05, "ac97", "sdi2")),
 661         MPP_MODE(18,
 662                 MPP_FUNCTION(0x00, "gpio", NULL),
 663                 MPP_FUNCTION(0x02, "uart3", "txd"),
 664                 MPP_FUNCTION(0x03, "sdio0", "buspwr"),
 665                 MPP_FUNCTION(0x04, "lcd0", "pwm"),
 666                 MPP_FUNCTION(0x05, "ac97", "sdi3")),
 667         MPP_MODE(19,
 668                 MPP_FUNCTION(0x00, "gpio", NULL),
 669                 MPP_FUNCTION(0x02, "uart3", "rxd"),
 670                 MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
 671                 MPP_FUNCTION(0x04, "twsi", "sck")),
 672         MPP_MODE(20,
 673                 MPP_FUNCTION(0x00, "gpio", NULL),
 674                 MPP_FUNCTION(0x01, "ac97", "sysclko"),
 675                 MPP_FUNCTION(0x02, "lcd-spi", "miso"),
 676                 MPP_FUNCTION(0x03, "sdio1", "cd"),
 677                 MPP_FUNCTION(0x05, "sdio0", "cd"),
 678                 MPP_FUNCTION(0x06, "spi1", "miso")),
 679         MPP_MODE(21,
 680                 MPP_FUNCTION(0x00, "gpio", NULL),
 681                 MPP_FUNCTION(0x01, "uart1", "rts"),
 682                 MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
 683                 MPP_FUNCTION(0x03, "sdio1", "wp"),
 684                 MPP_FUNCTION(0x04, "ssp", "sfrm"),
 685                 MPP_FUNCTION(0x05, "sdio0", "wp"),
 686                 MPP_FUNCTION(0x06, "spi1", "cs")),
 687         MPP_MODE(22,
 688                 MPP_FUNCTION(0x00, "gpio", NULL),
 689                 MPP_FUNCTION(0x01, "uart1", "cts"),
 690                 MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
 691                 MPP_FUNCTION(0x03, "sdio1", "buspwr"),
 692                 MPP_FUNCTION(0x04, "ssp", "txd"),
 693                 MPP_FUNCTION(0x05, "sdio0", "buspwr"),
 694                 MPP_FUNCTION(0x06, "spi1", "mosi")),
 695         MPP_MODE(23,
 696                 MPP_FUNCTION(0x00, "gpio", NULL),
 697                 MPP_FUNCTION(0x02, "lcd-spi", "sck"),
 698                 MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
 699                 MPP_FUNCTION(0x04, "ssp", "sclk"),
 700                 MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
 701                 MPP_FUNCTION(0x06, "spi1", "sck")),
 702         MPP_MODE(24,
 703                 MPP_FUNCTION(0x00, "camera", NULL),
 704                 MPP_FUNCTION(0x01, "gpio", NULL)),
 705         MPP_MODE(40,
 706                 MPP_FUNCTION(0x00, "sdio0", NULL),
 707                 MPP_FUNCTION(0x01, "gpio", NULL)),
 708         MPP_MODE(46,
 709                 MPP_FUNCTION(0x00, "sdio1", NULL),
 710                 MPP_FUNCTION(0x01, "gpio", NULL)),
 711         MPP_MODE(52,
 712                 MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
 713                 MPP_FUNCTION(0x02, "i2s1", NULL),
 714                 MPP_FUNCTION(0x08, "spdifo", NULL),
 715                 MPP_FUNCTION(0x0a, "gpio", NULL),
 716                 MPP_FUNCTION(0x0b, "twsi", NULL),
 717                 MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
 718                 MPP_FUNCTION(0x0e, "ssp", NULL),
 719                 MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
 720         MPP_MODE(58,
 721                 MPP_FUNCTION(0x00, "spi0", NULL),
 722                 MPP_FUNCTION(0x01, "gpio", NULL)),
 723         MPP_MODE(62,
 724                 MPP_FUNCTION(0x00, "uart1", NULL),
 725                 MPP_FUNCTION(0x01, "gpio", NULL)),
 726         MPP_MODE(64,
 727                 MPP_FUNCTION(0x00, "nand", NULL),
 728                 MPP_FUNCTION(0x01, "gpo", NULL)),
 729         MPP_MODE(72,
 730                 MPP_FUNCTION(0x00, "i2s", NULL),
 731                 MPP_FUNCTION(0x01, "ac97", NULL)),
 732         MPP_MODE(73,
 733                 MPP_FUNCTION(0x00, "twsi-none", NULL),
 734                 MPP_FUNCTION(0x01, "twsi-opt1", NULL),
 735                 MPP_FUNCTION(0x02, "twsi-opt2", NULL),
 736                 MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
 737 };
 738
 739 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
 740         MPP_GPIO_RANGE(0,  0,  0, 32),
 741         MPP_GPIO_RANGE(1, 32, 32, 32),
 742         MPP_GPIO_RANGE(2, 64, 64,  8),
 743 };
 744
 745 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
 746         .controls = dove_mpp_controls,
 747         .ncontrols = ARRAY_SIZE(dove_mpp_controls),
 748         .modes = dove_mpp_modes,
 749         .nmodes = ARRAY_SIZE(dove_mpp_modes),
 750         .gpioranges = dove_mpp_gpio_ranges,
 751         .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
 752         .variant = 0,
 753 };
 754
 755 static struct clk *clk;
 756
 757 static const struct of_device_id dove_pinctrl_of_match[] = {
 758         { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
 759         { }
 760 };
 761
 762 static const struct regmap_config gc_regmap_config = {
 763         .reg_bits = 32,
 764         .val_bits = 32,
 765         .reg_stride = 4,
 766         .max_register = 5,
 767 };
 768
 769 static int dove_pinctrl_probe(struct platform_device *pdev)
 770 {
 771         struct resource *res, *mpp_res;
 772         struct resource fb_res;
 773         const struct of_device_id *match =
 774                 of_match_device(dove_pinctrl_of_match, &pdev->dev);
 775         struct mvebu_mpp_ctrl_data *mpp_data;
 776         void __iomem *base;
 777         int i;
 778
 779         pdev->dev.platform_data = (void *)match->data;
 780
 781         /*
 782          * General MPP Configuration Register is part of pdma registers.
 783          * grab clk to make sure it is ticking.
 784          */
 785         clk = devm_clk_get(&pdev->dev, NULL);
 786         if (IS_ERR(clk)) {
 787                 dev_err(&pdev->dev, "Unable to get pdma clock");
 788                 return PTR_ERR(clk);
 789         }
 790         clk_prepare_enable(clk);
 791
 792         mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 793         base = devm_ioremap_resource(&pdev->dev, mpp_res);
 794         if (IS_ERR(base))
 795                 return PTR_ERR(base);
 796
 797         mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
 798                                 sizeof(*mpp_data), GFP_KERNEL);
 799         if (!mpp_data)
 800                 return -ENOMEM;
 801
 802         dove_pinctrl_info.control_data = mpp_data;
 803         for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
 804                 mpp_data[i].base = base;
 805
 806         /* prepare fallback resource */
 807         memcpy(&fb_res, mpp_res, sizeof(struct resource));
 808         fb_res.start = 0;
 809
 810         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 811         if (!res) {
 812                 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
 813                 adjust_resource(&fb_res,
 814                         (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
 815                 res = &fb_res;
 816         }
 817
 818         mpp4_base = devm_ioremap_resource(&pdev->dev, res);
 819         if (IS_ERR(mpp4_base))
 820                 return PTR_ERR(mpp4_base);
 821
 822         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 823         if (!res) {
 824                 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
 825                 adjust_resource(&fb_res,
 826                         (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
 827                 res = &fb_res;
 828         }
 829
 830         pmu_base = devm_ioremap_resource(&pdev->dev, res);
 831         if (IS_ERR(pmu_base))
 832                 return PTR_ERR(pmu_base);
 833
 834         gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
 835         if (IS_ERR(gconfmap)) {
 836                 void __iomem *gc_base;
 837
 838                 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
 839                 adjust_resource(&fb_res,
 840                         (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
 841                 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
 842                 if (IS_ERR(gc_base))
 843                         return PTR_ERR(gc_base);
 844                 gconfmap = devm_regmap_init_mmio(&pdev->dev,
 845                                                  gc_base, &gc_regmap_config);
 846                 if (IS_ERR(gconfmap))
 847                         return PTR_ERR(gconfmap);
 848         }
 849
 850         /* Warn on any missing DT resource */
 851         if (fb_res.start)
 852                 dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
 853
 854         return mvebu_pinctrl_probe(pdev);
 855 }
 856
 857 static int dove_pinctrl_remove(struct platform_device *pdev)
 858 {
 859         if (!IS_ERR(clk))
 860                 clk_disable_unprepare(clk);
 861         return 0;
 862 }
 863
 864 static struct platform_driver dove_pinctrl_driver = {
 865         .driver = {
 866                 .name = "dove-pinctrl",
 867                 .of_match_table = dove_pinctrl_of_match,
 868         },
 869         .probe = dove_pinctrl_probe,
 870         .remove = dove_pinctrl_remove,
 871 };
 872
 873 module_platform_driver(dove_pinctrl_driver);
 874
 875 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
 876 MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
 877 MODULE_LICENSE("GPL v2");