2 * Copyright (C) ST-Ericsson SA 2013
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/gpio.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/bitops.h>
22 #include <linux/mfd/abx500.h>
23 #include <linux/mfd/abx500/ab8500.h>
24 #include <linux/mfd/abx500/ab8500-gpio.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pinctrl/pinmux.h>
28 #include <linux/pinctrl/pinconf.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include "pinctrl-abx500.h"
34 * The AB9540 and AB8540 GPIO support are extended versions
35 * of the AB8500 GPIO support.
36 * The AB9540 supports an additional (7th) register so that
37 * more GPIO may be configured and used.
38 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
39 * internal pull-up and pull-down capabilities.
43 * GPIO registers offset
46 #define AB8500_GPIO_SEL1_REG 0x00
47 #define AB8500_GPIO_SEL2_REG 0x01
48 #define AB8500_GPIO_SEL3_REG 0x02
49 #define AB8500_GPIO_SEL4_REG 0x03
50 #define AB8500_GPIO_SEL5_REG 0x04
51 #define AB8500_GPIO_SEL6_REG 0x05
52 #define AB9540_GPIO_SEL7_REG 0x06
54 #define AB8500_GPIO_DIR1_REG 0x10
55 #define AB8500_GPIO_DIR2_REG 0x11
56 #define AB8500_GPIO_DIR3_REG 0x12
57 #define AB8500_GPIO_DIR4_REG 0x13
58 #define AB8500_GPIO_DIR5_REG 0x14
59 #define AB8500_GPIO_DIR6_REG 0x15
60 #define AB9540_GPIO_DIR7_REG 0x16
62 #define AB8500_GPIO_OUT1_REG 0x20
63 #define AB8500_GPIO_OUT2_REG 0x21
64 #define AB8500_GPIO_OUT3_REG 0x22
65 #define AB8500_GPIO_OUT4_REG 0x23
66 #define AB8500_GPIO_OUT5_REG 0x24
67 #define AB8500_GPIO_OUT6_REG 0x25
68 #define AB9540_GPIO_OUT7_REG 0x26
70 #define AB8500_GPIO_PUD1_REG 0x30
71 #define AB8500_GPIO_PUD2_REG 0x31
72 #define AB8500_GPIO_PUD3_REG 0x32
73 #define AB8500_GPIO_PUD4_REG 0x33
74 #define AB8500_GPIO_PUD5_REG 0x34
75 #define AB8500_GPIO_PUD6_REG 0x35
76 #define AB9540_GPIO_PUD7_REG 0x36
78 #define AB8500_GPIO_IN1_REG 0x40
79 #define AB8500_GPIO_IN2_REG 0x41
80 #define AB8500_GPIO_IN3_REG 0x42
81 #define AB8500_GPIO_IN4_REG 0x43
82 #define AB8500_GPIO_IN5_REG 0x44
83 #define AB8500_GPIO_IN6_REG 0x45
84 #define AB9540_GPIO_IN7_REG 0x46
85 #define AB8540_GPIO_VINSEL_REG 0x47
86 #define AB8540_GPIO_PULL_UPDOWN_REG 0x48
87 #define AB8500_GPIO_ALTFUN_REG 0x50
88 #define AB8500_NUM_VIR_GPIO_IRQ 16
89 #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
90 #define AB8540_GPIO_VINSEL_MASK 0x03
91 #define AB8540_GPIOX_VBAT_START 51
92 #define AB8540_GPIOX_VBAT_END 54
94 enum abx500_gpio_action
{
102 struct abx500_pinctrl
{
104 struct pinctrl_dev
*pctldev
;
105 struct abx500_pinctrl_soc_data
*soc
;
106 struct gpio_chip chip
;
107 struct ab8500
*parent
;
110 enum abx500_gpio_action irq_action
;
113 struct abx500_gpio_irq_cluster
*irq_cluster
;
114 int irq_cluster_size
;
115 int irq_gpio_rising_offset
;
116 int irq_gpio_falling_offset
;
121 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
122 * @chip: Member of the structure abx500_pinctrl
124 static inline struct abx500_pinctrl
*to_abx500_pinctrl(struct gpio_chip
*chip
)
126 return container_of(chip
, struct abx500_pinctrl
, chip
);
129 static int abx500_gpio_get_bit(struct gpio_chip
*chip
, u8 reg
,
130 unsigned offset
, bool *bit
)
132 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
138 ret
= abx500_get_register_interruptible(pct
->dev
,
139 AB8500_MISC
, reg
, &val
);
141 *bit
= !!(val
& BIT(pos
));
145 "%s read reg =%x, offset=%x failed\n",
146 __func__
, reg
, offset
);
151 static int abx500_gpio_set_bits(struct gpio_chip
*chip
, u8 reg
,
152 unsigned offset
, int val
)
154 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
159 ret
= abx500_mask_and_set_register_interruptible(pct
->dev
,
160 AB8500_MISC
, reg
, 1 << pos
, val
<< pos
);
162 dev_err(pct
->dev
, "%s write failed\n", __func__
);
166 * abx500_gpio_get() - Get the particular GPIO value
168 * @offset: GPIO number to read
170 static int abx500_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
172 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
176 ret
= abx500_gpio_get_bit(chip
, AB8500_GPIO_IN1_REG
,
179 dev_err(pct
->dev
, "%s failed\n", __func__
);
185 static void abx500_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
187 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
190 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_OUT1_REG
, offset
, val
);
192 dev_err(pct
->dev
, "%s write failed\n", __func__
);
195 static int abx500_config_pull_updown(struct abx500_pinctrl
*pct
,
196 int offset
, enum abx500_gpio_pull_updown val
)
200 struct pullud
*pullud
;
202 if (!pct
->soc
->pullud
) {
203 dev_err(pct
->dev
, "%s AB chip doesn't support pull up/down feature",
209 pullud
= pct
->soc
->pullud
;
211 if ((offset
< pullud
->first_pin
)
212 || (offset
> pullud
->last_pin
)) {
219 ret
= abx500_mask_and_set_register_interruptible(pct
->dev
,
220 AB8500_MISC
, AB8540_GPIO_PULL_UPDOWN_REG
,
221 AB8540_GPIO_PULL_UPDOWN_MASK
<< pos
, val
<< pos
);
225 dev_err(pct
->dev
, "%s failed (%d)\n", __func__
, ret
);
229 static int abx500_gpio_direction_output(struct gpio_chip
*chip
,
233 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
234 struct pullud
*pullud
= pct
->soc
->pullud
;
237 /* set direction as output */
238 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_DIR1_REG
, offset
, 1);
242 /* disable pull down */
243 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_PUD1_REG
, offset
, 1);
247 /* if supported, disable both pull down and pull up */
249 if (pullud
&& gpio
>= pullud
->first_pin
&& gpio
<= pullud
->last_pin
) {
250 ret
= abx500_config_pull_updown(pct
,
252 ABX500_GPIO_PULL_NONE
);
256 /* set the output as 1 or 0 */
257 return abx500_gpio_set_bits(chip
, AB8500_GPIO_OUT1_REG
, offset
, val
);
260 static int abx500_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
262 /* set the register as input */
263 return abx500_gpio_set_bits(chip
, AB8500_GPIO_DIR1_REG
, offset
, 0);
266 static int abx500_gpio_to_irq(struct gpio_chip
*chip
, unsigned offset
)
268 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
269 int base
= pct
->irq_base
;
272 for (i
= 0; i
< pct
->irq_cluster_size
; i
++) {
273 struct abx500_gpio_irq_cluster
*cluster
=
274 &pct
->irq_cluster
[i
];
276 if (offset
>= cluster
->start
&& offset
<= cluster
->end
)
277 return base
+ offset
- cluster
->start
;
279 /* Advance by the number of gpios in this cluster */
280 base
+= cluster
->end
+ cluster
->offset
- cluster
->start
+ 1;
286 static int abx500_set_mode(struct pinctrl_dev
*pctldev
, struct gpio_chip
*chip
,
287 unsigned gpio
, int alt_setting
)
289 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
290 struct alternate_functions af
= pct
->soc
->alternate_functions
[gpio
];
294 const char *modes
[] = {
295 [ABX500_DEFAULT
] = "default",
296 [ABX500_ALT_A
] = "altA",
297 [ABX500_ALT_B
] = "altB",
298 [ABX500_ALT_C
] = "altC",
302 if (((alt_setting
== ABX500_ALT_A
) && (af
.gpiosel_bit
== UNUSED
)) ||
303 ((alt_setting
== ABX500_ALT_B
) && (af
.alt_bit1
== UNUSED
)) ||
304 ((alt_setting
== ABX500_ALT_C
) && (af
.alt_bit2
== UNUSED
))) {
305 dev_dbg(pct
->dev
, "pin %d doesn't support %s mode\n", gpio
,
310 /* on ABx5xx, there is no GPIO0, so adjust the offset */
312 switch (alt_setting
) {
315 * for ABx5xx family, default mode is always selected by
316 * writing 0 to GPIOSELx register, except for pins which
317 * support at least ALT_B mode, default mode is selected
318 * by writing 1 to GPIOSELx register
321 if (af
.alt_bit1
!= UNUSED
)
324 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_SEL1_REG
,
329 * for ABx5xx family, alt_a mode is always selected by
330 * writing 1 to GPIOSELx register, except for pins which
331 * support at least ALT_B mode, alt_a mode is selected
332 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
335 if (af
.alt_bit1
!= UNUSED
) {
336 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_SEL1_REG
,
338 ret
= abx500_gpio_set_bits(chip
,
339 AB8500_GPIO_ALTFUN_REG
,
341 !!(af
.alta_val
&& BIT(0)));
342 if (af
.alt_bit2
!= UNUSED
)
343 ret
= abx500_gpio_set_bits(chip
,
344 AB8500_GPIO_ALTFUN_REG
,
346 !!(af
.alta_val
&& BIT(1)));
348 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_SEL1_REG
,
352 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_SEL1_REG
,
354 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_ALTFUN_REG
,
355 af
.alt_bit1
, !!(af
.altb_val
&& BIT(0)));
356 if (af
.alt_bit2
!= UNUSED
)
357 ret
= abx500_gpio_set_bits(chip
,
358 AB8500_GPIO_ALTFUN_REG
,
360 !!(af
.altb_val
&& BIT(1)));
363 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_SEL1_REG
,
365 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_ALTFUN_REG
,
366 af
.alt_bit2
, !!(af
.altc_val
&& BIT(0)));
367 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_ALTFUN_REG
,
368 af
.alt_bit2
, !!(af
.altc_val
&& BIT(1)));
372 dev_dbg(pct
->dev
, "unknow alt_setting %d\n", alt_setting
);
378 static u8
abx500_get_mode(struct pinctrl_dev
*pctldev
, struct gpio_chip
*chip
,
385 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
386 struct alternate_functions af
= pct
->soc
->alternate_functions
[gpio
];
389 * if gpiosel_bit is set to unused,
390 * it means no GPIO or special case
392 if (af
.gpiosel_bit
== UNUSED
)
393 return ABX500_DEFAULT
;
395 /* read GpioSelx register */
396 abx500_gpio_get_bit(chip
, AB8500_GPIO_SEL1_REG
+ (gpio
/ 8),
397 af
.gpiosel_bit
, &bit_mode
);
401 if ((af
.alt_bit1
< UNUSED
) || (af
.alt_bit1
> 7) ||
402 (af
.alt_bit2
< UNUSED
) || (af
.alt_bit2
> 7)) {
404 "alt_bitX value not in correct range (-1 to 7)\n");
407 /* if alt_bit2 is used, alt_bit1 must be used too */
408 if ((af
.alt_bit2
!= UNUSED
) && (af
.alt_bit1
== UNUSED
)) {
410 "if alt_bit2 is used, alt_bit1 can't be unused\n");
414 /* check if pin use AlternateFunction register */
415 if ((af
.alt_bit1
== UNUSED
) && (af
.alt_bit1
== UNUSED
))
418 * if pin GPIOSEL bit is set and pin supports alternate function,
419 * it means DEFAULT mode
422 return ABX500_DEFAULT
;
424 * pin use the AlternatFunction register
425 * read alt_bit1 value
427 abx500_gpio_get_bit(chip
, AB8500_GPIO_ALTFUN_REG
,
428 af
.alt_bit1
, &alt_bit1
);
430 if (af
.alt_bit2
!= UNUSED
)
431 /* read alt_bit2 value */
432 abx500_gpio_get_bit(chip
, AB8500_GPIO_ALTFUN_REG
, af
.alt_bit2
,
437 mode
= (alt_bit2
<< 1) + alt_bit1
;
438 if (mode
== af
.alta_val
)
440 else if (mode
== af
.altb_val
)
446 #ifdef CONFIG_DEBUG_FS
448 #include <linux/seq_file.h>
450 static void abx500_gpio_dbg_show_one(struct seq_file
*s
,
451 struct pinctrl_dev
*pctldev
, struct gpio_chip
*chip
,
452 unsigned offset
, unsigned gpio
)
454 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
455 const char *label
= gpiochip_is_requested(chip
, offset
- 1);
456 u8 gpio_offset
= offset
- 1;
460 const char *modes
[] = {
461 [ABX500_DEFAULT
] = "default",
462 [ABX500_ALT_A
] = "altA",
463 [ABX500_ALT_B
] = "altB",
464 [ABX500_ALT_C
] = "altC",
467 abx500_gpio_get_bit(chip
, AB8500_GPIO_DIR1_REG
, gpio_offset
, &is_out
);
468 abx500_gpio_get_bit(chip
, AB8500_GPIO_PUD1_REG
, gpio_offset
, &pull
);
471 mode
= abx500_get_mode(pctldev
, chip
, offset
);
473 seq_printf(s
, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
474 gpio
, label
?: "(none)",
475 is_out
? "out" : "in ",
478 ? (chip
->get(chip
, offset
) ? "hi" : "lo")
480 : (pull
? "pull up" : "pull down"),
481 (mode
< 0) ? "unknown" : modes
[mode
]);
483 if (label
&& !is_out
) {
484 int irq
= gpio_to_irq(gpio
);
485 struct irq_desc
*desc
= irq_to_desc(irq
);
487 if (irq
>= 0 && desc
->action
) {
489 int irq_offset
= irq
- pct
->irq_base
;
491 if (pct
->rising
& BIT(irq_offset
))
492 trigger
= "edge-rising";
493 else if (pct
->falling
& BIT(irq_offset
))
494 trigger
= "edge-falling";
496 trigger
= "edge-undefined";
498 seq_printf(s
, " irq-%d %s", irq
, trigger
);
503 static void abx500_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
506 unsigned gpio
= chip
->base
;
507 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
508 struct pinctrl_dev
*pctldev
= pct
->pctldev
;
510 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
511 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
512 abx500_gpio_dbg_show_one(s
, pctldev
, chip
, i
+ 1, gpio
);
518 static inline void abx500_gpio_dbg_show_one(struct seq_file
*s
,
519 struct pinctrl_dev
*pctldev
,
520 struct gpio_chip
*chip
,
521 unsigned offset
, unsigned gpio
)
524 #define abx500_gpio_dbg_show NULL
527 int abx500_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
529 int gpio
= chip
->base
+ offset
;
531 return pinctrl_request_gpio(gpio
);
534 void abx500_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
536 int gpio
= chip
->base
+ offset
;
538 pinctrl_free_gpio(gpio
);
541 static struct gpio_chip abx500gpio_chip
= {
542 .label
= "abx500-gpio",
543 .owner
= THIS_MODULE
,
544 .request
= abx500_gpio_request
,
545 .free
= abx500_gpio_free
,
546 .direction_input
= abx500_gpio_direction_input
,
547 .get
= abx500_gpio_get
,
548 .direction_output
= abx500_gpio_direction_output
,
549 .set
= abx500_gpio_set
,
550 .to_irq
= abx500_gpio_to_irq
,
551 .dbg_show
= abx500_gpio_dbg_show
,
554 static unsigned int irq_to_rising(unsigned int irq
)
556 struct abx500_pinctrl
*pct
= irq_get_chip_data(irq
);
557 int offset
= irq
- pct
->irq_base
;
560 new_irq
= offset
* pct
->irq_gpio_factor
561 + pct
->irq_gpio_rising_offset
562 + pct
->parent
->irq_base
;
567 static unsigned int irq_to_falling(unsigned int irq
)
569 struct abx500_pinctrl
*pct
= irq_get_chip_data(irq
);
570 int offset
= irq
- pct
->irq_base
;
573 new_irq
= offset
* pct
->irq_gpio_factor
574 + pct
->irq_gpio_falling_offset
575 + pct
->parent
->irq_base
;
580 static unsigned int rising_to_irq(unsigned int irq
, void *dev
)
582 struct abx500_pinctrl
*pct
= dev
;
585 offset
= irq
- pct
->irq_gpio_rising_offset
586 - pct
->parent
->irq_base
;
587 new_irq
= (offset
/ pct
->irq_gpio_factor
)
593 static unsigned int falling_to_irq(unsigned int irq
, void *dev
)
595 struct abx500_pinctrl
*pct
= dev
;
598 offset
= irq
- pct
->irq_gpio_falling_offset
599 - pct
->parent
->irq_base
;
600 new_irq
= (offset
/ pct
->irq_gpio_factor
)
610 static irqreturn_t
handle_rising(int irq
, void *dev
)
613 handle_nested_irq(rising_to_irq(irq
, dev
));
617 static irqreturn_t
handle_falling(int irq
, void *dev
)
620 handle_nested_irq(falling_to_irq(irq
, dev
));
624 static void abx500_gpio_irq_lock(struct irq_data
*data
)
626 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
627 mutex_lock(&pct
->lock
);
630 static void abx500_gpio_irq_sync_unlock(struct irq_data
*data
)
632 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
633 unsigned int irq
= data
->irq
;
634 int offset
= irq
- pct
->irq_base
;
635 bool rising
= pct
->rising
& BIT(offset
);
636 bool falling
= pct
->falling
& BIT(offset
);
639 switch (pct
->irq_action
) {
642 ret
= request_threaded_irq(irq_to_rising(irq
),
644 IRQF_TRIGGER_RISING
| IRQF_NO_SUSPEND
,
645 "abx500-gpio-r", pct
);
647 ret
= request_threaded_irq(irq_to_falling(irq
),
648 NULL
, handle_falling
,
649 IRQF_TRIGGER_FALLING
| IRQF_NO_SUSPEND
,
650 "abx500-gpio-f", pct
);
654 free_irq(irq_to_rising(irq
), pct
);
656 free_irq(irq_to_falling(irq
), pct
);
660 disable_irq(irq_to_rising(irq
));
662 disable_irq(irq_to_falling(irq
));
666 enable_irq(irq_to_rising(irq
));
668 enable_irq(irq_to_falling(irq
));
673 pct
->irq_action
= NONE
;
674 pct
->rising
&= ~(BIT(offset
));
675 pct
->falling
&= ~(BIT(offset
));
676 mutex_unlock(&pct
->lock
);
680 static void abx500_gpio_irq_mask(struct irq_data
*data
)
682 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
683 pct
->irq_action
= MASK
;
686 static void abx500_gpio_irq_unmask(struct irq_data
*data
)
688 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
689 pct
->irq_action
= UNMASK
;
692 static int abx500_gpio_irq_set_type(struct irq_data
*data
, unsigned int type
)
694 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
695 unsigned int irq
= data
->irq
;
696 int offset
= irq
- pct
->irq_base
;
698 if (type
== IRQ_TYPE_EDGE_BOTH
) {
699 pct
->rising
= BIT(offset
);
700 pct
->falling
= BIT(offset
);
701 } else if (type
== IRQ_TYPE_EDGE_RISING
) {
702 pct
->rising
= BIT(offset
);
704 pct
->falling
= BIT(offset
);
709 static unsigned int abx500_gpio_irq_startup(struct irq_data
*data
)
711 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
712 pct
->irq_action
= STARTUP
;
716 static void abx500_gpio_irq_shutdown(struct irq_data
*data
)
718 struct abx500_pinctrl
*pct
= irq_data_get_irq_chip_data(data
);
719 pct
->irq_action
= SHUTDOWN
;
722 static struct irq_chip abx500_gpio_irq_chip
= {
723 .name
= "abx500-gpio",
724 .irq_startup
= abx500_gpio_irq_startup
,
725 .irq_shutdown
= abx500_gpio_irq_shutdown
,
726 .irq_bus_lock
= abx500_gpio_irq_lock
,
727 .irq_bus_sync_unlock
= abx500_gpio_irq_sync_unlock
,
728 .irq_mask
= abx500_gpio_irq_mask
,
729 .irq_unmask
= abx500_gpio_irq_unmask
,
730 .irq_set_type
= abx500_gpio_irq_set_type
,
733 static int abx500_gpio_irq_init(struct abx500_pinctrl
*pct
)
735 u32 base
= pct
->irq_base
;
738 for (irq
= base
; irq
< base
+ AB8500_NUM_VIR_GPIO_IRQ
; irq
++) {
739 irq_set_chip_data(irq
, pct
);
740 irq_set_chip_and_handler(irq
, &abx500_gpio_irq_chip
,
742 irq_set_nested_thread(irq
, 1);
744 set_irq_flags(irq
, IRQF_VALID
);
746 irq_set_noprobe(irq
);
753 static void abx500_gpio_irq_remove(struct abx500_pinctrl
*pct
)
755 int base
= pct
->irq_base
;
758 for (irq
= base
; irq
< base
+ AB8500_NUM_VIR_GPIO_IRQ
; irq
++) {
760 set_irq_flags(irq
, 0);
762 irq_set_chip_and_handler(irq
, NULL
, NULL
);
763 irq_set_chip_data(irq
, NULL
);
767 static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev
*pctldev
)
769 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
771 return pct
->soc
->nfunctions
;
774 static const char *abx500_pmx_get_func_name(struct pinctrl_dev
*pctldev
,
777 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
779 return pct
->soc
->functions
[function
].name
;
782 static int abx500_pmx_get_func_groups(struct pinctrl_dev
*pctldev
,
784 const char * const **groups
,
785 unsigned * const num_groups
)
787 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
789 *groups
= pct
->soc
->functions
[function
].groups
;
790 *num_groups
= pct
->soc
->functions
[function
].ngroups
;
795 static void abx500_disable_lazy_irq(struct gpio_chip
*chip
, unsigned gpio
)
797 struct abx500_pinctrl
*pct
= to_abx500_pinctrl(chip
);
804 * check if gpio has interrupt capability and convert
806 * On ABx5xx, there is no GPIO0, GPIO1 is the
807 * first one, so adjust gpio number
810 irq
= gpio_to_irq(gpio
+ chip
->base
);
814 offset
= irq
- pct
->irq_base
;
815 rising
= pct
->rising
& BIT(offset
);
816 falling
= pct
->falling
& BIT(offset
);
819 if (!rising
&& !falling
)
823 disable_irq(irq_to_rising(irq
));
824 free_irq(irq_to_rising(irq
), pct
);
827 disable_irq(irq_to_falling(irq
));
828 free_irq(irq_to_falling(irq
), pct
);
832 static int abx500_pmx_enable(struct pinctrl_dev
*pctldev
, unsigned function
,
835 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
836 struct gpio_chip
*chip
= &pct
->chip
;
837 const struct abx500_pingroup
*g
;
841 g
= &pct
->soc
->groups
[group
];
842 if (g
->altsetting
< 0)
845 dev_dbg(pct
->dev
, "enable group %s, %u pins\n", g
->name
, g
->npins
);
847 for (i
= 0; i
< g
->npins
; i
++) {
848 dev_dbg(pct
->dev
, "setting pin %d to altsetting %d\n",
849 g
->pins
[i
], g
->altsetting
);
851 abx500_disable_lazy_irq(chip
, g
->pins
[i
]);
852 ret
= abx500_set_mode(pctldev
, chip
, g
->pins
[i
], g
->altsetting
);
857 static void abx500_pmx_disable(struct pinctrl_dev
*pctldev
,
858 unsigned function
, unsigned group
)
860 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
861 const struct abx500_pingroup
*g
;
863 g
= &pct
->soc
->groups
[group
];
864 if (g
->altsetting
< 0)
867 /* FIXME: poke out the mux, set the pin to some default state? */
868 dev_dbg(pct
->dev
, "disable group %s, %u pins\n", g
->name
, g
->npins
);
871 int abx500_gpio_request_enable(struct pinctrl_dev
*pctldev
,
872 struct pinctrl_gpio_range
*range
,
875 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
876 const struct abx500_pinrange
*p
;
881 * Different ranges have different ways to enable GPIO function on a
882 * pin, so refer back to our local range type, where we handily define
883 * what altfunc enables GPIO for a certain pin.
885 for (i
= 0; i
< pct
->soc
->gpio_num_ranges
; i
++) {
886 p
= &pct
->soc
->gpio_ranges
[i
];
887 if ((offset
>= p
->offset
) &&
888 (offset
< (p
->offset
+ p
->npins
)))
892 if (i
== pct
->soc
->gpio_num_ranges
) {
893 dev_err(pct
->dev
, "%s failed to locate range\n", __func__
);
897 dev_dbg(pct
->dev
, "enable GPIO by altfunc %d at gpio %d\n",
900 ret
= abx500_set_mode(pct
->pctldev
, &pct
->chip
,
903 dev_err(pct
->dev
, "%s setting altfunc failed\n", __func__
);
910 static void abx500_gpio_disable_free(struct pinctrl_dev
*pctldev
,
911 struct pinctrl_gpio_range
*range
,
916 static struct pinmux_ops abx500_pinmux_ops
= {
917 .get_functions_count
= abx500_pmx_get_funcs_cnt
,
918 .get_function_name
= abx500_pmx_get_func_name
,
919 .get_function_groups
= abx500_pmx_get_func_groups
,
920 .enable
= abx500_pmx_enable
,
921 .disable
= abx500_pmx_disable
,
922 .gpio_request_enable
= abx500_gpio_request_enable
,
923 .gpio_disable_free
= abx500_gpio_disable_free
,
926 static int abx500_get_groups_cnt(struct pinctrl_dev
*pctldev
)
928 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
930 return pct
->soc
->ngroups
;
933 static const char *abx500_get_group_name(struct pinctrl_dev
*pctldev
,
936 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
938 return pct
->soc
->groups
[selector
].name
;
941 static int abx500_get_group_pins(struct pinctrl_dev
*pctldev
,
943 const unsigned **pins
,
946 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
948 *pins
= pct
->soc
->groups
[selector
].pins
;
949 *num_pins
= pct
->soc
->groups
[selector
].npins
;
953 static void abx500_pin_dbg_show(struct pinctrl_dev
*pctldev
,
954 struct seq_file
*s
, unsigned offset
)
956 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
957 struct gpio_chip
*chip
= &pct
->chip
;
959 abx500_gpio_dbg_show_one(s
, pctldev
, chip
, offset
,
960 chip
->base
+ offset
- 1);
963 static struct pinctrl_ops abx500_pinctrl_ops
= {
964 .get_groups_count
= abx500_get_groups_cnt
,
965 .get_group_name
= abx500_get_group_name
,
966 .get_group_pins
= abx500_get_group_pins
,
967 .pin_dbg_show
= abx500_pin_dbg_show
,
970 int abx500_pin_config_get(struct pinctrl_dev
*pctldev
,
972 unsigned long *config
)
974 /* Not implemented */
978 int abx500_pin_config_set(struct pinctrl_dev
*pctldev
,
980 unsigned long config
)
982 struct abx500_pinctrl
*pct
= pinctrl_dev_get_drvdata(pctldev
);
983 struct pullud
*pullud
= pct
->soc
->pullud
;
984 struct gpio_chip
*chip
= &pct
->chip
;
987 enum pin_config_param param
= pinconf_to_config_param(config
);
988 enum pin_config_param argument
= pinconf_to_config_argument(config
);
990 dev_dbg(chip
->dev
, "pin %d [%#lx]: %s %s\n",
991 pin
, config
, (param
== PIN_CONFIG_OUTPUT
) ? "output " : "input",
992 (param
== PIN_CONFIG_OUTPUT
) ? (argument
? "high" : "low") :
993 (argument
? "pull up" : "pull down"));
994 /* on ABx500, there is no GPIO0, so adjust the offset */
998 case PIN_CONFIG_BIAS_PULL_DOWN
:
1000 * if argument = 1 set the pull down
1001 * else clear the pull down
1003 ret
= abx500_gpio_direction_input(chip
, offset
);
1005 * Some chips only support pull down, while some actually
1006 * support both pull up and pull down. Such chips have
1007 * a "pullud" range specified for the pins that support
1008 * both features. If the pin is not within that range, we
1009 * fall back to the old bit set that only support pull down.
1012 pin
>= pullud
->first_pin
&&
1013 pin
<= pullud
->last_pin
)
1014 ret
= abx500_config_pull_updown(pct
,
1016 argument
? ABX500_GPIO_PULL_DOWN
: ABX500_GPIO_PULL_NONE
);
1018 /* Chip only supports pull down */
1019 ret
= abx500_gpio_set_bits(chip
, AB8500_GPIO_PUD1_REG
,
1020 offset
, argument
? 0 : 1);
1022 case PIN_CONFIG_OUTPUT
:
1023 ret
= abx500_gpio_direction_output(chip
, offset
, argument
);
1026 dev_err(chip
->dev
, "illegal configuration requested\n");
1032 static struct pinconf_ops abx500_pinconf_ops
= {
1033 .pin_config_get
= abx500_pin_config_get
,
1034 .pin_config_set
= abx500_pin_config_set
,
1037 static struct pinctrl_desc abx500_pinctrl_desc
= {
1038 .name
= "pinctrl-abx500",
1039 .pctlops
= &abx500_pinctrl_ops
,
1040 .pmxops
= &abx500_pinmux_ops
,
1041 .confops
= &abx500_pinconf_ops
,
1042 .owner
= THIS_MODULE
,
1045 static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data
*soc
)
1047 unsigned int lowest
= 0;
1048 unsigned int highest
= 0;
1049 unsigned int npins
= 0;
1053 * Compute number of GPIOs from the last SoC gpio range descriptors
1054 * These ranges may include "holes" but the GPIO number space shall
1055 * still be homogeneous, so we need to detect and account for any
1056 * such holes so that these are included in the number of GPIO pins.
1058 for (i
= 0; i
< soc
->gpio_num_ranges
; i
++) {
1061 const struct abx500_pinrange
*p
;
1063 p
= &soc
->gpio_ranges
[i
];
1065 gend
= p
->offset
+ p
->npins
- 1;
1068 /* First iteration, set start values */
1072 if (gstart
< lowest
)
1078 /* this gives the absolute number of pins */
1079 npins
= highest
- lowest
+ 1;
1083 static int abx500_gpio_probe(struct platform_device
*pdev
)
1085 struct ab8500_platform_data
*abx500_pdata
=
1086 dev_get_platdata(pdev
->dev
.parent
);
1087 struct abx500_gpio_platform_data
*pdata
;
1088 struct abx500_pinctrl
*pct
;
1089 const struct platform_device_id
*platid
= platform_get_device_id(pdev
);
1093 pdata
= abx500_pdata
->gpio
;
1095 dev_err(&pdev
->dev
, "gpio platform data missing\n");
1099 pct
= devm_kzalloc(&pdev
->dev
, sizeof(struct abx500_pinctrl
),
1103 "failed to allocate memory for pct\n");
1107 pct
->dev
= &pdev
->dev
;
1108 pct
->parent
= dev_get_drvdata(pdev
->dev
.parent
);
1109 pct
->chip
= abx500gpio_chip
;
1110 pct
->chip
.dev
= &pdev
->dev
;
1111 pct
->chip
.base
= pdata
->gpio_base
;
1112 pct
->irq_base
= pdata
->irq_base
;
1114 /* initialize the lock */
1115 mutex_init(&pct
->lock
);
1117 /* Poke in other ASIC variants here */
1118 switch (platid
->driver_data
) {
1119 case PINCTRL_AB8500
:
1120 abx500_pinctrl_ab8500_init(&pct
->soc
);
1122 case PINCTRL_AB9540
:
1123 abx500_pinctrl_ab9540_init(&pct
->soc
);
1125 case PINCTRL_AB8505
:
1126 abx500_pinctrl_ab8505_init(&pct
->soc
);
1129 dev_err(&pdev
->dev
, "Unsupported pinctrl sub driver (%d)\n",
1130 (int) platid
->driver_data
);
1135 dev_err(&pdev
->dev
, "Invalid SOC data\n");
1139 pct
->chip
.ngpio
= abx500_get_gpio_num(pct
->soc
);
1140 pct
->irq_cluster
= pct
->soc
->gpio_irq_cluster
;
1141 pct
->irq_cluster_size
= pct
->soc
->ngpio_irq_cluster
;
1142 pct
->irq_gpio_rising_offset
= pct
->soc
->irq_gpio_rising_offset
;
1143 pct
->irq_gpio_falling_offset
= pct
->soc
->irq_gpio_falling_offset
;
1144 pct
->irq_gpio_factor
= pct
->soc
->irq_gpio_factor
;
1146 ret
= abx500_gpio_irq_init(pct
);
1149 ret
= gpiochip_add(&pct
->chip
);
1151 dev_err(&pdev
->dev
, "unable to add gpiochip: %d\n",
1155 dev_info(&pdev
->dev
, "added gpiochip\n");
1157 abx500_pinctrl_desc
.pins
= pct
->soc
->pins
;
1158 abx500_pinctrl_desc
.npins
= pct
->soc
->npins
;
1159 pct
->pctldev
= pinctrl_register(&abx500_pinctrl_desc
, &pdev
->dev
, pct
);
1160 if (!pct
->pctldev
) {
1162 "could not register abx500 pinctrl driver\n");
1165 dev_info(&pdev
->dev
, "registered pin controller\n");
1167 /* We will handle a range of GPIO pins */
1168 for (i
= 0; i
< pct
->soc
->gpio_num_ranges
; i
++) {
1169 const struct abx500_pinrange
*p
= &pct
->soc
->gpio_ranges
[i
];
1171 ret
= gpiochip_add_pin_range(&pct
->chip
,
1172 dev_name(&pdev
->dev
),
1173 p
->offset
- 1, p
->offset
, p
->npins
);
1178 platform_set_drvdata(pdev
, pct
);
1179 dev_info(&pdev
->dev
, "initialized abx500 pinctrl driver\n");
1184 ret
= gpiochip_remove(&pct
->chip
);
1186 dev_info(&pdev
->dev
, "failed to remove gpiochip\n");
1188 abx500_gpio_irq_remove(pct
);
1190 mutex_destroy(&pct
->lock
);
1195 * abx500_gpio_remove() - remove Ab8500-gpio driver
1196 * @pdev : Platform device registered
1198 static int abx500_gpio_remove(struct platform_device
*pdev
)
1200 struct abx500_pinctrl
*pct
= platform_get_drvdata(pdev
);
1203 ret
= gpiochip_remove(&pct
->chip
);
1205 dev_err(pct
->dev
, "unable to remove gpiochip: %d\n",
1210 mutex_destroy(&pct
->lock
);
1215 static const struct platform_device_id abx500_pinctrl_id
[] = {
1216 { "pinctrl-ab8500", PINCTRL_AB8500
},
1217 { "pinctrl-ab8540", PINCTRL_AB8540
},
1218 { "pinctrl-ab9540", PINCTRL_AB9540
},
1219 { "pinctrl-ab8505", PINCTRL_AB8505
},
1223 static struct platform_driver abx500_gpio_driver
= {
1225 .name
= "abx500-gpio",
1226 .owner
= THIS_MODULE
,
1228 .probe
= abx500_gpio_probe
,
1229 .remove
= abx500_gpio_remove
,
1230 .id_table
= abx500_pinctrl_id
,
1233 static int __init
abx500_gpio_init(void)
1235 return platform_driver_register(&abx500_gpio_driver
);
1237 core_initcall(abx500_gpio_init
);
1239 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1240 MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1241 MODULE_ALIAS("platform:abx500-gpio");
1242 MODULE_LICENSE("GPL v2");