]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/pinctrl/pinctrl-amd.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'drm-intel-fixes-2017-01-05' of git://anongit.freedesktop.org/git/drm-intel
[mirror_ubuntu-zesty-kernel.git] / drivers / pinctrl / pinctrl-amd.c
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
37
38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
39 {
40 unsigned long flags;
41 u32 pin_reg;
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
43
44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
49
50 return 0;
51 }
52
53 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
54 int value)
55 {
56 u32 pin_reg;
57 unsigned long flags;
58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
59
60 spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
63 if (value)
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
65 else
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 spin_unlock_irqrestore(&gpio_dev->lock, flags);
69
70 return 0;
71 }
72
73 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
74 {
75 u32 pin_reg;
76 unsigned long flags;
77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
78
79 spin_lock_irqsave(&gpio_dev->lock, flags);
80 pin_reg = readl(gpio_dev->base + offset * 4);
81 spin_unlock_irqrestore(&gpio_dev->lock, flags);
82
83 return !!(pin_reg & BIT(PIN_STS_OFF));
84 }
85
86 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
87 {
88 u32 pin_reg;
89 unsigned long flags;
90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
91
92 spin_lock_irqsave(&gpio_dev->lock, flags);
93 pin_reg = readl(gpio_dev->base + offset * 4);
94 if (value)
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
96 else
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
99 spin_unlock_irqrestore(&gpio_dev->lock, flags);
100 }
101
102 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
103 unsigned debounce)
104 {
105 u32 time;
106 u32 pin_reg;
107 int ret = 0;
108 unsigned long flags;
109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
110
111 spin_lock_irqsave(&gpio_dev->lock, flags);
112 pin_reg = readl(gpio_dev->base + offset * 4);
113
114 if (debounce) {
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
117 /*
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
120 Time
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
125 */
126
127 if (debounce < 61) {
128 pin_reg |= 1;
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else {
152 pin_reg &= ~DB_CNTRl_MASK;
153 ret = -EINVAL;
154 }
155 } else {
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
160 }
161 writel(pin_reg, gpio_dev->base + offset * 4);
162 spin_unlock_irqrestore(&gpio_dev->lock, flags);
163
164 return ret;
165 }
166
167 #ifdef CONFIG_DEBUG_FS
168 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
169 {
170 u32 pin_reg;
171 unsigned long flags;
172 unsigned int bank, i, pin_num;
173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
174
175 char *level_trig;
176 char *active_level;
177 char *interrupt_enable;
178 char *interrupt_mask;
179 char *wake_cntrl0;
180 char *wake_cntrl1;
181 char *wake_cntrl2;
182 char *pin_sts;
183 char *pull_up_sel;
184 char *pull_up_enable;
185 char *pull_down_enable;
186 char *output_value;
187 char *output_enable;
188
189 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
190 seq_printf(s, "GPIO bank%d\t", bank);
191
192 switch (bank) {
193 case 0:
194 i = 0;
195 pin_num = AMD_GPIO_PINS_BANK0;
196 break;
197 case 1:
198 i = 64;
199 pin_num = AMD_GPIO_PINS_BANK1 + i;
200 break;
201 case 2:
202 i = 128;
203 pin_num = AMD_GPIO_PINS_BANK2 + i;
204 break;
205 }
206
207 for (; i < pin_num; i++) {
208 seq_printf(s, "pin%d\t", i);
209 spin_lock_irqsave(&gpio_dev->lock, flags);
210 pin_reg = readl(gpio_dev->base + i * 4);
211 spin_unlock_irqrestore(&gpio_dev->lock, flags);
212
213 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
214 interrupt_enable = "interrupt is enabled|";
215
216 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
217 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
218 active_level = "Active low|";
219 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
220 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
221 active_level = "Active high|";
222 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
223 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
224 active_level = "Active on both|";
225 else
226 active_level = "Unknow Active level|";
227
228 if (pin_reg & BIT(LEVEL_TRIG_OFF))
229 level_trig = "Level trigger|";
230 else
231 level_trig = "Edge trigger|";
232
233 } else {
234 interrupt_enable =
235 "interrupt is disabled|";
236 active_level = " ";
237 level_trig = " ";
238 }
239
240 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
241 interrupt_mask =
242 "interrupt is unmasked|";
243 else
244 interrupt_mask =
245 "interrupt is masked|";
246
247 if (pin_reg & BIT(WAKE_CNTRL_OFF))
248 wake_cntrl0 = "enable wakeup in S0i3 state|";
249 else
250 wake_cntrl0 = "disable wakeup in S0i3 state|";
251
252 if (pin_reg & BIT(WAKE_CNTRL_OFF))
253 wake_cntrl1 = "enable wakeup in S3 state|";
254 else
255 wake_cntrl1 = "disable wakeup in S3 state|";
256
257 if (pin_reg & BIT(WAKE_CNTRL_OFF))
258 wake_cntrl2 = "enable wakeup in S4/S5 state|";
259 else
260 wake_cntrl2 = "disable wakeup in S4/S5 state|";
261
262 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
263 pull_up_enable = "pull-up is enabled|";
264 if (pin_reg & BIT(PULL_UP_SEL_OFF))
265 pull_up_sel = "8k pull-up|";
266 else
267 pull_up_sel = "4k pull-up|";
268 } else {
269 pull_up_enable = "pull-up is disabled|";
270 pull_up_sel = " ";
271 }
272
273 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
274 pull_down_enable = "pull-down is enabled|";
275 else
276 pull_down_enable = "Pull-down is disabled|";
277
278 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
279 pin_sts = " ";
280 output_enable = "output is enabled|";
281 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
282 output_value = "output is high|";
283 else
284 output_value = "output is low|";
285 } else {
286 output_enable = "output is disabled|";
287 output_value = " ";
288
289 if (pin_reg & BIT(PIN_STS_OFF))
290 pin_sts = "input is high|";
291 else
292 pin_sts = "input is low|";
293 }
294
295 seq_printf(s, "%s %s %s %s %s %s\n"
296 " %s %s %s %s %s %s %s 0x%x\n",
297 level_trig, active_level, interrupt_enable,
298 interrupt_mask, wake_cntrl0, wake_cntrl1,
299 wake_cntrl2, pin_sts, pull_up_sel,
300 pull_up_enable, pull_down_enable,
301 output_value, output_enable, pin_reg);
302 }
303 }
304 }
305 #else
306 #define amd_gpio_dbg_show NULL
307 #endif
308
309 static void amd_gpio_irq_enable(struct irq_data *d)
310 {
311 u32 pin_reg;
312 unsigned long flags;
313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
314 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
315
316 spin_lock_irqsave(&gpio_dev->lock, flags);
317 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
318 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
319 pin_reg |= BIT(INTERRUPT_MASK_OFF);
320 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
321 spin_unlock_irqrestore(&gpio_dev->lock, flags);
322 }
323
324 static void amd_gpio_irq_disable(struct irq_data *d)
325 {
326 u32 pin_reg;
327 unsigned long flags;
328 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
329 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
330
331 spin_lock_irqsave(&gpio_dev->lock, flags);
332 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
333 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
334 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
335 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
336 spin_unlock_irqrestore(&gpio_dev->lock, flags);
337 }
338
339 static void amd_gpio_irq_mask(struct irq_data *d)
340 {
341 u32 pin_reg;
342 unsigned long flags;
343 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
344 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
345
346 spin_lock_irqsave(&gpio_dev->lock, flags);
347 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
348 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
349 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
350 spin_unlock_irqrestore(&gpio_dev->lock, flags);
351 }
352
353 static void amd_gpio_irq_unmask(struct irq_data *d)
354 {
355 u32 pin_reg;
356 unsigned long flags;
357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
358 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
359
360 spin_lock_irqsave(&gpio_dev->lock, flags);
361 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
362 pin_reg |= BIT(INTERRUPT_MASK_OFF);
363 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
364 spin_unlock_irqrestore(&gpio_dev->lock, flags);
365 }
366
367 static void amd_gpio_irq_eoi(struct irq_data *d)
368 {
369 u32 reg;
370 unsigned long flags;
371 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
372 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
373
374 spin_lock_irqsave(&gpio_dev->lock, flags);
375 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
376 reg |= EOI_MASK;
377 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
378 spin_unlock_irqrestore(&gpio_dev->lock, flags);
379 }
380
381 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
382 {
383 int ret = 0;
384 u32 pin_reg;
385 unsigned long flags, irq_flags;
386 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
387 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
388
389 spin_lock_irqsave(&gpio_dev->lock, flags);
390 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
391
392 /* Ignore the settings coming from the client and
393 * read the values from the ACPI tables
394 * while setting the trigger type
395 */
396
397 irq_flags = irq_get_trigger_type(d->irq);
398 if (irq_flags != IRQ_TYPE_NONE)
399 type = irq_flags;
400
401 switch (type & IRQ_TYPE_SENSE_MASK) {
402 case IRQ_TYPE_EDGE_RISING:
403 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
404 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
405 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
406 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
407 irq_set_handler_locked(d, handle_edge_irq);
408 break;
409
410 case IRQ_TYPE_EDGE_FALLING:
411 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
412 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
413 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
414 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
415 irq_set_handler_locked(d, handle_edge_irq);
416 break;
417
418 case IRQ_TYPE_EDGE_BOTH:
419 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
421 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
423 irq_set_handler_locked(d, handle_edge_irq);
424 break;
425
426 case IRQ_TYPE_LEVEL_HIGH:
427 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
429 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
430 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
431 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
432 irq_set_handler_locked(d, handle_level_irq);
433 break;
434
435 case IRQ_TYPE_LEVEL_LOW:
436 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
437 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
438 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
439 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
440 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
441 irq_set_handler_locked(d, handle_level_irq);
442 break;
443
444 case IRQ_TYPE_NONE:
445 break;
446
447 default:
448 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
449 ret = -EINVAL;
450 }
451
452 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
453 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
454 spin_unlock_irqrestore(&gpio_dev->lock, flags);
455
456 return ret;
457 }
458
459 static void amd_irq_ack(struct irq_data *d)
460 {
461 /*
462 * based on HW design,there is no need to ack HW
463 * before handle current irq. But this routine is
464 * necessary for handle_edge_irq
465 */
466 }
467
468 static struct irq_chip amd_gpio_irqchip = {
469 .name = "amd_gpio",
470 .irq_ack = amd_irq_ack,
471 .irq_enable = amd_gpio_irq_enable,
472 .irq_disable = amd_gpio_irq_disable,
473 .irq_mask = amd_gpio_irq_mask,
474 .irq_unmask = amd_gpio_irq_unmask,
475 .irq_eoi = amd_gpio_irq_eoi,
476 .irq_set_type = amd_gpio_irq_set_type,
477 };
478
479 static void amd_gpio_irq_handler(struct irq_desc *desc)
480 {
481 u32 i;
482 u32 off;
483 u32 reg;
484 u32 pin_reg;
485 u64 reg64;
486 int handled = 0;
487 unsigned int irq;
488 unsigned long flags;
489 struct irq_chip *chip = irq_desc_get_chip(desc);
490 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
491 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
492
493 chained_irq_enter(chip, desc);
494 /*enable GPIO interrupt again*/
495 spin_lock_irqsave(&gpio_dev->lock, flags);
496 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
497 reg64 = reg;
498 reg64 = reg64 << 32;
499
500 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
501 reg64 |= reg;
502 spin_unlock_irqrestore(&gpio_dev->lock, flags);
503
504 /*
505 * first 46 bits indicates interrupt status.
506 * one bit represents four interrupt sources.
507 */
508 for (off = 0; off < 46 ; off++) {
509 if (reg64 & BIT(off)) {
510 for (i = 0; i < 4; i++) {
511 pin_reg = readl(gpio_dev->base +
512 (off * 4 + i) * 4);
513 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
514 (pin_reg & BIT(WAKE_STS_OFF))) {
515 irq = irq_find_mapping(gc->irqdomain,
516 off * 4 + i);
517 generic_handle_irq(irq);
518 writel(pin_reg,
519 gpio_dev->base
520 + (off * 4 + i) * 4);
521 handled++;
522 }
523 }
524 }
525 }
526
527 if (handled == 0)
528 handle_bad_irq(desc);
529
530 spin_lock_irqsave(&gpio_dev->lock, flags);
531 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
532 reg |= EOI_MASK;
533 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
534 spin_unlock_irqrestore(&gpio_dev->lock, flags);
535
536 chained_irq_exit(chip, desc);
537 }
538
539 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
540 {
541 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
542
543 return gpio_dev->ngroups;
544 }
545
546 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
547 unsigned group)
548 {
549 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
550
551 return gpio_dev->groups[group].name;
552 }
553
554 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
555 unsigned group,
556 const unsigned **pins,
557 unsigned *num_pins)
558 {
559 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
560
561 *pins = gpio_dev->groups[group].pins;
562 *num_pins = gpio_dev->groups[group].npins;
563 return 0;
564 }
565
566 static const struct pinctrl_ops amd_pinctrl_ops = {
567 .get_groups_count = amd_get_groups_count,
568 .get_group_name = amd_get_group_name,
569 .get_group_pins = amd_get_group_pins,
570 #ifdef CONFIG_OF
571 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
572 .dt_free_map = pinctrl_utils_free_map,
573 #endif
574 };
575
576 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
577 unsigned int pin,
578 unsigned long *config)
579 {
580 u32 pin_reg;
581 unsigned arg;
582 unsigned long flags;
583 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
584 enum pin_config_param param = pinconf_to_config_param(*config);
585
586 spin_lock_irqsave(&gpio_dev->lock, flags);
587 pin_reg = readl(gpio_dev->base + pin*4);
588 spin_unlock_irqrestore(&gpio_dev->lock, flags);
589 switch (param) {
590 case PIN_CONFIG_INPUT_DEBOUNCE:
591 arg = pin_reg & DB_TMR_OUT_MASK;
592 break;
593
594 case PIN_CONFIG_BIAS_PULL_DOWN:
595 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
596 break;
597
598 case PIN_CONFIG_BIAS_PULL_UP:
599 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
600 break;
601
602 case PIN_CONFIG_DRIVE_STRENGTH:
603 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
604 break;
605
606 default:
607 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
608 param);
609 return -ENOTSUPP;
610 }
611
612 *config = pinconf_to_config_packed(param, arg);
613
614 return 0;
615 }
616
617 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
618 unsigned long *configs, unsigned num_configs)
619 {
620 int i;
621 u32 arg;
622 int ret = 0;
623 u32 pin_reg;
624 unsigned long flags;
625 enum pin_config_param param;
626 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
627
628 spin_lock_irqsave(&gpio_dev->lock, flags);
629 for (i = 0; i < num_configs; i++) {
630 param = pinconf_to_config_param(configs[i]);
631 arg = pinconf_to_config_argument(configs[i]);
632 pin_reg = readl(gpio_dev->base + pin*4);
633
634 switch (param) {
635 case PIN_CONFIG_INPUT_DEBOUNCE:
636 pin_reg &= ~DB_TMR_OUT_MASK;
637 pin_reg |= arg & DB_TMR_OUT_MASK;
638 break;
639
640 case PIN_CONFIG_BIAS_PULL_DOWN:
641 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
642 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
643 break;
644
645 case PIN_CONFIG_BIAS_PULL_UP:
646 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
647 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
648 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
649 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
650 break;
651
652 case PIN_CONFIG_DRIVE_STRENGTH:
653 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
654 << DRV_STRENGTH_SEL_OFF);
655 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
656 << DRV_STRENGTH_SEL_OFF;
657 break;
658
659 default:
660 dev_err(&gpio_dev->pdev->dev,
661 "Invalid config param %04x\n", param);
662 ret = -ENOTSUPP;
663 }
664
665 writel(pin_reg, gpio_dev->base + pin*4);
666 }
667 spin_unlock_irqrestore(&gpio_dev->lock, flags);
668
669 return ret;
670 }
671
672 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
673 unsigned int group,
674 unsigned long *config)
675 {
676 const unsigned *pins;
677 unsigned npins;
678 int ret;
679
680 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
681 if (ret)
682 return ret;
683
684 if (amd_pinconf_get(pctldev, pins[0], config))
685 return -ENOTSUPP;
686
687 return 0;
688 }
689
690 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
691 unsigned group, unsigned long *configs,
692 unsigned num_configs)
693 {
694 const unsigned *pins;
695 unsigned npins;
696 int i, ret;
697
698 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
699 if (ret)
700 return ret;
701 for (i = 0; i < npins; i++) {
702 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
703 return -ENOTSUPP;
704 }
705 return 0;
706 }
707
708 static const struct pinconf_ops amd_pinconf_ops = {
709 .pin_config_get = amd_pinconf_get,
710 .pin_config_set = amd_pinconf_set,
711 .pin_config_group_get = amd_pinconf_group_get,
712 .pin_config_group_set = amd_pinconf_group_set,
713 };
714
715 static struct pinctrl_desc amd_pinctrl_desc = {
716 .pins = kerncz_pins,
717 .npins = ARRAY_SIZE(kerncz_pins),
718 .pctlops = &amd_pinctrl_ops,
719 .confops = &amd_pinconf_ops,
720 .owner = THIS_MODULE,
721 };
722
723 static int amd_gpio_probe(struct platform_device *pdev)
724 {
725 int ret = 0;
726 int irq_base;
727 struct resource *res;
728 struct amd_gpio *gpio_dev;
729
730 gpio_dev = devm_kzalloc(&pdev->dev,
731 sizeof(struct amd_gpio), GFP_KERNEL);
732 if (!gpio_dev)
733 return -ENOMEM;
734
735 spin_lock_init(&gpio_dev->lock);
736
737 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
738 if (!res) {
739 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
740 return -EINVAL;
741 }
742
743 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
744 resource_size(res));
745 if (!gpio_dev->base)
746 return -ENOMEM;
747
748 irq_base = platform_get_irq(pdev, 0);
749 if (irq_base < 0) {
750 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
751 return -EINVAL;
752 }
753
754 gpio_dev->pdev = pdev;
755 gpio_dev->gc.direction_input = amd_gpio_direction_input;
756 gpio_dev->gc.direction_output = amd_gpio_direction_output;
757 gpio_dev->gc.get = amd_gpio_get_value;
758 gpio_dev->gc.set = amd_gpio_set_value;
759 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
760 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
761
762 gpio_dev->gc.base = 0;
763 gpio_dev->gc.label = pdev->name;
764 gpio_dev->gc.owner = THIS_MODULE;
765 gpio_dev->gc.parent = &pdev->dev;
766 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
767 #if defined(CONFIG_OF_GPIO)
768 gpio_dev->gc.of_node = pdev->dev.of_node;
769 #endif
770
771 gpio_dev->groups = kerncz_groups;
772 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
773
774 amd_pinctrl_desc.name = dev_name(&pdev->dev);
775 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
776 gpio_dev);
777 if (IS_ERR(gpio_dev->pctrl)) {
778 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
779 return PTR_ERR(gpio_dev->pctrl);
780 }
781
782 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
783 if (ret)
784 return ret;
785
786 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
787 0, 0, TOTAL_NUMBER_OF_PINS);
788 if (ret) {
789 dev_err(&pdev->dev, "Failed to add pin range\n");
790 goto out2;
791 }
792
793 ret = gpiochip_irqchip_add(&gpio_dev->gc,
794 &amd_gpio_irqchip,
795 0,
796 handle_simple_irq,
797 IRQ_TYPE_NONE);
798 if (ret) {
799 dev_err(&pdev->dev, "could not add irqchip\n");
800 ret = -ENODEV;
801 goto out2;
802 }
803
804 gpiochip_set_chained_irqchip(&gpio_dev->gc,
805 &amd_gpio_irqchip,
806 irq_base,
807 amd_gpio_irq_handler);
808
809 platform_set_drvdata(pdev, gpio_dev);
810
811 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
812 return ret;
813
814 out2:
815 gpiochip_remove(&gpio_dev->gc);
816
817 return ret;
818 }
819
820 static int amd_gpio_remove(struct platform_device *pdev)
821 {
822 struct amd_gpio *gpio_dev;
823
824 gpio_dev = platform_get_drvdata(pdev);
825
826 gpiochip_remove(&gpio_dev->gc);
827
828 return 0;
829 }
830
831 static const struct acpi_device_id amd_gpio_acpi_match[] = {
832 { "AMD0030", 0 },
833 { "AMDI0030", 0},
834 { },
835 };
836 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
837
838 static struct platform_driver amd_gpio_driver = {
839 .driver = {
840 .name = "amd_gpio",
841 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
842 },
843 .probe = amd_gpio_probe,
844 .remove = amd_gpio_remove,
845 };
846
847 module_platform_driver(amd_gpio_driver);
848
849 MODULE_LICENSE("GPL v2");
850 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
851 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
ubuntu-zesty-kernel mirror