4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
38 static int amd_gpio_direction_input(struct gpio_chip
*gc
, unsigned offset
)
42 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
44 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
45 pin_reg
= readl(gpio_dev
->base
+ offset
* 4);
46 pin_reg
&= ~BIT(OUTPUT_ENABLE_OFF
);
47 writel(pin_reg
, gpio_dev
->base
+ offset
* 4);
48 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
53 static int amd_gpio_direction_output(struct gpio_chip
*gc
, unsigned offset
,
58 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
60 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
61 pin_reg
= readl(gpio_dev
->base
+ offset
* 4);
62 pin_reg
|= BIT(OUTPUT_ENABLE_OFF
);
64 pin_reg
|= BIT(OUTPUT_VALUE_OFF
);
66 pin_reg
&= ~BIT(OUTPUT_VALUE_OFF
);
67 writel(pin_reg
, gpio_dev
->base
+ offset
* 4);
68 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
73 static int amd_gpio_get_value(struct gpio_chip
*gc
, unsigned offset
)
77 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
79 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
80 pin_reg
= readl(gpio_dev
->base
+ offset
* 4);
81 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
83 return !!(pin_reg
& BIT(PIN_STS_OFF
));
86 static void amd_gpio_set_value(struct gpio_chip
*gc
, unsigned offset
, int value
)
90 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
92 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
93 pin_reg
= readl(gpio_dev
->base
+ offset
* 4);
95 pin_reg
|= BIT(OUTPUT_VALUE_OFF
);
97 pin_reg
&= ~BIT(OUTPUT_VALUE_OFF
);
98 writel(pin_reg
, gpio_dev
->base
+ offset
* 4);
99 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
102 static int amd_gpio_set_debounce(struct gpio_chip
*gc
, unsigned offset
,
109 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
111 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
112 pin_reg
= readl(gpio_dev
->base
+ offset
* 4);
115 pin_reg
|= DB_TYPE_REMOVE_GLITCH
<< DB_CNTRL_OFF
;
116 pin_reg
&= ~DB_TMR_OUT_MASK
;
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
129 pin_reg
&= ~BIT(DB_TMR_OUT_UNIT_OFF
);
130 pin_reg
&= ~BIT(DB_TMR_LARGE_OFF
);
131 } else if (debounce
< 976) {
132 time
= debounce
/ 61;
133 pin_reg
|= time
& DB_TMR_OUT_MASK
;
134 pin_reg
&= ~BIT(DB_TMR_OUT_UNIT_OFF
);
135 pin_reg
&= ~BIT(DB_TMR_LARGE_OFF
);
136 } else if (debounce
< 3900) {
137 time
= debounce
/ 244;
138 pin_reg
|= time
& DB_TMR_OUT_MASK
;
139 pin_reg
|= BIT(DB_TMR_OUT_UNIT_OFF
);
140 pin_reg
&= ~BIT(DB_TMR_LARGE_OFF
);
141 } else if (debounce
< 250000) {
142 time
= debounce
/ 15600;
143 pin_reg
|= time
& DB_TMR_OUT_MASK
;
144 pin_reg
&= ~BIT(DB_TMR_OUT_UNIT_OFF
);
145 pin_reg
|= BIT(DB_TMR_LARGE_OFF
);
146 } else if (debounce
< 1000000) {
147 time
= debounce
/ 62500;
148 pin_reg
|= time
& DB_TMR_OUT_MASK
;
149 pin_reg
|= BIT(DB_TMR_OUT_UNIT_OFF
);
150 pin_reg
|= BIT(DB_TMR_LARGE_OFF
);
152 pin_reg
&= ~DB_CNTRl_MASK
;
156 pin_reg
&= ~BIT(DB_TMR_OUT_UNIT_OFF
);
157 pin_reg
&= ~BIT(DB_TMR_LARGE_OFF
);
158 pin_reg
&= ~DB_TMR_OUT_MASK
;
159 pin_reg
&= ~DB_CNTRl_MASK
;
161 writel(pin_reg
, gpio_dev
->base
+ offset
* 4);
162 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
167 static int amd_gpio_set_config(struct gpio_chip
*gc
, unsigned offset
,
168 unsigned long config
)
172 if (pinconf_to_config_param(config
) != PIN_CONFIG_INPUT_DEBOUNCE
)
175 debounce
= pinconf_to_config_argument(config
);
176 return amd_gpio_set_debounce(gc
, offset
, debounce
);
179 #ifdef CONFIG_DEBUG_FS
180 static void amd_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*gc
)
184 unsigned int bank
, i
, pin_num
;
185 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
189 char *interrupt_enable
;
190 char *interrupt_mask
;
196 char *pull_up_enable
;
197 char *pull_down_enable
;
201 for (bank
= 0; bank
< gpio_dev
->hwbank_num
; bank
++) {
202 seq_printf(s
, "GPIO bank%d\t", bank
);
207 pin_num
= AMD_GPIO_PINS_BANK0
;
211 pin_num
= AMD_GPIO_PINS_BANK1
+ i
;
215 pin_num
= AMD_GPIO_PINS_BANK2
+ i
;
219 pin_num
= AMD_GPIO_PINS_BANK3
+ i
;
222 /* Illegal bank number, ignore */
225 for (; i
< pin_num
; i
++) {
226 seq_printf(s
, "pin%d\t", i
);
227 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
228 pin_reg
= readl(gpio_dev
->base
+ i
* 4);
229 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
231 if (pin_reg
& BIT(INTERRUPT_ENABLE_OFF
)) {
232 interrupt_enable
= "interrupt is enabled|";
234 if (!(pin_reg
& BIT(ACTIVE_LEVEL_OFF
)) &&
235 !(pin_reg
& BIT(ACTIVE_LEVEL_OFF
+ 1)))
236 active_level
= "Active low|";
237 else if (pin_reg
& BIT(ACTIVE_LEVEL_OFF
) &&
238 !(pin_reg
& BIT(ACTIVE_LEVEL_OFF
+ 1)))
239 active_level
= "Active high|";
240 else if (!(pin_reg
& BIT(ACTIVE_LEVEL_OFF
)) &&
241 pin_reg
& BIT(ACTIVE_LEVEL_OFF
+ 1))
242 active_level
= "Active on both|";
244 active_level
= "Unknown Active level|";
246 if (pin_reg
& BIT(LEVEL_TRIG_OFF
))
247 level_trig
= "Level trigger|";
249 level_trig
= "Edge trigger|";
253 "interrupt is disabled|";
258 if (pin_reg
& BIT(INTERRUPT_MASK_OFF
))
260 "interrupt is unmasked|";
263 "interrupt is masked|";
265 if (pin_reg
& BIT(WAKE_CNTRL_OFF_S0I3
))
266 wake_cntrl0
= "enable wakeup in S0i3 state|";
268 wake_cntrl0
= "disable wakeup in S0i3 state|";
270 if (pin_reg
& BIT(WAKE_CNTRL_OFF_S3
))
271 wake_cntrl1
= "enable wakeup in S3 state|";
273 wake_cntrl1
= "disable wakeup in S3 state|";
275 if (pin_reg
& BIT(WAKE_CNTRL_OFF_S4
))
276 wake_cntrl2
= "enable wakeup in S4/S5 state|";
278 wake_cntrl2
= "disable wakeup in S4/S5 state|";
280 if (pin_reg
& BIT(PULL_UP_ENABLE_OFF
)) {
281 pull_up_enable
= "pull-up is enabled|";
282 if (pin_reg
& BIT(PULL_UP_SEL_OFF
))
283 pull_up_sel
= "8k pull-up|";
285 pull_up_sel
= "4k pull-up|";
287 pull_up_enable
= "pull-up is disabled|";
291 if (pin_reg
& BIT(PULL_DOWN_ENABLE_OFF
))
292 pull_down_enable
= "pull-down is enabled|";
294 pull_down_enable
= "Pull-down is disabled|";
296 if (pin_reg
& BIT(OUTPUT_ENABLE_OFF
)) {
298 output_enable
= "output is enabled|";
299 if (pin_reg
& BIT(OUTPUT_VALUE_OFF
))
300 output_value
= "output is high|";
302 output_value
= "output is low|";
304 output_enable
= "output is disabled|";
307 if (pin_reg
& BIT(PIN_STS_OFF
))
308 pin_sts
= "input is high|";
310 pin_sts
= "input is low|";
313 seq_printf(s
, "%s %s %s %s %s %s\n"
314 " %s %s %s %s %s %s %s 0x%x\n",
315 level_trig
, active_level
, interrupt_enable
,
316 interrupt_mask
, wake_cntrl0
, wake_cntrl1
,
317 wake_cntrl2
, pin_sts
, pull_up_sel
,
318 pull_up_enable
, pull_down_enable
,
319 output_value
, output_enable
, pin_reg
);
324 #define amd_gpio_dbg_show NULL
327 static void amd_gpio_irq_enable(struct irq_data
*d
)
331 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
332 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
334 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
335 pin_reg
= readl(gpio_dev
->base
+ (d
->hwirq
)*4);
336 pin_reg
|= BIT(INTERRUPT_ENABLE_OFF
);
337 pin_reg
|= BIT(INTERRUPT_MASK_OFF
);
338 writel(pin_reg
, gpio_dev
->base
+ (d
->hwirq
)*4);
339 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
342 static void amd_gpio_irq_disable(struct irq_data
*d
)
346 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
347 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
349 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
350 pin_reg
= readl(gpio_dev
->base
+ (d
->hwirq
)*4);
351 pin_reg
&= ~BIT(INTERRUPT_ENABLE_OFF
);
352 pin_reg
&= ~BIT(INTERRUPT_MASK_OFF
);
353 writel(pin_reg
, gpio_dev
->base
+ (d
->hwirq
)*4);
354 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
357 static void amd_gpio_irq_mask(struct irq_data
*d
)
361 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
362 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
364 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
365 pin_reg
= readl(gpio_dev
->base
+ (d
->hwirq
)*4);
366 pin_reg
&= ~BIT(INTERRUPT_MASK_OFF
);
367 writel(pin_reg
, gpio_dev
->base
+ (d
->hwirq
)*4);
368 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
371 static void amd_gpio_irq_unmask(struct irq_data
*d
)
375 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
376 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
378 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
379 pin_reg
= readl(gpio_dev
->base
+ (d
->hwirq
)*4);
380 pin_reg
|= BIT(INTERRUPT_MASK_OFF
);
381 writel(pin_reg
, gpio_dev
->base
+ (d
->hwirq
)*4);
382 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
385 static void amd_gpio_irq_eoi(struct irq_data
*d
)
389 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
390 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
392 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
393 reg
= readl(gpio_dev
->base
+ WAKE_INT_MASTER_REG
);
395 writel(reg
, gpio_dev
->base
+ WAKE_INT_MASTER_REG
);
396 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
399 static int amd_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
403 unsigned long flags
, irq_flags
;
404 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
405 struct amd_gpio
*gpio_dev
= gpiochip_get_data(gc
);
407 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
408 pin_reg
= readl(gpio_dev
->base
+ (d
->hwirq
)*4);
410 /* Ignore the settings coming from the client and
411 * read the values from the ACPI tables
412 * while setting the trigger type
415 irq_flags
= irq_get_trigger_type(d
->irq
);
416 if (irq_flags
!= IRQ_TYPE_NONE
)
419 switch (type
& IRQ_TYPE_SENSE_MASK
) {
420 case IRQ_TYPE_EDGE_RISING
:
421 pin_reg
&= ~BIT(LEVEL_TRIG_OFF
);
422 pin_reg
&= ~(ACTIVE_LEVEL_MASK
<< ACTIVE_LEVEL_OFF
);
423 pin_reg
|= ACTIVE_HIGH
<< ACTIVE_LEVEL_OFF
;
424 pin_reg
|= DB_TYPE_REMOVE_GLITCH
<< DB_CNTRL_OFF
;
425 irq_set_handler_locked(d
, handle_edge_irq
);
428 case IRQ_TYPE_EDGE_FALLING
:
429 pin_reg
&= ~BIT(LEVEL_TRIG_OFF
);
430 pin_reg
&= ~(ACTIVE_LEVEL_MASK
<< ACTIVE_LEVEL_OFF
);
431 pin_reg
|= ACTIVE_LOW
<< ACTIVE_LEVEL_OFF
;
432 pin_reg
|= DB_TYPE_REMOVE_GLITCH
<< DB_CNTRL_OFF
;
433 irq_set_handler_locked(d
, handle_edge_irq
);
436 case IRQ_TYPE_EDGE_BOTH
:
437 pin_reg
&= ~BIT(LEVEL_TRIG_OFF
);
438 pin_reg
&= ~(ACTIVE_LEVEL_MASK
<< ACTIVE_LEVEL_OFF
);
439 pin_reg
|= BOTH_EADGE
<< ACTIVE_LEVEL_OFF
;
440 pin_reg
|= DB_TYPE_REMOVE_GLITCH
<< DB_CNTRL_OFF
;
441 irq_set_handler_locked(d
, handle_edge_irq
);
444 case IRQ_TYPE_LEVEL_HIGH
:
445 pin_reg
|= LEVEL_TRIGGER
<< LEVEL_TRIG_OFF
;
446 pin_reg
&= ~(ACTIVE_LEVEL_MASK
<< ACTIVE_LEVEL_OFF
);
447 pin_reg
|= ACTIVE_HIGH
<< ACTIVE_LEVEL_OFF
;
448 pin_reg
&= ~(DB_CNTRl_MASK
<< DB_CNTRL_OFF
);
449 pin_reg
|= DB_TYPE_PRESERVE_LOW_GLITCH
<< DB_CNTRL_OFF
;
450 irq_set_handler_locked(d
, handle_level_irq
);
453 case IRQ_TYPE_LEVEL_LOW
:
454 pin_reg
|= LEVEL_TRIGGER
<< LEVEL_TRIG_OFF
;
455 pin_reg
&= ~(ACTIVE_LEVEL_MASK
<< ACTIVE_LEVEL_OFF
);
456 pin_reg
|= ACTIVE_LOW
<< ACTIVE_LEVEL_OFF
;
457 pin_reg
&= ~(DB_CNTRl_MASK
<< DB_CNTRL_OFF
);
458 pin_reg
|= DB_TYPE_PRESERVE_HIGH_GLITCH
<< DB_CNTRL_OFF
;
459 irq_set_handler_locked(d
, handle_level_irq
);
466 dev_err(&gpio_dev
->pdev
->dev
, "Invalid type value\n");
470 pin_reg
|= CLR_INTR_STAT
<< INTERRUPT_STS_OFF
;
471 writel(pin_reg
, gpio_dev
->base
+ (d
->hwirq
)*4);
472 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
477 static void amd_irq_ack(struct irq_data
*d
)
480 * based on HW design,there is no need to ack HW
481 * before handle current irq. But this routine is
482 * necessary for handle_edge_irq
486 static struct irq_chip amd_gpio_irqchip
= {
488 .irq_ack
= amd_irq_ack
,
489 .irq_enable
= amd_gpio_irq_enable
,
490 .irq_disable
= amd_gpio_irq_disable
,
491 .irq_mask
= amd_gpio_irq_mask
,
492 .irq_unmask
= amd_gpio_irq_unmask
,
493 .irq_eoi
= amd_gpio_irq_eoi
,
494 .irq_set_type
= amd_gpio_irq_set_type
,
495 .flags
= IRQCHIP_SKIP_SET_WAKE
,
498 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
500 static irqreturn_t
amd_gpio_irq_handler(int irq
, void *dev_id
)
502 struct amd_gpio
*gpio_dev
= dev_id
;
503 struct gpio_chip
*gc
= &gpio_dev
->gc
;
504 irqreturn_t ret
= IRQ_NONE
;
505 unsigned int i
, irqnr
;
510 /* Read the wake status */
511 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
512 status
= readl(gpio_dev
->base
+ WAKE_INT_STATUS_REG1
);
514 status
|= readl(gpio_dev
->base
+ WAKE_INT_STATUS_REG0
);
515 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
517 /* Bit 0-45 contain the relevant status bits */
518 status
&= (1ULL << 46) - 1;
519 regs
= gpio_dev
->base
;
520 for (mask
= 1, irqnr
= 0; status
; mask
<<= 1, regs
+= 4, irqnr
+= 4) {
521 if (!(status
& mask
))
525 /* Each status bit covers four pins */
526 for (i
= 0; i
< 4; i
++) {
527 regval
= readl(regs
+ i
);
528 if (!(regval
& PIN_IRQ_PENDING
))
530 irq
= irq_find_mapping(gc
->irqdomain
, irqnr
+ i
);
531 generic_handle_irq(irq
);
532 /* Clear interrupt */
533 writel(regval
, regs
+ i
);
538 /* Signal EOI to the GPIO unit */
539 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
540 regval
= readl(gpio_dev
->base
+ WAKE_INT_MASTER_REG
);
542 writel(regval
, gpio_dev
->base
+ WAKE_INT_MASTER_REG
);
543 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
548 static int amd_get_groups_count(struct pinctrl_dev
*pctldev
)
550 struct amd_gpio
*gpio_dev
= pinctrl_dev_get_drvdata(pctldev
);
552 return gpio_dev
->ngroups
;
555 static const char *amd_get_group_name(struct pinctrl_dev
*pctldev
,
558 struct amd_gpio
*gpio_dev
= pinctrl_dev_get_drvdata(pctldev
);
560 return gpio_dev
->groups
[group
].name
;
563 static int amd_get_group_pins(struct pinctrl_dev
*pctldev
,
565 const unsigned **pins
,
568 struct amd_gpio
*gpio_dev
= pinctrl_dev_get_drvdata(pctldev
);
570 *pins
= gpio_dev
->groups
[group
].pins
;
571 *num_pins
= gpio_dev
->groups
[group
].npins
;
575 static const struct pinctrl_ops amd_pinctrl_ops
= {
576 .get_groups_count
= amd_get_groups_count
,
577 .get_group_name
= amd_get_group_name
,
578 .get_group_pins
= amd_get_group_pins
,
580 .dt_node_to_map
= pinconf_generic_dt_node_to_map_group
,
581 .dt_free_map
= pinctrl_utils_free_map
,
585 static int amd_pinconf_get(struct pinctrl_dev
*pctldev
,
587 unsigned long *config
)
592 struct amd_gpio
*gpio_dev
= pinctrl_dev_get_drvdata(pctldev
);
593 enum pin_config_param param
= pinconf_to_config_param(*config
);
595 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
596 pin_reg
= readl(gpio_dev
->base
+ pin
*4);
597 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
599 case PIN_CONFIG_INPUT_DEBOUNCE
:
600 arg
= pin_reg
& DB_TMR_OUT_MASK
;
603 case PIN_CONFIG_BIAS_PULL_DOWN
:
604 arg
= (pin_reg
>> PULL_DOWN_ENABLE_OFF
) & BIT(0);
607 case PIN_CONFIG_BIAS_PULL_UP
:
608 arg
= (pin_reg
>> PULL_UP_SEL_OFF
) & (BIT(0) | BIT(1));
611 case PIN_CONFIG_DRIVE_STRENGTH
:
612 arg
= (pin_reg
>> DRV_STRENGTH_SEL_OFF
) & DRV_STRENGTH_SEL_MASK
;
616 dev_err(&gpio_dev
->pdev
->dev
, "Invalid config param %04x\n",
621 *config
= pinconf_to_config_packed(param
, arg
);
626 static int amd_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
627 unsigned long *configs
, unsigned num_configs
)
634 enum pin_config_param param
;
635 struct amd_gpio
*gpio_dev
= pinctrl_dev_get_drvdata(pctldev
);
637 raw_spin_lock_irqsave(&gpio_dev
->lock
, flags
);
638 for (i
= 0; i
< num_configs
; i
++) {
639 param
= pinconf_to_config_param(configs
[i
]);
640 arg
= pinconf_to_config_argument(configs
[i
]);
641 pin_reg
= readl(gpio_dev
->base
+ pin
*4);
644 case PIN_CONFIG_INPUT_DEBOUNCE
:
645 pin_reg
&= ~DB_TMR_OUT_MASK
;
646 pin_reg
|= arg
& DB_TMR_OUT_MASK
;
649 case PIN_CONFIG_BIAS_PULL_DOWN
:
650 pin_reg
&= ~BIT(PULL_DOWN_ENABLE_OFF
);
651 pin_reg
|= (arg
& BIT(0)) << PULL_DOWN_ENABLE_OFF
;
654 case PIN_CONFIG_BIAS_PULL_UP
:
655 pin_reg
&= ~BIT(PULL_UP_SEL_OFF
);
656 pin_reg
|= (arg
& BIT(0)) << PULL_UP_SEL_OFF
;
657 pin_reg
&= ~BIT(PULL_UP_ENABLE_OFF
);
658 pin_reg
|= ((arg
>>1) & BIT(0)) << PULL_UP_ENABLE_OFF
;
661 case PIN_CONFIG_DRIVE_STRENGTH
:
662 pin_reg
&= ~(DRV_STRENGTH_SEL_MASK
663 << DRV_STRENGTH_SEL_OFF
);
664 pin_reg
|= (arg
& DRV_STRENGTH_SEL_MASK
)
665 << DRV_STRENGTH_SEL_OFF
;
669 dev_err(&gpio_dev
->pdev
->dev
,
670 "Invalid config param %04x\n", param
);
674 writel(pin_reg
, gpio_dev
->base
+ pin
*4);
676 raw_spin_unlock_irqrestore(&gpio_dev
->lock
, flags
);
681 static int amd_pinconf_group_get(struct pinctrl_dev
*pctldev
,
683 unsigned long *config
)
685 const unsigned *pins
;
689 ret
= amd_get_group_pins(pctldev
, group
, &pins
, &npins
);
693 if (amd_pinconf_get(pctldev
, pins
[0], config
))
699 static int amd_pinconf_group_set(struct pinctrl_dev
*pctldev
,
700 unsigned group
, unsigned long *configs
,
701 unsigned num_configs
)
703 const unsigned *pins
;
707 ret
= amd_get_group_pins(pctldev
, group
, &pins
, &npins
);
710 for (i
= 0; i
< npins
; i
++) {
711 if (amd_pinconf_set(pctldev
, pins
[i
], configs
, num_configs
))
717 static const struct pinconf_ops amd_pinconf_ops
= {
718 .pin_config_get
= amd_pinconf_get
,
719 .pin_config_set
= amd_pinconf_set
,
720 .pin_config_group_get
= amd_pinconf_group_get
,
721 .pin_config_group_set
= amd_pinconf_group_set
,
724 static struct pinctrl_desc amd_pinctrl_desc
= {
726 .npins
= ARRAY_SIZE(kerncz_pins
),
727 .pctlops
= &amd_pinctrl_ops
,
728 .confops
= &amd_pinconf_ops
,
729 .owner
= THIS_MODULE
,
732 static int amd_gpio_probe(struct platform_device
*pdev
)
736 struct resource
*res
;
737 struct amd_gpio
*gpio_dev
;
739 gpio_dev
= devm_kzalloc(&pdev
->dev
,
740 sizeof(struct amd_gpio
), GFP_KERNEL
);
744 raw_spin_lock_init(&gpio_dev
->lock
);
746 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
748 dev_err(&pdev
->dev
, "Failed to get gpio io resource.\n");
752 gpio_dev
->base
= devm_ioremap_nocache(&pdev
->dev
, res
->start
,
757 irq_base
= platform_get_irq(pdev
, 0);
759 dev_err(&pdev
->dev
, "Failed to get gpio IRQ.\n");
763 gpio_dev
->pdev
= pdev
;
764 gpio_dev
->gc
.direction_input
= amd_gpio_direction_input
;
765 gpio_dev
->gc
.direction_output
= amd_gpio_direction_output
;
766 gpio_dev
->gc
.get
= amd_gpio_get_value
;
767 gpio_dev
->gc
.set
= amd_gpio_set_value
;
768 gpio_dev
->gc
.set_config
= amd_gpio_set_config
;
769 gpio_dev
->gc
.dbg_show
= amd_gpio_dbg_show
;
771 gpio_dev
->gc
.base
= -1;
772 gpio_dev
->gc
.label
= pdev
->name
;
773 gpio_dev
->gc
.owner
= THIS_MODULE
;
774 gpio_dev
->gc
.parent
= &pdev
->dev
;
775 gpio_dev
->gc
.ngpio
= resource_size(res
) / 4;
776 #if defined(CONFIG_OF_GPIO)
777 gpio_dev
->gc
.of_node
= pdev
->dev
.of_node
;
780 gpio_dev
->hwbank_num
= gpio_dev
->gc
.ngpio
/ 64;
781 gpio_dev
->groups
= kerncz_groups
;
782 gpio_dev
->ngroups
= ARRAY_SIZE(kerncz_groups
);
784 amd_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
785 gpio_dev
->pctrl
= devm_pinctrl_register(&pdev
->dev
, &amd_pinctrl_desc
,
787 if (IS_ERR(gpio_dev
->pctrl
)) {
788 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
789 return PTR_ERR(gpio_dev
->pctrl
);
792 ret
= gpiochip_add_data(&gpio_dev
->gc
, gpio_dev
);
796 ret
= gpiochip_add_pin_range(&gpio_dev
->gc
, dev_name(&pdev
->dev
),
797 0, 0, gpio_dev
->gc
.ngpio
);
799 dev_err(&pdev
->dev
, "Failed to add pin range\n");
803 ret
= gpiochip_irqchip_add(&gpio_dev
->gc
,
809 dev_err(&pdev
->dev
, "could not add irqchip\n");
814 ret
= devm_request_irq(&pdev
->dev
, irq_base
, amd_gpio_irq_handler
, 0,
815 KBUILD_MODNAME
, gpio_dev
);
819 platform_set_drvdata(pdev
, gpio_dev
);
821 dev_dbg(&pdev
->dev
, "amd gpio driver loaded\n");
825 gpiochip_remove(&gpio_dev
->gc
);
830 static int amd_gpio_remove(struct platform_device
*pdev
)
832 struct amd_gpio
*gpio_dev
;
834 gpio_dev
= platform_get_drvdata(pdev
);
836 gpiochip_remove(&gpio_dev
->gc
);
841 static const struct acpi_device_id amd_gpio_acpi_match
[] = {
846 MODULE_DEVICE_TABLE(acpi
, amd_gpio_acpi_match
);
848 static struct platform_driver amd_gpio_driver
= {
851 .acpi_match_table
= ACPI_PTR(amd_gpio_acpi_match
),
853 .probe
= amd_gpio_probe
,
854 .remove
= amd_gpio_remove
,
857 module_platform_driver(amd_gpio_driver
);
859 MODULE_LICENSE("GPL v2");
860 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
861 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");