]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/pinctrl/pinctrl-at91-pio4.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'usb-serial-5.7-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / pinctrl-at91-pio4.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for the Atmel PIO4 controller
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/platform_device.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/slab.h>
22 #include "core.h"
23 #include "pinconf.h"
24 #include "pinctrl-utils.h"
25
26 /*
27 * Warning:
28 * In order to not introduce confusion between Atmel PIO groups and pinctrl
29 * framework groups, Atmel PIO groups will be called banks, line is kept to
30 * designed the pin id into this bank.
31 */
32
33 #define ATMEL_PIO_MSKR 0x0000
34 #define ATMEL_PIO_CFGR 0x0004
35 #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
36 #define ATMEL_PIO_DIR_MASK BIT(8)
37 #define ATMEL_PIO_PUEN_MASK BIT(9)
38 #define ATMEL_PIO_PDEN_MASK BIT(10)
39 #define ATMEL_PIO_IFEN_MASK BIT(12)
40 #define ATMEL_PIO_IFSCEN_MASK BIT(13)
41 #define ATMEL_PIO_OPD_MASK BIT(14)
42 #define ATMEL_PIO_SCHMITT_MASK BIT(15)
43 #define ATMEL_PIO_DRVSTR_MASK GENMASK(17, 16)
44 #define ATMEL_PIO_DRVSTR_OFFSET 16
45 #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
46 #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
47 #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
48 #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
49 #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
50 #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
51 #define ATMEL_PIO_PDSR 0x0008
52 #define ATMEL_PIO_LOCKSR 0x000C
53 #define ATMEL_PIO_SODR 0x0010
54 #define ATMEL_PIO_CODR 0x0014
55 #define ATMEL_PIO_ODSR 0x0018
56 #define ATMEL_PIO_IER 0x0020
57 #define ATMEL_PIO_IDR 0x0024
58 #define ATMEL_PIO_IMR 0x0028
59 #define ATMEL_PIO_ISR 0x002C
60 #define ATMEL_PIO_IOFR 0x003C
61
62 #define ATMEL_PIO_NPINS_PER_BANK 32
63 #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
64 #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
65 #define ATMEL_PIO_BANK_OFFSET 0x40
66
67 #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
68 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
69 #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
70
71 /* Custom pinconf parameters */
72 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
73
74 struct atmel_pioctrl_data {
75 unsigned nbanks;
76 };
77
78 struct atmel_group {
79 const char *name;
80 u32 pin;
81 };
82
83 struct atmel_pin {
84 unsigned pin_id;
85 unsigned mux;
86 unsigned ioset;
87 unsigned bank;
88 unsigned line;
89 const char *device;
90 };
91
92 /**
93 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
94 * @reg_base: base address of the controller.
95 * @clk: clock of the controller.
96 * @nbanks: number of PIO groups, it can vary depending on the SoC.
97 * @pinctrl_dev: pinctrl device registered.
98 * @groups: groups table to provide group name and pin in the group to pinctrl.
99 * @group_names: group names table to provide all the group/pin names to
100 * pinctrl or gpio.
101 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
102 * fields are set at probe time. Other ones are set when parsing dt
103 * pinctrl.
104 * @npins: number of pins.
105 * @gpio_chip: gpio chip registered.
106 * @irq_domain: irq domain for the gpio controller.
107 * @irqs: table containing the hw irq number of the bank. The index of the
108 * table is the bank id.
109 * @dev: device entry for the Atmel PIO controller.
110 * @node: node of the Atmel PIO controller.
111 */
112 struct atmel_pioctrl {
113 void __iomem *reg_base;
114 struct clk *clk;
115 unsigned nbanks;
116 struct pinctrl_dev *pinctrl_dev;
117 struct atmel_group *groups;
118 const char * const *group_names;
119 struct atmel_pin **pins;
120 unsigned npins;
121 struct gpio_chip *gpio_chip;
122 struct irq_domain *irq_domain;
123 int *irqs;
124 unsigned *pm_wakeup_sources;
125 struct {
126 u32 imr;
127 u32 odsr;
128 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK];
129 } *pm_suspend_backup;
130 struct device *dev;
131 struct device_node *node;
132 };
133
134 static const char * const atmel_functions[] = {
135 "GPIO", "A", "B", "C", "D", "E", "F", "G"
136 };
137
138 static const struct pinconf_generic_params atmel_custom_bindings[] = {
139 {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
140 };
141
142 /* --- GPIO --- */
143 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
144 unsigned int bank, unsigned int reg)
145 {
146 return readl_relaxed(atmel_pioctrl->reg_base
147 + ATMEL_PIO_BANK_OFFSET * bank + reg);
148 }
149
150 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
151 unsigned int bank, unsigned int reg,
152 unsigned int val)
153 {
154 writel_relaxed(val, atmel_pioctrl->reg_base
155 + ATMEL_PIO_BANK_OFFSET * bank + reg);
156 }
157
158 static void atmel_gpio_irq_ack(struct irq_data *d)
159 {
160 /*
161 * Nothing to do, interrupt is cleared when reading the status
162 * register.
163 */
164 }
165
166 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
167 {
168 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
169 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
170 unsigned reg;
171
172 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
173 BIT(pin->line));
174 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
175 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
176
177 switch (type) {
178 case IRQ_TYPE_EDGE_RISING:
179 irq_set_handler_locked(d, handle_edge_irq);
180 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
181 break;
182 case IRQ_TYPE_EDGE_FALLING:
183 irq_set_handler_locked(d, handle_edge_irq);
184 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
185 break;
186 case IRQ_TYPE_EDGE_BOTH:
187 irq_set_handler_locked(d, handle_edge_irq);
188 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
189 break;
190 case IRQ_TYPE_LEVEL_LOW:
191 irq_set_handler_locked(d, handle_level_irq);
192 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
193 break;
194 case IRQ_TYPE_LEVEL_HIGH:
195 irq_set_handler_locked(d, handle_level_irq);
196 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
197 break;
198 case IRQ_TYPE_NONE:
199 default:
200 return -EINVAL;
201 }
202
203 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
204
205 return 0;
206 }
207
208 static void atmel_gpio_irq_mask(struct irq_data *d)
209 {
210 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
211 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
212
213 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
214 BIT(pin->line));
215 }
216
217 static void atmel_gpio_irq_unmask(struct irq_data *d)
218 {
219 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
220 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
221
222 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
223 BIT(pin->line));
224 }
225
226 #ifdef CONFIG_PM_SLEEP
227
228 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
229 {
230 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
231 int bank = ATMEL_PIO_BANK(d->hwirq);
232 int line = ATMEL_PIO_LINE(d->hwirq);
233
234 /* The gpio controller has one interrupt line per bank. */
235 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
236
237 if (on)
238 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
239 else
240 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
241
242 return 0;
243 }
244 #else
245 #define atmel_gpio_irq_set_wake NULL
246 #endif /* CONFIG_PM_SLEEP */
247
248 static struct irq_chip atmel_gpio_irq_chip = {
249 .name = "GPIO",
250 .irq_ack = atmel_gpio_irq_ack,
251 .irq_mask = atmel_gpio_irq_mask,
252 .irq_unmask = atmel_gpio_irq_unmask,
253 .irq_set_type = atmel_gpio_irq_set_type,
254 .irq_set_wake = atmel_gpio_irq_set_wake,
255 };
256
257 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
258 {
259 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
260
261 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
262 }
263
264 static void atmel_gpio_irq_handler(struct irq_desc *desc)
265 {
266 unsigned int irq = irq_desc_get_irq(desc);
267 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
268 struct irq_chip *chip = irq_desc_get_chip(desc);
269 unsigned long isr;
270 int n, bank = -1;
271
272 /* Find from which bank is the irq received. */
273 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
274 if (atmel_pioctrl->irqs[n] == irq) {
275 bank = n;
276 break;
277 }
278 }
279
280 if (bank < 0) {
281 dev_err(atmel_pioctrl->dev,
282 "no bank associated to irq %u\n", irq);
283 return;
284 }
285
286 chained_irq_enter(chip, desc);
287
288 for (;;) {
289 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
290 ATMEL_PIO_ISR);
291 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
292 ATMEL_PIO_IMR);
293 if (!isr)
294 break;
295
296 for_each_set_bit(n, &isr, BITS_PER_LONG)
297 generic_handle_irq(atmel_gpio_to_irq(
298 atmel_pioctrl->gpio_chip,
299 bank * ATMEL_PIO_NPINS_PER_BANK + n));
300 }
301
302 chained_irq_exit(chip, desc);
303 }
304
305 static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
306 {
307 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
308 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
309 unsigned reg;
310
311 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
312 BIT(pin->line));
313 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
314 reg &= ~ATMEL_PIO_DIR_MASK;
315 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
316
317 return 0;
318 }
319
320 static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
321 {
322 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
323 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
324 unsigned reg;
325
326 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
327
328 return !!(reg & BIT(pin->line));
329 }
330
331 static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
332 unsigned long *bits)
333 {
334 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
335 unsigned int bank;
336
337 bitmap_zero(bits, atmel_pioctrl->npins);
338
339 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
340 unsigned int word = bank;
341 unsigned int offset = 0;
342 unsigned int reg;
343
344 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
345 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
346 offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
347 #endif
348 if (!mask[word])
349 continue;
350
351 reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
352 bits[word] |= mask[word] & (reg << offset);
353 }
354
355 return 0;
356 }
357
358 static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
359 int value)
360 {
361 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
362 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
363 unsigned reg;
364
365 atmel_gpio_write(atmel_pioctrl, pin->bank,
366 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
367 BIT(pin->line));
368
369 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
370 BIT(pin->line));
371 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
372 reg |= ATMEL_PIO_DIR_MASK;
373 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
374
375 return 0;
376 }
377
378 static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
379 {
380 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
381 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
382
383 atmel_gpio_write(atmel_pioctrl, pin->bank,
384 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
385 BIT(pin->line));
386 }
387
388 static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
389 unsigned long *bits)
390 {
391 struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
392 unsigned int bank;
393
394 for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
395 unsigned int bitmask;
396 unsigned int word = bank;
397
398 /*
399 * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
400 * two 32bit words to handle the whole bitmask
401 */
402 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
403 word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
404 #endif
405 if (!mask[word])
406 continue;
407
408 bitmask = mask[word] & bits[word];
409 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
410
411 bitmask = mask[word] & ~bits[word];
412 atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
413
414 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
415 mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
416 bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
417 #endif
418 }
419 }
420
421 static struct gpio_chip atmel_gpio_chip = {
422 .direction_input = atmel_gpio_direction_input,
423 .get = atmel_gpio_get,
424 .get_multiple = atmel_gpio_get_multiple,
425 .direction_output = atmel_gpio_direction_output,
426 .set = atmel_gpio_set,
427 .set_multiple = atmel_gpio_set_multiple,
428 .to_irq = atmel_gpio_to_irq,
429 .base = 0,
430 };
431
432 /* --- PINCTRL --- */
433 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
434 unsigned pin_id)
435 {
436 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
437 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
438 unsigned line = atmel_pioctrl->pins[pin_id]->line;
439 void __iomem *addr = atmel_pioctrl->reg_base
440 + bank * ATMEL_PIO_BANK_OFFSET;
441
442 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
443 /* Have to set MSKR first, to access the right pin CFGR. */
444 wmb();
445
446 return readl_relaxed(addr + ATMEL_PIO_CFGR);
447 }
448
449 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
450 unsigned pin_id, u32 conf)
451 {
452 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
453 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
454 unsigned line = atmel_pioctrl->pins[pin_id]->line;
455 void __iomem *addr = atmel_pioctrl->reg_base
456 + bank * ATMEL_PIO_BANK_OFFSET;
457
458 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
459 /* Have to set MSKR first, to access the right pin CFGR. */
460 wmb();
461 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
462 }
463
464 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
465 {
466 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
467
468 return atmel_pioctrl->npins;
469 }
470
471 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
472 unsigned selector)
473 {
474 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
475
476 return atmel_pioctrl->groups[selector].name;
477 }
478
479 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
480 unsigned selector, const unsigned **pins,
481 unsigned *num_pins)
482 {
483 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
484
485 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
486 *num_pins = 1;
487
488 return 0;
489 }
490
491 static struct atmel_group *
492 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
493 {
494 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
495 int i;
496
497 for (i = 0; i < atmel_pioctrl->npins; i++) {
498 struct atmel_group *grp = atmel_pioctrl->groups + i;
499
500 if (grp->pin == pin)
501 return grp;
502 }
503
504 return NULL;
505 }
506
507 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
508 struct device_node *np,
509 u32 pinfunc, const char **grp_name,
510 const char **func_name)
511 {
512 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
513 unsigned pin_id, func_id;
514 struct atmel_group *grp;
515
516 pin_id = ATMEL_GET_PIN_NO(pinfunc);
517 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
518
519 if (func_id >= ARRAY_SIZE(atmel_functions))
520 return -EINVAL;
521
522 *func_name = atmel_functions[func_id];
523
524 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
525 if (!grp)
526 return -EINVAL;
527 *grp_name = grp->name;
528
529 atmel_pioctrl->pins[pin_id]->mux = func_id;
530 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
531 /* Want the device name not the group one. */
532 if (np->parent == atmel_pioctrl->node)
533 atmel_pioctrl->pins[pin_id]->device = np->name;
534 else
535 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
536
537 return 0;
538 }
539
540 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
541 struct device_node *np,
542 struct pinctrl_map **map,
543 unsigned *reserved_maps,
544 unsigned *num_maps)
545 {
546 unsigned num_pins, num_configs, reserve;
547 unsigned long *configs;
548 struct property *pins;
549 u32 pinfunc;
550 int ret, i;
551
552 pins = of_find_property(np, "pinmux", NULL);
553 if (!pins)
554 return -EINVAL;
555
556 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
557 &num_configs);
558 if (ret < 0) {
559 dev_err(pctldev->dev, "%pOF: could not parse node property\n",
560 np);
561 return ret;
562 }
563
564 num_pins = pins->length / sizeof(u32);
565 if (!num_pins) {
566 dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
567 ret = -EINVAL;
568 goto exit;
569 }
570
571 /*
572 * Reserve maps, at least there is a mux map and an optional conf
573 * map for each pin.
574 */
575 reserve = 1;
576 if (num_configs)
577 reserve++;
578 reserve *= num_pins;
579 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
580 reserve);
581 if (ret < 0)
582 goto exit;
583
584 for (i = 0; i < num_pins; i++) {
585 const char *group, *func;
586
587 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
588 if (ret)
589 goto exit;
590
591 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
592 &func);
593 if (ret)
594 goto exit;
595
596 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
597 group, func);
598
599 if (num_configs) {
600 ret = pinctrl_utils_add_map_configs(pctldev, map,
601 reserved_maps, num_maps, group,
602 configs, num_configs,
603 PIN_MAP_TYPE_CONFIGS_GROUP);
604 if (ret < 0)
605 goto exit;
606 }
607 }
608
609 exit:
610 kfree(configs);
611 return ret;
612 }
613
614 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
615 struct device_node *np_config,
616 struct pinctrl_map **map,
617 unsigned *num_maps)
618 {
619 struct device_node *np;
620 unsigned reserved_maps;
621 int ret;
622
623 *map = NULL;
624 *num_maps = 0;
625 reserved_maps = 0;
626
627 /*
628 * If all the pins of a device have the same configuration (or no one),
629 * it is useless to add a subnode, so directly parse node referenced by
630 * phandle.
631 */
632 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
633 &reserved_maps, num_maps);
634 if (ret) {
635 for_each_child_of_node(np_config, np) {
636 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
637 &reserved_maps, num_maps);
638 if (ret < 0) {
639 of_node_put(np);
640 break;
641 }
642 }
643 }
644
645 if (ret < 0) {
646 pinctrl_utils_free_map(pctldev, *map, *num_maps);
647 dev_err(pctldev->dev, "can't create maps for node %pOF\n",
648 np_config);
649 }
650
651 return ret;
652 }
653
654 static const struct pinctrl_ops atmel_pctlops = {
655 .get_groups_count = atmel_pctl_get_groups_count,
656 .get_group_name = atmel_pctl_get_group_name,
657 .get_group_pins = atmel_pctl_get_group_pins,
658 .dt_node_to_map = atmel_pctl_dt_node_to_map,
659 .dt_free_map = pinctrl_utils_free_map,
660 };
661
662 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
663 {
664 return ARRAY_SIZE(atmel_functions);
665 }
666
667 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
668 unsigned selector)
669 {
670 return atmel_functions[selector];
671 }
672
673 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
674 unsigned selector,
675 const char * const **groups,
676 unsigned * const num_groups)
677 {
678 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
679
680 *groups = atmel_pioctrl->group_names;
681 *num_groups = atmel_pioctrl->npins;
682
683 return 0;
684 }
685
686 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
687 unsigned function,
688 unsigned group)
689 {
690 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
691 unsigned pin;
692 u32 conf;
693
694 dev_dbg(pctldev->dev, "enable function %s group %s\n",
695 atmel_functions[function], atmel_pioctrl->groups[group].name);
696
697 pin = atmel_pioctrl->groups[group].pin;
698 conf = atmel_pin_config_read(pctldev, pin);
699 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
700 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
701 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
702 atmel_pin_config_write(pctldev, pin, conf);
703
704 return 0;
705 }
706
707 static const struct pinmux_ops atmel_pmxops = {
708 .get_functions_count = atmel_pmx_get_functions_count,
709 .get_function_name = atmel_pmx_get_function_name,
710 .get_function_groups = atmel_pmx_get_function_groups,
711 .set_mux = atmel_pmx_set_mux,
712 };
713
714 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
715 unsigned group,
716 unsigned long *config)
717 {
718 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
719 unsigned param = pinconf_to_config_param(*config), arg = 0;
720 struct atmel_group *grp = atmel_pioctrl->groups + group;
721 unsigned pin_id = grp->pin;
722 u32 res;
723
724 res = atmel_pin_config_read(pctldev, pin_id);
725
726 switch (param) {
727 case PIN_CONFIG_BIAS_PULL_UP:
728 if (!(res & ATMEL_PIO_PUEN_MASK))
729 return -EINVAL;
730 arg = 1;
731 break;
732 case PIN_CONFIG_BIAS_PULL_DOWN:
733 if ((res & ATMEL_PIO_PUEN_MASK) ||
734 (!(res & ATMEL_PIO_PDEN_MASK)))
735 return -EINVAL;
736 arg = 1;
737 break;
738 case PIN_CONFIG_BIAS_DISABLE:
739 if ((res & ATMEL_PIO_PUEN_MASK) ||
740 ((res & ATMEL_PIO_PDEN_MASK)))
741 return -EINVAL;
742 arg = 1;
743 break;
744 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
745 if (!(res & ATMEL_PIO_OPD_MASK))
746 return -EINVAL;
747 arg = 1;
748 break;
749 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
750 if (!(res & ATMEL_PIO_SCHMITT_MASK))
751 return -EINVAL;
752 arg = 1;
753 break;
754 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
755 if (!(res & ATMEL_PIO_DRVSTR_MASK))
756 return -EINVAL;
757 arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
758 break;
759 default:
760 return -ENOTSUPP;
761 }
762
763 *config = pinconf_to_config_packed(param, arg);
764 return 0;
765 }
766
767 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
768 unsigned group,
769 unsigned long *configs,
770 unsigned num_configs)
771 {
772 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
773 struct atmel_group *grp = atmel_pioctrl->groups + group;
774 unsigned bank, pin, pin_id = grp->pin;
775 u32 mask, conf = 0;
776 int i;
777
778 conf = atmel_pin_config_read(pctldev, pin_id);
779
780 for (i = 0; i < num_configs; i++) {
781 unsigned param = pinconf_to_config_param(configs[i]);
782 unsigned arg = pinconf_to_config_argument(configs[i]);
783
784 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
785 __func__, pin_id, configs[i]);
786
787 switch (param) {
788 case PIN_CONFIG_BIAS_DISABLE:
789 conf &= (~ATMEL_PIO_PUEN_MASK);
790 conf &= (~ATMEL_PIO_PDEN_MASK);
791 break;
792 case PIN_CONFIG_BIAS_PULL_UP:
793 conf |= ATMEL_PIO_PUEN_MASK;
794 conf &= (~ATMEL_PIO_PDEN_MASK);
795 break;
796 case PIN_CONFIG_BIAS_PULL_DOWN:
797 conf |= ATMEL_PIO_PDEN_MASK;
798 conf &= (~ATMEL_PIO_PUEN_MASK);
799 break;
800 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
801 if (arg == 0)
802 conf &= (~ATMEL_PIO_OPD_MASK);
803 else
804 conf |= ATMEL_PIO_OPD_MASK;
805 break;
806 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
807 if (arg == 0)
808 conf |= ATMEL_PIO_SCHMITT_MASK;
809 else
810 conf &= (~ATMEL_PIO_SCHMITT_MASK);
811 break;
812 case PIN_CONFIG_INPUT_DEBOUNCE:
813 if (arg == 0) {
814 conf &= (~ATMEL_PIO_IFEN_MASK);
815 conf &= (~ATMEL_PIO_IFSCEN_MASK);
816 } else {
817 /*
818 * We don't care about the debounce value for several reasons:
819 * - can't have different debounce periods inside a same group,
820 * - the register to configure this period is a secure register.
821 * The debouncing filter can filter a pulse with a duration of less
822 * than 1/2 slow clock period.
823 */
824 conf |= ATMEL_PIO_IFEN_MASK;
825 conf |= ATMEL_PIO_IFSCEN_MASK;
826 }
827 break;
828 case PIN_CONFIG_OUTPUT:
829 conf |= ATMEL_PIO_DIR_MASK;
830 bank = ATMEL_PIO_BANK(pin_id);
831 pin = ATMEL_PIO_LINE(pin_id);
832 mask = 1 << pin;
833
834 if (arg == 0) {
835 writel_relaxed(mask, atmel_pioctrl->reg_base +
836 bank * ATMEL_PIO_BANK_OFFSET +
837 ATMEL_PIO_CODR);
838 } else {
839 writel_relaxed(mask, atmel_pioctrl->reg_base +
840 bank * ATMEL_PIO_BANK_OFFSET +
841 ATMEL_PIO_SODR);
842 }
843 break;
844 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
845 switch (arg) {
846 case ATMEL_PIO_DRVSTR_LO:
847 case ATMEL_PIO_DRVSTR_ME:
848 case ATMEL_PIO_DRVSTR_HI:
849 conf &= (~ATMEL_PIO_DRVSTR_MASK);
850 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
851 break;
852 default:
853 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
854 }
855 break;
856 default:
857 dev_warn(pctldev->dev,
858 "unsupported configuration parameter: %u\n",
859 param);
860 continue;
861 }
862 }
863
864 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
865 atmel_pin_config_write(pctldev, pin_id, conf);
866
867 return 0;
868 }
869
870 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
871 struct seq_file *s, unsigned pin_id)
872 {
873 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
874 u32 conf;
875
876 if (!atmel_pioctrl->pins[pin_id]->device)
877 return;
878
879 if (atmel_pioctrl->pins[pin_id])
880 seq_printf(s, " (%s, ioset %u) ",
881 atmel_pioctrl->pins[pin_id]->device,
882 atmel_pioctrl->pins[pin_id]->ioset);
883
884 conf = atmel_pin_config_read(pctldev, pin_id);
885 if (conf & ATMEL_PIO_PUEN_MASK)
886 seq_printf(s, "%s ", "pull-up");
887 if (conf & ATMEL_PIO_PDEN_MASK)
888 seq_printf(s, "%s ", "pull-down");
889 if (conf & ATMEL_PIO_IFEN_MASK)
890 seq_printf(s, "%s ", "debounce");
891 if (conf & ATMEL_PIO_OPD_MASK)
892 seq_printf(s, "%s ", "open-drain");
893 if (conf & ATMEL_PIO_SCHMITT_MASK)
894 seq_printf(s, "%s ", "schmitt");
895 if (conf & ATMEL_PIO_DRVSTR_MASK) {
896 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
897 case ATMEL_PIO_DRVSTR_ME:
898 seq_printf(s, "%s ", "medium-drive");
899 break;
900 case ATMEL_PIO_DRVSTR_HI:
901 seq_printf(s, "%s ", "high-drive");
902 break;
903 /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
904 default:
905 seq_printf(s, "%s ", "low-drive");
906 }
907 }
908 }
909
910 static const struct pinconf_ops atmel_confops = {
911 .pin_config_group_get = atmel_conf_pin_config_group_get,
912 .pin_config_group_set = atmel_conf_pin_config_group_set,
913 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
914 };
915
916 static struct pinctrl_desc atmel_pinctrl_desc = {
917 .name = "atmel_pinctrl",
918 .confops = &atmel_confops,
919 .pctlops = &atmel_pctlops,
920 .pmxops = &atmel_pmxops,
921 };
922
923 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
924 {
925 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
926 int i, j;
927
928 /*
929 * For each bank, save IMR to restore it later and disable all GPIO
930 * interrupts excepting the ones marked as wakeup sources.
931 */
932 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
933 atmel_pioctrl->pm_suspend_backup[i].imr =
934 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
935 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
936 ~atmel_pioctrl->pm_wakeup_sources[i]);
937 atmel_pioctrl->pm_suspend_backup[i].odsr =
938 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
939 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
940 atmel_gpio_write(atmel_pioctrl, i,
941 ATMEL_PIO_MSKR, BIT(j));
942 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
943 atmel_gpio_read(atmel_pioctrl, i,
944 ATMEL_PIO_CFGR);
945 }
946 }
947
948 return 0;
949 }
950
951 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
952 {
953 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
954 int i, j;
955
956 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
957 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
958 atmel_pioctrl->pm_suspend_backup[i].imr);
959 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
960 atmel_pioctrl->pm_suspend_backup[i].odsr);
961 for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
962 atmel_gpio_write(atmel_pioctrl, i,
963 ATMEL_PIO_MSKR, BIT(j));
964 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
965 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
966 }
967 }
968
969 return 0;
970 }
971
972 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
973 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
974 };
975
976 /*
977 * The number of banks can be different from a SoC to another one.
978 * We can have up to 16 banks.
979 */
980 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
981 .nbanks = 4,
982 };
983
984 static const struct of_device_id atmel_pctrl_of_match[] = {
985 {
986 .compatible = "atmel,sama5d2-pinctrl",
987 .data = &atmel_sama5d2_pioctrl_data,
988 }, {
989 /* sentinel */
990 }
991 };
992
993 static int atmel_pinctrl_probe(struct platform_device *pdev)
994 {
995 struct device *dev = &pdev->dev;
996 struct pinctrl_pin_desc *pin_desc;
997 const char **group_names;
998 const struct of_device_id *match;
999 int i, ret;
1000 struct resource *res;
1001 struct atmel_pioctrl *atmel_pioctrl;
1002 const struct atmel_pioctrl_data *atmel_pioctrl_data;
1003
1004 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
1005 if (!atmel_pioctrl)
1006 return -ENOMEM;
1007 atmel_pioctrl->dev = dev;
1008 atmel_pioctrl->node = dev->of_node;
1009 platform_set_drvdata(pdev, atmel_pioctrl);
1010
1011 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
1012 if (!match) {
1013 dev_err(dev, "unknown compatible string\n");
1014 return -ENODEV;
1015 }
1016 atmel_pioctrl_data = match->data;
1017 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
1018 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
1019
1020 atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1021 if (IS_ERR(atmel_pioctrl->reg_base))
1022 return -EINVAL;
1023
1024 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
1025 if (IS_ERR(atmel_pioctrl->clk)) {
1026 dev_err(dev, "failed to get clock\n");
1027 return PTR_ERR(atmel_pioctrl->clk);
1028 }
1029
1030 atmel_pioctrl->pins = devm_kcalloc(dev,
1031 atmel_pioctrl->npins,
1032 sizeof(*atmel_pioctrl->pins),
1033 GFP_KERNEL);
1034 if (!atmel_pioctrl->pins)
1035 return -ENOMEM;
1036
1037 pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
1038 GFP_KERNEL);
1039 if (!pin_desc)
1040 return -ENOMEM;
1041 atmel_pinctrl_desc.pins = pin_desc;
1042 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
1043 atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
1044 atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
1045
1046 /* One pin is one group since a pin can achieve all functions. */
1047 group_names = devm_kcalloc(dev,
1048 atmel_pioctrl->npins, sizeof(*group_names),
1049 GFP_KERNEL);
1050 if (!group_names)
1051 return -ENOMEM;
1052 atmel_pioctrl->group_names = group_names;
1053
1054 atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1055 atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1056 GFP_KERNEL);
1057 if (!atmel_pioctrl->groups)
1058 return -ENOMEM;
1059 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1060 struct atmel_group *group = atmel_pioctrl->groups + i;
1061 unsigned bank = ATMEL_PIO_BANK(i);
1062 unsigned line = ATMEL_PIO_LINE(i);
1063
1064 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1065 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1066 if (!atmel_pioctrl->pins[i])
1067 return -ENOMEM;
1068
1069 atmel_pioctrl->pins[i]->pin_id = i;
1070 atmel_pioctrl->pins[i]->bank = bank;
1071 atmel_pioctrl->pins[i]->line = line;
1072
1073 pin_desc[i].number = i;
1074 /* Pin naming convention: P(bank_name)(bank_pin_number). */
1075 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1076 bank + 'A', line);
1077
1078 group->name = group_names[i] = pin_desc[i].name;
1079 group->pin = pin_desc[i].number;
1080
1081 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1082 }
1083
1084 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1085 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
1086 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1087 atmel_pioctrl->gpio_chip->label = dev_name(dev);
1088 atmel_pioctrl->gpio_chip->parent = dev;
1089 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1090
1091 atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1092 atmel_pioctrl->nbanks,
1093 sizeof(*atmel_pioctrl->pm_wakeup_sources),
1094 GFP_KERNEL);
1095 if (!atmel_pioctrl->pm_wakeup_sources)
1096 return -ENOMEM;
1097
1098 atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1099 atmel_pioctrl->nbanks,
1100 sizeof(*atmel_pioctrl->pm_suspend_backup),
1101 GFP_KERNEL);
1102 if (!atmel_pioctrl->pm_suspend_backup)
1103 return -ENOMEM;
1104
1105 atmel_pioctrl->irqs = devm_kcalloc(dev,
1106 atmel_pioctrl->nbanks,
1107 sizeof(*atmel_pioctrl->irqs),
1108 GFP_KERNEL);
1109 if (!atmel_pioctrl->irqs)
1110 return -ENOMEM;
1111
1112 /* There is one controller but each bank has its own irq line. */
1113 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1114 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1115 if (!res) {
1116 dev_err(dev, "missing irq resource for group %c\n",
1117 'A' + i);
1118 return -EINVAL;
1119 }
1120 atmel_pioctrl->irqs[i] = res->start;
1121 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1122 irq_set_handler_data(res->start, atmel_pioctrl);
1123 dev_dbg(dev, "bank %i: irq=%pr\n", i, res);
1124 }
1125
1126 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1127 atmel_pioctrl->gpio_chip->ngpio,
1128 &irq_domain_simple_ops, NULL);
1129 if (!atmel_pioctrl->irq_domain) {
1130 dev_err(dev, "can't add the irq domain\n");
1131 return -ENODEV;
1132 }
1133 atmel_pioctrl->irq_domain->name = "atmel gpio";
1134
1135 for (i = 0; i < atmel_pioctrl->npins; i++) {
1136 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1137
1138 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1139 handle_simple_irq);
1140 irq_set_chip_data(irq, atmel_pioctrl);
1141 dev_dbg(dev,
1142 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1143 i, irq);
1144 }
1145
1146 ret = clk_prepare_enable(atmel_pioctrl->clk);
1147 if (ret) {
1148 dev_err(dev, "failed to prepare and enable clock\n");
1149 goto clk_prepare_enable_error;
1150 }
1151
1152 atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1153 &atmel_pinctrl_desc,
1154 atmel_pioctrl);
1155 if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1156 ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1157 dev_err(dev, "pinctrl registration failed\n");
1158 goto clk_unprep;
1159 }
1160
1161 ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1162 if (ret) {
1163 dev_err(dev, "failed to add gpiochip\n");
1164 goto clk_unprep;
1165 }
1166
1167 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1168 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1169 if (ret) {
1170 dev_err(dev, "failed to add gpio pin range\n");
1171 goto gpiochip_add_pin_range_error;
1172 }
1173
1174 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1175
1176 return 0;
1177
1178 gpiochip_add_pin_range_error:
1179 gpiochip_remove(atmel_pioctrl->gpio_chip);
1180
1181 clk_unprep:
1182 clk_disable_unprepare(atmel_pioctrl->clk);
1183
1184 clk_prepare_enable_error:
1185 irq_domain_remove(atmel_pioctrl->irq_domain);
1186
1187 return ret;
1188 }
1189
1190 static struct platform_driver atmel_pinctrl_driver = {
1191 .driver = {
1192 .name = "pinctrl-at91-pio4",
1193 .of_match_table = atmel_pctrl_of_match,
1194 .pm = &atmel_pctrl_pm_ops,
1195 .suppress_bind_attrs = true,
1196 },
1197 .probe = atmel_pinctrl_probe,
1198 };
1199 builtin_platform_driver(atmel_pinctrl_driver);
Ubuntu Jammy Linux kernel mirror