drivers/pinctrl/pinctrl-coh901.c

   1 /*
   2  * U300 GPIO module.
   3  *
   4  * Copyright (C) 2007-2012 ST-Ericsson AB
   5  * License terms: GNU General Public License (GPL) version 2
   6  * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
   7  * Author: Linus Walleij <linus.walleij@linaro.org>
   8  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   9  */
  10 #include <linux/module.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/delay.h>
  14 #include <linux/errno.h>
  15 #include <linux/io.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/gpio.h>
  21 #include <linux/list.h>
  22 #include <linux/slab.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/platform_data/pinctrl-coh901.h>
  26 #include "pinctrl-coh901.h"
  27
  28 #define U300_GPIO_PORT_STRIDE                           (0x30)
  29 /*
  30  * Control Register 32bit (R/W)
  31  * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
  32  * gives the number of GPIO pins.
  33  * bit 8-2  (mask 0x000001FC) contains the core version ID.
  34  */
  35 #define U300_GPIO_CR                                    (0x00)
  36 #define U300_GPIO_CR_SYNC_SEL_ENABLE                    (0x00000002UL)
  37 #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE                 (0x00000001UL)
  38 #define U300_GPIO_PXPDIR                                (0x04)
  39 #define U300_GPIO_PXPDOR                                (0x08)
  40 #define U300_GPIO_PXPCR                                 (0x0C)
  41 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK              (0x0000FFFFUL)
  42 #define U300_GPIO_PXPCR_PIN_MODE_MASK                   (0x00000003UL)
  43 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT                  (0x00000002UL)
  44 #define U300_GPIO_PXPCR_PIN_MODE_INPUT                  (0x00000000UL)
  45 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL       (0x00000001UL)
  46 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN      (0x00000002UL)
  47 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE     (0x00000003UL)
  48 #define U300_GPIO_PXPER                                 (0x10)
  49 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK        (0x000000FFUL)
  50 #define U300_GPIO_PXPER_PULL_UP_DISABLE                 (0x00000001UL)
  51 #define U300_GPIO_PXIEV                                 (0x14)
  52 #define U300_GPIO_PXIEN                                 (0x18)
  53 #define U300_GPIO_PXIFR                                 (0x1C)
  54 #define U300_GPIO_PXICR                                 (0x20)
  55 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK             (0x000000FFUL)
  56 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK                 (0x00000001UL)
  57 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE         (0x00000000UL)
  58 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
  59
  60 /* 8 bits per port, no version has more than 7 ports */
  61 #define U300_GPIO_PINS_PER_PORT 8
  62 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
  63
  64 struct u300_gpio {
  65         struct gpio_chip chip;
  66         struct list_head port_list;
  67         struct clk *clk;
  68         void __iomem *base;
  69         struct device *dev;
  70         u32 stride;
  71         /* Register offsets */
  72         u32 pcr;
  73         u32 dor;
  74         u32 dir;
  75         u32 per;
  76         u32 icr;
  77         u32 ien;
  78         u32 iev;
  79 };
  80
  81 struct u300_gpio_port {
  82         struct list_head node;
  83         struct u300_gpio *gpio;
  84         char name[8];
  85         struct irq_domain *domain;
  86         int irq;
  87         int number;
  88         u8 toggle_edge_mode;
  89 };
  90
  91 /*
  92  * Macro to expand to read a specific register found in the "gpio"
  93  * struct. It requires the struct u300_gpio *gpio variable to exist in
  94  * its context. It calculates the port offset from the given pin
  95  * offset, muliplies by the port stride and adds the register offset
  96  * so it provides a pointer to the desired register.
  97  */
  98 #define U300_PIN_REG(pin, reg) \
  99         (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
 100
 101 /*
 102  * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
 103  * register.
 104  */
 105 #define U300_PIN_BIT(pin) \
 106         (1 << (pin & 0x07))
 107
 108 struct u300_gpio_confdata {
 109         u16 bias_mode;
 110         bool output;
 111         int outval;
 112 };
 113
 114 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
 115 #define BS335_GPIO_NUM_PORTS 7
 116
 117 #define U300_FLOATING_INPUT { \
 118         .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
 119         .output = false, \
 120 }
 121
 122 #define U300_PULL_UP_INPUT { \
 123         .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
 124         .output = false, \
 125 }
 126
 127 #define U300_OUTPUT_LOW { \
 128         .output = true, \
 129         .outval = 0, \
 130 }
 131
 132 #define U300_OUTPUT_HIGH { \
 133         .output = true, \
 134         .outval = 1, \
 135 }
 136
 137 /* Initial configuration */
 138 static const struct __initconst u300_gpio_confdata
 139 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
 140         /* Port 0, pins 0-7 */
 141         {
 142                 U300_FLOATING_INPUT,
 143                 U300_OUTPUT_HIGH,
 144                 U300_FLOATING_INPUT,
 145                 U300_OUTPUT_LOW,
 146                 U300_OUTPUT_LOW,
 147                 U300_OUTPUT_LOW,
 148                 U300_OUTPUT_LOW,
 149                 U300_OUTPUT_LOW,
 150         },
 151         /* Port 1, pins 0-7 */
 152         {
 153                 U300_OUTPUT_LOW,
 154                 U300_OUTPUT_LOW,
 155                 U300_OUTPUT_LOW,
 156                 U300_PULL_UP_INPUT,
 157                 U300_FLOATING_INPUT,
 158                 U300_OUTPUT_HIGH,
 159                 U300_OUTPUT_LOW,
 160                 U300_OUTPUT_LOW,
 161         },
 162         /* Port 2, pins 0-7 */
 163         {
 164                 U300_FLOATING_INPUT,
 165                 U300_FLOATING_INPUT,
 166                 U300_FLOATING_INPUT,
 167                 U300_FLOATING_INPUT,
 168                 U300_OUTPUT_LOW,
 169                 U300_PULL_UP_INPUT,
 170                 U300_OUTPUT_LOW,
 171                 U300_PULL_UP_INPUT,
 172         },
 173         /* Port 3, pins 0-7 */
 174         {
 175                 U300_PULL_UP_INPUT,
 176                 U300_OUTPUT_LOW,
 177                 U300_FLOATING_INPUT,
 178                 U300_FLOATING_INPUT,
 179                 U300_FLOATING_INPUT,
 180                 U300_FLOATING_INPUT,
 181                 U300_FLOATING_INPUT,
 182                 U300_FLOATING_INPUT,
 183         },
 184         /* Port 4, pins 0-7 */
 185         {
 186                 U300_FLOATING_INPUT,
 187                 U300_FLOATING_INPUT,
 188                 U300_FLOATING_INPUT,
 189                 U300_FLOATING_INPUT,
 190                 U300_FLOATING_INPUT,
 191                 U300_FLOATING_INPUT,
 192                 U300_FLOATING_INPUT,
 193                 U300_FLOATING_INPUT,
 194         },
 195         /* Port 5, pins 0-7 */
 196         {
 197                 U300_FLOATING_INPUT,
 198                 U300_FLOATING_INPUT,
 199                 U300_FLOATING_INPUT,
 200                 U300_FLOATING_INPUT,
 201                 U300_FLOATING_INPUT,
 202                 U300_FLOATING_INPUT,
 203                 U300_FLOATING_INPUT,
 204                 U300_FLOATING_INPUT,
 205         },
 206         /* Port 6, pind 0-7 */
 207         {
 208                 U300_FLOATING_INPUT,
 209                 U300_FLOATING_INPUT,
 210                 U300_FLOATING_INPUT,
 211                 U300_FLOATING_INPUT,
 212                 U300_FLOATING_INPUT,
 213                 U300_FLOATING_INPUT,
 214                 U300_FLOATING_INPUT,
 215                 U300_FLOATING_INPUT,
 216         }
 217 };
 218
 219 /**
 220  * to_u300_gpio() - get the pointer to u300_gpio
 221  * @chip: the gpio chip member of the structure u300_gpio
 222  */
 223 static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
 224 {
 225         return container_of(chip, struct u300_gpio, chip);
 226 }
 227
 228 static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
 229 {
 230         /*
 231          * Map back to global GPIO space and request muxing, the direction
 232          * parameter does not matter for this controller.
 233          */
 234         int gpio = chip->base + offset;
 235
 236         return pinctrl_request_gpio(gpio);
 237 }
 238
 239 static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
 240 {
 241         int gpio = chip->base + offset;
 242
 243         pinctrl_free_gpio(gpio);
 244 }
 245
 246 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
 247 {
 248         struct u300_gpio *gpio = to_u300_gpio(chip);
 249
 250         return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
 251 }
 252
 253 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 254 {
 255         struct u300_gpio *gpio = to_u300_gpio(chip);
 256         unsigned long flags;
 257         u32 val;
 258
 259         local_irq_save(flags);
 260
 261         val = readl(U300_PIN_REG(offset, dor));
 262         if (value)
 263                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 264         else
 265                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
 266
 267         local_irq_restore(flags);
 268 }
 269
 270 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 271 {
 272         struct u300_gpio *gpio = to_u300_gpio(chip);
 273         unsigned long flags;
 274         u32 val;
 275
 276         local_irq_save(flags);
 277         val = readl(U300_PIN_REG(offset, pcr));
 278         /* Mask out this pin, note 2 bits per setting */
 279         val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 280         writel(val, U300_PIN_REG(offset, pcr));
 281         local_irq_restore(flags);
 282         return 0;
 283 }
 284
 285 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 286                                       int value)
 287 {
 288         struct u300_gpio *gpio = to_u300_gpio(chip);
 289         unsigned long flags;
 290         u32 oldmode;
 291         u32 val;
 292
 293         local_irq_save(flags);
 294         val = readl(U300_PIN_REG(offset, pcr));
 295         /*
 296          * Drive mode must be set by the special mode set function, set
 297          * push/pull mode by default if no mode has been selected.
 298          */
 299         oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
 300                          ((offset & 0x07) << 1));
 301         /* mode = 0 means input, else some mode is already set */
 302         if (oldmode == 0) {
 303                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
 304                          ((offset & 0x07) << 1));
 305                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 306                         << ((offset & 0x07) << 1));
 307                 writel(val, U300_PIN_REG(offset, pcr));
 308         }
 309         u300_gpio_set(chip, offset, value);
 310         local_irq_restore(flags);
 311         return 0;
 312 }
 313
 314 static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 315 {
 316         struct u300_gpio *gpio = to_u300_gpio(chip);
 317         int portno = offset >> 3;
 318         struct u300_gpio_port *port = NULL;
 319         struct list_head *p;
 320         int retirq;
 321
 322         list_for_each(p, &gpio->port_list) {
 323                 port = list_entry(p, struct u300_gpio_port, node);
 324                 if (port->number == portno)
 325                         break;
 326         }
 327         if (port == NULL) {
 328                 dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n",
 329                         offset);
 330                 return -EINVAL;
 331         }
 332
 333         /*
 334          * The local hwirqs on the port are the lower three bits, there
 335          * are exactly 8 IRQs per port since they are 8-bit
 336          */
 337         retirq = irq_find_mapping(port->domain, (offset & 0x7));
 338
 339         dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n",
 340                 offset, retirq, port->number);
 341         return retirq;
 342 }
 343
 344 /* Returning -EINVAL means "supported but not available" */
 345 int u300_gpio_config_get(struct gpio_chip *chip,
 346                          unsigned offset,
 347                          unsigned long *config)
 348 {
 349         struct u300_gpio *gpio = to_u300_gpio(chip);
 350         enum pin_config_param param = (enum pin_config_param) *config;
 351         bool biasmode;
 352         u32 drmode;
 353
 354         /* One bit per pin, clamp to bool range */
 355         biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
 356
 357         /* Mask out the two bits for this pin and shift to bits 0,1 */
 358         drmode = readl(U300_PIN_REG(offset, pcr));
 359         drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
 360         drmode >>= ((offset & 0x07) << 1);
 361
 362         switch(param) {
 363         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 364                 *config = 0;
 365                 if (biasmode)
 366                         return 0;
 367                 else
 368                         return -EINVAL;
 369                 break;
 370         case PIN_CONFIG_BIAS_PULL_UP:
 371                 *config = 0;
 372                 if (!biasmode)
 373                         return 0;
 374                 else
 375                         return -EINVAL;
 376                 break;
 377         case PIN_CONFIG_DRIVE_PUSH_PULL:
 378                 *config = 0;
 379                 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
 380                         return 0;
 381                 else
 382                         return -EINVAL;
 383                 break;
 384         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 385                 *config = 0;
 386                 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
 387                         return 0;
 388                 else
 389                         return -EINVAL;
 390                 break;
 391         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 392                 *config = 0;
 393                 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
 394                         return 0;
 395                 else
 396                         return -EINVAL;
 397                 break;
 398         default:
 399                 break;
 400         }
 401         return -ENOTSUPP;
 402 }
 403
 404 int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
 405                          enum pin_config_param param)
 406 {
 407         struct u300_gpio *gpio = to_u300_gpio(chip);
 408         unsigned long flags;
 409         u32 val;
 410
 411         local_irq_save(flags);
 412         switch (param) {
 413         case PIN_CONFIG_BIAS_DISABLE:
 414         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 415                 val = readl(U300_PIN_REG(offset, per));
 416                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 417                 break;
 418         case PIN_CONFIG_BIAS_PULL_UP:
 419                 val = readl(U300_PIN_REG(offset, per));
 420                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
 421                 break;
 422         case PIN_CONFIG_DRIVE_PUSH_PULL:
 423                 val = readl(U300_PIN_REG(offset, pcr));
 424                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 425                          << ((offset & 0x07) << 1));
 426                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 427                         << ((offset & 0x07) << 1));
 428                 writel(val, U300_PIN_REG(offset, pcr));
 429                 break;
 430         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 431                 val = readl(U300_PIN_REG(offset, pcr));
 432                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 433                          << ((offset & 0x07) << 1));
 434                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
 435                         << ((offset & 0x07) << 1));
 436                 writel(val, U300_PIN_REG(offset, pcr));
 437                 break;
 438         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
 439                 val = readl(U300_PIN_REG(offset, pcr));
 440                 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
 441                          << ((offset & 0x07) << 1));
 442                 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
 443                         << ((offset & 0x07) << 1));
 444                 writel(val, U300_PIN_REG(offset, pcr));
 445                 break;
 446         default:
 447                 local_irq_restore(flags);
 448                 dev_err(gpio->dev, "illegal configuration requested\n");
 449                 return -EINVAL;
 450         }
 451         local_irq_restore(flags);
 452         return 0;
 453 }
 454
 455 static struct gpio_chip u300_gpio_chip = {
 456         .label                  = "u300-gpio-chip",
 457         .owner                  = THIS_MODULE,
 458         .request                = u300_gpio_request,
 459         .free                   = u300_gpio_free,
 460         .get                    = u300_gpio_get,
 461         .set                    = u300_gpio_set,
 462         .direction_input        = u300_gpio_direction_input,
 463         .direction_output       = u300_gpio_direction_output,
 464         .to_irq                 = u300_gpio_to_irq,
 465 };
 466
 467 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
 468 {
 469         u32 val;
 470
 471         val = readl(U300_PIN_REG(offset, icr));
 472         /* Set mode depending on state */
 473         if (u300_gpio_get(&gpio->chip, offset)) {
 474                 /* High now, let's trigger on falling edge next then */
 475                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 476                 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
 477                         offset);
 478         } else {
 479                 /* Low now, let's trigger on rising edge next then */
 480                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 481                 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
 482                         offset);
 483         }
 484 }
 485
 486 static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
 487 {
 488         struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 489         struct u300_gpio *gpio = port->gpio;
 490         int offset = (port->number << 3) + d->hwirq;
 491         u32 val;
 492
 493         if ((trigger & IRQF_TRIGGER_RISING) &&
 494             (trigger & IRQF_TRIGGER_FALLING)) {
 495                 /*
 496                  * The GPIO block can only trigger on falling OR rising edges,
 497                  * not both. So we need to toggle the mode whenever the pin
 498                  * goes from one state to the other with a special state flag
 499                  */
 500                 dev_dbg(gpio->dev,
 501                         "trigger on both rising and falling edge on pin %d\n",
 502                         offset);
 503                 port->toggle_edge_mode |= U300_PIN_BIT(offset);
 504                 u300_toggle_trigger(gpio, offset);
 505         } else if (trigger & IRQF_TRIGGER_RISING) {
 506                 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
 507                         offset);
 508                 val = readl(U300_PIN_REG(offset, icr));
 509                 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 510                 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 511         } else if (trigger & IRQF_TRIGGER_FALLING) {
 512                 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
 513                         offset);
 514                 val = readl(U300_PIN_REG(offset, icr));
 515                 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
 516                 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
 517         }
 518
 519         return 0;
 520 }
 521
 522 static void u300_gpio_irq_enable(struct irq_data *d)
 523 {
 524         struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 525         struct u300_gpio *gpio = port->gpio;
 526         int offset = (port->number << 3) + d->hwirq;
 527         u32 val;
 528         unsigned long flags;
 529
 530         dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
 531                  d->hwirq, port->name, offset);
 532         local_irq_save(flags);
 533         val = readl(U300_PIN_REG(offset, ien));
 534         writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 535         local_irq_restore(flags);
 536 }
 537
 538 static void u300_gpio_irq_disable(struct irq_data *d)
 539 {
 540         struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
 541         struct u300_gpio *gpio = port->gpio;
 542         int offset = (port->number << 3) + d->hwirq;
 543         u32 val;
 544         unsigned long flags;
 545
 546         local_irq_save(flags);
 547         val = readl(U300_PIN_REG(offset, ien));
 548         writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
 549         local_irq_restore(flags);
 550 }
 551
 552 static struct irq_chip u300_gpio_irqchip = {
 553         .name                   = "u300-gpio-irqchip",
 554         .irq_enable             = u300_gpio_irq_enable,
 555         .irq_disable            = u300_gpio_irq_disable,
 556         .irq_set_type           = u300_gpio_irq_type,
 557
 558 };
 559
 560 static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 561 {
 562         struct u300_gpio_port *port = irq_get_handler_data(irq);
 563         struct u300_gpio *gpio = port->gpio;
 564         int pinoffset = port->number << 3; /* get the right stride */
 565         unsigned long val;
 566
 567         desc->irq_data.chip->irq_ack(&desc->irq_data);
 568         /* Read event register */
 569         val = readl(U300_PIN_REG(pinoffset, iev));
 570         /* Mask relevant bits */
 571         val &= 0xFFU; /* 8 bits per port */
 572         /* ACK IRQ (clear event) */
 573         writel(val, U300_PIN_REG(pinoffset, iev));
 574
 575         /* Call IRQ handler */
 576         if (val != 0) {
 577                 int irqoffset;
 578
 579                 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
 580                         int pin_irq = irq_find_mapping(port->domain, irqoffset);
 581                         int offset = pinoffset + irqoffset;
 582
 583                         dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
 584                                 pin_irq, offset);
 585                         generic_handle_irq(pin_irq);
 586                         /*
 587                          * Triggering IRQ on both rising and falling edge
 588                          * needs mockery
 589                          */
 590                         if (port->toggle_edge_mode & U300_PIN_BIT(offset))
 591                                 u300_toggle_trigger(gpio, offset);
 592                 }
 593         }
 594
 595         desc->irq_data.chip->irq_unmask(&desc->irq_data);
 596 }
 597
 598 static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
 599                                       int offset,
 600                                       const struct u300_gpio_confdata *conf)
 601 {
 602         /* Set mode: input or output */
 603         if (conf->output) {
 604                 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
 605
 606                 /* Deactivate bias mode for output */
 607                 u300_gpio_config_set(&gpio->chip, offset,
 608                                      PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
 609
 610                 /* Set drive mode for output */
 611                 u300_gpio_config_set(&gpio->chip, offset,
 612                                      PIN_CONFIG_DRIVE_PUSH_PULL);
 613
 614                 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
 615                         offset, conf->outval);
 616         } else {
 617                 u300_gpio_direction_input(&gpio->chip, offset);
 618
 619                 /* Always set output low on input pins */
 620                 u300_gpio_set(&gpio->chip, offset, 0);
 621
 622                 /* Set bias mode for input */
 623                 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
 624
 625                 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
 626                         offset, conf->bias_mode);
 627         }
 628 }
 629
 630 static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
 631                                      struct u300_gpio_platform *plat)
 632 {
 633         int i, j;
 634
 635         /* Write default config and values to all pins */
 636         for (i = 0; i < plat->ports; i++) {
 637                 for (j = 0; j < 8; j++) {
 638                         const struct u300_gpio_confdata *conf;
 639                         int offset = (i*8) + j;
 640
 641                         conf = &bs335_gpio_config[i][j];
 642                         u300_gpio_init_pin(gpio, offset, conf);
 643                 }
 644         }
 645 }
 646
 647 static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
 648 {
 649         struct u300_gpio_port *port;
 650         struct list_head *p, *n;
 651
 652         list_for_each_safe(p, n, &gpio->port_list) {
 653                 port = list_entry(p, struct u300_gpio_port, node);
 654                 list_del(&port->node);
 655                 if (port->domain)
 656                         irq_domain_remove(port->domain);
 657                 kfree(port);
 658         }
 659 }
 660
 661 static int __init u300_gpio_probe(struct platform_device *pdev)
 662 {
 663         struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
 664         struct u300_gpio *gpio;
 665         struct resource *memres;
 666         int err = 0;
 667         int portno;
 668         u32 val;
 669         u32 ifr;
 670         int i;
 671
 672         gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
 673         if (gpio == NULL)
 674                 return -ENOMEM;
 675
 676         gpio->chip = u300_gpio_chip;
 677         gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
 678         gpio->chip.dev = &pdev->dev;
 679         gpio->chip.base = plat->gpio_base;
 680         gpio->dev = &pdev->dev;
 681
 682         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 683         if (!memres) {
 684                 dev_err(gpio->dev, "could not get GPIO memory resource\n");
 685                 return -ENODEV;
 686         }
 687
 688         gpio->base = devm_request_and_ioremap(&pdev->dev, memres);
 689         if (!gpio->base) {
 690                 dev_err(gpio->dev, "could not get remap memory\n");
 691                 return -ENOMEM;
 692         }
 693
 694         gpio->clk = devm_clk_get(gpio->dev, NULL);
 695         if (IS_ERR(gpio->clk)) {
 696                 err = PTR_ERR(gpio->clk);
 697                 dev_err(gpio->dev, "could not get GPIO clock\n");
 698                 return err;
 699         }
 700
 701         err = clk_prepare_enable(gpio->clk);
 702         if (err) {
 703                 dev_err(gpio->dev, "could not enable GPIO clock\n");
 704                 return err;
 705         }
 706
 707         dev_info(gpio->dev,
 708                  "initializing GPIO Controller COH 901 571/3\n");
 709         gpio->stride = U300_GPIO_PORT_STRIDE;
 710         gpio->pcr = U300_GPIO_PXPCR;
 711         gpio->dor = U300_GPIO_PXPDOR;
 712         gpio->dir = U300_GPIO_PXPDIR;
 713         gpio->per = U300_GPIO_PXPER;
 714         gpio->icr = U300_GPIO_PXICR;
 715         gpio->ien = U300_GPIO_PXIEN;
 716         gpio->iev = U300_GPIO_PXIEV;
 717         ifr = U300_GPIO_PXIFR;
 718
 719         val = readl(gpio->base + U300_GPIO_CR);
 720         dev_info(gpio->dev, "COH901571/3 block version: %d, " \
 721                  "number of cores: %d totalling %d pins\n",
 722                  ((val & 0x000001FC) >> 2),
 723                  ((val & 0x0000FE00) >> 9),
 724                  ((val & 0x0000FE00) >> 9) * 8);
 725         writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
 726                gpio->base + U300_GPIO_CR);
 727         u300_gpio_init_coh901571(gpio, plat);
 728
 729         /* Add each port with its IRQ separately */
 730         INIT_LIST_HEAD(&gpio->port_list);
 731         for (portno = 0 ; portno < plat->ports; portno++) {
 732                 struct u300_gpio_port *port =
 733                         kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 734
 735                 if (!port) {
 736                         dev_err(gpio->dev, "out of memory\n");
 737                         err = -ENOMEM;
 738                         goto err_no_port;
 739                 }
 740
 741                 snprintf(port->name, 8, "gpio%d", portno);
 742                 port->number = portno;
 743                 port->gpio = gpio;
 744
 745                 port->irq = platform_get_irq_byname(pdev,
 746                                                     port->name);
 747
 748                 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
 749                         port->name);
 750
 751                 port->domain = irq_domain_add_linear(pdev->dev.of_node,
 752                                                      U300_GPIO_PINS_PER_PORT,
 753                                                      &irq_domain_simple_ops,
 754                                                      port);
 755                 if (!port->domain)
 756                         goto err_no_domain;
 757
 758                 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
 759                 irq_set_handler_data(port->irq, port);
 760
 761                 /* For each GPIO pin set the unique IRQ handler */
 762                 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
 763                         int irqno = irq_create_mapping(port->domain, i);
 764
 765                         dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n",
 766                                 gpio->chip.base + (port->number << 3) + i,
 767                                 port->name, irqno);
 768                         irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
 769                                                  handle_simple_irq);
 770                         set_irq_flags(irqno, IRQF_VALID);
 771                         irq_set_chip_data(irqno, port);
 772                 }
 773
 774                 /* Turns off irq force (test register) for this port */
 775                 writel(0x0, gpio->base + portno * gpio->stride + ifr);
 776
 777                 list_add_tail(&port->node, &gpio->port_list);
 778         }
 779         dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 780
 781         err = gpiochip_add(&gpio->chip);
 782         if (err) {
 783                 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
 784                 goto err_no_chip;
 785         }
 786
 787         /* Spawn pin controller device as child of the GPIO, pass gpio chip */
 788         plat->pinctrl_device->dev.platform_data = &gpio->chip;
 789         err = platform_device_register(plat->pinctrl_device);
 790         if (err)
 791                 goto err_no_pinctrl;
 792
 793         platform_set_drvdata(pdev, gpio);
 794
 795         return 0;
 796
 797 err_no_pinctrl:
 798         err = gpiochip_remove(&gpio->chip);
 799 err_no_chip:
 800 err_no_domain:
 801 err_no_port:
 802         u300_gpio_free_ports(gpio);
 803         clk_disable_unprepare(gpio->clk);
 804         dev_info(&pdev->dev, "module ERROR:%d\n", err);
 805         return err;
 806 }
 807
 808 static int __exit u300_gpio_remove(struct platform_device *pdev)
 809 {
 810         struct u300_gpio *gpio = platform_get_drvdata(pdev);
 811         int err;
 812
 813         /* Turn off the GPIO block */
 814         writel(0x00000000U, gpio->base + U300_GPIO_CR);
 815
 816         err = gpiochip_remove(&gpio->chip);
 817         if (err < 0) {
 818                 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
 819                 return err;
 820         }
 821         u300_gpio_free_ports(gpio);
 822         clk_disable_unprepare(gpio->clk);
 823         platform_set_drvdata(pdev, NULL);
 824         return 0;
 825 }
 826
 827 static struct platform_driver u300_gpio_driver = {
 828         .driver         = {
 829                 .name   = "u300-gpio",
 830         },
 831         .remove         = __exit_p(u300_gpio_remove),
 832 };
 833
 834 static int __init u300_gpio_init(void)
 835 {
 836         return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
 837 }
 838
 839 static void __exit u300_gpio_exit(void)
 840 {
 841         platform_driver_unregister(&u300_gpio_driver);
 842 }
 843
 844 arch_initcall(u300_gpio_init);
 845 module_exit(u300_gpio_exit);
 846
 847 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 848 MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
 849 MODULE_LICENSE("GPL");