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[mirror_ubuntu-eoan-kernel.git] / drivers / pinctrl / pinctrl-pistachio.c
1 /*
2 * Pistachio SoC pinctrl driver
3 *
4 * Copyright (C) 2014 Imagination Technologies Ltd.
5 * Copyright (C) 2014 Google, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 */
11
12 #include <linux/gpio/driver.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/irq.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25
26 #include "pinctrl-utils.h"
27
28 #define PADS_SCHMITT_EN0 0x000
29 #define PADS_SCHMITT_EN_REG(pin) (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
30 #define PADS_SCHMITT_EN_BIT(pin) BIT((pin) % 32)
31
32 #define PADS_PU_PD0 0x040
33 #define PADS_PU_PD_REG(pin) (PADS_PU_PD0 + 0x4 * ((pin) / 16))
34 #define PADS_PU_PD_SHIFT(pin) (2 * ((pin) % 16))
35 #define PADS_PU_PD_MASK 0x3
36 #define PADS_PU_PD_HIGHZ 0x0
37 #define PADS_PU_PD_UP 0x1
38 #define PADS_PU_PD_DOWN 0x2
39 #define PADS_PU_PD_BUS 0x3
40
41 #define PADS_FUNCTION_SELECT0 0x0c0
42 #define PADS_FUNCTION_SELECT1 0x0c4
43 #define PADS_FUNCTION_SELECT2 0x0c8
44 #define PADS_SCENARIO_SELECT 0x0f8
45
46 #define PADS_SLEW_RATE0 0x100
47 #define PADS_SLEW_RATE_REG(pin) (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
48 #define PADS_SLEW_RATE_BIT(pin) BIT((pin) % 32)
49
50 #define PADS_DRIVE_STRENGTH0 0x120
51 #define PADS_DRIVE_STRENGTH_REG(pin) \
52 (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
53 #define PADS_DRIVE_STRENGTH_SHIFT(pin) (2 * ((pin) % 16))
54 #define PADS_DRIVE_STRENGTH_MASK 0x3
55 #define PADS_DRIVE_STRENGTH_2MA 0x0
56 #define PADS_DRIVE_STRENGTH_4MA 0x1
57 #define PADS_DRIVE_STRENGTH_8MA 0x2
58 #define PADS_DRIVE_STRENGTH_12MA 0x3
59
60 #define GPIO_BANK_BASE(bank) (0x200 + 0x24 * (bank))
61
62 #define GPIO_BIT_EN 0x00
63 #define GPIO_OUTPUT_EN 0x04
64 #define GPIO_OUTPUT 0x08
65 #define GPIO_INPUT 0x0c
66 #define GPIO_INPUT_POLARITY 0x10
67 #define GPIO_INTERRUPT_TYPE 0x14
68 #define GPIO_INTERRUPT_TYPE_LEVEL 0x0
69 #define GPIO_INTERRUPT_TYPE_EDGE 0x1
70 #define GPIO_INTERRUPT_EDGE 0x18
71 #define GPIO_INTERRUPT_EDGE_SINGLE 0x0
72 #define GPIO_INTERRUPT_EDGE_DUAL 0x1
73 #define GPIO_INTERRUPT_EN 0x1c
74 #define GPIO_INTERRUPT_STATUS 0x20
75
76 struct pistachio_function {
77 const char *name;
78 const char * const *groups;
79 unsigned int ngroups;
80 const int *scenarios;
81 unsigned int nscenarios;
82 unsigned int scenario_reg;
83 unsigned int scenario_shift;
84 unsigned int scenario_mask;
85 };
86
87 struct pistachio_pin_group {
88 const char *name;
89 unsigned int pin;
90 int mux_option[3];
91 int mux_reg;
92 int mux_shift;
93 int mux_mask;
94 };
95
96 struct pistachio_gpio_bank {
97 struct pistachio_pinctrl *pctl;
98 void __iomem *base;
99 unsigned int pin_base;
100 unsigned int npins;
101 struct gpio_chip gpio_chip;
102 struct irq_chip irq_chip;
103 };
104
105 struct pistachio_pinctrl {
106 struct device *dev;
107 void __iomem *base;
108 struct pinctrl_dev *pctldev;
109 const struct pinctrl_pin_desc *pins;
110 unsigned int npins;
111 const struct pistachio_function *functions;
112 unsigned int nfunctions;
113 const struct pistachio_pin_group *groups;
114 unsigned int ngroups;
115 struct pistachio_gpio_bank *gpio_banks;
116 unsigned int nbanks;
117 };
118
119 #define PISTACHIO_PIN_MFIO(p) (p)
120 #define PISTACHIO_PIN_TCK 90
121 #define PISTACHIO_PIN_TRSTN 91
122 #define PISTACHIO_PIN_TDI 92
123 #define PISTACHIO_PIN_TMS 93
124 #define PISTACHIO_PIN_TDO 94
125 #define PISTACHIO_PIN_JTAG_COMPLY 95
126 #define PISTACHIO_PIN_SAFE_MODE 96
127 #define PISTACHIO_PIN_POR_DISABLE 97
128 #define PISTACHIO_PIN_RESETN 98
129
130 #define MFIO_PIN_DESC(p) PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p)
131
132 static const struct pinctrl_pin_desc pistachio_pins[] = {
133 MFIO_PIN_DESC(0),
134 MFIO_PIN_DESC(1),
135 MFIO_PIN_DESC(2),
136 MFIO_PIN_DESC(3),
137 MFIO_PIN_DESC(4),
138 MFIO_PIN_DESC(5),
139 MFIO_PIN_DESC(6),
140 MFIO_PIN_DESC(7),
141 MFIO_PIN_DESC(8),
142 MFIO_PIN_DESC(9),
143 MFIO_PIN_DESC(10),
144 MFIO_PIN_DESC(11),
145 MFIO_PIN_DESC(12),
146 MFIO_PIN_DESC(13),
147 MFIO_PIN_DESC(14),
148 MFIO_PIN_DESC(15),
149 MFIO_PIN_DESC(16),
150 MFIO_PIN_DESC(17),
151 MFIO_PIN_DESC(18),
152 MFIO_PIN_DESC(19),
153 MFIO_PIN_DESC(20),
154 MFIO_PIN_DESC(21),
155 MFIO_PIN_DESC(22),
156 MFIO_PIN_DESC(23),
157 MFIO_PIN_DESC(24),
158 MFIO_PIN_DESC(25),
159 MFIO_PIN_DESC(26),
160 MFIO_PIN_DESC(27),
161 MFIO_PIN_DESC(28),
162 MFIO_PIN_DESC(29),
163 MFIO_PIN_DESC(30),
164 MFIO_PIN_DESC(31),
165 MFIO_PIN_DESC(32),
166 MFIO_PIN_DESC(33),
167 MFIO_PIN_DESC(34),
168 MFIO_PIN_DESC(35),
169 MFIO_PIN_DESC(36),
170 MFIO_PIN_DESC(37),
171 MFIO_PIN_DESC(38),
172 MFIO_PIN_DESC(39),
173 MFIO_PIN_DESC(40),
174 MFIO_PIN_DESC(41),
175 MFIO_PIN_DESC(42),
176 MFIO_PIN_DESC(43),
177 MFIO_PIN_DESC(44),
178 MFIO_PIN_DESC(45),
179 MFIO_PIN_DESC(46),
180 MFIO_PIN_DESC(47),
181 MFIO_PIN_DESC(48),
182 MFIO_PIN_DESC(49),
183 MFIO_PIN_DESC(50),
184 MFIO_PIN_DESC(51),
185 MFIO_PIN_DESC(52),
186 MFIO_PIN_DESC(53),
187 MFIO_PIN_DESC(54),
188 MFIO_PIN_DESC(55),
189 MFIO_PIN_DESC(56),
190 MFIO_PIN_DESC(57),
191 MFIO_PIN_DESC(58),
192 MFIO_PIN_DESC(59),
193 MFIO_PIN_DESC(60),
194 MFIO_PIN_DESC(61),
195 MFIO_PIN_DESC(62),
196 MFIO_PIN_DESC(63),
197 MFIO_PIN_DESC(64),
198 MFIO_PIN_DESC(65),
199 MFIO_PIN_DESC(66),
200 MFIO_PIN_DESC(67),
201 MFIO_PIN_DESC(68),
202 MFIO_PIN_DESC(69),
203 MFIO_PIN_DESC(70),
204 MFIO_PIN_DESC(71),
205 MFIO_PIN_DESC(72),
206 MFIO_PIN_DESC(73),
207 MFIO_PIN_DESC(74),
208 MFIO_PIN_DESC(75),
209 MFIO_PIN_DESC(76),
210 MFIO_PIN_DESC(77),
211 MFIO_PIN_DESC(78),
212 MFIO_PIN_DESC(79),
213 MFIO_PIN_DESC(80),
214 MFIO_PIN_DESC(81),
215 MFIO_PIN_DESC(82),
216 MFIO_PIN_DESC(83),
217 MFIO_PIN_DESC(84),
218 MFIO_PIN_DESC(85),
219 MFIO_PIN_DESC(86),
220 MFIO_PIN_DESC(87),
221 MFIO_PIN_DESC(88),
222 MFIO_PIN_DESC(89),
223 PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"),
224 PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"),
225 PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"),
226 PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"),
227 PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"),
228 PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"),
229 PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"),
230 PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"),
231 PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"),
232 };
233
234 static const char * const pistachio_spim0_groups[] = {
235 "mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29",
236 "mfio30", "mfio55", "mfio56", "mfio57",
237 };
238
239 static const char * const pistachio_spim1_groups[] = {
240 "mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6",
241 "mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58",
242 };
243
244 static const char * const pistachio_spis_groups[] = {
245 "mfio11", "mfio12", "mfio13", "mfio14",
246 };
247
248 static const char *const pistachio_sdhost_groups[] = {
249 "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
250 "mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26",
251 "mfio27",
252 };
253
254 static const char * const pistachio_i2c0_groups[] = {
255 "mfio28", "mfio29",
256 };
257
258 static const char * const pistachio_i2c1_groups[] = {
259 "mfio30", "mfio31",
260 };
261
262 static const char * const pistachio_i2c2_groups[] = {
263 "mfio32", "mfio33",
264 };
265
266 static const char * const pistachio_i2c3_groups[] = {
267 "mfio34", "mfio35",
268 };
269
270 static const char * const pistachio_audio_clk_in_groups[] = {
271 "mfio36",
272 };
273
274 static const char * const pistachio_i2s_out_groups[] = {
275 "mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41",
276 "mfio42", "mfio43", "mfio44",
277 };
278
279 static const char * const pistachio_debug_raw_cca_ind_groups[] = {
280 "mfio37",
281 };
282
283 static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = {
284 "mfio38",
285 };
286
287 static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = {
288 "mfio39",
289 };
290
291 static const char * const pistachio_debug_agc_done_0_groups[] = {
292 "mfio40",
293 };
294
295 static const char * const pistachio_debug_agc_done_1_groups[] = {
296 "mfio41",
297 };
298
299 static const char * const pistachio_debug_ed_cca_ind_groups[] = {
300 "mfio42",
301 };
302
303 static const char * const pistachio_debug_s2l_done_groups[] = {
304 "mfio43",
305 };
306
307 static const char * const pistachio_i2s_dac_clk_groups[] = {
308 "mfio45",
309 };
310
311 static const char * const pistachio_audio_sync_groups[] = {
312 "mfio45",
313 };
314
315 static const char * const pistachio_audio_trigger_groups[] = {
316 "mfio46",
317 };
318
319 static const char * const pistachio_i2s_in_groups[] = {
320 "mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52",
321 "mfio53", "mfio54",
322 };
323
324 static const char * const pistachio_uart0_groups[] = {
325 "mfio55", "mfio56", "mfio57", "mfio58",
326 };
327
328 static const char * const pistachio_uart1_groups[] = {
329 "mfio59", "mfio60", "mfio1", "mfio2",
330 };
331
332 static const char * const pistachio_spdif_out_groups[] = {
333 "mfio61",
334 };
335
336 static const char * const pistachio_spdif_in_groups[] = {
337 "mfio62", "mfio54",
338 };
339 static const int pistachio_spdif_in_scenarios[] = {
340 PISTACHIO_PIN_MFIO(62),
341 PISTACHIO_PIN_MFIO(54),
342 };
343
344 static const char * const pistachio_eth_groups[] = {
345 "mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68",
346 "mfio69", "mfio70", "mfio71",
347 };
348
349 static const char * const pistachio_ir_groups[] = {
350 "mfio72",
351 };
352
353 static const char * const pistachio_pwmpdm_groups[] = {
354 "mfio73", "mfio74", "mfio75", "mfio76",
355 };
356
357 static const char * const pistachio_mips_trace_clk_groups[] = {
358 "mfio15", "mfio63", "mfio73",
359 };
360
361 static const char * const pistachio_mips_trace_dint_groups[] = {
362 "mfio16", "mfio64", "mfio74",
363 };
364 static const int pistachio_mips_trace_dint_scenarios[] = {
365 PISTACHIO_PIN_MFIO(16),
366 PISTACHIO_PIN_MFIO(64),
367 PISTACHIO_PIN_MFIO(74),
368 };
369
370 static const char * const pistachio_mips_trace_trigout_groups[] = {
371 "mfio17", "mfio65", "mfio75",
372 };
373
374 static const char * const pistachio_mips_trace_trigin_groups[] = {
375 "mfio18", "mfio66", "mfio76",
376 };
377 static const int pistachio_mips_trace_trigin_scenarios[] = {
378 PISTACHIO_PIN_MFIO(18),
379 PISTACHIO_PIN_MFIO(66),
380 PISTACHIO_PIN_MFIO(76),
381 };
382
383 static const char * const pistachio_mips_trace_dm_groups[] = {
384 "mfio19", "mfio67", "mfio77",
385 };
386
387 static const char * const pistachio_mips_probe_n_groups[] = {
388 "mfio20", "mfio68", "mfio78",
389 };
390 static const int pistachio_mips_probe_n_scenarios[] = {
391 PISTACHIO_PIN_MFIO(20),
392 PISTACHIO_PIN_MFIO(68),
393 PISTACHIO_PIN_MFIO(78),
394 };
395
396 static const char * const pistachio_mips_trace_data_groups[] = {
397 "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
398 "mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66",
399 "mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80",
400 "mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86",
401 };
402
403 static const char * const pistachio_sram_debug_groups[] = {
404 "mfio73", "mfio74",
405 };
406
407 static const char * const pistachio_rom_debug_groups[] = {
408 "mfio75", "mfio76",
409 };
410
411 static const char * const pistachio_rpu_debug_groups[] = {
412 "mfio77", "mfio78",
413 };
414
415 static const char * const pistachio_mips_debug_groups[] = {
416 "mfio79", "mfio80",
417 };
418
419 static const char * const pistachio_eth_debug_groups[] = {
420 "mfio81", "mfio82",
421 };
422
423 static const char * const pistachio_usb_debug_groups[] = {
424 "mfio83", "mfio84",
425 };
426
427 static const char * const pistachio_sdhost_debug_groups[] = {
428 "mfio85", "mfio86",
429 };
430
431 static const char * const pistachio_socif_debug_groups[] = {
432 "mfio87", "mfio88",
433 };
434
435 static const char * const pistachio_mdc_debug_groups[] = {
436 "mfio77", "mfio78",
437 };
438
439 static const char * const pistachio_ddr_debug_groups[] = {
440 "mfio79", "mfio80",
441 };
442
443 static const char * const pistachio_dreq0_groups[] = {
444 "mfio81",
445 };
446
447 static const char * const pistachio_dreq1_groups[] = {
448 "mfio82",
449 };
450
451 static const char * const pistachio_dreq2_groups[] = {
452 "mfio87",
453 };
454
455 static const char * const pistachio_dreq3_groups[] = {
456 "mfio88",
457 };
458
459 static const char * const pistachio_dreq4_groups[] = {
460 "mfio89",
461 };
462
463 static const char * const pistachio_dreq5_groups[] = {
464 "mfio89",
465 };
466
467 static const char * const pistachio_mips_pll_lock_groups[] = {
468 "mfio83",
469 };
470
471 static const char * const pistachio_audio_pll_lock_groups[] = {
472 "mfio84",
473 };
474
475 static const char * const pistachio_rpu_v_pll_lock_groups[] = {
476 "mfio85",
477 };
478
479 static const char * const pistachio_rpu_l_pll_lock_groups[] = {
480 "mfio86",
481 };
482
483 static const char * const pistachio_sys_pll_lock_groups[] = {
484 "mfio87",
485 };
486
487 static const char * const pistachio_wifi_pll_lock_groups[] = {
488 "mfio88",
489 };
490
491 static const char * const pistachio_bt_pll_lock_groups[] = {
492 "mfio89",
493 };
494
495 #define FUNCTION(_name) \
496 { \
497 .name = #_name, \
498 .groups = pistachio_##_name##_groups, \
499 .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
500 }
501
502 #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask) \
503 { \
504 .name = #_name, \
505 .groups = pistachio_##_name##_groups, \
506 .ngroups = ARRAY_SIZE(pistachio_##_name##_groups), \
507 .scenarios = pistachio_##_name##_scenarios, \
508 .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\
509 .scenario_reg = _reg, \
510 .scenario_shift = _shift, \
511 .scenario_mask = _mask, \
512 }
513
514 enum pistachio_mux_option {
515 PISTACHIO_FUNCTION_NONE = -1,
516 PISTACHIO_FUNCTION_SPIM0,
517 PISTACHIO_FUNCTION_SPIM1,
518 PISTACHIO_FUNCTION_SPIS,
519 PISTACHIO_FUNCTION_SDHOST,
520 PISTACHIO_FUNCTION_I2C0,
521 PISTACHIO_FUNCTION_I2C1,
522 PISTACHIO_FUNCTION_I2C2,
523 PISTACHIO_FUNCTION_I2C3,
524 PISTACHIO_FUNCTION_AUDIO_CLK_IN,
525 PISTACHIO_FUNCTION_I2S_OUT,
526 PISTACHIO_FUNCTION_I2S_DAC_CLK,
527 PISTACHIO_FUNCTION_AUDIO_SYNC,
528 PISTACHIO_FUNCTION_AUDIO_TRIGGER,
529 PISTACHIO_FUNCTION_I2S_IN,
530 PISTACHIO_FUNCTION_UART0,
531 PISTACHIO_FUNCTION_UART1,
532 PISTACHIO_FUNCTION_SPDIF_OUT,
533 PISTACHIO_FUNCTION_SPDIF_IN,
534 PISTACHIO_FUNCTION_ETH,
535 PISTACHIO_FUNCTION_IR,
536 PISTACHIO_FUNCTION_PWMPDM,
537 PISTACHIO_FUNCTION_MIPS_TRACE_CLK,
538 PISTACHIO_FUNCTION_MIPS_TRACE_DINT,
539 PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT,
540 PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN,
541 PISTACHIO_FUNCTION_MIPS_TRACE_DM,
542 PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N,
543 PISTACHIO_FUNCTION_MIPS_TRACE_DATA,
544 PISTACHIO_FUNCTION_SRAM_DEBUG,
545 PISTACHIO_FUNCTION_ROM_DEBUG,
546 PISTACHIO_FUNCTION_RPU_DEBUG,
547 PISTACHIO_FUNCTION_MIPS_DEBUG,
548 PISTACHIO_FUNCTION_ETH_DEBUG,
549 PISTACHIO_FUNCTION_USB_DEBUG,
550 PISTACHIO_FUNCTION_SDHOST_DEBUG,
551 PISTACHIO_FUNCTION_SOCIF_DEBUG,
552 PISTACHIO_FUNCTION_MDC_DEBUG,
553 PISTACHIO_FUNCTION_DDR_DEBUG,
554 PISTACHIO_FUNCTION_DREQ0,
555 PISTACHIO_FUNCTION_DREQ1,
556 PISTACHIO_FUNCTION_DREQ2,
557 PISTACHIO_FUNCTION_DREQ3,
558 PISTACHIO_FUNCTION_DREQ4,
559 PISTACHIO_FUNCTION_DREQ5,
560 PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
561 PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
562 PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
563 PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
564 PISTACHIO_FUNCTION_SYS_PLL_LOCK,
565 PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
566 PISTACHIO_FUNCTION_BT_PLL_LOCK,
567 PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
568 PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
569 PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
570 PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0,
571 PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1,
572 PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND,
573 PISTACHIO_FUNCTION_DEBUG_S2L_DONE,
574 };
575
576 static const struct pistachio_function pistachio_functions[] = {
577 FUNCTION(spim0),
578 FUNCTION(spim1),
579 FUNCTION(spis),
580 FUNCTION(sdhost),
581 FUNCTION(i2c0),
582 FUNCTION(i2c1),
583 FUNCTION(i2c2),
584 FUNCTION(i2c3),
585 FUNCTION(audio_clk_in),
586 FUNCTION(i2s_out),
587 FUNCTION(i2s_dac_clk),
588 FUNCTION(audio_sync),
589 FUNCTION(audio_trigger),
590 FUNCTION(i2s_in),
591 FUNCTION(uart0),
592 FUNCTION(uart1),
593 FUNCTION(spdif_out),
594 FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1),
595 FUNCTION(eth),
596 FUNCTION(ir),
597 FUNCTION(pwmpdm),
598 FUNCTION(mips_trace_clk),
599 FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3),
600 FUNCTION(mips_trace_trigout),
601 FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3),
602 FUNCTION(mips_trace_dm),
603 FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3),
604 FUNCTION(mips_trace_data),
605 FUNCTION(sram_debug),
606 FUNCTION(rom_debug),
607 FUNCTION(rpu_debug),
608 FUNCTION(mips_debug),
609 FUNCTION(eth_debug),
610 FUNCTION(usb_debug),
611 FUNCTION(sdhost_debug),
612 FUNCTION(socif_debug),
613 FUNCTION(mdc_debug),
614 FUNCTION(ddr_debug),
615 FUNCTION(dreq0),
616 FUNCTION(dreq1),
617 FUNCTION(dreq2),
618 FUNCTION(dreq3),
619 FUNCTION(dreq4),
620 FUNCTION(dreq5),
621 FUNCTION(mips_pll_lock),
622 FUNCTION(audio_pll_lock),
623 FUNCTION(rpu_v_pll_lock),
624 FUNCTION(rpu_l_pll_lock),
625 FUNCTION(sys_pll_lock),
626 FUNCTION(wifi_pll_lock),
627 FUNCTION(bt_pll_lock),
628 FUNCTION(debug_raw_cca_ind),
629 FUNCTION(debug_ed_sec20_cca_ind),
630 FUNCTION(debug_ed_sec40_cca_ind),
631 FUNCTION(debug_agc_done_0),
632 FUNCTION(debug_agc_done_1),
633 FUNCTION(debug_ed_cca_ind),
634 FUNCTION(debug_s2l_done),
635 };
636
637 #define PIN_GROUP(_pin, _name) \
638 { \
639 .name = #_name, \
640 .pin = PISTACHIO_PIN_##_pin, \
641 .mux_option = { \
642 PISTACHIO_FUNCTION_NONE, \
643 PISTACHIO_FUNCTION_NONE, \
644 PISTACHIO_FUNCTION_NONE, \
645 }, \
646 .mux_reg = -1, \
647 .mux_shift = -1, \
648 .mux_mask = -1, \
649 }
650
651 #define MFIO_PIN_GROUP(_pin, _func) \
652 { \
653 .name = "mfio" #_pin, \
654 .pin = PISTACHIO_PIN_MFIO(_pin), \
655 .mux_option = { \
656 PISTACHIO_FUNCTION_##_func, \
657 PISTACHIO_FUNCTION_NONE, \
658 PISTACHIO_FUNCTION_NONE, \
659 }, \
660 .mux_reg = -1, \
661 .mux_shift = -1, \
662 .mux_mask = -1, \
663 }
664
665 #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask) \
666 { \
667 .name = "mfio" #_pin, \
668 .pin = PISTACHIO_PIN_MFIO(_pin), \
669 .mux_option = { \
670 PISTACHIO_FUNCTION_##_f0, \
671 PISTACHIO_FUNCTION_##_f1, \
672 PISTACHIO_FUNCTION_##_f2, \
673 }, \
674 .mux_reg = _reg, \
675 .mux_shift = _shift, \
676 .mux_mask = _mask, \
677 }
678
679 static const struct pistachio_pin_group pistachio_groups[] = {
680 MFIO_PIN_GROUP(0, SPIM1),
681 MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1,
682 PADS_FUNCTION_SELECT0, 0, 0x3),
683 MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1,
684 PADS_FUNCTION_SELECT0, 2, 0x3),
685 MFIO_PIN_GROUP(3, SPIM1),
686 MFIO_PIN_GROUP(4, SPIM1),
687 MFIO_PIN_GROUP(5, SPIM1),
688 MFIO_PIN_GROUP(6, SPIM1),
689 MFIO_PIN_GROUP(7, SPIM1),
690 MFIO_PIN_GROUP(8, SPIM0),
691 MFIO_PIN_GROUP(9, SPIM0),
692 MFIO_PIN_GROUP(10, SPIM0),
693 MFIO_PIN_GROUP(11, SPIS),
694 MFIO_PIN_GROUP(12, SPIS),
695 MFIO_PIN_GROUP(13, SPIS),
696 MFIO_PIN_GROUP(14, SPIS),
697 MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
698 PADS_FUNCTION_SELECT0, 4, 0x3),
699 MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
700 PADS_FUNCTION_SELECT0, 6, 0x3),
701 MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
702 PADS_FUNCTION_SELECT0, 8, 0x3),
703 MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
704 PADS_FUNCTION_SELECT0, 10, 0x3),
705 MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA,
706 PADS_FUNCTION_SELECT0, 12, 0x3),
707 MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
708 PADS_FUNCTION_SELECT0, 14, 0x3),
709 MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA,
710 PADS_FUNCTION_SELECT0, 16, 0x3),
711 MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA,
712 PADS_FUNCTION_SELECT0, 18, 0x3),
713 MFIO_PIN_GROUP(23, SDHOST),
714 MFIO_PIN_GROUP(24, SDHOST),
715 MFIO_PIN_GROUP(25, SDHOST),
716 MFIO_PIN_GROUP(26, SDHOST),
717 MFIO_PIN_GROUP(27, SDHOST),
718 MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE,
719 PADS_FUNCTION_SELECT0, 20, 0x1),
720 MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE,
721 PADS_FUNCTION_SELECT0, 21, 0x1),
722 MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE,
723 PADS_FUNCTION_SELECT0, 22, 0x1),
724 MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE,
725 PADS_FUNCTION_SELECT0, 23, 0x1),
726 MFIO_PIN_GROUP(32, I2C2),
727 MFIO_PIN_GROUP(33, I2C2),
728 MFIO_PIN_GROUP(34, I2C3),
729 MFIO_PIN_GROUP(35, I2C3),
730 MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE,
731 PADS_FUNCTION_SELECT0, 24, 0x1),
732 MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE,
733 PADS_FUNCTION_SELECT0, 25, 0x1),
734 MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE,
735 PADS_FUNCTION_SELECT0, 26, 0x1),
736 MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE,
737 PADS_FUNCTION_SELECT0, 27, 0x1),
738 MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE,
739 PADS_FUNCTION_SELECT0, 28, 0x1),
740 MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE,
741 PADS_FUNCTION_SELECT0, 29, 0x1),
742 MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE,
743 PADS_FUNCTION_SELECT0, 30, 0x1),
744 MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE,
745 PADS_FUNCTION_SELECT0, 31, 0x1),
746 MFIO_PIN_GROUP(44, I2S_OUT),
747 MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE,
748 PADS_FUNCTION_SELECT1, 0, 0x1),
749 MFIO_PIN_GROUP(46, AUDIO_TRIGGER),
750 MFIO_PIN_GROUP(47, I2S_IN),
751 MFIO_PIN_GROUP(48, I2S_IN),
752 MFIO_PIN_GROUP(49, I2S_IN),
753 MFIO_PIN_GROUP(50, I2S_IN),
754 MFIO_PIN_GROUP(51, I2S_IN),
755 MFIO_PIN_GROUP(52, I2S_IN),
756 MFIO_PIN_GROUP(53, I2S_IN),
757 MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN,
758 PADS_FUNCTION_SELECT1, 1, 0x3),
759 MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1,
760 PADS_FUNCTION_SELECT1, 3, 0x3),
761 MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1,
762 PADS_FUNCTION_SELECT1, 5, 0x3),
763 MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1,
764 PADS_FUNCTION_SELECT1, 7, 0x3),
765 MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE,
766 PADS_FUNCTION_SELECT1, 9, 0x1),
767 MFIO_PIN_GROUP(59, UART1),
768 MFIO_PIN_GROUP(60, UART1),
769 MFIO_PIN_GROUP(61, SPDIF_OUT),
770 MFIO_PIN_GROUP(62, SPDIF_IN),
771 MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
772 PADS_FUNCTION_SELECT1, 10, 0x3),
773 MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
774 PADS_FUNCTION_SELECT1, 12, 0x3),
775 MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
776 PADS_FUNCTION_SELECT1, 14, 0x3),
777 MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
778 PADS_FUNCTION_SELECT1, 16, 0x3),
779 MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA,
780 PADS_FUNCTION_SELECT1, 18, 0x3),
781 MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
782 PADS_FUNCTION_SELECT1, 20, 0x3),
783 MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA,
784 PADS_FUNCTION_SELECT1, 22, 0x3),
785 MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA,
786 PADS_FUNCTION_SELECT1, 24, 0x3),
787 MFIO_PIN_GROUP(71, ETH),
788 MFIO_PIN_GROUP(72, IR),
789 MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG,
790 PADS_FUNCTION_SELECT1, 26, 0x3),
791 MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG,
792 PADS_FUNCTION_SELECT1, 28, 0x3),
793 MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG,
794 PADS_FUNCTION_SELECT1, 30, 0x3),
795 MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG,
796 PADS_FUNCTION_SELECT2, 0, 0x3),
797 MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG,
798 PADS_FUNCTION_SELECT2, 2, 0x3),
799 MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG,
800 PADS_FUNCTION_SELECT2, 4, 0x3),
801 MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
802 PADS_FUNCTION_SELECT2, 6, 0x3),
803 MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
804 PADS_FUNCTION_SELECT2, 8, 0x3),
805 MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG,
806 PADS_FUNCTION_SELECT2, 10, 0x3),
807 MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG,
808 PADS_FUNCTION_SELECT2, 12, 0x3),
809 MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
810 PADS_FUNCTION_SELECT2, 14, 0x3),
811 MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
812 PADS_FUNCTION_SELECT2, 16, 0x3),
813 MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
814 PADS_FUNCTION_SELECT2, 18, 0x3),
815 MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
816 PADS_FUNCTION_SELECT2, 20, 0x3),
817 MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG,
818 PADS_FUNCTION_SELECT2, 22, 0x3),
819 MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG,
820 PADS_FUNCTION_SELECT2, 24, 0x3),
821 MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5,
822 PADS_FUNCTION_SELECT2, 26, 0x3),
823 PIN_GROUP(TCK, "tck"),
824 PIN_GROUP(TRSTN, "trstn"),
825 PIN_GROUP(TDI, "tdi"),
826 PIN_GROUP(TMS, "tms"),
827 PIN_GROUP(TDO, "tdo"),
828 PIN_GROUP(JTAG_COMPLY, "jtag_comply"),
829 PIN_GROUP(SAFE_MODE, "safe_mode"),
830 PIN_GROUP(POR_DISABLE, "por_disable"),
831 PIN_GROUP(RESETN, "resetn"),
832 };
833
834 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
835 {
836 return readl(pctl->base + reg);
837 }
838
839 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
840 {
841 writel(val, pctl->base + reg);
842 }
843
844 static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d)
845 {
846 return gpiochip_get_data(irq_data_get_irq_chip_data(d));
847 }
848
849 static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
850 {
851 return readl(bank->base + reg);
852 }
853
854 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
855 u32 reg)
856 {
857 writel(val, bank->base + reg);
858 }
859
860 static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
861 u32 reg, unsigned int bit, u32 val)
862 {
863 /*
864 * For most of the GPIO registers, bit 16 + X must be set in order to
865 * write bit X.
866 */
867 gpio_writel(bank, (0x10000 | val) << bit, reg);
868 }
869
870 static inline void gpio_enable(struct pistachio_gpio_bank *bank,
871 unsigned offset)
872 {
873 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
874 }
875
876 static inline void gpio_disable(struct pistachio_gpio_bank *bank,
877 unsigned offset)
878 {
879 gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
880 }
881
882 static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
883 {
884 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
885
886 return pctl->ngroups;
887 }
888
889 static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
890 unsigned group)
891 {
892 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
893
894 return pctl->groups[group].name;
895 }
896
897 static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
898 unsigned group,
899 const unsigned **pins,
900 unsigned *num_pins)
901 {
902 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
903
904 *pins = &pctl->groups[group].pin;
905 *num_pins = 1;
906
907 return 0;
908 }
909
910 static const struct pinctrl_ops pistachio_pinctrl_ops = {
911 .get_groups_count = pistachio_pinctrl_get_groups_count,
912 .get_group_name = pistachio_pinctrl_get_group_name,
913 .get_group_pins = pistachio_pinctrl_get_group_pins,
914 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
915 .dt_free_map = pinctrl_utils_free_map,
916 };
917
918 static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
919 {
920 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
921
922 return pctl->nfunctions;
923 }
924
925 static const char *
926 pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
927 {
928 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
929
930 return pctl->functions[func].name;
931 }
932
933 static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
934 unsigned func,
935 const char * const **groups,
936 unsigned * const num_groups)
937 {
938 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
939
940 *groups = pctl->functions[func].groups;
941 *num_groups = pctl->functions[func].ngroups;
942
943 return 0;
944 }
945
946 static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
947 unsigned func, unsigned group)
948 {
949 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
950 const struct pistachio_pin_group *pg = &pctl->groups[group];
951 const struct pistachio_function *pf = &pctl->functions[func];
952 struct pinctrl_gpio_range *range;
953 unsigned int i;
954 u32 val;
955
956 if (pg->mux_reg > 0) {
957 for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {
958 if (pg->mux_option[i] == func)
959 break;
960 }
961 if (i == ARRAY_SIZE(pg->mux_option)) {
962 dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
963 group, func);
964 return -EINVAL;
965 }
966
967 val = pctl_readl(pctl, pg->mux_reg);
968 val &= ~(pg->mux_mask << pg->mux_shift);
969 val |= i << pg->mux_shift;
970 pctl_writel(pctl, val, pg->mux_reg);
971
972 if (pf->scenarios) {
973 for (i = 0; i < pf->nscenarios; i++) {
974 if (pf->scenarios[i] == group)
975 break;
976 }
977 if (WARN_ON(i == pf->nscenarios))
978 return -EINVAL;
979
980 val = pctl_readl(pctl, pf->scenario_reg);
981 val &= ~(pf->scenario_mask << pf->scenario_shift);
982 val |= i << pf->scenario_shift;
983 pctl_writel(pctl, val, pf->scenario_reg);
984 }
985 }
986
987 range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
988 if (range)
989 gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);
990
991 return 0;
992 }
993
994 static const struct pinmux_ops pistachio_pinmux_ops = {
995 .get_functions_count = pistachio_pinmux_get_functions_count,
996 .get_function_name = pistachio_pinmux_get_function_name,
997 .get_function_groups = pistachio_pinmux_get_function_groups,
998 .set_mux = pistachio_pinmux_enable,
999 };
1000
1001 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
1002 unsigned long *config)
1003 {
1004 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1005 enum pin_config_param param = pinconf_to_config_param(*config);
1006 u32 val, arg;
1007
1008 switch (param) {
1009 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1010 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1011 arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
1012 break;
1013 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1014 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1015 PADS_PU_PD_SHIFT(pin);
1016 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
1017 break;
1018 case PIN_CONFIG_BIAS_PULL_UP:
1019 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1020 PADS_PU_PD_SHIFT(pin);
1021 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
1022 break;
1023 case PIN_CONFIG_BIAS_PULL_DOWN:
1024 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1025 PADS_PU_PD_SHIFT(pin);
1026 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
1027 break;
1028 case PIN_CONFIG_BIAS_BUS_HOLD:
1029 val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1030 PADS_PU_PD_SHIFT(pin);
1031 arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
1032 break;
1033 case PIN_CONFIG_SLEW_RATE:
1034 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1035 arg = !!(val & PADS_SLEW_RATE_BIT(pin));
1036 break;
1037 case PIN_CONFIG_DRIVE_STRENGTH:
1038 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1039 PADS_DRIVE_STRENGTH_SHIFT(pin);
1040 switch (val & PADS_DRIVE_STRENGTH_MASK) {
1041 case PADS_DRIVE_STRENGTH_2MA:
1042 arg = 2;
1043 break;
1044 case PADS_DRIVE_STRENGTH_4MA:
1045 arg = 4;
1046 break;
1047 case PADS_DRIVE_STRENGTH_8MA:
1048 arg = 8;
1049 break;
1050 case PADS_DRIVE_STRENGTH_12MA:
1051 default:
1052 arg = 12;
1053 break;
1054 }
1055 break;
1056 default:
1057 dev_dbg(pctl->dev, "Property %u not supported\n", param);
1058 return -ENOTSUPP;
1059 }
1060
1061 *config = pinconf_to_config_packed(param, arg);
1062
1063 return 0;
1064 }
1065
1066 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1067 unsigned long *configs, unsigned num_configs)
1068 {
1069 struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1070 enum pin_config_param param;
1071 u32 drv, val, arg;
1072 unsigned int i;
1073
1074 for (i = 0; i < num_configs; i++) {
1075 param = pinconf_to_config_param(configs[i]);
1076 arg = pinconf_to_config_argument(configs[i]);
1077
1078 switch (param) {
1079 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1080 val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1081 if (arg)
1082 val |= PADS_SCHMITT_EN_BIT(pin);
1083 else
1084 val &= ~PADS_SCHMITT_EN_BIT(pin);
1085 pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1086 break;
1087 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1088 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1089 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1090 val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
1091 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1092 break;
1093 case PIN_CONFIG_BIAS_PULL_UP:
1094 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1095 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1096 val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
1097 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1098 break;
1099 case PIN_CONFIG_BIAS_PULL_DOWN:
1100 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1101 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1102 val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
1103 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1104 break;
1105 case PIN_CONFIG_BIAS_BUS_HOLD:
1106 val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1107 val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1108 val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
1109 pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1110 break;
1111 case PIN_CONFIG_SLEW_RATE:
1112 val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1113 if (arg)
1114 val |= PADS_SLEW_RATE_BIT(pin);
1115 else
1116 val &= ~PADS_SLEW_RATE_BIT(pin);
1117 pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1118 break;
1119 case PIN_CONFIG_DRIVE_STRENGTH:
1120 val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1121 val &= ~(PADS_DRIVE_STRENGTH_MASK <<
1122 PADS_DRIVE_STRENGTH_SHIFT(pin));
1123 switch (arg) {
1124 case 2:
1125 drv = PADS_DRIVE_STRENGTH_2MA;
1126 break;
1127 case 4:
1128 drv = PADS_DRIVE_STRENGTH_4MA;
1129 break;
1130 case 8:
1131 drv = PADS_DRIVE_STRENGTH_8MA;
1132 break;
1133 case 12:
1134 drv = PADS_DRIVE_STRENGTH_12MA;
1135 break;
1136 default:
1137 dev_err(pctl->dev,
1138 "Drive strength %umA not supported\n",
1139 arg);
1140 return -EINVAL;
1141 }
1142 val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
1143 pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
1144 break;
1145 default:
1146 dev_err(pctl->dev, "Property %u not supported\n",
1147 param);
1148 return -ENOTSUPP;
1149 }
1150 }
1151
1152 return 0;
1153 }
1154
1155 static const struct pinconf_ops pistachio_pinconf_ops = {
1156 .pin_config_get = pistachio_pinconf_get,
1157 .pin_config_set = pistachio_pinconf_set,
1158 .is_generic = true,
1159 };
1160
1161 static struct pinctrl_desc pistachio_pinctrl_desc = {
1162 .name = "pistachio-pinctrl",
1163 .pctlops = &pistachio_pinctrl_ops,
1164 .pmxops = &pistachio_pinmux_ops,
1165 .confops = &pistachio_pinconf_ops,
1166 };
1167
1168 static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1169 {
1170 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1171
1172 return !(gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset));
1173 }
1174
1175 static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
1176 {
1177 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1178 u32 reg;
1179
1180 if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1181 reg = GPIO_OUTPUT;
1182 else
1183 reg = GPIO_INPUT;
1184
1185 return !!(gpio_readl(bank, reg) & BIT(offset));
1186 }
1187
1188 static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
1189 int value)
1190 {
1191 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1192
1193 gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
1194 }
1195
1196 static int pistachio_gpio_direction_input(struct gpio_chip *chip,
1197 unsigned offset)
1198 {
1199 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1200
1201 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
1202 gpio_enable(bank, offset);
1203
1204 return 0;
1205 }
1206
1207 static int pistachio_gpio_direction_output(struct gpio_chip *chip,
1208 unsigned offset, int value)
1209 {
1210 struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1211
1212 pistachio_gpio_set(chip, offset, value);
1213 gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
1214 gpio_enable(bank, offset);
1215
1216 return 0;
1217 }
1218
1219 static void pistachio_gpio_irq_ack(struct irq_data *data)
1220 {
1221 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1222
1223 gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
1224 }
1225
1226 static void pistachio_gpio_irq_mask(struct irq_data *data)
1227 {
1228 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1229
1230 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
1231 }
1232
1233 static void pistachio_gpio_irq_unmask(struct irq_data *data)
1234 {
1235 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1236
1237 gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
1238 }
1239
1240 static unsigned int pistachio_gpio_irq_startup(struct irq_data *data)
1241 {
1242 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1243
1244 pistachio_gpio_direction_input(chip, data->hwirq);
1245 pistachio_gpio_irq_unmask(data);
1246
1247 return 0;
1248 }
1249
1250 static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1251 {
1252 struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1253
1254 switch (type & IRQ_TYPE_SENSE_MASK) {
1255 case IRQ_TYPE_EDGE_RISING:
1256 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1257 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1258 GPIO_INTERRUPT_TYPE_EDGE);
1259 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1260 GPIO_INTERRUPT_EDGE_SINGLE);
1261 break;
1262 case IRQ_TYPE_EDGE_FALLING:
1263 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1264 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1265 GPIO_INTERRUPT_TYPE_EDGE);
1266 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1267 GPIO_INTERRUPT_EDGE_SINGLE);
1268 break;
1269 case IRQ_TYPE_EDGE_BOTH:
1270 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1271 GPIO_INTERRUPT_TYPE_EDGE);
1272 gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1273 GPIO_INTERRUPT_EDGE_DUAL);
1274 break;
1275 case IRQ_TYPE_LEVEL_HIGH:
1276 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1277 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1278 GPIO_INTERRUPT_TYPE_LEVEL);
1279 break;
1280 case IRQ_TYPE_LEVEL_LOW:
1281 gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1282 gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1283 GPIO_INTERRUPT_TYPE_LEVEL);
1284 break;
1285 default:
1286 return -EINVAL;
1287 }
1288
1289 if (type & IRQ_TYPE_LEVEL_MASK)
1290 irq_set_handler_locked(data, handle_level_irq);
1291 else
1292 irq_set_handler_locked(data, handle_edge_irq);
1293
1294 return 0;
1295 }
1296
1297 static void pistachio_gpio_irq_handler(struct irq_desc *desc)
1298 {
1299 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1300 struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);
1301 struct irq_chip *chip = irq_desc_get_chip(desc);
1302 unsigned long pending;
1303 unsigned int pin;
1304
1305 chained_irq_enter(chip, desc);
1306 pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1307 gpio_readl(bank, GPIO_INTERRUPT_EN);
1308 for_each_set_bit(pin, &pending, 16)
1309 generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin));
1310 chained_irq_exit(chip, desc);
1311 }
1312
1313 #define GPIO_BANK(_bank, _pin_base, _npins) \
1314 { \
1315 .pin_base = _pin_base, \
1316 .npins = _npins, \
1317 .gpio_chip = { \
1318 .label = "GPIO" #_bank, \
1319 .request = gpiochip_generic_request, \
1320 .free = gpiochip_generic_free, \
1321 .get_direction = pistachio_gpio_get_direction, \
1322 .direction_input = pistachio_gpio_direction_input, \
1323 .direction_output = pistachio_gpio_direction_output, \
1324 .get = pistachio_gpio_get, \
1325 .set = pistachio_gpio_set, \
1326 .base = _pin_base, \
1327 .ngpio = _npins, \
1328 }, \
1329 .irq_chip = { \
1330 .name = "GPIO" #_bank, \
1331 .irq_startup = pistachio_gpio_irq_startup, \
1332 .irq_ack = pistachio_gpio_irq_ack, \
1333 .irq_mask = pistachio_gpio_irq_mask, \
1334 .irq_unmask = pistachio_gpio_irq_unmask, \
1335 .irq_set_type = pistachio_gpio_irq_set_type, \
1336 }, \
1337 }
1338
1339 static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
1340 GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16),
1341 GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16),
1342 GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16),
1343 GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16),
1344 GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16),
1345 GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10),
1346 };
1347
1348 static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1349 {
1350 struct device_node *node = pctl->dev->of_node;
1351 struct pistachio_gpio_bank *bank;
1352 unsigned int i;
1353 int irq, ret = 0;
1354
1355 for (i = 0; i < pctl->nbanks; i++) {
1356 char child_name[sizeof("gpioXX")];
1357 struct device_node *child;
1358
1359 snprintf(child_name, sizeof(child_name), "gpio%d", i);
1360 child = of_get_child_by_name(node, child_name);
1361 if (!child) {
1362 dev_err(pctl->dev, "No node for bank %u\n", i);
1363 ret = -ENODEV;
1364 goto err;
1365 }
1366
1367 if (!of_find_property(child, "gpio-controller", NULL)) {
1368 dev_err(pctl->dev,
1369 "No gpio-controller property for bank %u\n", i);
1370 ret = -ENODEV;
1371 goto err;
1372 }
1373
1374 irq = irq_of_parse_and_map(child, 0);
1375 if (irq < 0) {
1376 dev_err(pctl->dev, "No IRQ for bank %u: %d\n", i, irq);
1377 ret = irq;
1378 goto err;
1379 }
1380
1381 bank = &pctl->gpio_banks[i];
1382 bank->pctl = pctl;
1383 bank->base = pctl->base + GPIO_BANK_BASE(i);
1384
1385 bank->gpio_chip.parent = pctl->dev;
1386 bank->gpio_chip.of_node = child;
1387 ret = gpiochip_add_data(&bank->gpio_chip, bank);
1388 if (ret < 0) {
1389 dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1390 i, ret);
1391 goto err;
1392 }
1393
1394 ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1395 0, handle_level_irq, IRQ_TYPE_NONE);
1396 if (ret < 0) {
1397 dev_err(pctl->dev, "Failed to add IRQ chip %u: %d\n",
1398 i, ret);
1399 gpiochip_remove(&bank->gpio_chip);
1400 goto err;
1401 }
1402 gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1403 irq, pistachio_gpio_irq_handler);
1404
1405 ret = gpiochip_add_pin_range(&bank->gpio_chip,
1406 dev_name(pctl->dev), 0,
1407 bank->pin_base, bank->npins);
1408 if (ret < 0) {
1409 dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
1410 i, ret);
1411 gpiochip_remove(&bank->gpio_chip);
1412 goto err;
1413 }
1414 }
1415
1416 return 0;
1417 err:
1418 for (; i > 0; i--) {
1419 bank = &pctl->gpio_banks[i - 1];
1420 gpiochip_remove(&bank->gpio_chip);
1421 }
1422 return ret;
1423 }
1424
1425 static const struct of_device_id pistachio_pinctrl_of_match[] = {
1426 { .compatible = "img,pistachio-system-pinctrl", },
1427 { },
1428 };
1429
1430 static int pistachio_pinctrl_probe(struct platform_device *pdev)
1431 {
1432 struct pistachio_pinctrl *pctl;
1433 struct resource *res;
1434
1435 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1436 if (!pctl)
1437 return -ENOMEM;
1438 pctl->dev = &pdev->dev;
1439 dev_set_drvdata(&pdev->dev, pctl);
1440
1441 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1442 pctl->base = devm_ioremap_resource(&pdev->dev, res);
1443 if (IS_ERR(pctl->base))
1444 return PTR_ERR(pctl->base);
1445
1446 pctl->pins = pistachio_pins;
1447 pctl->npins = ARRAY_SIZE(pistachio_pins);
1448 pctl->functions = pistachio_functions;
1449 pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
1450 pctl->groups = pistachio_groups;
1451 pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1452 pctl->gpio_banks = pistachio_gpio_banks;
1453 pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1454
1455 pistachio_pinctrl_desc.pins = pctl->pins;
1456 pistachio_pinctrl_desc.npins = pctl->npins;
1457
1458 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
1459 pctl);
1460 if (IS_ERR(pctl->pctldev)) {
1461 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1462 return PTR_ERR(pctl->pctldev);
1463 }
1464
1465 return pistachio_gpio_register(pctl);
1466 }
1467
1468 static struct platform_driver pistachio_pinctrl_driver = {
1469 .driver = {
1470 .name = "pistachio-pinctrl",
1471 .of_match_table = pistachio_pinctrl_of_match,
1472 .suppress_bind_attrs = true,
1473 },
1474 .probe = pistachio_pinctrl_probe,
1475 };
1476
1477 static int __init pistachio_pinctrl_register(void)
1478 {
1479 return platform_driver_register(&pistachio_pinctrl_driver);
1480 }
1481 arch_initcall(pistachio_pinctrl_register);
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