drivers/pinctrl/pinctrl-rza1.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
   4  *
   5  * Copyright (C) 2017 Jacopo Mondi
   6  */
   7
   8 /*
   9  * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
  10  * family.
  11  * This includes SoCs which are sub- or super- sets of this particular line,
  12  * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/gpio/driver.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinmux.h>
  27 #include <linux/slab.h>
  28
  29 #include "core.h"
  30 #include "devicetree.h"
  31 #include "pinconf.h"
  32 #include "pinmux.h"
  33
  34 #define DRIVER_NAME                     "pinctrl-rza1"
  35
  36 #define RZA1_P_REG                      0x0000
  37 #define RZA1_PPR_REG                    0x0200
  38 #define RZA1_PM_REG                     0x0300
  39 #define RZA1_PMC_REG                    0x0400
  40 #define RZA1_PFC_REG                    0x0500
  41 #define RZA1_PFCE_REG                   0x0600
  42 #define RZA1_PFCEA_REG                  0x0a00
  43 #define RZA1_PIBC_REG                   0x4000
  44 #define RZA1_PBDC_REG                   0x4100
  45 #define RZA1_PIPC_REG                   0x4200
  46
  47 #define RZA1_ADDR(mem, reg, port)       ((mem) + (reg) + ((port) * 4))
  48
  49 #define RZA1_NPORTS                     12
  50 #define RZA1_PINS_PER_PORT              16
  51 #define RZA1_NPINS                      (RZA1_PINS_PER_PORT * RZA1_NPORTS)
  52 #define RZA1_PIN_ID_TO_PORT(id)         ((id) / RZA1_PINS_PER_PORT)
  53 #define RZA1_PIN_ID_TO_PIN(id)          ((id) % RZA1_PINS_PER_PORT)
  54
  55 /*
  56  * Use 16 lower bits [15:0] for pin identifier
  57  * Use 16 higher bits [31:16] for pin mux function
  58  */
  59 #define MUX_PIN_ID_MASK                 GENMASK(15, 0)
  60 #define MUX_FUNC_MASK                   GENMASK(31, 16)
  61
  62 #define MUX_FUNC_OFFS                   16
  63 #define MUX_FUNC(pinconf)               \
  64         ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
  65 #define MUX_FUNC_PFC_MASK               BIT(0)
  66 #define MUX_FUNC_PFCE_MASK              BIT(1)
  67 #define MUX_FUNC_PFCEA_MASK             BIT(2)
  68
  69 /* Pin mux flags */
  70 #define MUX_FLAGS_BIDIR                 BIT(0)
  71 #define MUX_FLAGS_SWIO_INPUT            BIT(1)
  72 #define MUX_FLAGS_SWIO_OUTPUT           BIT(2)
  73
  74 /* ----------------------------------------------------------------------------
  75  * RZ/A1 pinmux flags
  76  */
  77
  78 /**
  79  * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
  80  */
  81 struct rza1_bidir_pin {
  82         u8 pin: 4;
  83         u8 func: 4;
  84 };
  85
  86 /**
  87  * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
  88  *                    Each struct rza1_bidir_entry describes a port.
  89  */
  90 struct rza1_bidir_entry {
  91         const unsigned int npins;
  92         const struct rza1_bidir_pin *pins;
  93 };
  94
  95 /**
  96  * rza1_swio_pin - describe a single pin that needs bidir flag applied.
  97  */
  98 struct rza1_swio_pin {
  99         u16 pin: 4;
 100         u16 port: 4;
 101         u16 func: 4;
 102         u16 input: 1;
 103 };
 104
 105 /**
 106  * rza1_swio_entry - describe a list of pins that needs swio flag applied
 107  */
 108 struct rza1_swio_entry {
 109         const unsigned int npins;
 110         const struct rza1_swio_pin *pins;
 111 };
 112
 113 /**
 114  * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
 115  */
 116 struct rza1_pinmux_conf {
 117         const struct rza1_bidir_entry *bidir_entries;
 118         const struct rza1_swio_entry *swio_entries;
 119 };
 120
 121 /* ----------------------------------------------------------------------------
 122  * RZ/A1H (r7s72100) pinmux flags
 123  */
 124
 125 static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
 126         { .pin = 0, .func = 1 },
 127         { .pin = 1, .func = 1 },
 128         { .pin = 2, .func = 1 },
 129         { .pin = 3, .func = 1 },
 130         { .pin = 4, .func = 1 },
 131         { .pin = 5, .func = 1 },
 132         { .pin = 6, .func = 1 },
 133         { .pin = 7, .func = 1 },
 134 };
 135
 136 static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
 137         { .pin = 0, .func = 1 },
 138         { .pin = 1, .func = 1 },
 139         { .pin = 2, .func = 1 },
 140         { .pin = 3, .func = 1 },
 141         { .pin = 4, .func = 1 },
 142         { .pin = 0, .func = 4 },
 143         { .pin = 1, .func = 4 },
 144         { .pin = 2, .func = 4 },
 145         { .pin = 3, .func = 4 },
 146         { .pin = 5, .func = 1 },
 147         { .pin = 6, .func = 1 },
 148         { .pin = 7, .func = 1 },
 149         { .pin = 8, .func = 1 },
 150         { .pin = 9, .func = 1 },
 151         { .pin = 10, .func = 1 },
 152         { .pin = 11, .func = 1 },
 153         { .pin = 12, .func = 1 },
 154         { .pin = 13, .func = 1 },
 155         { .pin = 14, .func = 1 },
 156         { .pin = 15, .func = 1 },
 157         { .pin = 12, .func = 4 },
 158         { .pin = 13, .func = 4 },
 159         { .pin = 14, .func = 4 },
 160         { .pin = 15, .func = 4 },
 161 };
 162
 163 static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
 164         { .pin = 3, .func = 2 },
 165         { .pin = 10, .func = 7 },
 166         { .pin = 11, .func = 7 },
 167         { .pin = 13, .func = 7 },
 168         { .pin = 14, .func = 7 },
 169         { .pin = 15, .func = 7 },
 170         { .pin = 10, .func = 8 },
 171         { .pin = 11, .func = 8 },
 172         { .pin = 13, .func = 8 },
 173         { .pin = 14, .func = 8 },
 174         { .pin = 15, .func = 8 },
 175 };
 176
 177 static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
 178         { .pin = 0, .func = 8 },
 179         { .pin = 1, .func = 8 },
 180         { .pin = 2, .func = 8 },
 181         { .pin = 3, .func = 8 },
 182         { .pin = 10, .func = 3 },
 183         { .pin = 11, .func = 3 },
 184         { .pin = 13, .func = 3 },
 185         { .pin = 14, .func = 3 },
 186         { .pin = 15, .func = 3 },
 187         { .pin = 10, .func = 4 },
 188         { .pin = 11, .func = 4 },
 189         { .pin = 13, .func = 4 },
 190         { .pin = 14, .func = 4 },
 191         { .pin = 15, .func = 4 },
 192         { .pin = 12, .func = 5 },
 193         { .pin = 13, .func = 5 },
 194         { .pin = 14, .func = 5 },
 195         { .pin = 15, .func = 5 },
 196 };
 197
 198 static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
 199         { .pin = 0, .func = 1 },
 200         { .pin = 1, .func = 1 },
 201         { .pin = 2, .func = 1 },
 202         { .pin = 3, .func = 1 },
 203         { .pin = 4, .func = 1 },
 204         { .pin = 5, .func = 1 },
 205         { .pin = 6, .func = 1 },
 206         { .pin = 7, .func = 1 },
 207         { .pin = 8, .func = 1 },
 208         { .pin = 9, .func = 1 },
 209         { .pin = 10, .func = 1 },
 210         { .pin = 11, .func = 1 },
 211         { .pin = 12, .func = 1 },
 212         { .pin = 13, .func = 1 },
 213         { .pin = 14, .func = 1 },
 214         { .pin = 15, .func = 1 },
 215 };
 216
 217 static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
 218         { .pin = 13, .func = 3 },
 219 };
 220
 221 static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
 222         { .pin = 8, .func = 3 },
 223         { .pin = 9, .func = 3 },
 224         { .pin = 10, .func = 3 },
 225         { .pin = 11, .func = 3 },
 226         { .pin = 14, .func = 2 },
 227         { .pin = 15, .func = 2 },
 228         { .pin = 14, .func = 3 },
 229         { .pin = 15, .func = 3 },
 230 };
 231
 232 static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
 233         { .pin = 0, .func = 2 },
 234         { .pin = 1, .func = 2 },
 235         { .pin = 4, .func = 2 },
 236         { .pin = 5, .func = 2 },
 237         { .pin = 6, .func = 2 },
 238         { .pin = 7, .func = 2 },
 239 };
 240
 241 static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
 242         { .pin = 6, .func = 2 },
 243         { .pin = 7, .func = 2 },
 244         { .pin = 9, .func = 2 },
 245         { .pin = 6, .func = 4 },
 246         { .pin = 7, .func = 4 },
 247         { .pin = 9, .func = 4 },
 248         { .pin = 10, .func = 2 },
 249         { .pin = 11, .func = 2 },
 250         { .pin = 10, .func = 4 },
 251         { .pin = 11, .func = 4 },
 252         { .pin = 12, .func = 4 },
 253         { .pin = 13, .func = 4 },
 254         { .pin = 14, .func = 4 },
 255         { .pin = 15, .func = 4 },
 256 };
 257
 258 static const struct rza1_swio_pin rza1h_swio_pins[] = {
 259         { .port = 2, .pin = 7, .func = 4, .input = 0 },
 260         { .port = 2, .pin = 11, .func = 4, .input = 0 },
 261         { .port = 3, .pin = 7, .func = 3, .input = 0 },
 262         { .port = 3, .pin = 7, .func = 8, .input = 0 },
 263         { .port = 4, .pin = 7, .func = 5, .input = 0 },
 264         { .port = 4, .pin = 7, .func = 11, .input = 0 },
 265         { .port = 4, .pin = 15, .func = 6, .input = 0 },
 266         { .port = 5, .pin = 0, .func = 1, .input = 1 },
 267         { .port = 5, .pin = 1, .func = 1, .input = 1 },
 268         { .port = 5, .pin = 2, .func = 1, .input = 1 },
 269         { .port = 5, .pin = 3, .func = 1, .input = 1 },
 270         { .port = 5, .pin = 4, .func = 1, .input = 1 },
 271         { .port = 5, .pin = 5, .func = 1, .input = 1 },
 272         { .port = 5, .pin = 6, .func = 1, .input = 1 },
 273         { .port = 5, .pin = 7, .func = 1, .input = 1 },
 274         { .port = 7, .pin = 4, .func = 6, .input = 0 },
 275         { .port = 7, .pin = 11, .func = 2, .input = 0 },
 276         { .port = 8, .pin = 10, .func = 8, .input = 0 },
 277         { .port = 10, .pin = 15, .func = 2, .input = 0 },
 278 };
 279
 280 static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
 281         [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
 282         [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
 283         [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
 284         [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
 285         [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
 286         [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
 287         [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
 288         [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
 289         [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
 290 };
 291
 292 static const struct rza1_swio_entry rza1h_swio_entries[] = {
 293         [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
 294 };
 295
 296 /* RZ/A1H (r7s72100x) pinmux flags table */
 297 static const struct rza1_pinmux_conf rza1h_pmx_conf = {
 298         .bidir_entries  = rza1h_bidir_entries,
 299         .swio_entries   = rza1h_swio_entries,
 300 };
 301
 302 /* ----------------------------------------------------------------------------
 303  * RZ/A1L (r7s72102) pinmux flags
 304  */
 305
 306 static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
 307         { .pin = 0, .func = 1 },
 308         { .pin = 1, .func = 1 },
 309         { .pin = 2, .func = 1 },
 310         { .pin = 3, .func = 1 },
 311         { .pin = 4, .func = 1 },
 312         { .pin = 5, .func = 1 },
 313         { .pin = 6, .func = 1 },
 314         { .pin = 7, .func = 1 },
 315 };
 316
 317 static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
 318         { .pin = 0, .func = 2 },
 319         { .pin = 1, .func = 2 },
 320         { .pin = 2, .func = 2 },
 321         { .pin = 4, .func = 2 },
 322         { .pin = 5, .func = 2 },
 323         { .pin = 10, .func = 2 },
 324         { .pin = 11, .func = 2 },
 325         { .pin = 12, .func = 2 },
 326         { .pin = 13, .func = 2 },
 327 };
 328
 329 static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
 330         { .pin = 1, .func = 4 },
 331         { .pin = 2, .func = 2 },
 332         { .pin = 3, .func = 2 },
 333         { .pin = 6, .func = 2 },
 334         { .pin = 7, .func = 2 },
 335 };
 336
 337 static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
 338         { .pin = 0, .func = 1 },
 339         { .pin = 1, .func = 1 },
 340         { .pin = 2, .func = 1 },
 341         { .pin = 3, .func = 1 },
 342         { .pin = 4, .func = 1 },
 343         { .pin = 5, .func = 1 },
 344         { .pin = 6, .func = 1 },
 345         { .pin = 7, .func = 1 },
 346         { .pin = 8, .func = 1 },
 347         { .pin = 9, .func = 1 },
 348         { .pin = 10, .func = 1 },
 349         { .pin = 11, .func = 1 },
 350         { .pin = 12, .func = 1 },
 351         { .pin = 13, .func = 1 },
 352         { .pin = 14, .func = 1 },
 353         { .pin = 15, .func = 1 },
 354         { .pin = 0, .func = 2 },
 355         { .pin = 1, .func = 2 },
 356         { .pin = 2, .func = 2 },
 357         { .pin = 3, .func = 2 },
 358 };
 359
 360 static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
 361         { .pin = 0, .func = 1 },
 362         { .pin = 1, .func = 1 },
 363         { .pin = 2, .func = 1 },
 364         { .pin = 3, .func = 1 },
 365         { .pin = 4, .func = 1 },
 366         { .pin = 5, .func = 1 },
 367         { .pin = 6, .func = 1 },
 368         { .pin = 7, .func = 1 },
 369         { .pin = 8, .func = 1 },
 370         { .pin = 9, .func = 1 },
 371         { .pin = 10, .func = 1 },
 372         { .pin = 11, .func = 1 },
 373         { .pin = 12, .func = 1 },
 374         { .pin = 13, .func = 1 },
 375         { .pin = 14, .func = 1 },
 376         { .pin = 15, .func = 1 },
 377 };
 378
 379 static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
 380         { .pin = 2, .func = 2 },
 381         { .pin = 3, .func = 2 },
 382         { .pin = 5, .func = 2 },
 383         { .pin = 6, .func = 2 },
 384         { .pin = 7, .func = 2 },
 385         { .pin = 2, .func = 3 },
 386         { .pin = 3, .func = 3 },
 387         { .pin = 5, .func = 3 },
 388         { .pin = 6, .func = 3 },
 389         { .pin = 7, .func = 3 },
 390 };
 391
 392 static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
 393         { .pin = 1, .func = 2 },
 394         { .pin = 0, .func = 3 },
 395         { .pin = 1, .func = 3 },
 396         { .pin = 3, .func = 3 },
 397         { .pin = 4, .func = 3 },
 398         { .pin = 5, .func = 3 },
 399 };
 400
 401 static const struct rza1_swio_pin rza1l_swio_pins[] = {
 402         { .port = 2, .pin = 8, .func = 2, .input = 0 },
 403         { .port = 5, .pin = 6, .func = 3, .input = 0 },
 404         { .port = 6, .pin = 6, .func = 3, .input = 0 },
 405         { .port = 6, .pin = 10, .func = 3, .input = 0 },
 406         { .port = 7, .pin = 10, .func = 2, .input = 0 },
 407         { .port = 8, .pin = 2, .func = 3, .input = 0 },
 408 };
 409
 410 static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
 411         [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
 412         [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
 413         [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
 414         [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
 415         [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
 416         [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
 417         [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
 418 };
 419
 420 static const struct rza1_swio_entry rza1l_swio_entries[] = {
 421         [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
 422 };
 423
 424 /* RZ/A1L (r7s72102x) pinmux flags table */
 425 static const struct rza1_pinmux_conf rza1l_pmx_conf = {
 426         .bidir_entries  = rza1l_bidir_entries,
 427         .swio_entries   = rza1l_swio_entries,
 428 };
 429
 430 /* ----------------------------------------------------------------------------
 431  * RZ/A1 types
 432  */
 433 /**
 434  * rza1_mux_conf - describes a pin multiplexing operation
 435  *
 436  * @id: the pin identifier from 0 to RZA1_NPINS
 437  * @port: the port where pin sits on
 438  * @pin: pin id
 439  * @mux_func: alternate function id number
 440  * @mux_flags: alternate function flags
 441  * @value: output value to set the pin to
 442  */
 443 struct rza1_mux_conf {
 444         u16 id;
 445         u8 port;
 446         u8 pin;
 447         u8 mux_func;
 448         u8 mux_flags;
 449         u8 value;
 450 };
 451
 452 /**
 453  * rza1_port - describes a pin port
 454  *
 455  * This is mostly useful to lock register writes per-bank and not globally.
 456  *
 457  * @lock: protect access to HW registers
 458  * @id: port number
 459  * @base: logical address base
 460  * @pins: pins sitting on this port
 461  */
 462 struct rza1_port {
 463         spinlock_t lock;
 464         unsigned int id;
 465         void __iomem *base;
 466         struct pinctrl_pin_desc *pins;
 467 };
 468
 469 /**
 470  * rza1_pinctrl - RZ pincontroller device
 471  *
 472  * @dev: parent device structure
 473  * @mutex: protect [pinctrl|pinmux]_generic functions
 474  * @base: logical address base
 475  * @nports: number of pin controller ports
 476  * @ports: pin controller banks
 477  * @pins: pin array for pinctrl core
 478  * @desc: pincontroller desc for pinctrl core
 479  * @pctl: pinctrl device
 480  * @data: device specific data
 481  */
 482 struct rza1_pinctrl {
 483         struct device *dev;
 484
 485         struct mutex mutex;
 486
 487         void __iomem *base;
 488
 489         unsigned int nport;
 490         struct rza1_port *ports;
 491
 492         struct pinctrl_pin_desc *pins;
 493         struct pinctrl_desc desc;
 494         struct pinctrl_dev *pctl;
 495
 496         const void *data;
 497 };
 498
 499 /* ----------------------------------------------------------------------------
 500  * RZ/A1 pinmux flags
 501  */
 502 static inline bool rza1_pinmux_get_bidir(unsigned int port,
 503                                          unsigned int pin,
 504                                          unsigned int func,
 505                                          const struct rza1_bidir_entry *table)
 506 {
 507         const struct rza1_bidir_entry *entry = &table[port];
 508         const struct rza1_bidir_pin *bidir_pin;
 509         unsigned int i;
 510
 511         for (i = 0; i < entry->npins; ++i) {
 512                 bidir_pin = &entry->pins[i];
 513                 if (bidir_pin->pin == pin && bidir_pin->func == func)
 514                         return true;
 515         }
 516
 517         return false;
 518 }
 519
 520 static inline int rza1_pinmux_get_swio(unsigned int port,
 521                                        unsigned int pin,
 522                                        unsigned int func,
 523                                        const struct rza1_swio_entry *table)
 524 {
 525         const struct rza1_swio_pin *swio_pin;
 526         unsigned int i;
 527
 528
 529         for (i = 0; i < table->npins; ++i) {
 530                 swio_pin = &table->pins[i];
 531                 if (swio_pin->port == port && swio_pin->pin == pin &&
 532                     swio_pin->func == func)
 533                         return swio_pin->input;
 534         }
 535
 536         return -ENOENT;
 537 }
 538
 539 /**
 540  * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
 541  */
 542 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
 543                                           unsigned int func,
 544                                           struct rza1_pinctrl *rza1_pctl)
 545
 546 {
 547         const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
 548         const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
 549         const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
 550         unsigned int pmx_flags = 0;
 551         int ret;
 552
 553         if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
 554                 pmx_flags |= MUX_FLAGS_BIDIR;
 555
 556         ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
 557         if (ret == 0)
 558                 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
 559         else if (ret > 0)
 560                 pmx_flags |= MUX_FLAGS_SWIO_INPUT;
 561
 562         return pmx_flags;
 563 }
 564
 565 /* ----------------------------------------------------------------------------
 566  * RZ/A1 SoC operations
 567  */
 568
 569 /**
 570  * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
 571  *                  registers
 572  */
 573 static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
 574                                 unsigned int bit, bool set)
 575 {
 576         void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
 577         u16 val = ioread16(mem);
 578
 579         if (set)
 580                 val |= BIT(bit);
 581         else
 582                 val &= ~BIT(bit);
 583
 584         iowrite16(val, mem);
 585 }
 586
 587 static inline unsigned int rza1_get_bit(struct rza1_port *port,
 588                                         unsigned int reg, unsigned int bit)
 589 {
 590         void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
 591
 592         return ioread16(mem) & BIT(bit);
 593 }
 594
 595 /**
 596  * rza1_pin_reset() - reset a pin to default initial state
 597  *
 598  * Reset pin state disabling input buffer and bi-directional control,
 599  * and configure it as input port.
 600  * Note that pin is now configured with direction as input but with input
 601  * buffer disabled. This implies the pin value cannot be read in this state.
 602  *
 603  * @port: port where pin sits on
 604  * @pin: pin offset
 605  */
 606 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
 607 {
 608         unsigned long irqflags;
 609
 610         spin_lock_irqsave(&port->lock, irqflags);
 611         rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
 612         rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
 613
 614         rza1_set_bit(port, RZA1_PM_REG, pin, 1);
 615         rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
 616         rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
 617         spin_unlock_irqrestore(&port->lock, irqflags);
 618 }
 619
 620 static inline int rza1_pin_get_direction(struct rza1_port *port,
 621                                          unsigned int pin)
 622 {
 623         return !!rza1_get_bit(port, RZA1_PM_REG, pin);
 624 }
 625
 626 /**
 627  * rza1_pin_set_direction() - set I/O direction on a pin in port mode
 628  *
 629  * When running in output port mode keep PBDC enabled to allow reading the
 630  * pin value from PPR.
 631  *
 632  * @port: port where pin sits on
 633  * @pin: pin offset
 634  * @input: input enable/disable flag
 635  */
 636 static inline void rza1_pin_set_direction(struct rza1_port *port,
 637                                           unsigned int pin, bool input)
 638 {
 639         unsigned long irqflags;
 640
 641         spin_lock_irqsave(&port->lock, irqflags);
 642
 643         rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
 644         if (input) {
 645                 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
 646                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
 647         } else {
 648                 rza1_set_bit(port, RZA1_PM_REG, pin, 0);
 649                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
 650         }
 651
 652         spin_unlock_irqrestore(&port->lock, irqflags);
 653 }
 654
 655 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
 656                                 unsigned int value)
 657 {
 658         unsigned long irqflags;
 659
 660         spin_lock_irqsave(&port->lock, irqflags);
 661         rza1_set_bit(port, RZA1_P_REG, pin, !!value);
 662         spin_unlock_irqrestore(&port->lock, irqflags);
 663 }
 664
 665 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
 666 {
 667         return rza1_get_bit(port, RZA1_PPR_REG, pin);
 668 }
 669
 670 /**
 671  * rza1_pin_mux_single() - configure pin multiplexing on a single pin
 672  *
 673  * @pinctrl: RZ/A1 pin controller device
 674  * @mux_conf: pin multiplexing descriptor
 675  */
 676 static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
 677                                struct rza1_mux_conf *mux_conf)
 678 {
 679         struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
 680         unsigned int pin = mux_conf->pin;
 681         u8 mux_func = mux_conf->mux_func;
 682         u8 mux_flags = mux_conf->mux_flags;
 683         u8 mux_flags_from_table;
 684
 685         rza1_pin_reset(port, pin);
 686
 687         /* SWIO pinmux flags coming from DT are high precedence */
 688         mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
 689                                                      rza1_pctl);
 690         if (mux_flags)
 691                 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
 692         else
 693                 mux_flags = mux_flags_from_table;
 694
 695         if (mux_flags & MUX_FLAGS_BIDIR)
 696                 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
 697
 698         /*
 699          * Enable alternate function mode and select it.
 700          *
 701          * Be careful here: the pin mux sub-nodes in device tree
 702          * enumerate alternate functions from 1 to 8;
 703          * subtract 1 before using macros to match registers configuration
 704          * which expects numbers from 0 to 7 instead.
 705          *
 706          * ----------------------------------------------------
 707          * Alternate mode selection table:
 708          *
 709          * PMC  PFC     PFCE    PFCAE   (mux_func - 1)
 710          * 1    0       0       0       0
 711          * 1    1       0       0       1
 712          * 1    0       1       0       2
 713          * 1    1       1       0       3
 714          * 1    0       0       1       4
 715          * 1    1       0       1       5
 716          * 1    0       1       1       6
 717          * 1    1       1       1       7
 718          * ----------------------------------------------------
 719          */
 720         mux_func -= 1;
 721         rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
 722         rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
 723         rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
 724
 725         /*
 726          * All alternate functions except a few need PIPCn = 1.
 727          * If PIPCn has to stay disabled (SW IO mode), configure PMn according
 728          * to I/O direction specified by pin configuration -after- PMC has been
 729          * set to one.
 730          */
 731         if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
 732                 rza1_set_bit(port, RZA1_PM_REG, pin,
 733                              mux_flags & MUX_FLAGS_SWIO_INPUT);
 734         else
 735                 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
 736
 737         rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
 738
 739         return 0;
 740 }
 741
 742 /* ----------------------------------------------------------------------------
 743  * gpio operations
 744  */
 745
 746 /**
 747  * rza1_gpio_request() - configure pin in port mode
 748  *
 749  * Configure a pin as gpio (port mode).
 750  * After reset, the pin is in input mode with input buffer disabled.
 751  * To use the pin as input or output, set_direction shall be called first
 752  *
 753  * @chip: gpio chip where the gpio sits on
 754  * @gpio: gpio offset
 755  */
 756 static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
 757 {
 758         struct rza1_port *port = gpiochip_get_data(chip);
 759
 760         rza1_pin_reset(port, gpio);
 761
 762         return 0;
 763 }
 764
 765 /**
 766  * rza1_gpio_disable_free() - reset a pin
 767  *
 768  * Surprisingly, disable_free a gpio, is equivalent to request it.
 769  * Reset pin to port mode, with input buffer disabled. This overwrites all
 770  * port direction settings applied with set_direction
 771  *
 772  * @chip: gpio chip where the gpio sits on
 773  * @gpio: gpio offset
 774  */
 775 static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
 776 {
 777         struct rza1_port *port = gpiochip_get_data(chip);
 778
 779         rza1_pin_reset(port, gpio);
 780 }
 781
 782 static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 783 {
 784         struct rza1_port *port = gpiochip_get_data(chip);
 785
 786         return rza1_pin_get_direction(port, gpio);
 787 }
 788
 789 static int rza1_gpio_direction_input(struct gpio_chip *chip,
 790                                      unsigned int gpio)
 791 {
 792         struct rza1_port *port = gpiochip_get_data(chip);
 793
 794         rza1_pin_set_direction(port, gpio, true);
 795
 796         return 0;
 797 }
 798
 799 static int rza1_gpio_direction_output(struct gpio_chip *chip,
 800                                       unsigned int gpio,
 801                                       int value)
 802 {
 803         struct rza1_port *port = gpiochip_get_data(chip);
 804
 805         /* Set value before driving pin direction */
 806         rza1_pin_set(port, gpio, value);
 807         rza1_pin_set_direction(port, gpio, false);
 808
 809         return 0;
 810 }
 811
 812 /**
 813  * rza1_gpio_get() - read a gpio pin value
 814  *
 815  * Read gpio pin value through PPR register.
 816  * Requires bi-directional mode to work when reading the value of a pin
 817  * in output mode
 818  *
 819  * @chip: gpio chip where the gpio sits on
 820  * @gpio: gpio offset
 821  */
 822 static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 823 {
 824         struct rza1_port *port = gpiochip_get_data(chip);
 825
 826         return rza1_pin_get(port, gpio);
 827 }
 828
 829 static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
 830                           int value)
 831 {
 832         struct rza1_port *port = gpiochip_get_data(chip);
 833
 834         rza1_pin_set(port, gpio, value);
 835 }
 836
 837 static const struct gpio_chip rza1_gpiochip_template = {
 838         .request                = rza1_gpio_request,
 839         .free                   = rza1_gpio_free,
 840         .get_direction          = rza1_gpio_get_direction,
 841         .direction_input        = rza1_gpio_direction_input,
 842         .direction_output       = rza1_gpio_direction_output,
 843         .get                    = rza1_gpio_get,
 844         .set                    = rza1_gpio_set,
 845 };
 846 /* ----------------------------------------------------------------------------
 847  * pinctrl operations
 848  */
 849
 850 /**
 851  * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
 852  *                            children sub-nodes
 853  *
 854  * @np: device tree node to parse
 855  */
 856 static int rza1_dt_node_pin_count(struct device_node *np)
 857 {
 858         struct device_node *child;
 859         struct property *of_pins;
 860         unsigned int npins;
 861
 862         of_pins = of_find_property(np, "pinmux", NULL);
 863         if (of_pins)
 864                 return of_pins->length / sizeof(u32);
 865
 866         npins = 0;
 867         for_each_child_of_node(np, child) {
 868                 of_pins = of_find_property(child, "pinmux", NULL);
 869                 if (!of_pins)
 870                         return -EINVAL;
 871
 872                 npins += of_pins->length / sizeof(u32);
 873         }
 874
 875         return npins;
 876 }
 877
 878 /**
 879  * rza1_parse_pmx_function() - parse a pin mux sub-node
 880  *
 881  * @rza1_pctl: RZ/A1 pin controller device
 882  * @np: of pmx sub-node
 883  * @mux_confs: array of pin mux configurations to fill with parsed info
 884  * @grpins: array of pin ids to mux
 885  */
 886 static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
 887                                   struct device_node *np,
 888                                   struct rza1_mux_conf *mux_confs,
 889                                   unsigned int *grpins)
 890 {
 891         struct pinctrl_dev *pctldev = rza1_pctl->pctl;
 892         char const *prop_name = "pinmux";
 893         unsigned long *pin_configs;
 894         unsigned int npin_configs;
 895         struct property *of_pins;
 896         unsigned int npins;
 897         u8 pinmux_flags;
 898         unsigned int i;
 899         int ret;
 900
 901         of_pins = of_find_property(np, prop_name, NULL);
 902         if (!of_pins) {
 903                 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
 904                 return -ENOENT;
 905         }
 906         npins = of_pins->length / sizeof(u32);
 907
 908         /*
 909          * Collect pin configuration properties: they apply to all pins in
 910          * this sub-node
 911          */
 912         ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
 913                                               &npin_configs);
 914         if (ret) {
 915                 dev_err(rza1_pctl->dev,
 916                         "Unable to parse pin configuration options for %pOFn\n",
 917                         np);
 918                 return ret;
 919         }
 920
 921         /*
 922          * Create a mask with pinmux flags from pin configuration;
 923          * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
 924          * specified in device tree.
 925          */
 926         pinmux_flags = 0;
 927         for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
 928                 switch (pinconf_to_config_param(pin_configs[i])) {
 929                 case PIN_CONFIG_INPUT_ENABLE:
 930                         pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
 931                         break;
 932                 case PIN_CONFIG_OUTPUT:
 933                         pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
 934                 default:
 935                         break;
 936
 937                 }
 938
 939         kfree(pin_configs);
 940
 941         /* Collect pin positions and their mux settings. */
 942         for (i = 0; i < npins; ++i) {
 943                 u32 of_pinconf;
 944                 struct rza1_mux_conf *mux_conf = &mux_confs[i];
 945
 946                 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
 947                 if (ret)
 948                         return ret;
 949
 950                 mux_conf->id            = of_pinconf & MUX_PIN_ID_MASK;
 951                 mux_conf->port          = RZA1_PIN_ID_TO_PORT(mux_conf->id);
 952                 mux_conf->pin           = RZA1_PIN_ID_TO_PIN(mux_conf->id);
 953                 mux_conf->mux_func      = MUX_FUNC(of_pinconf);
 954                 mux_conf->mux_flags     = pinmux_flags;
 955
 956                 if (mux_conf->port >= RZA1_NPORTS ||
 957                     mux_conf->pin >= RZA1_PINS_PER_PORT) {
 958                         dev_err(rza1_pctl->dev,
 959                                 "Wrong port %u pin %u for %s property\n",
 960                                 mux_conf->port, mux_conf->pin, prop_name);
 961                         return -EINVAL;
 962                 }
 963
 964                 grpins[i] = mux_conf->id;
 965         }
 966
 967         return npins;
 968 }
 969
 970 /**
 971  * rza1_dt_node_to_map() - map a pin mux node to a function/group
 972  *
 973  * Parse and register a pin mux function.
 974  *
 975  * @pctldev: pin controller device
 976  * @np: device tree node to parse
 977  * @map: pointer to pin map (output)
 978  * @num_maps: number of collected maps (output)
 979  */
 980 static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
 981                                struct device_node *np,
 982                                struct pinctrl_map **map,
 983                                unsigned int *num_maps)
 984 {
 985         struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
 986         struct rza1_mux_conf *mux_confs, *mux_conf;
 987         unsigned int *grpins, *grpin;
 988         struct device_node *child;
 989         const char *grpname;
 990         const char **fngrps;
 991         int ret, npins;
 992         int gsel, fsel;
 993
 994         npins = rza1_dt_node_pin_count(np);
 995         if (npins < 0) {
 996                 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
 997                 return -EINVAL;
 998         }
 999
1000         /*
1001          * Functions are made of 1 group only;
1002          * in fact, functions and groups are identical for this pin controller
1003          * except that functions carry an array of per-pin mux configuration
1004          * settings.
1005          */
1006         mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
1007                                  GFP_KERNEL);
1008         grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
1009                               GFP_KERNEL);
1010         fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
1011
1012         if (!mux_confs || !grpins || !fngrps)
1013                 return -ENOMEM;
1014
1015         /*
1016          * Parse the pinmux node.
1017          * If the node does not contain "pinmux" property (-ENOENT)
1018          * that property shall be specified in all its children sub-nodes.
1019          */
1020         mux_conf = &mux_confs[0];
1021         grpin = &grpins[0];
1022
1023         ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1024         if (ret == -ENOENT)
1025                 for_each_child_of_node(np, child) {
1026                         ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1027                                                      grpin);
1028                         if (ret < 0)
1029                                 return ret;
1030
1031                         grpin += ret;
1032                         mux_conf += ret;
1033                 }
1034         else if (ret < 0)
1035                 return ret;
1036
1037         /* Register pin group and function name to pinctrl_generic */
1038         grpname = np->name;
1039         fngrps[0] = grpname;
1040
1041         mutex_lock(&rza1_pctl->mutex);
1042         gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
1043                                          NULL);
1044         if (gsel < 0) {
1045                 mutex_unlock(&rza1_pctl->mutex);
1046                 return gsel;
1047         }
1048
1049         fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
1050                                            mux_confs);
1051         if (fsel < 0) {
1052                 ret = fsel;
1053                 goto remove_group;
1054         }
1055
1056         dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
1057                                  grpname, npins);
1058
1059         /* Create map where to retrieve function and mux settings from */
1060         *num_maps = 0;
1061         *map = kzalloc(sizeof(**map), GFP_KERNEL);
1062         if (!*map) {
1063                 ret = -ENOMEM;
1064                 goto remove_function;
1065         }
1066
1067         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1068         (*map)->data.mux.group = np->name;
1069         (*map)->data.mux.function = np->name;
1070         *num_maps = 1;
1071         mutex_unlock(&rza1_pctl->mutex);
1072
1073         return 0;
1074
1075 remove_function:
1076         pinmux_generic_remove_function(pctldev, fsel);
1077
1078 remove_group:
1079         pinctrl_generic_remove_group(pctldev, gsel);
1080         mutex_unlock(&rza1_pctl->mutex);
1081
1082         dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
1083                                  grpname);
1084
1085         return ret;
1086 }
1087
1088 static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
1089                              struct pinctrl_map *map, unsigned int num_maps)
1090 {
1091         kfree(map);
1092 }
1093
1094 static const struct pinctrl_ops rza1_pinctrl_ops = {
1095         .get_groups_count       = pinctrl_generic_get_group_count,
1096         .get_group_name         = pinctrl_generic_get_group_name,
1097         .get_group_pins         = pinctrl_generic_get_group_pins,
1098         .dt_node_to_map         = rza1_dt_node_to_map,
1099         .dt_free_map            = rza1_dt_free_map,
1100 };
1101
1102 /* ----------------------------------------------------------------------------
1103  * pinmux operations
1104  */
1105
1106 /**
1107  * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1108  *
1109  * @pctldev: pin controller device
1110  * @selector: function selector
1111  * @group: group selector
1112  */
1113 static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1114                            unsigned int group)
1115 {
1116         struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1117         struct rza1_mux_conf *mux_confs;
1118         struct function_desc *func;
1119         struct group_desc *grp;
1120         int i;
1121
1122         grp = pinctrl_generic_get_group(pctldev, group);
1123         if (!grp)
1124                 return -EINVAL;
1125
1126         func = pinmux_generic_get_function(pctldev, selector);
1127         if (!func)
1128                 return -EINVAL;
1129
1130         mux_confs = (struct rza1_mux_conf *)func->data;
1131         for (i = 0; i < grp->num_pins; ++i) {
1132                 int ret;
1133
1134                 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1135                 if (ret)
1136                         return ret;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static const struct pinmux_ops rza1_pinmux_ops = {
1143         .get_functions_count    = pinmux_generic_get_function_count,
1144         .get_function_name      = pinmux_generic_get_function_name,
1145         .get_function_groups    = pinmux_generic_get_function_groups,
1146         .set_mux                = rza1_set_mux,
1147         .strict                 = true,
1148 };
1149
1150 /* ----------------------------------------------------------------------------
1151  * RZ/A1 pin controller driver operations
1152  */
1153
1154 static unsigned int rza1_count_gpio_chips(struct device_node *np)
1155 {
1156         struct device_node *child;
1157         unsigned int count = 0;
1158
1159         for_each_child_of_node(np, child) {
1160                 if (!of_property_read_bool(child, "gpio-controller"))
1161                         continue;
1162
1163                 count++;
1164         }
1165
1166         return count;
1167 }
1168
1169 /**
1170  * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1171  *
1172  * The gpio controller subnode shall provide a "gpio-ranges" list property as
1173  * defined by gpio device tree binding documentation.
1174  *
1175  * @rza1_pctl: RZ/A1 pin controller device
1176  * @np: of gpio-controller node
1177  * @chip: gpio chip to register to gpiolib
1178  * @range: pin range to register to pinctrl core
1179  */
1180 static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1181                                struct device_node *np,
1182                                struct gpio_chip *chip,
1183                                struct pinctrl_gpio_range *range)
1184 {
1185         const char *list_name = "gpio-ranges";
1186         struct of_phandle_args of_args;
1187         unsigned int gpioport;
1188         u32 pinctrl_base;
1189         int ret;
1190
1191         ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
1192         if (ret) {
1193                 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1194                         list_name);
1195                 return ret;
1196         }
1197
1198         /*
1199          * Find out on which port this gpio-chip maps to by inspecting the
1200          * second argument of the "gpio-ranges" property.
1201          */
1202         pinctrl_base = of_args.args[1];
1203         gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
1204         if (gpioport >= RZA1_NPORTS) {
1205                 dev_err(rza1_pctl->dev,
1206                         "Invalid values in property %s\n", list_name);
1207                 return -EINVAL;
1208         }
1209
1210         *chip           = rza1_gpiochip_template;
1211         chip->base      = -1;
1212         chip->label     = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
1213                                          np);
1214         if (!chip->label)
1215                 return -ENOMEM;
1216
1217         chip->ngpio     = of_args.args[2];
1218         chip->of_node   = np;
1219         chip->parent    = rza1_pctl->dev;
1220
1221         range->id       = gpioport;
1222         range->name     = chip->label;
1223         range->pin_base = range->base = pinctrl_base;
1224         range->npins    = of_args.args[2];
1225         range->gc       = chip;
1226
1227         ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1228                                      &rza1_pctl->ports[gpioport]);
1229         if (ret)
1230                 return ret;
1231
1232         pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1233
1234         dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1235                  chip->label, chip->ngpio);
1236
1237         return 0;
1238 }
1239
1240 /**
1241  * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1242  *
1243  * @rza1_pctl: RZ/A1 pin controller device
1244  */
1245 static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1246 {
1247         struct device_node *np = rza1_pctl->dev->of_node;
1248         struct pinctrl_gpio_range *gpio_ranges;
1249         struct gpio_chip *gpio_chips;
1250         struct device_node *child;
1251         unsigned int ngpiochips;
1252         unsigned int i;
1253         int ret;
1254
1255         ngpiochips = rza1_count_gpio_chips(np);
1256         if (ngpiochips == 0) {
1257                 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1258                 return 0;
1259         }
1260
1261         gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1262                                   sizeof(*gpio_chips), GFP_KERNEL);
1263         gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1264                                    sizeof(*gpio_ranges), GFP_KERNEL);
1265         if (!gpio_chips || !gpio_ranges)
1266                 return -ENOMEM;
1267
1268         i = 0;
1269         for_each_child_of_node(np, child) {
1270                 if (!of_property_read_bool(child, "gpio-controller"))
1271                         continue;
1272
1273                 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1274                                           &gpio_ranges[i]);
1275                 if (ret)
1276                         return ret;
1277
1278                 ++i;
1279         }
1280
1281         dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1282
1283         return 0;
1284 }
1285
1286 /**
1287  * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1288  *                           them to pinctrl and gpio cores.
1289  *
1290  * @rza1_pctl: RZ/A1 pin controller device
1291  */
1292 static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1293 {
1294         struct pinctrl_pin_desc *pins;
1295         struct rza1_port *ports;
1296         unsigned int i;
1297         int ret;
1298
1299         pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1300                             GFP_KERNEL);
1301         ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1302                              GFP_KERNEL);
1303         if (!pins || !ports)
1304                 return -ENOMEM;
1305
1306         rza1_pctl->pins         = pins;
1307         rza1_pctl->desc.pins    = pins;
1308         rza1_pctl->desc.npins   = RZA1_NPINS;
1309         rza1_pctl->ports        = ports;
1310
1311         for (i = 0; i < RZA1_NPINS; ++i) {
1312                 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1313                 unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1314
1315                 pins[i].number = i;
1316                 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1317                                               "P%u-%u", port, pin);
1318                 if (!pins[i].name)
1319                         return -ENOMEM;
1320
1321                 if (i % RZA1_PINS_PER_PORT == 0) {
1322                         /*
1323                          * Setup ports;
1324                          * they provide per-port lock and logical base address.
1325                          */
1326                         unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1327
1328                         ports[port_id].id       = port_id;
1329                         ports[port_id].base     = rza1_pctl->base;
1330                         ports[port_id].pins     = &pins[i];
1331                         spin_lock_init(&ports[port_id].lock);
1332                 }
1333         }
1334
1335         ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1336                                              rza1_pctl, &rza1_pctl->pctl);
1337         if (ret) {
1338                 dev_err(rza1_pctl->dev,
1339                         "RZ/A1 pin controller registration failed\n");
1340                 return ret;
1341         }
1342
1343         ret = pinctrl_enable(rza1_pctl->pctl);
1344         if (ret) {
1345                 dev_err(rza1_pctl->dev,
1346                         "RZ/A1 pin controller failed to start\n");
1347                 return ret;
1348         }
1349
1350         ret = rza1_gpio_register(rza1_pctl);
1351         if (ret) {
1352                 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1353                 return ret;
1354         }
1355
1356         return 0;
1357 }
1358
1359 static int rza1_pinctrl_probe(struct platform_device *pdev)
1360 {
1361         struct rza1_pinctrl *rza1_pctl;
1362         struct resource *res;
1363         int ret;
1364
1365         rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1366         if (!rza1_pctl)
1367                 return -ENOMEM;
1368
1369         rza1_pctl->dev = &pdev->dev;
1370
1371         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372         rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
1373         if (IS_ERR(rza1_pctl->base))
1374                 return PTR_ERR(rza1_pctl->base);
1375
1376         mutex_init(&rza1_pctl->mutex);
1377
1378         platform_set_drvdata(pdev, rza1_pctl);
1379
1380         rza1_pctl->desc.name    = DRIVER_NAME;
1381         rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1382         rza1_pctl->desc.pmxops  = &rza1_pinmux_ops;
1383         rza1_pctl->desc.owner   = THIS_MODULE;
1384         rza1_pctl->data         = of_device_get_match_data(&pdev->dev);
1385
1386         ret = rza1_pinctrl_register(rza1_pctl);
1387         if (ret)
1388                 return ret;
1389
1390         dev_info(&pdev->dev,
1391                  "RZ/A1 pin controller and gpio successfully registered\n");
1392
1393         return 0;
1394 }
1395
1396 static const struct of_device_id rza1_pinctrl_of_match[] = {
1397         {
1398                 /* RZ/A1H, RZ/A1M */
1399                 .compatible     = "renesas,r7s72100-ports",
1400                 .data           = &rza1h_pmx_conf,
1401         },
1402         {
1403                 /* RZ/A1L */
1404                 .compatible     = "renesas,r7s72102-ports",
1405                 .data           = &rza1l_pmx_conf,
1406         },
1407         { }
1408 };
1409
1410 static struct platform_driver rza1_pinctrl_driver = {
1411         .driver = {
1412                 .name = DRIVER_NAME,
1413                 .of_match_table = rza1_pinctrl_of_match,
1414         },
1415         .probe = rza1_pinctrl_probe,
1416 };
1417
1418 static int __init rza1_pinctrl_init(void)
1419 {
1420         return platform_driver_register(&rza1_pinctrl_driver);
1421 }
1422 core_initcall(rza1_pinctrl_init);
1423
1424 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1425 MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1426 MODULE_LICENSE("GPL v2");