2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
34 #include "../pinconf.h"
35 #include "pinctrl-msm.h"
36 #include "../pinctrl-utils.h"
38 #define MAX_NR_GPIO 300
39 #define PS_HOLD_OFFSET 0x820
42 * struct msm_pinctrl - state for a pinctrl-msm device
43 * @dev: device handle.
44 * @pctrl: pinctrl handle.
45 * @chip: gpiochip handle.
46 * @restart_nb: restart notifier block.
47 * @irq: parent irq for the TLMM irq_chip.
48 * @lock: Spinlock to protect register resources as well
49 * as msm_pinctrl data structures.
50 * @enabled_irqs: Bitmap of currently enabled irqs.
51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
53 * @soc; Reference to soc_data of platform specific data.
54 * @regs: Base address for the TLMM register map.
58 struct pinctrl_dev
*pctrl
;
59 struct gpio_chip chip
;
60 struct notifier_block restart_nb
;
65 DECLARE_BITMAP(dual_edge_irqs
, MAX_NR_GPIO
);
66 DECLARE_BITMAP(enabled_irqs
, MAX_NR_GPIO
);
68 const struct msm_pinctrl_soc_data
*soc
;
72 static inline struct msm_pinctrl
*to_msm_pinctrl(struct gpio_chip
*gc
)
74 return container_of(gc
, struct msm_pinctrl
, chip
);
77 static int msm_get_groups_count(struct pinctrl_dev
*pctldev
)
79 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
81 return pctrl
->soc
->ngroups
;
84 static const char *msm_get_group_name(struct pinctrl_dev
*pctldev
,
87 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
89 return pctrl
->soc
->groups
[group
].name
;
92 static int msm_get_group_pins(struct pinctrl_dev
*pctldev
,
94 const unsigned **pins
,
97 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
99 *pins
= pctrl
->soc
->groups
[group
].pins
;
100 *num_pins
= pctrl
->soc
->groups
[group
].npins
;
104 static const struct pinctrl_ops msm_pinctrl_ops
= {
105 .get_groups_count
= msm_get_groups_count
,
106 .get_group_name
= msm_get_group_name
,
107 .get_group_pins
= msm_get_group_pins
,
108 .dt_node_to_map
= pinconf_generic_dt_node_to_map_group
,
109 .dt_free_map
= pinctrl_utils_dt_free_map
,
112 static int msm_get_functions_count(struct pinctrl_dev
*pctldev
)
114 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
116 return pctrl
->soc
->nfunctions
;
119 static const char *msm_get_function_name(struct pinctrl_dev
*pctldev
,
122 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
124 return pctrl
->soc
->functions
[function
].name
;
127 static int msm_get_function_groups(struct pinctrl_dev
*pctldev
,
129 const char * const **groups
,
130 unsigned * const num_groups
)
132 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
134 *groups
= pctrl
->soc
->functions
[function
].groups
;
135 *num_groups
= pctrl
->soc
->functions
[function
].ngroups
;
139 static int msm_pinmux_set_mux(struct pinctrl_dev
*pctldev
,
143 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
144 const struct msm_pingroup
*g
;
149 g
= &pctrl
->soc
->groups
[group
];
151 for (i
= 0; i
< g
->nfuncs
; i
++) {
152 if (g
->funcs
[i
] == function
)
156 if (WARN_ON(i
== g
->nfuncs
))
159 spin_lock_irqsave(&pctrl
->lock
, flags
);
161 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
162 val
&= ~(0x7 << g
->mux_bit
);
163 val
|= i
<< g
->mux_bit
;
164 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
166 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
171 static const struct pinmux_ops msm_pinmux_ops
= {
172 .get_functions_count
= msm_get_functions_count
,
173 .get_function_name
= msm_get_function_name
,
174 .get_function_groups
= msm_get_function_groups
,
175 .set_mux
= msm_pinmux_set_mux
,
178 static int msm_config_reg(struct msm_pinctrl
*pctrl
,
179 const struct msm_pingroup
*g
,
185 case PIN_CONFIG_BIAS_DISABLE
:
186 case PIN_CONFIG_BIAS_PULL_DOWN
:
187 case PIN_CONFIG_BIAS_BUS_HOLD
:
188 case PIN_CONFIG_BIAS_PULL_UP
:
192 case PIN_CONFIG_DRIVE_STRENGTH
:
196 case PIN_CONFIG_OUTPUT
:
197 case PIN_CONFIG_INPUT_ENABLE
:
208 #define MSM_NO_PULL 0
209 #define MSM_PULL_DOWN 1
211 #define MSM_PULL_UP 3
213 static unsigned msm_regval_to_drive(u32 val
)
215 return (val
+ 1) * 2;
218 static int msm_config_group_get(struct pinctrl_dev
*pctldev
,
220 unsigned long *config
)
222 const struct msm_pingroup
*g
;
223 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
224 unsigned param
= pinconf_to_config_param(*config
);
231 g
= &pctrl
->soc
->groups
[group
];
233 ret
= msm_config_reg(pctrl
, g
, param
, &mask
, &bit
);
237 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
238 arg
= (val
>> bit
) & mask
;
240 /* Convert register value to pinconf value */
242 case PIN_CONFIG_BIAS_DISABLE
:
243 arg
= arg
== MSM_NO_PULL
;
245 case PIN_CONFIG_BIAS_PULL_DOWN
:
246 arg
= arg
== MSM_PULL_DOWN
;
248 case PIN_CONFIG_BIAS_BUS_HOLD
:
249 arg
= arg
== MSM_KEEPER
;
251 case PIN_CONFIG_BIAS_PULL_UP
:
252 arg
= arg
== MSM_PULL_UP
;
254 case PIN_CONFIG_DRIVE_STRENGTH
:
255 arg
= msm_regval_to_drive(arg
);
257 case PIN_CONFIG_OUTPUT
:
258 /* Pin is not output */
262 val
= readl(pctrl
->regs
+ g
->io_reg
);
263 arg
= !!(val
& BIT(g
->in_bit
));
265 case PIN_CONFIG_INPUT_ENABLE
:
275 *config
= pinconf_to_config_packed(param
, arg
);
280 static int msm_config_group_set(struct pinctrl_dev
*pctldev
,
282 unsigned long *configs
,
283 unsigned num_configs
)
285 const struct msm_pingroup
*g
;
286 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
296 g
= &pctrl
->soc
->groups
[group
];
298 for (i
= 0; i
< num_configs
; i
++) {
299 param
= pinconf_to_config_param(configs
[i
]);
300 arg
= pinconf_to_config_argument(configs
[i
]);
302 ret
= msm_config_reg(pctrl
, g
, param
, &mask
, &bit
);
306 /* Convert pinconf values to register values */
308 case PIN_CONFIG_BIAS_DISABLE
:
311 case PIN_CONFIG_BIAS_PULL_DOWN
:
314 case PIN_CONFIG_BIAS_BUS_HOLD
:
317 case PIN_CONFIG_BIAS_PULL_UP
:
320 case PIN_CONFIG_DRIVE_STRENGTH
:
321 /* Check for invalid values */
322 if (arg
> 16 || arg
< 2 || (arg
% 2) != 0)
327 case PIN_CONFIG_OUTPUT
:
328 /* set output value */
329 spin_lock_irqsave(&pctrl
->lock
, flags
);
330 val
= readl(pctrl
->regs
+ g
->io_reg
);
332 val
|= BIT(g
->out_bit
);
334 val
&= ~BIT(g
->out_bit
);
335 writel(val
, pctrl
->regs
+ g
->io_reg
);
336 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
341 case PIN_CONFIG_INPUT_ENABLE
:
346 dev_err(pctrl
->dev
, "Unsupported config parameter: %x\n",
351 /* Range-check user-supplied value */
353 dev_err(pctrl
->dev
, "config %x: %x is invalid\n", param
, arg
);
357 spin_lock_irqsave(&pctrl
->lock
, flags
);
358 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
359 val
&= ~(mask
<< bit
);
361 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
362 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
368 static const struct pinconf_ops msm_pinconf_ops
= {
370 .pin_config_group_get
= msm_config_group_get
,
371 .pin_config_group_set
= msm_config_group_set
,
374 static struct pinctrl_desc msm_pinctrl_desc
= {
375 .pctlops
= &msm_pinctrl_ops
,
376 .pmxops
= &msm_pinmux_ops
,
377 .confops
= &msm_pinconf_ops
,
378 .owner
= THIS_MODULE
,
381 static int msm_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
383 const struct msm_pingroup
*g
;
384 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
388 g
= &pctrl
->soc
->groups
[offset
];
390 spin_lock_irqsave(&pctrl
->lock
, flags
);
392 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
393 val
&= ~BIT(g
->oe_bit
);
394 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
396 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
401 static int msm_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
403 const struct msm_pingroup
*g
;
404 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
408 g
= &pctrl
->soc
->groups
[offset
];
410 spin_lock_irqsave(&pctrl
->lock
, flags
);
412 val
= readl(pctrl
->regs
+ g
->io_reg
);
414 val
|= BIT(g
->out_bit
);
416 val
&= ~BIT(g
->out_bit
);
417 writel(val
, pctrl
->regs
+ g
->io_reg
);
419 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
420 val
|= BIT(g
->oe_bit
);
421 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
423 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
428 static int msm_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
430 const struct msm_pingroup
*g
;
431 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
434 g
= &pctrl
->soc
->groups
[offset
];
436 val
= readl(pctrl
->regs
+ g
->io_reg
);
437 return !!(val
& BIT(g
->in_bit
));
440 static void msm_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
442 const struct msm_pingroup
*g
;
443 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
447 g
= &pctrl
->soc
->groups
[offset
];
449 spin_lock_irqsave(&pctrl
->lock
, flags
);
451 val
= readl(pctrl
->regs
+ g
->io_reg
);
453 val
|= BIT(g
->out_bit
);
455 val
&= ~BIT(g
->out_bit
);
456 writel(val
, pctrl
->regs
+ g
->io_reg
);
458 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
461 static int msm_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
463 int gpio
= chip
->base
+ offset
;
464 return pinctrl_request_gpio(gpio
);
467 static void msm_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
469 int gpio
= chip
->base
+ offset
;
470 return pinctrl_free_gpio(gpio
);
473 #ifdef CONFIG_DEBUG_FS
474 #include <linux/seq_file.h>
476 static void msm_gpio_dbg_show_one(struct seq_file
*s
,
477 struct pinctrl_dev
*pctldev
,
478 struct gpio_chip
*chip
,
482 const struct msm_pingroup
*g
;
483 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
490 static const char * const pulls
[] = {
497 g
= &pctrl
->soc
->groups
[offset
];
498 ctl_reg
= readl(pctrl
->regs
+ g
->ctl_reg
);
500 is_out
= !!(ctl_reg
& BIT(g
->oe_bit
));
501 func
= (ctl_reg
>> g
->mux_bit
) & 7;
502 drive
= (ctl_reg
>> g
->drv_bit
) & 7;
503 pull
= (ctl_reg
>> g
->pull_bit
) & 3;
505 seq_printf(s
, " %-8s: %-3s %d", g
->name
, is_out
? "out" : "in", func
);
506 seq_printf(s
, " %dmA", msm_regval_to_drive(drive
));
507 seq_printf(s
, " %s", pulls
[pull
]);
510 static void msm_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
512 unsigned gpio
= chip
->base
;
515 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
516 msm_gpio_dbg_show_one(s
, NULL
, chip
, i
, gpio
);
522 #define msm_gpio_dbg_show NULL
525 static struct gpio_chip msm_gpio_template
= {
526 .direction_input
= msm_gpio_direction_input
,
527 .direction_output
= msm_gpio_direction_output
,
530 .request
= msm_gpio_request
,
531 .free
= msm_gpio_free
,
532 .dbg_show
= msm_gpio_dbg_show
,
535 /* For dual-edge interrupts in software, since some hardware has no
538 * At appropriate moments, this function may be called to flip the polarity
539 * settings of both-edge irq lines to try and catch the next edge.
541 * The attempt is considered successful if:
542 * - the status bit goes high, indicating that an edge was caught, or
543 * - the input value of the gpio doesn't change during the attempt.
544 * If the value changes twice during the process, that would cause the first
545 * test to fail but would force the second, as two opposite
546 * transitions would cause a detection no matter the polarity setting.
548 * The do-loop tries to sledge-hammer closed the timing hole between
549 * the initial value-read and the polarity-write - if the line value changes
550 * during that window, an interrupt is lost, the new polarity setting is
551 * incorrect, and the first success test will fail, causing a retry.
553 * Algorithm comes from Google's msmgpio driver.
555 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl
*pctrl
,
556 const struct msm_pingroup
*g
,
559 int loop_limit
= 100;
560 unsigned val
, val2
, intstat
;
564 val
= readl(pctrl
->regs
+ g
->io_reg
) & BIT(g
->in_bit
);
566 pol
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
567 pol
^= BIT(g
->intr_polarity_bit
);
568 writel(pol
, pctrl
->regs
+ g
->intr_cfg_reg
);
570 val2
= readl(pctrl
->regs
+ g
->io_reg
) & BIT(g
->in_bit
);
571 intstat
= readl(pctrl
->regs
+ g
->intr_status_reg
);
572 if (intstat
|| (val
== val2
))
574 } while (loop_limit
-- > 0);
575 dev_err(pctrl
->dev
, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
579 static void msm_gpio_irq_mask(struct irq_data
*d
)
581 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
582 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
583 const struct msm_pingroup
*g
;
587 g
= &pctrl
->soc
->groups
[d
->hwirq
];
589 spin_lock_irqsave(&pctrl
->lock
, flags
);
591 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
592 val
&= ~BIT(g
->intr_enable_bit
);
593 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
595 clear_bit(d
->hwirq
, pctrl
->enabled_irqs
);
597 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
600 static void msm_gpio_irq_unmask(struct irq_data
*d
)
602 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
603 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
604 const struct msm_pingroup
*g
;
608 g
= &pctrl
->soc
->groups
[d
->hwirq
];
610 spin_lock_irqsave(&pctrl
->lock
, flags
);
612 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
613 val
&= ~BIT(g
->intr_status_bit
);
614 writel(val
, pctrl
->regs
+ g
->intr_status_reg
);
616 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
617 val
|= BIT(g
->intr_enable_bit
);
618 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
620 set_bit(d
->hwirq
, pctrl
->enabled_irqs
);
622 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
625 static void msm_gpio_irq_ack(struct irq_data
*d
)
627 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
628 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
629 const struct msm_pingroup
*g
;
633 g
= &pctrl
->soc
->groups
[d
->hwirq
];
635 spin_lock_irqsave(&pctrl
->lock
, flags
);
637 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
638 if (g
->intr_ack_high
)
639 val
|= BIT(g
->intr_status_bit
);
641 val
&= ~BIT(g
->intr_status_bit
);
642 writel(val
, pctrl
->regs
+ g
->intr_status_reg
);
644 if (test_bit(d
->hwirq
, pctrl
->dual_edge_irqs
))
645 msm_gpio_update_dual_edge_pos(pctrl
, g
, d
);
647 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
650 static int msm_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
652 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
653 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
654 const struct msm_pingroup
*g
;
658 g
= &pctrl
->soc
->groups
[d
->hwirq
];
660 spin_lock_irqsave(&pctrl
->lock
, flags
);
663 * For hw without possibility of detecting both edges
665 if (g
->intr_detection_width
== 1 && type
== IRQ_TYPE_EDGE_BOTH
)
666 set_bit(d
->hwirq
, pctrl
->dual_edge_irqs
);
668 clear_bit(d
->hwirq
, pctrl
->dual_edge_irqs
);
670 /* Route interrupts to application cpu */
671 val
= readl(pctrl
->regs
+ g
->intr_target_reg
);
672 val
&= ~(7 << g
->intr_target_bit
);
673 val
|= g
->intr_target_kpss_val
<< g
->intr_target_bit
;
674 writel(val
, pctrl
->regs
+ g
->intr_target_reg
);
676 /* Update configuration for gpio.
677 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
678 * internal circuitry of TLMM, toggling the RAW_STATUS
679 * could cause the INTR_STATUS to be set for EDGE interrupts.
681 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
682 val
|= BIT(g
->intr_raw_status_bit
);
683 if (g
->intr_detection_width
== 2) {
684 val
&= ~(3 << g
->intr_detection_bit
);
685 val
&= ~(1 << g
->intr_polarity_bit
);
687 case IRQ_TYPE_EDGE_RISING
:
688 val
|= 1 << g
->intr_detection_bit
;
689 val
|= BIT(g
->intr_polarity_bit
);
691 case IRQ_TYPE_EDGE_FALLING
:
692 val
|= 2 << g
->intr_detection_bit
;
693 val
|= BIT(g
->intr_polarity_bit
);
695 case IRQ_TYPE_EDGE_BOTH
:
696 val
|= 3 << g
->intr_detection_bit
;
697 val
|= BIT(g
->intr_polarity_bit
);
699 case IRQ_TYPE_LEVEL_LOW
:
701 case IRQ_TYPE_LEVEL_HIGH
:
702 val
|= BIT(g
->intr_polarity_bit
);
705 } else if (g
->intr_detection_width
== 1) {
706 val
&= ~(1 << g
->intr_detection_bit
);
707 val
&= ~(1 << g
->intr_polarity_bit
);
709 case IRQ_TYPE_EDGE_RISING
:
710 val
|= BIT(g
->intr_detection_bit
);
711 val
|= BIT(g
->intr_polarity_bit
);
713 case IRQ_TYPE_EDGE_FALLING
:
714 val
|= BIT(g
->intr_detection_bit
);
716 case IRQ_TYPE_EDGE_BOTH
:
717 val
|= BIT(g
->intr_detection_bit
);
718 val
|= BIT(g
->intr_polarity_bit
);
720 case IRQ_TYPE_LEVEL_LOW
:
722 case IRQ_TYPE_LEVEL_HIGH
:
723 val
|= BIT(g
->intr_polarity_bit
);
729 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
731 if (test_bit(d
->hwirq
, pctrl
->dual_edge_irqs
))
732 msm_gpio_update_dual_edge_pos(pctrl
, g
, d
);
734 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
736 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
737 irq_set_handler_locked(d
, handle_level_irq
);
738 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
739 irq_set_handler_locked(d
, handle_edge_irq
);
744 static int msm_gpio_irq_set_wake(struct irq_data
*d
, unsigned int on
)
746 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
747 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
750 spin_lock_irqsave(&pctrl
->lock
, flags
);
752 irq_set_irq_wake(pctrl
->irq
, on
);
754 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
759 static struct irq_chip msm_gpio_irq_chip
= {
761 .irq_mask
= msm_gpio_irq_mask
,
762 .irq_unmask
= msm_gpio_irq_unmask
,
763 .irq_ack
= msm_gpio_irq_ack
,
764 .irq_set_type
= msm_gpio_irq_set_type
,
765 .irq_set_wake
= msm_gpio_irq_set_wake
,
768 static void msm_gpio_irq_handler(unsigned int __irq
, struct irq_desc
*desc
)
770 unsigned int irq
= irq_desc_get_irq(desc
);
771 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
772 const struct msm_pingroup
*g
;
773 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
774 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
780 chained_irq_enter(chip
, desc
);
783 * Each pin has it's own IRQ status register, so use
784 * enabled_irq bitmap to limit the number of reads.
786 for_each_set_bit(i
, pctrl
->enabled_irqs
, pctrl
->chip
.ngpio
) {
787 g
= &pctrl
->soc
->groups
[i
];
788 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
789 if (val
& BIT(g
->intr_status_bit
)) {
790 irq_pin
= irq_find_mapping(gc
->irqdomain
, i
);
791 generic_handle_irq(irq_pin
);
796 /* No interrupts were flagged */
798 handle_bad_irq(irq
, desc
);
800 chained_irq_exit(chip
, desc
);
803 static int msm_gpio_init(struct msm_pinctrl
*pctrl
)
805 struct gpio_chip
*chip
;
807 unsigned ngpio
= pctrl
->soc
->ngpios
;
809 if (WARN_ON(ngpio
> MAX_NR_GPIO
))
815 chip
->label
= dev_name(pctrl
->dev
);
816 chip
->dev
= pctrl
->dev
;
817 chip
->owner
= THIS_MODULE
;
818 chip
->of_node
= pctrl
->dev
->of_node
;
820 ret
= gpiochip_add(&pctrl
->chip
);
822 dev_err(pctrl
->dev
, "Failed register gpiochip\n");
826 ret
= gpiochip_add_pin_range(&pctrl
->chip
, dev_name(pctrl
->dev
), 0, 0, chip
->ngpio
);
828 dev_err(pctrl
->dev
, "Failed to add pin range\n");
829 gpiochip_remove(&pctrl
->chip
);
833 ret
= gpiochip_irqchip_add(chip
,
839 dev_err(pctrl
->dev
, "Failed to add irqchip to gpiochip\n");
840 gpiochip_remove(&pctrl
->chip
);
844 gpiochip_set_chained_irqchip(chip
, &msm_gpio_irq_chip
, pctrl
->irq
,
845 msm_gpio_irq_handler
);
850 static int msm_ps_hold_restart(struct notifier_block
*nb
, unsigned long action
,
853 struct msm_pinctrl
*pctrl
= container_of(nb
, struct msm_pinctrl
, restart_nb
);
855 writel(0, pctrl
->regs
+ PS_HOLD_OFFSET
);
860 static struct msm_pinctrl
*poweroff_pctrl
;
862 static void msm_ps_hold_poweroff(void)
864 msm_ps_hold_restart(&poweroff_pctrl
->restart_nb
, 0, NULL
);
867 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl
*pctrl
)
870 const struct msm_function
*func
= pctrl
->soc
->functions
;
872 for (i
= 0; i
< pctrl
->soc
->nfunctions
; i
++)
873 if (!strcmp(func
[i
].name
, "ps_hold")) {
874 pctrl
->restart_nb
.notifier_call
= msm_ps_hold_restart
;
875 pctrl
->restart_nb
.priority
= 128;
876 if (register_restart_handler(&pctrl
->restart_nb
))
878 "failed to setup restart handler.\n");
879 poweroff_pctrl
= pctrl
;
880 pm_power_off
= msm_ps_hold_poweroff
;
885 int msm_pinctrl_probe(struct platform_device
*pdev
,
886 const struct msm_pinctrl_soc_data
*soc_data
)
888 struct msm_pinctrl
*pctrl
;
889 struct resource
*res
;
892 pctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctrl
), GFP_KERNEL
);
894 dev_err(&pdev
->dev
, "Can't allocate msm_pinctrl\n");
897 pctrl
->dev
= &pdev
->dev
;
898 pctrl
->soc
= soc_data
;
899 pctrl
->chip
= msm_gpio_template
;
901 spin_lock_init(&pctrl
->lock
);
903 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
904 pctrl
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
905 if (IS_ERR(pctrl
->regs
))
906 return PTR_ERR(pctrl
->regs
);
908 msm_pinctrl_setup_pm_reset(pctrl
);
910 pctrl
->irq
= platform_get_irq(pdev
, 0);
911 if (pctrl
->irq
< 0) {
912 dev_err(&pdev
->dev
, "No interrupt defined for msmgpio\n");
916 msm_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
917 msm_pinctrl_desc
.pins
= pctrl
->soc
->pins
;
918 msm_pinctrl_desc
.npins
= pctrl
->soc
->npins
;
919 pctrl
->pctrl
= pinctrl_register(&msm_pinctrl_desc
, &pdev
->dev
, pctrl
);
920 if (IS_ERR(pctrl
->pctrl
)) {
921 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
922 return PTR_ERR(pctrl
->pctrl
);
925 ret
= msm_gpio_init(pctrl
);
927 pinctrl_unregister(pctrl
->pctrl
);
931 platform_set_drvdata(pdev
, pctrl
);
933 dev_dbg(&pdev
->dev
, "Probed Qualcomm pinctrl driver\n");
937 EXPORT_SYMBOL(msm_pinctrl_probe
);
939 int msm_pinctrl_remove(struct platform_device
*pdev
)
941 struct msm_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
943 gpiochip_remove(&pctrl
->chip
);
944 pinctrl_unregister(pctrl
->pctrl
);
946 unregister_restart_handler(&pctrl
->restart_nb
);
950 EXPORT_SYMBOL(msm_pinctrl_remove
);