2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
31 #include <asm/system_misc.h>
34 #include "../pinconf.h"
35 #include "pinctrl-msm.h"
36 #include "../pinctrl-utils.h"
38 #define MAX_NR_GPIO 300
39 #define PS_HOLD_OFFSET 0x820
42 * struct msm_pinctrl - state for a pinctrl-msm device
43 * @dev: device handle.
44 * @pctrl: pinctrl handle.
45 * @chip: gpiochip handle.
46 * @irq: parent irq for the TLMM irq_chip.
47 * @lock: Spinlock to protect register resources as well
48 * as msm_pinctrl data structures.
49 * @enabled_irqs: Bitmap of currently enabled irqs.
50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52 * @soc; Reference to soc_data of platform specific data.
53 * @regs: Base address for the TLMM register map.
57 struct pinctrl_dev
*pctrl
;
58 struct gpio_chip chip
;
63 DECLARE_BITMAP(dual_edge_irqs
, MAX_NR_GPIO
);
64 DECLARE_BITMAP(enabled_irqs
, MAX_NR_GPIO
);
66 const struct msm_pinctrl_soc_data
*soc
;
70 static inline struct msm_pinctrl
*to_msm_pinctrl(struct gpio_chip
*gc
)
72 return container_of(gc
, struct msm_pinctrl
, chip
);
75 static int msm_get_groups_count(struct pinctrl_dev
*pctldev
)
77 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
79 return pctrl
->soc
->ngroups
;
82 static const char *msm_get_group_name(struct pinctrl_dev
*pctldev
,
85 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
87 return pctrl
->soc
->groups
[group
].name
;
90 static int msm_get_group_pins(struct pinctrl_dev
*pctldev
,
92 const unsigned **pins
,
95 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
97 *pins
= pctrl
->soc
->groups
[group
].pins
;
98 *num_pins
= pctrl
->soc
->groups
[group
].npins
;
102 static const struct pinctrl_ops msm_pinctrl_ops
= {
103 .get_groups_count
= msm_get_groups_count
,
104 .get_group_name
= msm_get_group_name
,
105 .get_group_pins
= msm_get_group_pins
,
106 .dt_node_to_map
= pinconf_generic_dt_node_to_map_group
,
107 .dt_free_map
= pinctrl_utils_dt_free_map
,
110 static int msm_get_functions_count(struct pinctrl_dev
*pctldev
)
112 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
114 return pctrl
->soc
->nfunctions
;
117 static const char *msm_get_function_name(struct pinctrl_dev
*pctldev
,
120 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
122 return pctrl
->soc
->functions
[function
].name
;
125 static int msm_get_function_groups(struct pinctrl_dev
*pctldev
,
127 const char * const **groups
,
128 unsigned * const num_groups
)
130 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
132 *groups
= pctrl
->soc
->functions
[function
].groups
;
133 *num_groups
= pctrl
->soc
->functions
[function
].ngroups
;
137 static int msm_pinmux_set_mux(struct pinctrl_dev
*pctldev
,
141 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
142 const struct msm_pingroup
*g
;
147 g
= &pctrl
->soc
->groups
[group
];
149 for (i
= 0; i
< g
->nfuncs
; i
++) {
150 if (g
->funcs
[i
] == function
)
154 if (WARN_ON(i
== g
->nfuncs
))
157 spin_lock_irqsave(&pctrl
->lock
, flags
);
159 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
160 val
&= ~(0x7 << g
->mux_bit
);
161 val
|= i
<< g
->mux_bit
;
162 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
164 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
169 static const struct pinmux_ops msm_pinmux_ops
= {
170 .get_functions_count
= msm_get_functions_count
,
171 .get_function_name
= msm_get_function_name
,
172 .get_function_groups
= msm_get_function_groups
,
173 .set_mux
= msm_pinmux_set_mux
,
176 static int msm_config_reg(struct msm_pinctrl
*pctrl
,
177 const struct msm_pingroup
*g
,
183 case PIN_CONFIG_BIAS_DISABLE
:
184 case PIN_CONFIG_BIAS_PULL_DOWN
:
185 case PIN_CONFIG_BIAS_BUS_HOLD
:
186 case PIN_CONFIG_BIAS_PULL_UP
:
190 case PIN_CONFIG_DRIVE_STRENGTH
:
194 case PIN_CONFIG_OUTPUT
:
199 dev_err(pctrl
->dev
, "Invalid config param %04x\n", param
);
206 static int msm_config_get(struct pinctrl_dev
*pctldev
,
208 unsigned long *config
)
210 dev_err(pctldev
->dev
, "pin_config_set op not supported\n");
214 static int msm_config_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
215 unsigned long *configs
, unsigned num_configs
)
217 dev_err(pctldev
->dev
, "pin_config_set op not supported\n");
221 #define MSM_NO_PULL 0
222 #define MSM_PULL_DOWN 1
224 #define MSM_PULL_UP 3
226 static unsigned msm_regval_to_drive(u32 val
)
228 return (val
+ 1) * 2;
231 static int msm_config_group_get(struct pinctrl_dev
*pctldev
,
233 unsigned long *config
)
235 const struct msm_pingroup
*g
;
236 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
237 unsigned param
= pinconf_to_config_param(*config
);
244 g
= &pctrl
->soc
->groups
[group
];
246 ret
= msm_config_reg(pctrl
, g
, param
, &mask
, &bit
);
250 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
251 arg
= (val
>> bit
) & mask
;
253 /* Convert register value to pinconf value */
255 case PIN_CONFIG_BIAS_DISABLE
:
256 arg
= arg
== MSM_NO_PULL
;
258 case PIN_CONFIG_BIAS_PULL_DOWN
:
259 arg
= arg
== MSM_PULL_DOWN
;
261 case PIN_CONFIG_BIAS_BUS_HOLD
:
262 arg
= arg
== MSM_KEEPER
;
264 case PIN_CONFIG_BIAS_PULL_UP
:
265 arg
= arg
== MSM_PULL_UP
;
267 case PIN_CONFIG_DRIVE_STRENGTH
:
268 arg
= msm_regval_to_drive(arg
);
270 case PIN_CONFIG_OUTPUT
:
271 /* Pin is not output */
275 val
= readl(pctrl
->regs
+ g
->io_reg
);
276 arg
= !!(val
& BIT(g
->in_bit
));
279 dev_err(pctrl
->dev
, "Unsupported config parameter: %x\n",
284 *config
= pinconf_to_config_packed(param
, arg
);
289 static int msm_config_group_set(struct pinctrl_dev
*pctldev
,
291 unsigned long *configs
,
292 unsigned num_configs
)
294 const struct msm_pingroup
*g
;
295 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
305 g
= &pctrl
->soc
->groups
[group
];
307 for (i
= 0; i
< num_configs
; i
++) {
308 param
= pinconf_to_config_param(configs
[i
]);
309 arg
= pinconf_to_config_argument(configs
[i
]);
311 ret
= msm_config_reg(pctrl
, g
, param
, &mask
, &bit
);
315 /* Convert pinconf values to register values */
317 case PIN_CONFIG_BIAS_DISABLE
:
320 case PIN_CONFIG_BIAS_PULL_DOWN
:
323 case PIN_CONFIG_BIAS_BUS_HOLD
:
326 case PIN_CONFIG_BIAS_PULL_UP
:
329 case PIN_CONFIG_DRIVE_STRENGTH
:
330 /* Check for invalid values */
331 if (arg
> 16 || arg
< 2 || (arg
% 2) != 0)
336 case PIN_CONFIG_OUTPUT
:
337 /* set output value */
338 spin_lock_irqsave(&pctrl
->lock
, flags
);
339 val
= readl(pctrl
->regs
+ g
->io_reg
);
341 val
|= BIT(g
->out_bit
);
343 val
&= ~BIT(g
->out_bit
);
344 writel(val
, pctrl
->regs
+ g
->io_reg
);
345 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
351 dev_err(pctrl
->dev
, "Unsupported config parameter: %x\n",
356 /* Range-check user-supplied value */
358 dev_err(pctrl
->dev
, "config %x: %x is invalid\n", param
, arg
);
362 spin_lock_irqsave(&pctrl
->lock
, flags
);
363 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
364 val
&= ~(mask
<< bit
);
366 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
367 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
373 static const struct pinconf_ops msm_pinconf_ops
= {
374 .pin_config_get
= msm_config_get
,
375 .pin_config_set
= msm_config_set
,
376 .pin_config_group_get
= msm_config_group_get
,
377 .pin_config_group_set
= msm_config_group_set
,
380 static struct pinctrl_desc msm_pinctrl_desc
= {
381 .pctlops
= &msm_pinctrl_ops
,
382 .pmxops
= &msm_pinmux_ops
,
383 .confops
= &msm_pinconf_ops
,
384 .owner
= THIS_MODULE
,
387 static int msm_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
389 const struct msm_pingroup
*g
;
390 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
394 g
= &pctrl
->soc
->groups
[offset
];
396 spin_lock_irqsave(&pctrl
->lock
, flags
);
398 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
399 val
&= ~BIT(g
->oe_bit
);
400 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
402 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
407 static int msm_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
409 const struct msm_pingroup
*g
;
410 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
414 g
= &pctrl
->soc
->groups
[offset
];
416 spin_lock_irqsave(&pctrl
->lock
, flags
);
418 val
= readl(pctrl
->regs
+ g
->io_reg
);
420 val
|= BIT(g
->out_bit
);
422 val
&= ~BIT(g
->out_bit
);
423 writel(val
, pctrl
->regs
+ g
->io_reg
);
425 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
426 val
|= BIT(g
->oe_bit
);
427 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
429 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
434 static int msm_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
436 const struct msm_pingroup
*g
;
437 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
440 g
= &pctrl
->soc
->groups
[offset
];
442 val
= readl(pctrl
->regs
+ g
->io_reg
);
443 return !!(val
& BIT(g
->in_bit
));
446 static void msm_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
448 const struct msm_pingroup
*g
;
449 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
453 g
= &pctrl
->soc
->groups
[offset
];
455 spin_lock_irqsave(&pctrl
->lock
, flags
);
457 val
= readl(pctrl
->regs
+ g
->io_reg
);
459 val
|= BIT(g
->out_bit
);
461 val
&= ~BIT(g
->out_bit
);
462 writel(val
, pctrl
->regs
+ g
->io_reg
);
464 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
467 static int msm_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
469 int gpio
= chip
->base
+ offset
;
470 return pinctrl_request_gpio(gpio
);
473 static void msm_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
475 int gpio
= chip
->base
+ offset
;
476 return pinctrl_free_gpio(gpio
);
479 #ifdef CONFIG_DEBUG_FS
480 #include <linux/seq_file.h>
482 static void msm_gpio_dbg_show_one(struct seq_file
*s
,
483 struct pinctrl_dev
*pctldev
,
484 struct gpio_chip
*chip
,
488 const struct msm_pingroup
*g
;
489 struct msm_pinctrl
*pctrl
= container_of(chip
, struct msm_pinctrl
, chip
);
496 static const char * const pulls
[] = {
503 g
= &pctrl
->soc
->groups
[offset
];
504 ctl_reg
= readl(pctrl
->regs
+ g
->ctl_reg
);
506 is_out
= !!(ctl_reg
& BIT(g
->oe_bit
));
507 func
= (ctl_reg
>> g
->mux_bit
) & 7;
508 drive
= (ctl_reg
>> g
->drv_bit
) & 7;
509 pull
= (ctl_reg
>> g
->pull_bit
) & 3;
511 seq_printf(s
, " %-8s: %-3s %d", g
->name
, is_out
? "out" : "in", func
);
512 seq_printf(s
, " %dmA", msm_regval_to_drive(drive
));
513 seq_printf(s
, " %s", pulls
[pull
]);
516 static void msm_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
518 unsigned gpio
= chip
->base
;
521 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
522 msm_gpio_dbg_show_one(s
, NULL
, chip
, i
, gpio
);
528 #define msm_gpio_dbg_show NULL
531 static struct gpio_chip msm_gpio_template
= {
532 .direction_input
= msm_gpio_direction_input
,
533 .direction_output
= msm_gpio_direction_output
,
536 .request
= msm_gpio_request
,
537 .free
= msm_gpio_free
,
538 .dbg_show
= msm_gpio_dbg_show
,
541 /* For dual-edge interrupts in software, since some hardware has no
544 * At appropriate moments, this function may be called to flip the polarity
545 * settings of both-edge irq lines to try and catch the next edge.
547 * The attempt is considered successful if:
548 * - the status bit goes high, indicating that an edge was caught, or
549 * - the input value of the gpio doesn't change during the attempt.
550 * If the value changes twice during the process, that would cause the first
551 * test to fail but would force the second, as two opposite
552 * transitions would cause a detection no matter the polarity setting.
554 * The do-loop tries to sledge-hammer closed the timing hole between
555 * the initial value-read and the polarity-write - if the line value changes
556 * during that window, an interrupt is lost, the new polarity setting is
557 * incorrect, and the first success test will fail, causing a retry.
559 * Algorithm comes from Google's msmgpio driver.
561 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl
*pctrl
,
562 const struct msm_pingroup
*g
,
565 int loop_limit
= 100;
566 unsigned val
, val2
, intstat
;
570 val
= readl(pctrl
->regs
+ g
->io_reg
) & BIT(g
->in_bit
);
572 pol
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
573 pol
^= BIT(g
->intr_polarity_bit
);
574 writel(pol
, pctrl
->regs
+ g
->intr_cfg_reg
);
576 val2
= readl(pctrl
->regs
+ g
->io_reg
) & BIT(g
->in_bit
);
577 intstat
= readl(pctrl
->regs
+ g
->intr_status_reg
);
578 if (intstat
|| (val
== val2
))
580 } while (loop_limit
-- > 0);
581 dev_err(pctrl
->dev
, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
585 static void msm_gpio_irq_mask(struct irq_data
*d
)
587 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
588 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
589 const struct msm_pingroup
*g
;
593 g
= &pctrl
->soc
->groups
[d
->hwirq
];
595 spin_lock_irqsave(&pctrl
->lock
, flags
);
597 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
598 val
&= ~BIT(g
->intr_enable_bit
);
599 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
601 clear_bit(d
->hwirq
, pctrl
->enabled_irqs
);
603 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
606 static void msm_gpio_irq_unmask(struct irq_data
*d
)
608 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
609 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
610 const struct msm_pingroup
*g
;
614 g
= &pctrl
->soc
->groups
[d
->hwirq
];
616 spin_lock_irqsave(&pctrl
->lock
, flags
);
618 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
619 val
&= ~BIT(g
->intr_status_bit
);
620 writel(val
, pctrl
->regs
+ g
->intr_status_reg
);
622 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
623 val
|= BIT(g
->intr_enable_bit
);
624 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
626 set_bit(d
->hwirq
, pctrl
->enabled_irqs
);
628 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
631 static void msm_gpio_irq_ack(struct irq_data
*d
)
633 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
634 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
635 const struct msm_pingroup
*g
;
639 g
= &pctrl
->soc
->groups
[d
->hwirq
];
641 spin_lock_irqsave(&pctrl
->lock
, flags
);
643 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
644 if (g
->intr_ack_high
)
645 val
|= BIT(g
->intr_status_bit
);
647 val
&= ~BIT(g
->intr_status_bit
);
648 writel(val
, pctrl
->regs
+ g
->intr_status_reg
);
650 if (test_bit(d
->hwirq
, pctrl
->dual_edge_irqs
))
651 msm_gpio_update_dual_edge_pos(pctrl
, g
, d
);
653 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
656 #define INTR_TARGET_PROC_APPS 4
658 static int msm_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
660 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
661 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
662 const struct msm_pingroup
*g
;
666 g
= &pctrl
->soc
->groups
[d
->hwirq
];
668 spin_lock_irqsave(&pctrl
->lock
, flags
);
671 * For hw without possibility of detecting both edges
673 if (g
->intr_detection_width
== 1 && type
== IRQ_TYPE_EDGE_BOTH
)
674 set_bit(d
->hwirq
, pctrl
->dual_edge_irqs
);
676 clear_bit(d
->hwirq
, pctrl
->dual_edge_irqs
);
678 /* Route interrupts to application cpu */
679 val
= readl(pctrl
->regs
+ g
->intr_target_reg
);
680 val
&= ~(7 << g
->intr_target_bit
);
681 val
|= INTR_TARGET_PROC_APPS
<< g
->intr_target_bit
;
682 writel(val
, pctrl
->regs
+ g
->intr_target_reg
);
684 /* Update configuration for gpio.
685 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
686 * internal circuitry of TLMM, toggling the RAW_STATUS
687 * could cause the INTR_STATUS to be set for EDGE interrupts.
689 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
690 val
|= BIT(g
->intr_raw_status_bit
);
691 if (g
->intr_detection_width
== 2) {
692 val
&= ~(3 << g
->intr_detection_bit
);
693 val
&= ~(1 << g
->intr_polarity_bit
);
695 case IRQ_TYPE_EDGE_RISING
:
696 val
|= 1 << g
->intr_detection_bit
;
697 val
|= BIT(g
->intr_polarity_bit
);
699 case IRQ_TYPE_EDGE_FALLING
:
700 val
|= 2 << g
->intr_detection_bit
;
701 val
|= BIT(g
->intr_polarity_bit
);
703 case IRQ_TYPE_EDGE_BOTH
:
704 val
|= 3 << g
->intr_detection_bit
;
705 val
|= BIT(g
->intr_polarity_bit
);
707 case IRQ_TYPE_LEVEL_LOW
:
709 case IRQ_TYPE_LEVEL_HIGH
:
710 val
|= BIT(g
->intr_polarity_bit
);
713 } else if (g
->intr_detection_width
== 1) {
714 val
&= ~(1 << g
->intr_detection_bit
);
715 val
&= ~(1 << g
->intr_polarity_bit
);
717 case IRQ_TYPE_EDGE_RISING
:
718 val
|= BIT(g
->intr_detection_bit
);
719 val
|= BIT(g
->intr_polarity_bit
);
721 case IRQ_TYPE_EDGE_FALLING
:
722 val
|= BIT(g
->intr_detection_bit
);
724 case IRQ_TYPE_EDGE_BOTH
:
725 val
|= BIT(g
->intr_detection_bit
);
726 val
|= BIT(g
->intr_polarity_bit
);
728 case IRQ_TYPE_LEVEL_LOW
:
730 case IRQ_TYPE_LEVEL_HIGH
:
731 val
|= BIT(g
->intr_polarity_bit
);
737 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
739 if (test_bit(d
->hwirq
, pctrl
->dual_edge_irqs
))
740 msm_gpio_update_dual_edge_pos(pctrl
, g
, d
);
742 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
744 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
745 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
746 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
747 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
752 static int msm_gpio_irq_set_wake(struct irq_data
*d
, unsigned int on
)
754 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
755 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
758 spin_lock_irqsave(&pctrl
->lock
, flags
);
760 irq_set_irq_wake(pctrl
->irq
, on
);
762 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
767 static struct irq_chip msm_gpio_irq_chip
= {
769 .irq_mask
= msm_gpio_irq_mask
,
770 .irq_unmask
= msm_gpio_irq_unmask
,
771 .irq_ack
= msm_gpio_irq_ack
,
772 .irq_set_type
= msm_gpio_irq_set_type
,
773 .irq_set_wake
= msm_gpio_irq_set_wake
,
776 static void msm_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
778 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
779 const struct msm_pingroup
*g
;
780 struct msm_pinctrl
*pctrl
= to_msm_pinctrl(gc
);
781 struct irq_chip
*chip
= irq_get_chip(irq
);
787 chained_irq_enter(chip
, desc
);
790 * Each pin has it's own IRQ status register, so use
791 * enabled_irq bitmap to limit the number of reads.
793 for_each_set_bit(i
, pctrl
->enabled_irqs
, pctrl
->chip
.ngpio
) {
794 g
= &pctrl
->soc
->groups
[i
];
795 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
796 if (val
& BIT(g
->intr_status_bit
)) {
797 irq_pin
= irq_find_mapping(gc
->irqdomain
, i
);
798 generic_handle_irq(irq_pin
);
803 /* No interrupts were flagged */
805 handle_bad_irq(irq
, desc
);
807 chained_irq_exit(chip
, desc
);
810 static int msm_gpio_init(struct msm_pinctrl
*pctrl
)
812 struct gpio_chip
*chip
;
814 unsigned ngpio
= pctrl
->soc
->ngpios
;
816 if (WARN_ON(ngpio
> MAX_NR_GPIO
))
822 chip
->label
= dev_name(pctrl
->dev
);
823 chip
->dev
= pctrl
->dev
;
824 chip
->owner
= THIS_MODULE
;
825 chip
->of_node
= pctrl
->dev
->of_node
;
827 ret
= gpiochip_add(&pctrl
->chip
);
829 dev_err(pctrl
->dev
, "Failed register gpiochip\n");
833 ret
= gpiochip_add_pin_range(&pctrl
->chip
, dev_name(pctrl
->dev
), 0, 0, chip
->ngpio
);
835 dev_err(pctrl
->dev
, "Failed to add pin range\n");
836 gpiochip_remove(&pctrl
->chip
);
840 ret
= gpiochip_irqchip_add(chip
,
846 dev_err(pctrl
->dev
, "Failed to add irqchip to gpiochip\n");
847 gpiochip_remove(&pctrl
->chip
);
851 gpiochip_set_chained_irqchip(chip
, &msm_gpio_irq_chip
, pctrl
->irq
,
852 msm_gpio_irq_handler
);
858 static void __iomem
*msm_ps_hold
;
860 static void msm_reset(enum reboot_mode reboot_mode
, const char *cmd
)
862 writel(0, msm_ps_hold
);
866 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl
*pctrl
)
869 const struct msm_function
*func
= pctrl
->soc
->functions
;
871 for (; i
<= pctrl
->soc
->nfunctions
; i
++)
872 if (!strcmp(func
[i
].name
, "ps_hold")) {
873 msm_ps_hold
= pctrl
->regs
+ PS_HOLD_OFFSET
;
874 arm_pm_restart
= msm_reset
;
878 static void msm_pinctrl_setup_pm_reset(const struct msm_pinctrl
*pctrl
) {}
881 int msm_pinctrl_probe(struct platform_device
*pdev
,
882 const struct msm_pinctrl_soc_data
*soc_data
)
884 struct msm_pinctrl
*pctrl
;
885 struct resource
*res
;
888 pctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctrl
), GFP_KERNEL
);
890 dev_err(&pdev
->dev
, "Can't allocate msm_pinctrl\n");
893 pctrl
->dev
= &pdev
->dev
;
894 pctrl
->soc
= soc_data
;
895 pctrl
->chip
= msm_gpio_template
;
897 spin_lock_init(&pctrl
->lock
);
899 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
900 pctrl
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
901 if (IS_ERR(pctrl
->regs
))
902 return PTR_ERR(pctrl
->regs
);
904 msm_pinctrl_setup_pm_reset(pctrl
);
906 pctrl
->irq
= platform_get_irq(pdev
, 0);
907 if (pctrl
->irq
< 0) {
908 dev_err(&pdev
->dev
, "No interrupt defined for msmgpio\n");
912 msm_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
913 msm_pinctrl_desc
.pins
= pctrl
->soc
->pins
;
914 msm_pinctrl_desc
.npins
= pctrl
->soc
->npins
;
915 pctrl
->pctrl
= pinctrl_register(&msm_pinctrl_desc
, &pdev
->dev
, pctrl
);
917 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
921 ret
= msm_gpio_init(pctrl
);
923 pinctrl_unregister(pctrl
->pctrl
);
927 platform_set_drvdata(pdev
, pctrl
);
929 dev_dbg(&pdev
->dev
, "Probed Qualcomm pinctrl driver\n");
933 EXPORT_SYMBOL(msm_pinctrl_probe
);
935 int msm_pinctrl_remove(struct platform_device
*pdev
)
937 struct msm_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
940 ret
= gpiochip_remove(&pctrl
->chip
);
942 dev_err(&pdev
->dev
, "Failed to remove gpiochip\n");
946 pinctrl_unregister(pctrl
->pctrl
);
950 EXPORT_SYMBOL(msm_pinctrl_remove
);