2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
32 #include <linux/log2.h>
35 #include "../pinconf.h"
36 #include "pinctrl-msm.h"
37 #include "../pinctrl-utils.h"
39 #define MAX_NR_GPIO 300
40 #define PS_HOLD_OFFSET 0x820
43 * struct msm_pinctrl - state for a pinctrl-msm device
44 * @dev: device handle.
45 * @pctrl: pinctrl handle.
46 * @chip: gpiochip handle.
47 * @restart_nb: restart notifier block.
48 * @irq: parent irq for the TLMM irq_chip.
49 * @lock: Spinlock to protect register resources as well
50 * as msm_pinctrl data structures.
51 * @enabled_irqs: Bitmap of currently enabled irqs.
52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
54 * @soc; Reference to soc_data of platform specific data.
55 * @regs: Base address for the TLMM register map.
59 struct pinctrl_dev
*pctrl
;
60 struct gpio_chip chip
;
61 struct notifier_block restart_nb
;
66 DECLARE_BITMAP(dual_edge_irqs
, MAX_NR_GPIO
);
67 DECLARE_BITMAP(enabled_irqs
, MAX_NR_GPIO
);
69 const struct msm_pinctrl_soc_data
*soc
;
73 static int msm_get_groups_count(struct pinctrl_dev
*pctldev
)
75 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
77 return pctrl
->soc
->ngroups
;
80 static const char *msm_get_group_name(struct pinctrl_dev
*pctldev
,
83 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
85 return pctrl
->soc
->groups
[group
].name
;
88 static int msm_get_group_pins(struct pinctrl_dev
*pctldev
,
90 const unsigned **pins
,
93 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
95 *pins
= pctrl
->soc
->groups
[group
].pins
;
96 *num_pins
= pctrl
->soc
->groups
[group
].npins
;
100 static const struct pinctrl_ops msm_pinctrl_ops
= {
101 .get_groups_count
= msm_get_groups_count
,
102 .get_group_name
= msm_get_group_name
,
103 .get_group_pins
= msm_get_group_pins
,
104 .dt_node_to_map
= pinconf_generic_dt_node_to_map_group
,
105 .dt_free_map
= pinctrl_utils_free_map
,
108 static int msm_get_functions_count(struct pinctrl_dev
*pctldev
)
110 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
112 return pctrl
->soc
->nfunctions
;
115 static const char *msm_get_function_name(struct pinctrl_dev
*pctldev
,
118 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
120 return pctrl
->soc
->functions
[function
].name
;
123 static int msm_get_function_groups(struct pinctrl_dev
*pctldev
,
125 const char * const **groups
,
126 unsigned * const num_groups
)
128 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
130 *groups
= pctrl
->soc
->functions
[function
].groups
;
131 *num_groups
= pctrl
->soc
->functions
[function
].ngroups
;
135 static int msm_pinmux_set_mux(struct pinctrl_dev
*pctldev
,
139 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
140 const struct msm_pingroup
*g
;
145 g
= &pctrl
->soc
->groups
[group
];
146 mask
= GENMASK(g
->mux_bit
+ order_base_2(g
->nfuncs
) - 1, g
->mux_bit
);
148 for (i
= 0; i
< g
->nfuncs
; i
++) {
149 if (g
->funcs
[i
] == function
)
153 if (WARN_ON(i
== g
->nfuncs
))
156 spin_lock_irqsave(&pctrl
->lock
, flags
);
158 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
160 val
|= i
<< g
->mux_bit
;
161 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
163 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
168 static const struct pinmux_ops msm_pinmux_ops
= {
169 .get_functions_count
= msm_get_functions_count
,
170 .get_function_name
= msm_get_function_name
,
171 .get_function_groups
= msm_get_function_groups
,
172 .set_mux
= msm_pinmux_set_mux
,
175 static int msm_config_reg(struct msm_pinctrl
*pctrl
,
176 const struct msm_pingroup
*g
,
182 case PIN_CONFIG_BIAS_DISABLE
:
183 case PIN_CONFIG_BIAS_PULL_DOWN
:
184 case PIN_CONFIG_BIAS_BUS_HOLD
:
185 case PIN_CONFIG_BIAS_PULL_UP
:
189 case PIN_CONFIG_DRIVE_STRENGTH
:
193 case PIN_CONFIG_OUTPUT
:
194 case PIN_CONFIG_INPUT_ENABLE
:
205 #define MSM_NO_PULL 0
206 #define MSM_PULL_DOWN 1
208 #define MSM_PULL_UP 3
210 static unsigned msm_regval_to_drive(u32 val
)
212 return (val
+ 1) * 2;
215 static int msm_config_group_get(struct pinctrl_dev
*pctldev
,
217 unsigned long *config
)
219 const struct msm_pingroup
*g
;
220 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
221 unsigned param
= pinconf_to_config_param(*config
);
228 g
= &pctrl
->soc
->groups
[group
];
230 ret
= msm_config_reg(pctrl
, g
, param
, &mask
, &bit
);
234 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
235 arg
= (val
>> bit
) & mask
;
237 /* Convert register value to pinconf value */
239 case PIN_CONFIG_BIAS_DISABLE
:
240 arg
= arg
== MSM_NO_PULL
;
242 case PIN_CONFIG_BIAS_PULL_DOWN
:
243 arg
= arg
== MSM_PULL_DOWN
;
245 case PIN_CONFIG_BIAS_BUS_HOLD
:
246 arg
= arg
== MSM_KEEPER
;
248 case PIN_CONFIG_BIAS_PULL_UP
:
249 arg
= arg
== MSM_PULL_UP
;
251 case PIN_CONFIG_DRIVE_STRENGTH
:
252 arg
= msm_regval_to_drive(arg
);
254 case PIN_CONFIG_OUTPUT
:
255 /* Pin is not output */
259 val
= readl(pctrl
->regs
+ g
->io_reg
);
260 arg
= !!(val
& BIT(g
->in_bit
));
262 case PIN_CONFIG_INPUT_ENABLE
:
272 *config
= pinconf_to_config_packed(param
, arg
);
277 static int msm_config_group_set(struct pinctrl_dev
*pctldev
,
279 unsigned long *configs
,
280 unsigned num_configs
)
282 const struct msm_pingroup
*g
;
283 struct msm_pinctrl
*pctrl
= pinctrl_dev_get_drvdata(pctldev
);
293 g
= &pctrl
->soc
->groups
[group
];
295 for (i
= 0; i
< num_configs
; i
++) {
296 param
= pinconf_to_config_param(configs
[i
]);
297 arg
= pinconf_to_config_argument(configs
[i
]);
299 ret
= msm_config_reg(pctrl
, g
, param
, &mask
, &bit
);
303 /* Convert pinconf values to register values */
305 case PIN_CONFIG_BIAS_DISABLE
:
308 case PIN_CONFIG_BIAS_PULL_DOWN
:
311 case PIN_CONFIG_BIAS_BUS_HOLD
:
314 case PIN_CONFIG_BIAS_PULL_UP
:
317 case PIN_CONFIG_DRIVE_STRENGTH
:
318 /* Check for invalid values */
319 if (arg
> 16 || arg
< 2 || (arg
% 2) != 0)
324 case PIN_CONFIG_OUTPUT
:
325 /* set output value */
326 spin_lock_irqsave(&pctrl
->lock
, flags
);
327 val
= readl(pctrl
->regs
+ g
->io_reg
);
329 val
|= BIT(g
->out_bit
);
331 val
&= ~BIT(g
->out_bit
);
332 writel(val
, pctrl
->regs
+ g
->io_reg
);
333 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
338 case PIN_CONFIG_INPUT_ENABLE
:
343 dev_err(pctrl
->dev
, "Unsupported config parameter: %x\n",
348 /* Range-check user-supplied value */
350 dev_err(pctrl
->dev
, "config %x: %x is invalid\n", param
, arg
);
354 spin_lock_irqsave(&pctrl
->lock
, flags
);
355 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
356 val
&= ~(mask
<< bit
);
358 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
359 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
365 static const struct pinconf_ops msm_pinconf_ops
= {
367 .pin_config_group_get
= msm_config_group_get
,
368 .pin_config_group_set
= msm_config_group_set
,
371 static struct pinctrl_desc msm_pinctrl_desc
= {
372 .pctlops
= &msm_pinctrl_ops
,
373 .pmxops
= &msm_pinmux_ops
,
374 .confops
= &msm_pinconf_ops
,
375 .owner
= THIS_MODULE
,
378 static int msm_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
380 const struct msm_pingroup
*g
;
381 struct msm_pinctrl
*pctrl
= gpiochip_get_data(chip
);
385 g
= &pctrl
->soc
->groups
[offset
];
387 spin_lock_irqsave(&pctrl
->lock
, flags
);
389 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
390 val
&= ~BIT(g
->oe_bit
);
391 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
393 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
398 static int msm_gpio_direction_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
400 const struct msm_pingroup
*g
;
401 struct msm_pinctrl
*pctrl
= gpiochip_get_data(chip
);
405 g
= &pctrl
->soc
->groups
[offset
];
407 spin_lock_irqsave(&pctrl
->lock
, flags
);
409 val
= readl(pctrl
->regs
+ g
->io_reg
);
411 val
|= BIT(g
->out_bit
);
413 val
&= ~BIT(g
->out_bit
);
414 writel(val
, pctrl
->regs
+ g
->io_reg
);
416 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
417 val
|= BIT(g
->oe_bit
);
418 writel(val
, pctrl
->regs
+ g
->ctl_reg
);
420 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
425 static int msm_gpio_get_direction(struct gpio_chip
*chip
, unsigned int offset
)
427 struct msm_pinctrl
*pctrl
= gpiochip_get_data(chip
);
428 const struct msm_pingroup
*g
;
431 g
= &pctrl
->soc
->groups
[offset
];
433 val
= readl(pctrl
->regs
+ g
->ctl_reg
);
435 /* 0 = output, 1 = input */
436 return val
& BIT(g
->oe_bit
) ? 0 : 1;
439 static int msm_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
441 const struct msm_pingroup
*g
;
442 struct msm_pinctrl
*pctrl
= gpiochip_get_data(chip
);
445 g
= &pctrl
->soc
->groups
[offset
];
447 val
= readl(pctrl
->regs
+ g
->io_reg
);
448 return !!(val
& BIT(g
->in_bit
));
451 static void msm_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
453 const struct msm_pingroup
*g
;
454 struct msm_pinctrl
*pctrl
= gpiochip_get_data(chip
);
458 g
= &pctrl
->soc
->groups
[offset
];
460 spin_lock_irqsave(&pctrl
->lock
, flags
);
462 val
= readl(pctrl
->regs
+ g
->io_reg
);
464 val
|= BIT(g
->out_bit
);
466 val
&= ~BIT(g
->out_bit
);
467 writel(val
, pctrl
->regs
+ g
->io_reg
);
469 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
472 #ifdef CONFIG_DEBUG_FS
473 #include <linux/seq_file.h>
475 static void msm_gpio_dbg_show_one(struct seq_file
*s
,
476 struct pinctrl_dev
*pctldev
,
477 struct gpio_chip
*chip
,
481 const struct msm_pingroup
*g
;
482 struct msm_pinctrl
*pctrl
= gpiochip_get_data(chip
);
489 static const char * const pulls
[] = {
496 g
= &pctrl
->soc
->groups
[offset
];
497 ctl_reg
= readl(pctrl
->regs
+ g
->ctl_reg
);
499 is_out
= !!(ctl_reg
& BIT(g
->oe_bit
));
500 func
= (ctl_reg
>> g
->mux_bit
) & 7;
501 drive
= (ctl_reg
>> g
->drv_bit
) & 7;
502 pull
= (ctl_reg
>> g
->pull_bit
) & 3;
504 seq_printf(s
, " %-8s: %-3s %d", g
->name
, is_out
? "out" : "in", func
);
505 seq_printf(s
, " %dmA", msm_regval_to_drive(drive
));
506 seq_printf(s
, " %s", pulls
[pull
]);
509 static void msm_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
511 unsigned gpio
= chip
->base
;
514 for (i
= 0; i
< chip
->ngpio
; i
++, gpio
++) {
515 msm_gpio_dbg_show_one(s
, NULL
, chip
, i
, gpio
);
521 #define msm_gpio_dbg_show NULL
524 static struct gpio_chip msm_gpio_template
= {
525 .direction_input
= msm_gpio_direction_input
,
526 .direction_output
= msm_gpio_direction_output
,
527 .get_direction
= msm_gpio_get_direction
,
530 .request
= gpiochip_generic_request
,
531 .free
= gpiochip_generic_free
,
532 .dbg_show
= msm_gpio_dbg_show
,
535 /* For dual-edge interrupts in software, since some hardware has no
538 * At appropriate moments, this function may be called to flip the polarity
539 * settings of both-edge irq lines to try and catch the next edge.
541 * The attempt is considered successful if:
542 * - the status bit goes high, indicating that an edge was caught, or
543 * - the input value of the gpio doesn't change during the attempt.
544 * If the value changes twice during the process, that would cause the first
545 * test to fail but would force the second, as two opposite
546 * transitions would cause a detection no matter the polarity setting.
548 * The do-loop tries to sledge-hammer closed the timing hole between
549 * the initial value-read and the polarity-write - if the line value changes
550 * during that window, an interrupt is lost, the new polarity setting is
551 * incorrect, and the first success test will fail, causing a retry.
553 * Algorithm comes from Google's msmgpio driver.
555 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl
*pctrl
,
556 const struct msm_pingroup
*g
,
559 int loop_limit
= 100;
560 unsigned val
, val2
, intstat
;
564 val
= readl(pctrl
->regs
+ g
->io_reg
) & BIT(g
->in_bit
);
566 pol
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
567 pol
^= BIT(g
->intr_polarity_bit
);
568 writel(pol
, pctrl
->regs
+ g
->intr_cfg_reg
);
570 val2
= readl(pctrl
->regs
+ g
->io_reg
) & BIT(g
->in_bit
);
571 intstat
= readl(pctrl
->regs
+ g
->intr_status_reg
);
572 if (intstat
|| (val
== val2
))
574 } while (loop_limit
-- > 0);
575 dev_err(pctrl
->dev
, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
579 static void msm_gpio_irq_mask(struct irq_data
*d
)
581 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
582 struct msm_pinctrl
*pctrl
= gpiochip_get_data(gc
);
583 const struct msm_pingroup
*g
;
587 g
= &pctrl
->soc
->groups
[d
->hwirq
];
589 spin_lock_irqsave(&pctrl
->lock
, flags
);
591 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
592 val
&= ~BIT(g
->intr_enable_bit
);
593 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
595 clear_bit(d
->hwirq
, pctrl
->enabled_irqs
);
597 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
600 static void msm_gpio_irq_unmask(struct irq_data
*d
)
602 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
603 struct msm_pinctrl
*pctrl
= gpiochip_get_data(gc
);
604 const struct msm_pingroup
*g
;
608 g
= &pctrl
->soc
->groups
[d
->hwirq
];
610 spin_lock_irqsave(&pctrl
->lock
, flags
);
612 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
613 val
|= BIT(g
->intr_enable_bit
);
614 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
616 set_bit(d
->hwirq
, pctrl
->enabled_irqs
);
618 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
621 static void msm_gpio_irq_ack(struct irq_data
*d
)
623 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
624 struct msm_pinctrl
*pctrl
= gpiochip_get_data(gc
);
625 const struct msm_pingroup
*g
;
629 g
= &pctrl
->soc
->groups
[d
->hwirq
];
631 spin_lock_irqsave(&pctrl
->lock
, flags
);
633 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
634 if (g
->intr_ack_high
)
635 val
|= BIT(g
->intr_status_bit
);
637 val
&= ~BIT(g
->intr_status_bit
);
638 writel(val
, pctrl
->regs
+ g
->intr_status_reg
);
640 if (test_bit(d
->hwirq
, pctrl
->dual_edge_irqs
))
641 msm_gpio_update_dual_edge_pos(pctrl
, g
, d
);
643 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
646 static int msm_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
648 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
649 struct msm_pinctrl
*pctrl
= gpiochip_get_data(gc
);
650 const struct msm_pingroup
*g
;
654 g
= &pctrl
->soc
->groups
[d
->hwirq
];
656 spin_lock_irqsave(&pctrl
->lock
, flags
);
659 * For hw without possibility of detecting both edges
661 if (g
->intr_detection_width
== 1 && type
== IRQ_TYPE_EDGE_BOTH
)
662 set_bit(d
->hwirq
, pctrl
->dual_edge_irqs
);
664 clear_bit(d
->hwirq
, pctrl
->dual_edge_irqs
);
666 /* Route interrupts to application cpu */
667 val
= readl(pctrl
->regs
+ g
->intr_target_reg
);
668 val
&= ~(7 << g
->intr_target_bit
);
669 val
|= g
->intr_target_kpss_val
<< g
->intr_target_bit
;
670 writel(val
, pctrl
->regs
+ g
->intr_target_reg
);
672 /* Update configuration for gpio.
673 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
674 * internal circuitry of TLMM, toggling the RAW_STATUS
675 * could cause the INTR_STATUS to be set for EDGE interrupts.
677 val
= readl(pctrl
->regs
+ g
->intr_cfg_reg
);
678 val
|= BIT(g
->intr_raw_status_bit
);
679 if (g
->intr_detection_width
== 2) {
680 val
&= ~(3 << g
->intr_detection_bit
);
681 val
&= ~(1 << g
->intr_polarity_bit
);
683 case IRQ_TYPE_EDGE_RISING
:
684 val
|= 1 << g
->intr_detection_bit
;
685 val
|= BIT(g
->intr_polarity_bit
);
687 case IRQ_TYPE_EDGE_FALLING
:
688 val
|= 2 << g
->intr_detection_bit
;
689 val
|= BIT(g
->intr_polarity_bit
);
691 case IRQ_TYPE_EDGE_BOTH
:
692 val
|= 3 << g
->intr_detection_bit
;
693 val
|= BIT(g
->intr_polarity_bit
);
695 case IRQ_TYPE_LEVEL_LOW
:
697 case IRQ_TYPE_LEVEL_HIGH
:
698 val
|= BIT(g
->intr_polarity_bit
);
701 } else if (g
->intr_detection_width
== 1) {
702 val
&= ~(1 << g
->intr_detection_bit
);
703 val
&= ~(1 << g
->intr_polarity_bit
);
705 case IRQ_TYPE_EDGE_RISING
:
706 val
|= BIT(g
->intr_detection_bit
);
707 val
|= BIT(g
->intr_polarity_bit
);
709 case IRQ_TYPE_EDGE_FALLING
:
710 val
|= BIT(g
->intr_detection_bit
);
712 case IRQ_TYPE_EDGE_BOTH
:
713 val
|= BIT(g
->intr_detection_bit
);
714 val
|= BIT(g
->intr_polarity_bit
);
716 case IRQ_TYPE_LEVEL_LOW
:
718 case IRQ_TYPE_LEVEL_HIGH
:
719 val
|= BIT(g
->intr_polarity_bit
);
725 writel(val
, pctrl
->regs
+ g
->intr_cfg_reg
);
727 if (test_bit(d
->hwirq
, pctrl
->dual_edge_irqs
))
728 msm_gpio_update_dual_edge_pos(pctrl
, g
, d
);
730 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
732 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
733 irq_set_handler_locked(d
, handle_level_irq
);
734 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
735 irq_set_handler_locked(d
, handle_edge_irq
);
740 static int msm_gpio_irq_set_wake(struct irq_data
*d
, unsigned int on
)
742 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
743 struct msm_pinctrl
*pctrl
= gpiochip_get_data(gc
);
746 spin_lock_irqsave(&pctrl
->lock
, flags
);
748 irq_set_irq_wake(pctrl
->irq
, on
);
750 spin_unlock_irqrestore(&pctrl
->lock
, flags
);
755 static struct irq_chip msm_gpio_irq_chip
= {
757 .irq_mask
= msm_gpio_irq_mask
,
758 .irq_unmask
= msm_gpio_irq_unmask
,
759 .irq_ack
= msm_gpio_irq_ack
,
760 .irq_set_type
= msm_gpio_irq_set_type
,
761 .irq_set_wake
= msm_gpio_irq_set_wake
,
764 static void msm_gpio_irq_handler(struct irq_desc
*desc
)
766 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
767 const struct msm_pingroup
*g
;
768 struct msm_pinctrl
*pctrl
= gpiochip_get_data(gc
);
769 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
775 chained_irq_enter(chip
, desc
);
778 * Each pin has it's own IRQ status register, so use
779 * enabled_irq bitmap to limit the number of reads.
781 for_each_set_bit(i
, pctrl
->enabled_irqs
, pctrl
->chip
.ngpio
) {
782 g
= &pctrl
->soc
->groups
[i
];
783 val
= readl(pctrl
->regs
+ g
->intr_status_reg
);
784 if (val
& BIT(g
->intr_status_bit
)) {
785 irq_pin
= irq_find_mapping(gc
->irqdomain
, i
);
786 generic_handle_irq(irq_pin
);
791 /* No interrupts were flagged */
793 handle_bad_irq(desc
);
795 chained_irq_exit(chip
, desc
);
798 static int msm_gpio_init(struct msm_pinctrl
*pctrl
)
800 struct gpio_chip
*chip
;
802 unsigned ngpio
= pctrl
->soc
->ngpios
;
804 if (WARN_ON(ngpio
> MAX_NR_GPIO
))
810 chip
->label
= dev_name(pctrl
->dev
);
811 chip
->parent
= pctrl
->dev
;
812 chip
->owner
= THIS_MODULE
;
813 chip
->of_node
= pctrl
->dev
->of_node
;
815 ret
= gpiochip_add_data(&pctrl
->chip
, pctrl
);
817 dev_err(pctrl
->dev
, "Failed register gpiochip\n");
821 ret
= gpiochip_add_pin_range(&pctrl
->chip
, dev_name(pctrl
->dev
), 0, 0, chip
->ngpio
);
823 dev_err(pctrl
->dev
, "Failed to add pin range\n");
824 gpiochip_remove(&pctrl
->chip
);
828 ret
= gpiochip_irqchip_add(chip
,
834 dev_err(pctrl
->dev
, "Failed to add irqchip to gpiochip\n");
835 gpiochip_remove(&pctrl
->chip
);
839 gpiochip_set_chained_irqchip(chip
, &msm_gpio_irq_chip
, pctrl
->irq
,
840 msm_gpio_irq_handler
);
845 static int msm_ps_hold_restart(struct notifier_block
*nb
, unsigned long action
,
848 struct msm_pinctrl
*pctrl
= container_of(nb
, struct msm_pinctrl
, restart_nb
);
850 writel(0, pctrl
->regs
+ PS_HOLD_OFFSET
);
855 static struct msm_pinctrl
*poweroff_pctrl
;
857 static void msm_ps_hold_poweroff(void)
859 msm_ps_hold_restart(&poweroff_pctrl
->restart_nb
, 0, NULL
);
862 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl
*pctrl
)
865 const struct msm_function
*func
= pctrl
->soc
->functions
;
867 for (i
= 0; i
< pctrl
->soc
->nfunctions
; i
++)
868 if (!strcmp(func
[i
].name
, "ps_hold")) {
869 pctrl
->restart_nb
.notifier_call
= msm_ps_hold_restart
;
870 pctrl
->restart_nb
.priority
= 128;
871 if (register_restart_handler(&pctrl
->restart_nb
))
873 "failed to setup restart handler.\n");
874 poweroff_pctrl
= pctrl
;
875 pm_power_off
= msm_ps_hold_poweroff
;
880 int msm_pinctrl_probe(struct platform_device
*pdev
,
881 const struct msm_pinctrl_soc_data
*soc_data
)
883 struct msm_pinctrl
*pctrl
;
884 struct resource
*res
;
887 pctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*pctrl
), GFP_KERNEL
);
889 dev_err(&pdev
->dev
, "Can't allocate msm_pinctrl\n");
892 pctrl
->dev
= &pdev
->dev
;
893 pctrl
->soc
= soc_data
;
894 pctrl
->chip
= msm_gpio_template
;
896 spin_lock_init(&pctrl
->lock
);
898 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
899 pctrl
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
900 if (IS_ERR(pctrl
->regs
))
901 return PTR_ERR(pctrl
->regs
);
903 msm_pinctrl_setup_pm_reset(pctrl
);
905 pctrl
->irq
= platform_get_irq(pdev
, 0);
906 if (pctrl
->irq
< 0) {
907 dev_err(&pdev
->dev
, "No interrupt defined for msmgpio\n");
911 msm_pinctrl_desc
.name
= dev_name(&pdev
->dev
);
912 msm_pinctrl_desc
.pins
= pctrl
->soc
->pins
;
913 msm_pinctrl_desc
.npins
= pctrl
->soc
->npins
;
914 pctrl
->pctrl
= devm_pinctrl_register(&pdev
->dev
, &msm_pinctrl_desc
,
916 if (IS_ERR(pctrl
->pctrl
)) {
917 dev_err(&pdev
->dev
, "Couldn't register pinctrl driver\n");
918 return PTR_ERR(pctrl
->pctrl
);
921 ret
= msm_gpio_init(pctrl
);
925 platform_set_drvdata(pdev
, pctrl
);
927 dev_dbg(&pdev
->dev
, "Probed Qualcomm pinctrl driver\n");
931 EXPORT_SYMBOL(msm_pinctrl_probe
);
933 int msm_pinctrl_remove(struct platform_device
*pdev
)
935 struct msm_pinctrl
*pctrl
= platform_get_drvdata(pdev
);
937 gpiochip_remove(&pctrl
->chip
);
939 unregister_restart_handler(&pctrl
->restart_nb
);
943 EXPORT_SYMBOL(msm_pinctrl_remove
);